drivers/firewire/ohci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for OHCI 1394 controllers
   4  *
   5  * Copyright (C) 2003-2006 Kristian Hoegsberg <[email protected]>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/bug.h>
  10 #include <linux/compiler.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/firewire.h>
  15 #include <linux/firewire-constants.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/kernel.h>
  20 #include <linux/list.h>
  21 #include <linux/mm.h>
  22 #include <linux/module.h>
  23 #include <linux/moduleparam.h>
  24 #include <linux/mutex.h>
  25 #include <linux/pci.h>
  26 #include <linux/pci_ids.h>
  27 #include <linux/slab.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/string.h>
  30 #include <linux/time.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/workqueue.h>
  33
  34 #include <asm/byteorder.h>
  35 #include <asm/page.h>
  36
  37 #ifdef CONFIG_PPC_PMAC
  38 #include <asm/pmac_feature.h>
  39 #endif
  40
  41 #include "core.h"
  42 #include "ohci.h"
  43 #include "packet-header-definitions.h"
  44 #include "phy-packet-definitions.h"
  45
  46 #include <trace/events/firewire.h>
  47
  48 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk);
  49
  50 #define CREATE_TRACE_POINTS
  51 #include <trace/events/firewire_ohci.h>
  52
  53 #define ohci_notice(ohci, f, args...)   dev_notice(ohci->card.device, f, ##args)
  54 #define ohci_err(ohci, f, args...)      dev_err(ohci->card.device, f, ##args)
  55
  56 #define DESCRIPTOR_OUTPUT_MORE          0
  57 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  58 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  59 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  60 #define DESCRIPTOR_STATUS               (1 << 11)
  61 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  62 #define DESCRIPTOR_PING                 (1 << 7)
  63 #define DESCRIPTOR_YY                   (1 << 6)
  64 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  65 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  66 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  67 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  68 #define DESCRIPTOR_WAIT                 (3 << 0)
  69
  70 #define DESCRIPTOR_CMD                  (0xf << 12)
  71
  72 struct descriptor {
  73         __le16 req_count;
  74         __le16 control;
  75         __le32 data_address;
  76         __le32 branch_address;
  77         __le16 res_count;
  78         __le16 transfer_status;
  79 } __aligned(16);
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 #define AR_BUFFER_SIZE  (32*1024)
  87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  88 /* we need at least two pages for proper list management */
  89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  90
  91 #define MAX_ASYNC_PAYLOAD       4096
  92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  94
  95 struct ar_context {
  96         struct fw_ohci *ohci;
  97         struct page *pages[AR_BUFFERS];
  98         void *buffer;
  99         struct descriptor *descriptors;
 100         dma_addr_t descriptors_bus;
 101         void *pointer;
 102         unsigned int last_buffer_index;
 103         u32 regs;
 104         struct tasklet_struct tasklet;
 105 };
 106
 107 struct context;
 108
 109 typedef int (*descriptor_callback_t)(struct context *ctx,
 110                                      struct descriptor *d,
 111                                      struct descriptor *last);
 112
 113 /*
 114  * A buffer that contains a block of DMA-able coherent memory used for
 115  * storing a portion of a DMA descriptor program.
 116  */
 117 struct descriptor_buffer {
 118         struct list_head list;
 119         dma_addr_t buffer_bus;
 120         size_t buffer_size;
 121         size_t used;
 122         struct descriptor buffer[];
 123 };
 124
 125 struct context {
 126         struct fw_ohci *ohci;
 127         u32 regs;
 128         int total_allocation;
 129         u32 current_bus;
 130         bool running;
 131         bool flushing;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor block in the DMA program. It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157         int prev_z;
 158
 159         descriptor_callback_t callback;
 160
 161         struct tasklet_struct tasklet;
 162 };
 163
 164 struct iso_context {
 165         struct fw_iso_context base;
 166         struct context context;
 167         void *header;
 168         size_t header_length;
 169         unsigned long flushing_completions;
 170         u32 mc_buffer_bus;
 171         u16 mc_completed;
 172         u16 last_timestamp;
 173         u8 sync;
 174         u8 tags;
 175 };
 176
 177 #define CONFIG_ROM_SIZE         (CSR_CONFIG_ROM_END - CSR_CONFIG_ROM)
 178
 179 struct fw_ohci {
 180         struct fw_card card;
 181
 182         __iomem char *registers;
 183         int node_id;
 184         int generation;
 185         int request_generation; /* for timestamping incoming requests */
 186         unsigned quirks;
 187         unsigned int pri_req_max;
 188         u32 bus_time;
 189         bool bus_time_running;
 190         bool is_root;
 191         bool csr_state_setclear_abdicate;
 192         int n_ir;
 193         int n_it;
 194         /*
 195          * Spinlock for accessing fw_ohci data.  Never call out of
 196          * this driver with this lock held.
 197          */
 198         spinlock_t lock;
 199
 200         struct mutex phy_reg_mutex;
 201
 202         void *misc_buffer;
 203         dma_addr_t misc_buffer_bus;
 204
 205         struct ar_context ar_request_ctx;
 206         struct ar_context ar_response_ctx;
 207         struct context at_request_ctx;
 208         struct context at_response_ctx;
 209
 210         u32 it_context_support;
 211         u32 it_context_mask;     /* unoccupied IT contexts */
 212         struct iso_context *it_context_list;
 213         u64 ir_context_channels; /* unoccupied channels */
 214         u32 ir_context_support;
 215         u32 ir_context_mask;     /* unoccupied IR contexts */
 216         struct iso_context *ir_context_list;
 217         u64 mc_channels; /* channels in use by the multichannel IR context */
 218         bool mc_allocated;
 219
 220         __be32    *config_rom;
 221         dma_addr_t config_rom_bus;
 222         __be32    *next_config_rom;
 223         dma_addr_t next_config_rom_bus;
 224         __be32     next_header;
 225
 226         __le32    *self_id;
 227         dma_addr_t self_id_bus;
 228         struct work_struct bus_reset_work;
 229
 230         u32 self_id_buffer[512];
 231 };
 232
 233 static struct workqueue_struct *selfid_workqueue;
 234
 235 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 236 {
 237         return container_of(card, struct fw_ohci, card);
 238 }
 239
 240 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 241 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 242 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 243 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 244 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 245 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 246
 247 #define CONTEXT_RUN     0x8000
 248 #define CONTEXT_WAKE    0x1000
 249 #define CONTEXT_DEAD    0x0800
 250 #define CONTEXT_ACTIVE  0x0400
 251
 252 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 253 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 254 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 255
 256 #define OHCI1394_REGISTER_SIZE          0x800
 257 #define OHCI1394_PCI_HCI_Control        0x40
 258 #define SELF_ID_BUF_SIZE                0x800
 259 #define OHCI_VERSION_1_1                0x010010
 260
 261 static char ohci_driver_name[] = KBUILD_MODNAME;
 262
 263 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 264 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 265 #define PCI_DEVICE_ID_CREATIVE_SB1394   0x4001
 266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 267 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 268 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 269 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 270 #define PCI_DEVICE_ID_VIA_VT630X        0x3044
 271 #define PCI_REV_ID_VIA_VT6306           0x46
 272 #define PCI_DEVICE_ID_VIA_VT6315        0x3403
 273
 274 #define QUIRK_CYCLE_TIMER               0x1
 275 #define QUIRK_RESET_PACKET              0x2
 276 #define QUIRK_BE_HEADERS                0x4
 277 #define QUIRK_NO_1394A                  0x8
 278 #define QUIRK_NO_MSI                    0x10
 279 #define QUIRK_TI_SLLZ059                0x20
 280 #define QUIRK_IR_WAKE                   0x40
 281
 282 // On PCI Express Root Complex in any type of AMD Ryzen machine, VIA VT6306/6307/6308 with Asmedia
 283 // ASM1083/1085 brings an inconvenience that the read accesses to 'Isochronous Cycle Timer' register
 284 // (at offset 0xf0 in PCI I/O space) often causes unexpected system reboot. The mechanism is not
 285 // clear, since the read access to the other registers is enough safe; e.g. 'Node ID' register,
 286 // while it is probable due to detection of any type of PCIe error.
 287 #define QUIRK_REBOOT_BY_CYCLE_TIMER_READ        0x80000000
 288
 289 #if IS_ENABLED(CONFIG_X86)
 290
 291 static bool has_reboot_by_cycle_timer_read_quirk(const struct fw_ohci *ohci)
 292 {
 293         return !!(ohci->quirks & QUIRK_REBOOT_BY_CYCLE_TIMER_READ);
 294 }
 295
 296 #define PCI_DEVICE_ID_ASMEDIA_ASM108X   0x1080
 297
 298 static bool detect_vt630x_with_asm1083_on_amd_ryzen_machine(const struct pci_dev *pdev)
 299 {
 300         const struct pci_dev *pcie_to_pci_bridge;
 301
 302         // Detect any type of AMD Ryzen machine.
 303         if (!static_cpu_has(X86_FEATURE_ZEN))
 304                 return false;
 305
 306         // Detect VIA VT6306/6307/6308.
 307         if (pdev->vendor != PCI_VENDOR_ID_VIA)
 308                 return false;
 309         if (pdev->device != PCI_DEVICE_ID_VIA_VT630X)
 310                 return false;
 311
 312         // Detect Asmedia ASM1083/1085.
 313         pcie_to_pci_bridge = pdev->bus->self;
 314         if (pcie_to_pci_bridge->vendor != PCI_VENDOR_ID_ASMEDIA)
 315                 return false;
 316         if (pcie_to_pci_bridge->device != PCI_DEVICE_ID_ASMEDIA_ASM108X)
 317                 return false;
 318
 319         return true;
 320 }
 321
 322 #else
 323 #define has_reboot_by_cycle_timer_read_quirk(ohci) false
 324 #define detect_vt630x_with_asm1083_on_amd_ryzen_machine(pdev)   false
 325 #endif
 326
 327 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 328 static const struct {
 329         unsigned short vendor, device, revision, flags;
 330 } ohci_quirks[] = {
 331         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 332                 QUIRK_CYCLE_TIMER},
 333
 334         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 335                 QUIRK_BE_HEADERS},
 336
 337         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 338                 QUIRK_NO_MSI},
 339
 340         {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
 341                 QUIRK_RESET_PACKET},
 342
 343         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 344                 QUIRK_NO_MSI},
 345
 346         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 347                 QUIRK_CYCLE_TIMER},
 348
 349         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 350                 QUIRK_NO_MSI},
 351
 352         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 353                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 354
 355         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 356                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 357
 358         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 359                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 360
 361         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 362                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 363
 364         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 365                 QUIRK_RESET_PACKET},
 366
 367         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
 368                 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
 369
 370         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
 371                 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
 372
 373         {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
 374                 QUIRK_NO_MSI},
 375
 376         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 377                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 378 };
 379
 380 /* This overrides anything that was found in ohci_quirks[]. */
 381 static int param_quirks;
 382 module_param_named(quirks, param_quirks, int, 0644);
 383 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 384         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 385         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 386         ", AR/selfID endianness = "     __stringify(QUIRK_BE_HEADERS)
 387         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 388         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 389         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 390         ", IR wake unreliable = "       __stringify(QUIRK_IR_WAKE)
 391         ")");
 392
 393 #define OHCI_PARAM_DEBUG_AT_AR          1
 394 #define OHCI_PARAM_DEBUG_SELFIDS        2
 395 #define OHCI_PARAM_DEBUG_IRQS           4
 396
 397 static int param_debug;
 398 module_param_named(debug, param_debug, int, 0644);
 399 MODULE_PARM_DESC(debug, "Verbose logging, deprecated in v6.11 kernel or later. (default = 0"
 400         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 401         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 402         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 403         ", or a combination, or all = -1)");
 404
 405 static bool param_remote_dma;
 406 module_param_named(remote_dma, param_remote_dma, bool, 0444);
 407 MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
 408
 409 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 410 {
 411         if (likely(!(param_debug & OHCI_PARAM_DEBUG_IRQS)))
 412                 return;
 413
 414         ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 415             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 416             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 417             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 418             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 419             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 420             evt & OHCI1394_isochRx              ? " IR"                 : "",
 421             evt & OHCI1394_isochTx              ? " IT"                 : "",
 422             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 423             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 424             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 425             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 426             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 427             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 428             evt & OHCI1394_busReset             ? " busReset"           : "",
 429             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 430                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 431                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 432                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 433                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 434                     OHCI1394_cycleInconsistent |
 435                     OHCI1394_regAccessFail | OHCI1394_busReset)
 436                                                 ? " ?"                  : "");
 437 }
 438
 439 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 440 {
 441         static const char *const speed[] = {
 442                 [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 443         };
 444         static const char *const power[] = {
 445                 [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 446                 [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 447         };
 448         static const char port[] = {
 449                 [PHY_PACKET_SELF_ID_PORT_STATUS_NONE] = '.',
 450                 [PHY_PACKET_SELF_ID_PORT_STATUS_NCONN] = '-',
 451                 [PHY_PACKET_SELF_ID_PORT_STATUS_PARENT] = 'p',
 452                 [PHY_PACKET_SELF_ID_PORT_STATUS_CHILD] = 'c',
 453         };
 454         struct self_id_sequence_enumerator enumerator = {
 455                 .cursor = ohci->self_id_buffer,
 456                 .quadlet_count = self_id_count,
 457         };
 458
 459         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 460                 return;
 461
 462         ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
 463                     self_id_count, generation, ohci->node_id);
 464
 465         while (enumerator.quadlet_count > 0) {
 466                 unsigned int quadlet_count;
 467                 unsigned int port_index;
 468                 const u32 *s;
 469                 int i;
 470
 471                 s = self_id_sequence_enumerator_next(&enumerator, &quadlet_count);
 472                 if (IS_ERR(s))
 473                         break;
 474
 475                 ohci_notice(ohci,
 476                     "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
 477                     *s,
 478                     phy_packet_self_id_get_phy_id(*s),
 479                     port[self_id_sequence_get_port_status(s, quadlet_count, 0)],
 480                     port[self_id_sequence_get_port_status(s, quadlet_count, 1)],
 481                     port[self_id_sequence_get_port_status(s, quadlet_count, 2)],
 482                     speed[*s >> 14 & 3], *s >> 16 & 63,
 483                     power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 484                     *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 485
 486                 port_index = 3;
 487                 for (i = 1; i < quadlet_count; ++i) {
 488                         ohci_notice(ohci,
 489                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 490                             s[i],
 491                             phy_packet_self_id_get_phy_id(s[i]),
 492                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index)],
 493                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 1)],
 494                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 2)],
 495                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 3)],
 496                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 4)],
 497                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 5)],
 498                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 6)],
 499                             port[self_id_sequence_get_port_status(s, quadlet_count, port_index + 7)]
 500                         );
 501
 502                         port_index += 8;
 503                 }
 504         }
 505 }
 506
 507 static const char *evts[] = {
 508         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 509         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 510         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 511         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 512         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 513         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 514         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 515         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 516         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 517         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 518         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 519         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 520         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 521         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 522         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 523         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 524         [0x20] = "pending/cancelled",
 525 };
 526
 527 static void log_ar_at_event(struct fw_ohci *ohci,
 528                             char dir, int speed, u32 *header, int evt)
 529 {
 530         static const char *const tcodes[] = {
 531                 [TCODE_WRITE_QUADLET_REQUEST]   = "QW req",
 532                 [TCODE_WRITE_BLOCK_REQUEST]     = "BW req",
 533                 [TCODE_WRITE_RESPONSE]          = "W resp",
 534                 [0x3]                           = "-reserved-",
 535                 [TCODE_READ_QUADLET_REQUEST]    = "QR req",
 536                 [TCODE_READ_BLOCK_REQUEST]      = "BR req",
 537                 [TCODE_READ_QUADLET_RESPONSE]   = "QR resp",
 538                 [TCODE_READ_BLOCK_RESPONSE]     = "BR resp",
 539                 [TCODE_CYCLE_START]             = "cycle start",
 540                 [TCODE_LOCK_REQUEST]            = "Lk req",
 541                 [TCODE_STREAM_DATA]             = "async stream packet",
 542                 [TCODE_LOCK_RESPONSE]           = "Lk resp",
 543                 [0xc]                           = "-reserved-",
 544                 [0xd]                           = "-reserved-",
 545                 [TCODE_LINK_INTERNAL]           = "link internal",
 546                 [0xf]                           = "-reserved-",
 547         };
 548         int tcode = async_header_get_tcode(header);
 549         char specific[12];
 550
 551         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 552                 return;
 553
 554         if (unlikely(evt >= ARRAY_SIZE(evts)))
 555                 evt = 0x1f;
 556
 557         if (evt == OHCI1394_evt_bus_reset) {
 558                 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
 559                             dir, (header[2] >> 16) & 0xff);
 560                 return;
 561         }
 562
 563         switch (tcode) {
 564         case TCODE_WRITE_QUADLET_REQUEST:
 565         case TCODE_READ_QUADLET_RESPONSE:
 566         case TCODE_CYCLE_START:
 567                 snprintf(specific, sizeof(specific), " = %08x",
 568                          be32_to_cpu((__force __be32)header[3]));
 569                 break;
 570         case TCODE_WRITE_BLOCK_REQUEST:
 571         case TCODE_READ_BLOCK_REQUEST:
 572         case TCODE_READ_BLOCK_RESPONSE:
 573         case TCODE_LOCK_REQUEST:
 574         case TCODE_LOCK_RESPONSE:
 575                 snprintf(specific, sizeof(specific), " %x,%x",
 576                          async_header_get_data_length(header),
 577                          async_header_get_extended_tcode(header));
 578                 break;
 579         default:
 580                 specific[0] = '\0';
 581         }
 582
 583         switch (tcode) {
 584         case TCODE_STREAM_DATA:
 585                 ohci_notice(ohci, "A%c %s, %s\n",
 586                             dir, evts[evt], tcodes[tcode]);
 587                 break;
 588         case TCODE_LINK_INTERNAL:
 589                 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
 590                             dir, evts[evt], header[1], header[2]);
 591                 break;
 592         case TCODE_WRITE_QUADLET_REQUEST:
 593         case TCODE_WRITE_BLOCK_REQUEST:
 594         case TCODE_READ_QUADLET_REQUEST:
 595         case TCODE_READ_BLOCK_REQUEST:
 596         case TCODE_LOCK_REQUEST:
 597                 ohci_notice(ohci,
 598                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %012llx%s\n",
 599                             dir, speed, async_header_get_tlabel(header),
 600                             async_header_get_source(header), async_header_get_destination(header),
 601                             evts[evt], tcodes[tcode], async_header_get_offset(header), specific);
 602                 break;
 603         default:
 604                 ohci_notice(ohci,
 605                             "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
 606                             dir, speed, async_header_get_tlabel(header),
 607                             async_header_get_source(header), async_header_get_destination(header),
 608                             evts[evt], tcodes[tcode], specific);
 609         }
 610 }
 611
 612 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 613 {
 614         writel(data, ohci->registers + offset);
 615 }
 616
 617 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 618 {
 619         return readl(ohci->registers + offset);
 620 }
 621
 622 static inline void flush_writes(const struct fw_ohci *ohci)
 623 {
 624         /* Do a dummy read to flush writes. */
 625         reg_read(ohci, OHCI1394_Version);
 626 }
 627
 628 /*
 629  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 630  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 631  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 632  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 633  */
 634 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 635 {
 636         u32 val;
 637         int i;
 638
 639         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 640         for (i = 0; i < 3 + 100; i++) {
 641                 val = reg_read(ohci, OHCI1394_PhyControl);
 642                 if (!~val)
 643                         return -ENODEV; /* Card was ejected. */
 644
 645                 if (val & OHCI1394_PhyControl_ReadDone)
 646                         return OHCI1394_PhyControl_ReadData(val);
 647
 648                 /*
 649                  * Try a few times without waiting.  Sleeping is necessary
 650                  * only when the link/PHY interface is busy.
 651                  */
 652                 if (i >= 3)
 653                         msleep(1);
 654         }
 655         ohci_err(ohci, "failed to read phy reg %d\n", addr);
 656         dump_stack();
 657
 658         return -EBUSY;
 659 }
 660
 661 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 662 {
 663         int i;
 664
 665         reg_write(ohci, OHCI1394_PhyControl,
 666                   OHCI1394_PhyControl_Write(addr, val));
 667         for (i = 0; i < 3 + 100; i++) {
 668                 val = reg_read(ohci, OHCI1394_PhyControl);
 669                 if (!~val)
 670                         return -ENODEV; /* Card was ejected. */
 671
 672                 if (!(val & OHCI1394_PhyControl_WritePending))
 673                         return 0;
 674
 675                 if (i >= 3)
 676                         msleep(1);
 677         }
 678         ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
 679         dump_stack();
 680
 681         return -EBUSY;
 682 }
 683
 684 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 685                           int clear_bits, int set_bits)
 686 {
 687         int ret = read_phy_reg(ohci, addr);
 688         if (ret < 0)
 689                 return ret;
 690
 691         /*
 692          * The interrupt status bits are cleared by writing a one bit.
 693          * Avoid clearing them unless explicitly requested in set_bits.
 694          */
 695         if (addr == 5)
 696                 clear_bits |= PHY_INT_STATUS_BITS;
 697
 698         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 699 }
 700
 701 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 702 {
 703         int ret;
 704
 705         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 706         if (ret < 0)
 707                 return ret;
 708
 709         return read_phy_reg(ohci, addr);
 710 }
 711
 712 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 713 {
 714         struct fw_ohci *ohci = fw_ohci(card);
 715
 716         guard(mutex)(&ohci->phy_reg_mutex);
 717
 718         return read_phy_reg(ohci, addr);
 719 }
 720
 721 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 722                                int clear_bits, int set_bits)
 723 {
 724         struct fw_ohci *ohci = fw_ohci(card);
 725
 726         guard(mutex)(&ohci->phy_reg_mutex);
 727
 728         return update_phy_reg(ohci, addr, clear_bits, set_bits);
 729 }
 730
 731 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 732 {
 733         return page_private(ctx->pages[i]);
 734 }
 735
 736 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 737 {
 738         struct descriptor *d;
 739
 740         d = &ctx->descriptors[index];
 741         d->branch_address  &= cpu_to_le32(~0xf);
 742         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 743         d->transfer_status =  0;
 744
 745         wmb(); /* finish init of new descriptors before branch_address update */
 746         d = &ctx->descriptors[ctx->last_buffer_index];
 747         d->branch_address  |= cpu_to_le32(1);
 748
 749         ctx->last_buffer_index = index;
 750
 751         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 752 }
 753
 754 static void ar_context_release(struct ar_context *ctx)
 755 {
 756         struct device *dev = ctx->ohci->card.device;
 757         unsigned int i;
 758
 759         if (!ctx->buffer)
 760                 return;
 761
 762         vunmap(ctx->buffer);
 763
 764         for (i = 0; i < AR_BUFFERS; i++) {
 765                 if (ctx->pages[i])
 766                         dma_free_pages(dev, PAGE_SIZE, ctx->pages[i],
 767                                        ar_buffer_bus(ctx, i), DMA_FROM_DEVICE);
 768         }
 769 }
 770
 771 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 772 {
 773         struct fw_ohci *ohci = ctx->ohci;
 774
 775         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 776                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 777                 flush_writes(ohci);
 778
 779                 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
 780         }
 781         /* FIXME: restart? */
 782 }
 783
 784 static inline unsigned int ar_next_buffer_index(unsigned int index)
 785 {
 786         return (index + 1) % AR_BUFFERS;
 787 }
 788
 789 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 790 {
 791         return ar_next_buffer_index(ctx->last_buffer_index);
 792 }
 793
 794 /*
 795  * We search for the buffer that contains the last AR packet DMA data written
 796  * by the controller.
 797  */
 798 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 799                                                  unsigned int *buffer_offset)
 800 {
 801         unsigned int i, next_i, last = ctx->last_buffer_index;
 802         __le16 res_count, next_res_count;
 803
 804         i = ar_first_buffer_index(ctx);
 805         res_count = READ_ONCE(ctx->descriptors[i].res_count);
 806
 807         /* A buffer that is not yet completely filled must be the last one. */
 808         while (i != last && res_count == 0) {
 809
 810                 /* Peek at the next descriptor. */
 811                 next_i = ar_next_buffer_index(i);
 812                 rmb(); /* read descriptors in order */
 813                 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
 814                 /*
 815                  * If the next descriptor is still empty, we must stop at this
 816                  * descriptor.
 817                  */
 818                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 819                         /*
 820                          * The exception is when the DMA data for one packet is
 821                          * split over three buffers; in this case, the middle
 822                          * buffer's descriptor might be never updated by the
 823                          * controller and look still empty, and we have to peek
 824                          * at the third one.
 825                          */
 826                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 827                                 next_i = ar_next_buffer_index(next_i);
 828                                 rmb();
 829                                 next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
 830                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 831                                         goto next_buffer_is_active;
 832                         }
 833
 834                         break;
 835                 }
 836
 837 next_buffer_is_active:
 838                 i = next_i;
 839                 res_count = next_res_count;
 840         }
 841
 842         rmb(); /* read res_count before the DMA data */
 843
 844         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 845         if (*buffer_offset > PAGE_SIZE) {
 846                 *buffer_offset = 0;
 847                 ar_context_abort(ctx, "corrupted descriptor");
 848         }
 849
 850         return i;
 851 }
 852
 853 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 854                                     unsigned int end_buffer_index,
 855                                     unsigned int end_buffer_offset)
 856 {
 857         unsigned int i;
 858
 859         i = ar_first_buffer_index(ctx);
 860         while (i != end_buffer_index) {
 861                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 862                                         ar_buffer_bus(ctx, i),
 863                                         PAGE_SIZE, DMA_FROM_DEVICE);
 864                 i = ar_next_buffer_index(i);
 865         }
 866         if (end_buffer_offset > 0)
 867                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 868                                         ar_buffer_bus(ctx, i),
 869                                         end_buffer_offset, DMA_FROM_DEVICE);
 870 }
 871
 872 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 873 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk)
 874 {
 875         return has_be_header_quirk ? (__force __u32)value : le32_to_cpu(value);
 876 }
 877
 878 static bool has_be_header_quirk(const struct fw_ohci *ohci)
 879 {
 880         return !!(ohci->quirks & QUIRK_BE_HEADERS);
 881 }
 882 #else
 883 static u32 cond_le32_to_cpu(__le32 value, bool has_be_header_quirk __maybe_unused)
 884 {
 885         return le32_to_cpu(value);
 886 }
 887
 888 static bool has_be_header_quirk(const struct fw_ohci *ohci)
 889 {
 890         return false;
 891 }
 892 #endif
 893
 894 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 895 {
 896         struct fw_ohci *ohci = ctx->ohci;
 897         struct fw_packet p;
 898         u32 status, length, tcode;
 899         int evt;
 900
 901         p.header[0] = cond_le32_to_cpu(buffer[0], has_be_header_quirk(ohci));
 902         p.header[1] = cond_le32_to_cpu(buffer[1], has_be_header_quirk(ohci));
 903         p.header[2] = cond_le32_to_cpu(buffer[2], has_be_header_quirk(ohci));
 904
 905         tcode = async_header_get_tcode(p.header);
 906         switch (tcode) {
 907         case TCODE_WRITE_QUADLET_REQUEST:
 908         case TCODE_READ_QUADLET_RESPONSE:
 909                 p.header[3] = (__force __u32) buffer[3];
 910                 p.header_length = 16;
 911                 p.payload_length = 0;
 912                 break;
 913
 914         case TCODE_READ_BLOCK_REQUEST :
 915                 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci));
 916                 p.header_length = 16;
 917                 p.payload_length = 0;
 918                 break;
 919
 920         case TCODE_WRITE_BLOCK_REQUEST:
 921         case TCODE_READ_BLOCK_RESPONSE:
 922         case TCODE_LOCK_REQUEST:
 923         case TCODE_LOCK_RESPONSE:
 924                 p.header[3] = cond_le32_to_cpu(buffer[3], has_be_header_quirk(ohci));
 925                 p.header_length = 16;
 926                 p.payload_length = async_header_get_data_length(p.header);
 927                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 928                         ar_context_abort(ctx, "invalid packet length");
 929                         return NULL;
 930                 }
 931                 break;
 932
 933         case TCODE_WRITE_RESPONSE:
 934         case TCODE_READ_QUADLET_REQUEST:
 935         case TCODE_LINK_INTERNAL:
 936                 p.header_length = 12;
 937                 p.payload_length = 0;
 938                 break;
 939
 940         default:
 941                 ar_context_abort(ctx, "invalid tcode");
 942                 return NULL;
 943         }
 944
 945         p.payload = (void *) buffer + p.header_length;
 946
 947         /* FIXME: What to do about evt_* errors? */
 948         length = (p.header_length + p.payload_length + 3) / 4;
 949         status = cond_le32_to_cpu(buffer[length], has_be_header_quirk(ohci));
 950         evt    = (status >> 16) & 0x1f;
 951
 952         p.ack        = evt - 16;
 953         p.speed      = (status >> 21) & 0x7;
 954         p.timestamp  = status & 0xffff;
 955         p.generation = ohci->request_generation;
 956
 957         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 958
 959         /*
 960          * Several controllers, notably from NEC and VIA, forget to
 961          * write ack_complete status at PHY packet reception.
 962          */
 963         if (evt == OHCI1394_evt_no_status && tcode == TCODE_LINK_INTERNAL)
 964                 p.ack = ACK_COMPLETE;
 965
 966         /*
 967          * The OHCI bus reset handler synthesizes a PHY packet with
 968          * the new generation number when a bus reset happens (see
 969          * section 8.4.2.3).  This helps us determine when a request
 970          * was received and make sure we send the response in the same
 971          * generation.  We only need this for requests; for responses
 972          * we use the unique tlabel for finding the matching
 973          * request.
 974          *
 975          * Alas some chips sometimes emit bus reset packets with a
 976          * wrong generation.  We set the correct generation for these
 977          * at a slightly incorrect time (in bus_reset_work).
 978          */
 979         if (evt == OHCI1394_evt_bus_reset) {
 980                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 981                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 982         } else if (ctx == &ohci->ar_request_ctx) {
 983                 fw_core_handle_request(&ohci->card, &p);
 984         } else {
 985                 fw_core_handle_response(&ohci->card, &p);
 986         }
 987
 988         return buffer + length + 1;
 989 }
 990
 991 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 992 {
 993         void *next;
 994
 995         while (p < end) {
 996                 next = handle_ar_packet(ctx, p);
 997                 if (!next)
 998                         return p;
 999                 p = next;
1000         }
1001
1002         return p;
1003 }
1004
1005 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
1006 {
1007         unsigned int i;
1008
1009         i = ar_first_buffer_index(ctx);
1010         while (i != end_buffer) {
1011                 dma_sync_single_for_device(ctx->ohci->card.device,
1012                                            ar_buffer_bus(ctx, i),
1013                                            PAGE_SIZE, DMA_FROM_DEVICE);
1014                 ar_context_link_page(ctx, i);
1015                 i = ar_next_buffer_index(i);
1016         }
1017 }
1018
1019 static void ar_context_tasklet(unsigned long data)
1020 {
1021         struct ar_context *ctx = (struct ar_context *)data;
1022         unsigned int end_buffer_index, end_buffer_offset;
1023         void *p, *end;
1024
1025         p = ctx->pointer;
1026         if (!p)
1027                 return;
1028
1029         end_buffer_index = ar_search_last_active_buffer(ctx,
1030                                                         &end_buffer_offset);
1031         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
1032         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
1033
1034         if (end_buffer_index < ar_first_buffer_index(ctx)) {
1035                 /*
1036                  * The filled part of the overall buffer wraps around; handle
1037                  * all packets up to the buffer end here.  If the last packet
1038                  * wraps around, its tail will be visible after the buffer end
1039                  * because the buffer start pages are mapped there again.
1040                  */
1041                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
1042                 p = handle_ar_packets(ctx, p, buffer_end);
1043                 if (p < buffer_end)
1044                         goto error;
1045                 /* adjust p to point back into the actual buffer */
1046                 p -= AR_BUFFERS * PAGE_SIZE;
1047         }
1048
1049         p = handle_ar_packets(ctx, p, end);
1050         if (p != end) {
1051                 if (p > end)
1052                         ar_context_abort(ctx, "inconsistent descriptor");
1053                 goto error;
1054         }
1055
1056         ctx->pointer = p;
1057         ar_recycle_buffers(ctx, end_buffer_index);
1058
1059         return;
1060
1061 error:
1062         ctx->pointer = NULL;
1063 }
1064
1065 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
1066                            unsigned int descriptors_offset, u32 regs)
1067 {
1068         struct device *dev = ohci->card.device;
1069         unsigned int i;
1070         dma_addr_t dma_addr;
1071         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
1072         struct descriptor *d;
1073
1074         ctx->regs        = regs;
1075         ctx->ohci        = ohci;
1076         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
1077
1078         for (i = 0; i < AR_BUFFERS; i++) {
1079                 ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr,
1080                                                 DMA_FROM_DEVICE, GFP_KERNEL);
1081                 if (!ctx->pages[i])
1082                         goto out_of_memory;
1083                 set_page_private(ctx->pages[i], dma_addr);
1084                 dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE,
1085                                            DMA_FROM_DEVICE);
1086         }
1087
1088         for (i = 0; i < AR_BUFFERS; i++)
1089                 pages[i]              = ctx->pages[i];
1090         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1091                 pages[AR_BUFFERS + i] = ctx->pages[i];
1092         ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
1093         if (!ctx->buffer)
1094                 goto out_of_memory;
1095
1096         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1097         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1098
1099         for (i = 0; i < AR_BUFFERS; i++) {
1100                 d = &ctx->descriptors[i];
1101                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1102                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1103                                                 DESCRIPTOR_STATUS |
1104                                                 DESCRIPTOR_BRANCH_ALWAYS);
1105                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1106                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1107                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1108         }
1109
1110         return 0;
1111
1112 out_of_memory:
1113         ar_context_release(ctx);
1114
1115         return -ENOMEM;
1116 }
1117
1118 static void ar_context_run(struct ar_context *ctx)
1119 {
1120         unsigned int i;
1121
1122         for (i = 0; i < AR_BUFFERS; i++)
1123                 ar_context_link_page(ctx, i);
1124
1125         ctx->pointer = ctx->buffer;
1126
1127         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1128         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1129 }
1130
1131 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1132 {
1133         __le16 branch;
1134
1135         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1136
1137         /* figure out which descriptor the branch address goes in */
1138         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1139                 return d;
1140         else
1141                 return d + z - 1;
1142 }
1143
1144 static void context_retire_descriptors(struct context *ctx)
1145 {
1146         struct descriptor *d, *last;
1147         u32 address;
1148         int z;
1149         struct descriptor_buffer *desc;
1150
1151         desc = list_entry(ctx->buffer_list.next,
1152                         struct descriptor_buffer, list);
1153         last = ctx->last;
1154         while (last->branch_address != 0) {
1155                 struct descriptor_buffer *old_desc = desc;
1156                 address = le32_to_cpu(last->branch_address);
1157                 z = address & 0xf;
1158                 address &= ~0xf;
1159                 ctx->current_bus = address;
1160
1161                 /* If the branch address points to a buffer outside of the
1162                  * current buffer, advance to the next buffer. */
1163                 if (address < desc->buffer_bus ||
1164                                 address >= desc->buffer_bus + desc->used)
1165                         desc = list_entry(desc->list.next,
1166                                         struct descriptor_buffer, list);
1167                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1168                 last = find_branch_descriptor(d, z);
1169
1170                 if (!ctx->callback(ctx, d, last))
1171                         break;
1172
1173                 if (old_desc != desc) {
1174                         // If we've advanced to the next buffer, move the previous buffer to the
1175                         // free list.
1176                         old_desc->used = 0;
1177                         guard(spinlock_irqsave)(&ctx->ohci->lock);
1178                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1179                 }
1180                 ctx->last = last;
1181         }
1182 }
1183
1184 static void context_tasklet(unsigned long data)
1185 {
1186         struct context *ctx = (struct context *) data;
1187
1188         context_retire_descriptors(ctx);
1189 }
1190
1191 static void ohci_isoc_context_work(struct work_struct *work)
1192 {
1193         struct fw_iso_context *base = container_of(work, struct fw_iso_context, work);
1194         struct iso_context *isoc_ctx = container_of(base, struct iso_context, base);
1195
1196         context_retire_descriptors(&isoc_ctx->context);
1197 }
1198
1199 /*
1200  * Allocate a new buffer and add it to the list of free buffers for this
1201  * context.  Must be called with ohci->lock held.
1202  */
1203 static int context_add_buffer(struct context *ctx)
1204 {
1205         struct descriptor_buffer *desc;
1206         dma_addr_t bus_addr;
1207         int offset;
1208
1209         /*
1210          * 16MB of descriptors should be far more than enough for any DMA
1211          * program.  This will catch run-away userspace or DoS attacks.
1212          */
1213         if (ctx->total_allocation >= 16*1024*1024)
1214                 return -ENOMEM;
1215
1216         desc = dmam_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, &bus_addr, GFP_ATOMIC);
1217         if (!desc)
1218                 return -ENOMEM;
1219
1220         offset = (void *)&desc->buffer - (void *)desc;
1221         /*
1222          * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
1223          * for descriptors, even 0x10-byte ones. This can cause page faults when
1224          * an IOMMU is in use and the oversized read crosses a page boundary.
1225          * Work around this by always leaving at least 0x10 bytes of padding.
1226          */
1227         desc->buffer_size = PAGE_SIZE - offset - 0x10;
1228         desc->buffer_bus = bus_addr + offset;
1229         desc->used = 0;
1230
1231         list_add_tail(&desc->list, &ctx->buffer_list);
1232         ctx->total_allocation += PAGE_SIZE;
1233
1234         return 0;
1235 }
1236
1237 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1238                         u32 regs, descriptor_callback_t callback)
1239 {
1240         ctx->ohci = ohci;
1241         ctx->regs = regs;
1242         ctx->total_allocation = 0;
1243
1244         INIT_LIST_HEAD(&ctx->buffer_list);
1245         if (context_add_buffer(ctx) < 0)
1246                 return -ENOMEM;
1247
1248         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1249                         struct descriptor_buffer, list);
1250
1251         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1252         ctx->callback = callback;
1253
1254         /*
1255          * We put a dummy descriptor in the buffer that has a NULL
1256          * branch address and looks like it's been sent.  That way we
1257          * have a descriptor to append DMA programs to.
1258          */
1259         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1260         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1261         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1262         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1263         ctx->last = ctx->buffer_tail->buffer;
1264         ctx->prev = ctx->buffer_tail->buffer;
1265         ctx->prev_z = 1;
1266
1267         return 0;
1268 }
1269
1270 static void context_release(struct context *ctx)
1271 {
1272         struct fw_card *card = &ctx->ohci->card;
1273         struct descriptor_buffer *desc, *tmp;
1274
1275         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) {
1276                 dmam_free_coherent(card->device, PAGE_SIZE, desc,
1277                                    desc->buffer_bus - ((void *)&desc->buffer - (void *)desc));
1278         }
1279 }
1280
1281 /* Must be called with ohci->lock held */
1282 static struct descriptor *context_get_descriptors(struct context *ctx,
1283                                                   int z, dma_addr_t *d_bus)
1284 {
1285         struct descriptor *d = NULL;
1286         struct descriptor_buffer *desc = ctx->buffer_tail;
1287
1288         if (z * sizeof(*d) > desc->buffer_size)
1289                 return NULL;
1290
1291         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1292                 /* No room for the descriptor in this buffer, so advance to the
1293                  * next one. */
1294
1295                 if (desc->list.next == &ctx->buffer_list) {
1296                         /* If there is no free buffer next in the list,
1297                          * allocate one. */
1298                         if (context_add_buffer(ctx) < 0)
1299                                 return NULL;
1300                 }
1301                 desc = list_entry(desc->list.next,
1302                                 struct descriptor_buffer, list);
1303                 ctx->buffer_tail = desc;
1304         }
1305
1306         d = desc->buffer + desc->used / sizeof(*d);
1307         memset(d, 0, z * sizeof(*d));
1308         *d_bus = desc->buffer_bus + desc->used;
1309
1310         return d;
1311 }
1312
1313 static void context_run(struct context *ctx, u32 extra)
1314 {
1315         struct fw_ohci *ohci = ctx->ohci;
1316
1317         reg_write(ohci, COMMAND_PTR(ctx->regs),
1318                   le32_to_cpu(ctx->last->branch_address));
1319         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1320         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1321         ctx->running = true;
1322         flush_writes(ohci);
1323 }
1324
1325 static void context_append(struct context *ctx,
1326                            struct descriptor *d, int z, int extra)
1327 {
1328         dma_addr_t d_bus;
1329         struct descriptor_buffer *desc = ctx->buffer_tail;
1330         struct descriptor *d_branch;
1331
1332         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1333
1334         desc->used += (z + extra) * sizeof(*d);
1335
1336         wmb(); /* finish init of new descriptors before branch_address update */
1337
1338         d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1339         d_branch->branch_address = cpu_to_le32(d_bus | z);
1340
1341         /*
1342          * VT6306 incorrectly checks only the single descriptor at the
1343          * CommandPtr when the wake bit is written, so if it's a
1344          * multi-descriptor block starting with an INPUT_MORE, put a copy of
1345          * the branch address in the first descriptor.
1346          *
1347          * Not doing this for transmit contexts since not sure how it interacts
1348          * with skip addresses.
1349          */
1350         if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1351             d_branch != ctx->prev &&
1352             (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1353              cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1354                 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1355         }
1356
1357         ctx->prev = d;
1358         ctx->prev_z = z;
1359 }
1360
1361 static void context_stop(struct context *ctx)
1362 {
1363         struct fw_ohci *ohci = ctx->ohci;
1364         u32 reg;
1365         int i;
1366
1367         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1368         ctx->running = false;
1369
1370         for (i = 0; i < 1000; i++) {
1371                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1372                 if ((reg & CONTEXT_ACTIVE) == 0)
1373                         return;
1374
1375                 if (i)
1376                         udelay(10);
1377         }
1378         ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
1379 }
1380
1381 struct driver_data {
1382         u8 inline_data[8];
1383         struct fw_packet *packet;
1384 };
1385
1386 /*
1387  * This function appends a packet to the DMA queue for transmission.
1388  * Must always be called with the ochi->lock held to ensure proper
1389  * generation handling and locking around packet queue manipulation.
1390  */
1391 static int at_context_queue_packet(struct context *ctx,
1392                                    struct fw_packet *packet)
1393 {
1394         struct fw_ohci *ohci = ctx->ohci;
1395         dma_addr_t d_bus, payload_bus;
1396         struct driver_data *driver_data;
1397         struct descriptor *d, *last;
1398         __le32 *header;
1399         int z, tcode;
1400
1401         d = context_get_descriptors(ctx, 4, &d_bus);
1402         if (d == NULL) {
1403                 packet->ack = RCODE_SEND_ERROR;
1404                 return -1;
1405         }
1406
1407         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1408         d[0].res_count = cpu_to_le16(packet->timestamp);
1409
1410         tcode = async_header_get_tcode(packet->header);
1411         header = (__le32 *) &d[1];
1412         switch (tcode) {
1413         case TCODE_WRITE_QUADLET_REQUEST:
1414         case TCODE_WRITE_BLOCK_REQUEST:
1415         case TCODE_WRITE_RESPONSE:
1416         case TCODE_READ_QUADLET_REQUEST:
1417         case TCODE_READ_BLOCK_REQUEST:
1418         case TCODE_READ_QUADLET_RESPONSE:
1419         case TCODE_READ_BLOCK_RESPONSE:
1420         case TCODE_LOCK_REQUEST:
1421         case TCODE_LOCK_RESPONSE:
1422                 ohci1394_at_data_set_src_bus_id(header, false);
1423                 ohci1394_at_data_set_speed(header, packet->speed);
1424                 ohci1394_at_data_set_tlabel(header, async_header_get_tlabel(packet->header));
1425                 ohci1394_at_data_set_retry(header, async_header_get_retry(packet->header));
1426                 ohci1394_at_data_set_tcode(header, tcode);
1427
1428                 ohci1394_at_data_set_destination_id(header,
1429                                                     async_header_get_destination(packet->header));
1430
1431                 if (ctx == &ctx->ohci->at_response_ctx) {
1432                         ohci1394_at_data_set_rcode(header, async_header_get_rcode(packet->header));
1433                 } else {
1434                         ohci1394_at_data_set_destination_offset(header,
1435                                                         async_header_get_offset(packet->header));
1436                 }
1437
1438                 if (tcode_is_block_packet(tcode))
1439                         header[3] = cpu_to_le32(packet->header[3]);
1440                 else
1441                         header[3] = (__force __le32) packet->header[3];
1442
1443                 d[0].req_count = cpu_to_le16(packet->header_length);
1444                 break;
1445         case TCODE_LINK_INTERNAL:
1446                 ohci1394_at_data_set_speed(header, packet->speed);
1447                 ohci1394_at_data_set_tcode(header, TCODE_LINK_INTERNAL);
1448
1449                 header[1] = cpu_to_le32(packet->header[1]);
1450                 header[2] = cpu_to_le32(packet->header[2]);
1451                 d[0].req_count = cpu_to_le16(12);
1452
1453                 if (is_ping_packet(&packet->header[1]))
1454                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1455                 break;
1456
1457         case TCODE_STREAM_DATA:
1458                 ohci1394_it_data_set_speed(header, packet->speed);
1459                 ohci1394_it_data_set_tag(header, isoc_header_get_tag(packet->header[0]));
1460                 ohci1394_it_data_set_channel(header, isoc_header_get_channel(packet->header[0]));
1461                 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA);
1462                 ohci1394_it_data_set_sync(header, isoc_header_get_sy(packet->header[0]));
1463
1464                 ohci1394_it_data_set_data_length(header, isoc_header_get_data_length(packet->header[0]));
1465
1466                 d[0].req_count = cpu_to_le16(8);
1467                 break;
1468
1469         default:
1470                 /* BUG(); */
1471                 packet->ack = RCODE_SEND_ERROR;
1472                 return -1;
1473         }
1474
1475         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1476         driver_data = (struct driver_data *) &d[3];
1477         driver_data->packet = packet;
1478         packet->driver_data = driver_data;
1479
1480         if (packet->payload_length > 0) {
1481                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1482                         payload_bus = dma_map_single(ohci->card.device,
1483                                                      packet->payload,
1484                                                      packet->payload_length,
1485                                                      DMA_TO_DEVICE);
1486                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1487                                 packet->ack = RCODE_SEND_ERROR;
1488                                 return -1;
1489                         }
1490                         packet->payload_bus     = payload_bus;
1491                         packet->payload_mapped  = true;
1492                 } else {
1493                         memcpy(driver_data->inline_data, packet->payload,
1494                                packet->payload_length);
1495                         payload_bus = d_bus + 3 * sizeof(*d);
1496                 }
1497
1498                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1499                 d[2].data_address = cpu_to_le32(payload_bus);
1500                 last = &d[2];
1501                 z = 3;
1502         } else {
1503                 last = &d[0];
1504                 z = 2;
1505         }
1506
1507         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1508                                      DESCRIPTOR_IRQ_ALWAYS |
1509                                      DESCRIPTOR_BRANCH_ALWAYS);
1510
1511         /* FIXME: Document how the locking works. */
1512         if (ohci->generation != packet->generation) {
1513                 if (packet->payload_mapped)
1514                         dma_unmap_single(ohci->card.device, payload_bus,
1515                                          packet->payload_length, DMA_TO_DEVICE);
1516                 packet->ack = RCODE_GENERATION;
1517                 return -1;
1518         }
1519
1520         context_append(ctx, d, z, 4 - z);
1521
1522         if (ctx->running)
1523                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1524         else
1525                 context_run(ctx, 0);
1526
1527         return 0;
1528 }
1529
1530 static void at_context_flush(struct context *ctx)
1531 {
1532         tasklet_disable(&ctx->tasklet);
1533
1534         ctx->flushing = true;
1535         context_tasklet((unsigned long)ctx);
1536         ctx->flushing = false;
1537
1538         tasklet_enable(&ctx->tasklet);
1539 }
1540
1541 static int handle_at_packet(struct context *context,
1542                             struct descriptor *d,
1543                             struct descriptor *last)
1544 {
1545         struct driver_data *driver_data;
1546         struct fw_packet *packet;
1547         struct fw_ohci *ohci = context->ohci;
1548         int evt;
1549
1550         if (last->transfer_status == 0 && !context->flushing)
1551                 /* This descriptor isn't done yet, stop iteration. */
1552                 return 0;
1553
1554         driver_data = (struct driver_data *) &d[3];
1555         packet = driver_data->packet;
1556         if (packet == NULL)
1557                 /* This packet was cancelled, just continue. */
1558                 return 1;
1559
1560         if (packet->payload_mapped)
1561                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1562                                  packet->payload_length, DMA_TO_DEVICE);
1563
1564         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1565         packet->timestamp = le16_to_cpu(last->res_count);
1566
1567         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1568
1569         switch (evt) {
1570         case OHCI1394_evt_timeout:
1571                 /* Async response transmit timed out. */
1572                 packet->ack = RCODE_CANCELLED;
1573                 break;
1574
1575         case OHCI1394_evt_flushed:
1576                 /*
1577                  * The packet was flushed should give same error as
1578                  * when we try to use a stale generation count.
1579                  */
1580                 packet->ack = RCODE_GENERATION;
1581                 break;
1582
1583         case OHCI1394_evt_missing_ack:
1584                 if (context->flushing)
1585                         packet->ack = RCODE_GENERATION;
1586                 else {
1587                         /*
1588                          * Using a valid (current) generation count, but the
1589                          * node is not on the bus or not sending acks.
1590                          */
1591                         packet->ack = RCODE_NO_ACK;
1592                 }
1593                 break;
1594
1595         case ACK_COMPLETE + 0x10:
1596         case ACK_PENDING + 0x10:
1597         case ACK_BUSY_X + 0x10:
1598         case ACK_BUSY_A + 0x10:
1599         case ACK_BUSY_B + 0x10:
1600         case ACK_DATA_ERROR + 0x10:
1601         case ACK_TYPE_ERROR + 0x10:
1602                 packet->ack = evt - 0x10;
1603                 break;
1604
1605         case OHCI1394_evt_no_status:
1606                 if (context->flushing) {
1607                         packet->ack = RCODE_GENERATION;
1608                         break;
1609                 }
1610                 fallthrough;
1611
1612         default:
1613                 packet->ack = RCODE_SEND_ERROR;
1614                 break;
1615         }
1616
1617         packet->callback(packet, &ohci->card, packet->ack);
1618
1619         return 1;
1620 }
1621
1622 static u32 get_cycle_time(struct fw_ohci *ohci);
1623
1624 static void handle_local_rom(struct fw_ohci *ohci,
1625                              struct fw_packet *packet, u32 csr)
1626 {
1627         struct fw_packet response;
1628         int tcode, length, i;
1629
1630         tcode = async_header_get_tcode(packet->header);
1631         if (tcode_is_block_packet(tcode))
1632                 length = async_header_get_data_length(packet->header);
1633         else
1634                 length = 4;
1635
1636         i = csr - CSR_CONFIG_ROM;
1637         if (i + length > CONFIG_ROM_SIZE) {
1638                 fw_fill_response(&response, packet->header,
1639                                  RCODE_ADDRESS_ERROR, NULL, 0);
1640         } else if (!tcode_is_read_request(tcode)) {
1641                 fw_fill_response(&response, packet->header,
1642                                  RCODE_TYPE_ERROR, NULL, 0);
1643         } else {
1644                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1645                                  (void *) ohci->config_rom + i, length);
1646         }
1647
1648         // Timestamping on behalf of the hardware.
1649         response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci));
1650         fw_core_handle_response(&ohci->card, &response);
1651 }
1652
1653 static void handle_local_lock(struct fw_ohci *ohci,
1654                               struct fw_packet *packet, u32 csr)
1655 {
1656         struct fw_packet response;
1657         int tcode, length, ext_tcode, sel, try;
1658         __be32 *payload, lock_old;
1659         u32 lock_arg, lock_data;
1660
1661         tcode = async_header_get_tcode(packet->header);
1662         length = async_header_get_data_length(packet->header);
1663         payload = packet->payload;
1664         ext_tcode = async_header_get_extended_tcode(packet->header);
1665
1666         if (tcode == TCODE_LOCK_REQUEST &&
1667             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1668                 lock_arg = be32_to_cpu(payload[0]);
1669                 lock_data = be32_to_cpu(payload[1]);
1670         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1671                 lock_arg = 0;
1672                 lock_data = 0;
1673         } else {
1674                 fw_fill_response(&response, packet->header,
1675                                  RCODE_TYPE_ERROR, NULL, 0);
1676                 goto out;
1677         }
1678
1679         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1680         reg_write(ohci, OHCI1394_CSRData, lock_data);
1681         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1682         reg_write(ohci, OHCI1394_CSRControl, sel);
1683
1684         for (try = 0; try < 20; try++)
1685                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1686                         lock_old = cpu_to_be32(reg_read(ohci,
1687                                                         OHCI1394_CSRData));
1688                         fw_fill_response(&response, packet->header,
1689                                          RCODE_COMPLETE,
1690                                          &lock_old, sizeof(lock_old));
1691                         goto out;
1692                 }
1693
1694         ohci_err(ohci, "swap not done (CSR lock timeout)\n");
1695         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1696
1697  out:
1698         // Timestamping on behalf of the hardware.
1699         response.timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci));
1700         fw_core_handle_response(&ohci->card, &response);
1701 }
1702
1703 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1704 {
1705         u64 offset, csr;
1706
1707         if (ctx == &ctx->ohci->at_request_ctx) {
1708                 packet->ack = ACK_PENDING;
1709                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1710         }
1711
1712         offset = async_header_get_offset(packet->header);
1713         csr = offset - CSR_REGISTER_BASE;
1714
1715         /* Handle config rom reads. */
1716         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1717                 handle_local_rom(ctx->ohci, packet, csr);
1718         else switch (csr) {
1719         case CSR_BUS_MANAGER_ID:
1720         case CSR_BANDWIDTH_AVAILABLE:
1721         case CSR_CHANNELS_AVAILABLE_HI:
1722         case CSR_CHANNELS_AVAILABLE_LO:
1723                 handle_local_lock(ctx->ohci, packet, csr);
1724                 break;
1725         default:
1726                 if (ctx == &ctx->ohci->at_request_ctx)
1727                         fw_core_handle_request(&ctx->ohci->card, packet);
1728                 else
1729                         fw_core_handle_response(&ctx->ohci->card, packet);
1730                 break;
1731         }
1732
1733         if (ctx == &ctx->ohci->at_response_ctx) {
1734                 packet->ack = ACK_COMPLETE;
1735                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1736         }
1737 }
1738
1739 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1740 {
1741         unsigned long flags;
1742         int ret;
1743
1744         spin_lock_irqsave(&ctx->ohci->lock, flags);
1745
1746         if (async_header_get_destination(packet->header) == ctx->ohci->node_id &&
1747             ctx->ohci->generation == packet->generation) {
1748                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1749
1750                 // Timestamping on behalf of the hardware.
1751                 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci));
1752
1753                 handle_local_request(ctx, packet);
1754                 return;
1755         }
1756
1757         ret = at_context_queue_packet(ctx, packet);
1758         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1759
1760         if (ret < 0) {
1761                 // Timestamping on behalf of the hardware.
1762                 packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ctx->ohci));
1763
1764                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1765         }
1766 }
1767
1768 static void detect_dead_context(struct fw_ohci *ohci,
1769                                 const char *name, unsigned int regs)
1770 {
1771         u32 ctl;
1772
1773         ctl = reg_read(ohci, CONTROL_SET(regs));
1774         if (ctl & CONTEXT_DEAD)
1775                 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
1776                         name, evts[ctl & 0x1f]);
1777 }
1778
1779 static void handle_dead_contexts(struct fw_ohci *ohci)
1780 {
1781         unsigned int i;
1782         char name[8];
1783
1784         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1785         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1786         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1787         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1788         for (i = 0; i < 32; ++i) {
1789                 if (!(ohci->it_context_support & (1 << i)))
1790                         continue;
1791                 sprintf(name, "IT%u", i);
1792                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1793         }
1794         for (i = 0; i < 32; ++i) {
1795                 if (!(ohci->ir_context_support & (1 << i)))
1796                         continue;
1797                 sprintf(name, "IR%u", i);
1798                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1799         }
1800         /* TODO: maybe try to flush and restart the dead contexts */
1801 }
1802
1803 static u32 cycle_timer_ticks(u32 cycle_timer)
1804 {
1805         u32 ticks;
1806
1807         ticks = cycle_timer & 0xfff;
1808         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1809         ticks += (3072 * 8000) * (cycle_timer >> 25);
1810
1811         return ticks;
1812 }
1813
1814 /*
1815  * Some controllers exhibit one or more of the following bugs when updating the
1816  * iso cycle timer register:
1817  *  - When the lowest six bits are wrapping around to zero, a read that happens
1818  *    at the same time will return garbage in the lowest ten bits.
1819  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1820  *    not incremented for about 60 ns.
1821  *  - Occasionally, the entire register reads zero.
1822  *
1823  * To catch these, we read the register three times and ensure that the
1824  * difference between each two consecutive reads is approximately the same, i.e.
1825  * less than twice the other.  Furthermore, any negative difference indicates an
1826  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1827  * execute, so we have enough precision to compute the ratio of the differences.)
1828  */
1829 static u32 get_cycle_time(struct fw_ohci *ohci)
1830 {
1831         u32 c0, c1, c2;
1832         u32 t0, t1, t2;
1833         s32 diff01, diff12;
1834         int i;
1835
1836         if (has_reboot_by_cycle_timer_read_quirk(ohci))
1837                 return 0;
1838
1839         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1840
1841         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1842                 i = 0;
1843                 c1 = c2;
1844                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1845                 do {
1846                         c0 = c1;
1847                         c1 = c2;
1848                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1849                         t0 = cycle_timer_ticks(c0);
1850                         t1 = cycle_timer_ticks(c1);
1851                         t2 = cycle_timer_ticks(c2);
1852                         diff01 = t1 - t0;
1853                         diff12 = t2 - t1;
1854                 } while ((diff01 <= 0 || diff12 <= 0 ||
1855                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1856                          && i++ < 20);
1857         }
1858
1859         return c2;
1860 }
1861
1862 /*
1863  * This function has to be called at least every 64 seconds.  The bus_time
1864  * field stores not only the upper 25 bits of the BUS_TIME register but also
1865  * the most significant bit of the cycle timer in bit 6 so that we can detect
1866  * changes in this bit.
1867  */
1868 static u32 update_bus_time(struct fw_ohci *ohci)
1869 {
1870         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1871
1872         if (unlikely(!ohci->bus_time_running)) {
1873                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1874                 ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) |
1875                                  (cycle_time_seconds & 0x40);
1876                 ohci->bus_time_running = true;
1877         }
1878
1879         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1880                 ohci->bus_time += 0x40;
1881
1882         return ohci->bus_time | cycle_time_seconds;
1883 }
1884
1885 static int get_status_for_port(struct fw_ohci *ohci, int port_index,
1886                                enum phy_packet_self_id_port_status *status)
1887 {
1888         int reg;
1889
1890         scoped_guard(mutex, &ohci->phy_reg_mutex) {
1891                 reg = write_phy_reg(ohci, 7, port_index);
1892                 if (reg < 0)
1893                         return reg;
1894
1895                 reg = read_phy_reg(ohci, 8);
1896                 if (reg < 0)
1897                         return reg;
1898         }
1899
1900         switch (reg & 0x0f) {
1901         case 0x06:
1902                 // is child node (connected to parent node)
1903                 *status = PHY_PACKET_SELF_ID_PORT_STATUS_PARENT;
1904                 break;
1905         case 0x0e:
1906                 // is parent node (connected to child node)
1907                 *status = PHY_PACKET_SELF_ID_PORT_STATUS_CHILD;
1908                 break;
1909         default:
1910                 // not connected
1911                 *status = PHY_PACKET_SELF_ID_PORT_STATUS_NCONN;
1912                 break;
1913         }
1914
1915         return 0;
1916 }
1917
1918 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1919         int self_id_count)
1920 {
1921         unsigned int left_phy_id = phy_packet_self_id_get_phy_id(self_id);
1922         int i;
1923
1924         for (i = 0; i < self_id_count; i++) {
1925                 u32 entry = ohci->self_id_buffer[i];
1926                 unsigned int right_phy_id = phy_packet_self_id_get_phy_id(entry);
1927
1928                 if (left_phy_id == right_phy_id)
1929                         return -1;
1930                 if (left_phy_id < right_phy_id)
1931                         return i;
1932         }
1933         return i;
1934 }
1935
1936 static int detect_initiated_reset(struct fw_ohci *ohci, bool *is_initiated_reset)
1937 {
1938         int reg;
1939
1940         guard(mutex)(&ohci->phy_reg_mutex);
1941
1942         // Select page 7
1943         reg = write_phy_reg(ohci, 7, 0xe0);
1944         if (reg < 0)
1945                 return reg;
1946
1947         reg = read_phy_reg(ohci, 8);
1948         if (reg < 0)
1949                 return reg;
1950
1951         // set PMODE bit
1952         reg |= 0x40;
1953         reg = write_phy_reg(ohci, 8, reg);
1954         if (reg < 0)
1955                 return reg;
1956
1957         // read register 12
1958         reg = read_phy_reg(ohci, 12);
1959         if (reg < 0)
1960                 return reg;
1961
1962         // bit 3 indicates "initiated reset"
1963         *is_initiated_reset = !!((reg & 0x08) == 0x08);
1964
1965         return 0;
1966 }
1967
1968 /*
1969  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1970  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1971  * Construct the selfID from phy register contents.
1972  */
1973 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1974 {
1975         int reg, i, pos, err;
1976         bool is_initiated_reset;
1977         u32 self_id = 0;
1978
1979         // link active 1, speed 3, bridge 0, contender 1, more packets 0.
1980         phy_packet_set_packet_identifier(&self_id, PHY_PACKET_PACKET_IDENTIFIER_SELF_ID);
1981         phy_packet_self_id_zero_set_link_active(&self_id, true);
1982         phy_packet_self_id_zero_set_scode(&self_id, SCODE_800);
1983         phy_packet_self_id_zero_set_contender(&self_id, true);
1984
1985         reg = reg_read(ohci, OHCI1394_NodeID);
1986         if (!(reg & OHCI1394_NodeID_idValid)) {
1987                 ohci_notice(ohci,
1988                             "node ID not valid, new bus reset in progress\n");
1989                 return -EBUSY;
1990         }
1991         phy_packet_self_id_set_phy_id(&self_id, reg & 0x3f);
1992
1993         reg = ohci_read_phy_reg(&ohci->card, 4);
1994         if (reg < 0)
1995                 return reg;
1996         phy_packet_self_id_zero_set_power_class(&self_id, reg & 0x07);
1997
1998         reg = ohci_read_phy_reg(&ohci->card, 1);
1999         if (reg < 0)
2000                 return reg;
2001         phy_packet_self_id_zero_set_gap_count(&self_id, reg & 0x3f);
2002
2003         for (i = 0; i < 3; i++) {
2004                 enum phy_packet_self_id_port_status status;
2005
2006                 err = get_status_for_port(ohci, i, &status);
2007                 if (err < 0)
2008                         return err;
2009
2010                 self_id_sequence_set_port_status(&self_id, 1, i, status);
2011         }
2012
2013         err = detect_initiated_reset(ohci, &is_initiated_reset);
2014         if (err < 0)
2015                 return err;
2016         phy_packet_self_id_zero_set_initiated_reset(&self_id, is_initiated_reset);
2017
2018         pos = get_self_id_pos(ohci, self_id, self_id_count);
2019         if (pos >= 0) {
2020                 memmove(&(ohci->self_id_buffer[pos+1]),
2021                         &(ohci->self_id_buffer[pos]),
2022                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
2023                 ohci->self_id_buffer[pos] = self_id;
2024                 self_id_count++;
2025         }
2026         return self_id_count;
2027 }
2028
2029 static void bus_reset_work(struct work_struct *work)
2030 {
2031         struct fw_ohci *ohci =
2032                 container_of(work, struct fw_ohci, bus_reset_work);
2033         int self_id_count, generation, new_generation, i, j;
2034         u32 reg, quadlet;
2035         void *free_rom = NULL;
2036         dma_addr_t free_rom_bus = 0;
2037         bool is_new_root;
2038
2039         reg = reg_read(ohci, OHCI1394_NodeID);
2040         if (!(reg & OHCI1394_NodeID_idValid)) {
2041                 ohci_notice(ohci,
2042                             "node ID not valid, new bus reset in progress\n");
2043                 return;
2044         }
2045         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
2046                 ohci_notice(ohci, "malconfigured bus\n");
2047                 return;
2048         }
2049         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
2050                                OHCI1394_NodeID_nodeNumber);
2051
2052         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
2053         if (!(ohci->is_root && is_new_root))
2054                 reg_write(ohci, OHCI1394_LinkControlSet,
2055                           OHCI1394_LinkControl_cycleMaster);
2056         ohci->is_root = is_new_root;
2057
2058         reg = reg_read(ohci, OHCI1394_SelfIDCount);
2059         if (ohci1394_self_id_count_is_error(reg)) {
2060                 ohci_notice(ohci, "self ID receive error\n");
2061                 return;
2062         }
2063         /*
2064          * The count in the SelfIDCount register is the number of
2065          * bytes in the self ID receive buffer.  Since we also receive
2066          * the inverted quadlets and a header quadlet, we shift one
2067          * bit extra to get the actual number of self IDs.
2068          */
2069         self_id_count = ohci1394_self_id_count_get_size(reg) >> 1;
2070
2071         if (self_id_count > 252) {
2072                 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
2073                 return;
2074         }
2075
2076         quadlet = cond_le32_to_cpu(ohci->self_id[0], has_be_header_quirk(ohci));
2077         generation = ohci1394_self_id_receive_q0_get_generation(quadlet);
2078         rmb();
2079
2080         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
2081                 u32 id  = cond_le32_to_cpu(ohci->self_id[i], has_be_header_quirk(ohci));
2082                 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1], has_be_header_quirk(ohci));
2083
2084                 if (id != ~id2) {
2085                         /*
2086                          * If the invalid data looks like a cycle start packet,
2087                          * it's likely to be the result of the cycle master
2088                          * having a wrong gap count.  In this case, the self IDs
2089                          * so far are valid and should be processed so that the
2090                          * bus manager can then correct the gap count.
2091                          */
2092                         if (id == 0xffff008f) {
2093                                 ohci_notice(ohci, "ignoring spurious self IDs\n");
2094                                 self_id_count = j;
2095                                 break;
2096                         }
2097
2098                         ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
2099                                     j, self_id_count, id, id2);
2100                         return;
2101                 }
2102                 ohci->self_id_buffer[j] = id;
2103         }
2104
2105         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2106                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
2107                 if (self_id_count < 0) {
2108                         ohci_notice(ohci,
2109                                     "could not construct local self ID\n");
2110                         return;
2111                 }
2112         }
2113
2114         if (self_id_count == 0) {
2115                 ohci_notice(ohci, "no self IDs\n");
2116                 return;
2117         }
2118         rmb();
2119
2120         /*
2121          * Check the consistency of the self IDs we just read.  The
2122          * problem we face is that a new bus reset can start while we
2123          * read out the self IDs from the DMA buffer. If this happens,
2124          * the DMA buffer will be overwritten with new self IDs and we
2125          * will read out inconsistent data.  The OHCI specification
2126          * (section 11.2) recommends a technique similar to
2127          * linux/seqlock.h, where we remember the generation of the
2128          * self IDs in the buffer before reading them out and compare
2129          * it to the current generation after reading them out.  If
2130          * the two generations match we know we have a consistent set
2131          * of self IDs.
2132          */
2133
2134         reg = reg_read(ohci, OHCI1394_SelfIDCount);
2135         new_generation = ohci1394_self_id_count_get_generation(reg);
2136         if (new_generation != generation) {
2137                 ohci_notice(ohci, "new bus reset, discarding self ids\n");
2138                 return;
2139         }
2140
2141         // FIXME: Document how the locking works.
2142         scoped_guard(spinlock_irq, &ohci->lock) {
2143                 ohci->generation = -1; // prevent AT packet queueing
2144                 context_stop(&ohci->at_request_ctx);
2145                 context_stop(&ohci->at_response_ctx);
2146         }
2147
2148         /*
2149          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2150          * packets in the AT queues and software needs to drain them.
2151          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2152          */
2153         at_context_flush(&ohci->at_request_ctx);
2154         at_context_flush(&ohci->at_response_ctx);
2155
2156         scoped_guard(spinlock_irq, &ohci->lock) {
2157                 ohci->generation = generation;
2158                 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2159                 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2160
2161                 if (ohci->quirks & QUIRK_RESET_PACKET)
2162                         ohci->request_generation = generation;
2163
2164                 // This next bit is unrelated to the AT context stuff but we have to do it under the
2165                 // spinlock also. If a new config rom was set up before this reset, the old one is
2166                 // now no longer in use and we can free it. Update the config rom pointers to point
2167                 // to the current config rom and clear the next_config_rom pointer so a new update
2168                 // can take place.
2169                 if (ohci->next_config_rom != NULL) {
2170                         if (ohci->next_config_rom != ohci->config_rom) {
2171                                 free_rom      = ohci->config_rom;
2172                                 free_rom_bus  = ohci->config_rom_bus;
2173                         }
2174                         ohci->config_rom      = ohci->next_config_rom;
2175                         ohci->config_rom_bus  = ohci->next_config_rom_bus;
2176                         ohci->next_config_rom = NULL;
2177
2178                         // Restore config_rom image and manually update config_rom registers.
2179                         // Writing the header quadlet will indicate that the config rom is ready,
2180                         // so we do that last.
2181                         reg_write(ohci, OHCI1394_BusOptions, be32_to_cpu(ohci->config_rom[2]));
2182                         ohci->config_rom[0] = ohci->next_header;
2183                         reg_write(ohci, OHCI1394_ConfigROMhdr, be32_to_cpu(ohci->next_header));
2184                 }
2185
2186                 if (param_remote_dma) {
2187                         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2188                         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2189                 }
2190         }
2191
2192         if (free_rom)
2193                 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, free_rom, free_rom_bus);
2194
2195         log_selfids(ohci, generation, self_id_count);
2196
2197         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
2198                                  self_id_count, ohci->self_id_buffer,
2199                                  ohci->csr_state_setclear_abdicate);
2200         ohci->csr_state_setclear_abdicate = false;
2201 }
2202
2203 static irqreturn_t irq_handler(int irq, void *data)
2204 {
2205         struct fw_ohci *ohci = data;
2206         u32 event, iso_event;
2207         int i;
2208
2209         event = reg_read(ohci, OHCI1394_IntEventClear);
2210
2211         if (!event || !~event)
2212                 return IRQ_NONE;
2213
2214         if (unlikely(param_debug > 0)) {
2215                 dev_notice_ratelimited(ohci->card.device,
2216                                        "The debug parameter is superseded by tracepoints events, and deprecated.");
2217         }
2218
2219         /*
2220          * busReset and postedWriteErr events must not be cleared yet
2221          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2222          */
2223         reg_write(ohci, OHCI1394_IntEventClear,
2224                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2225         trace_irqs(ohci->card.index, event);
2226         log_irqs(ohci, event);
2227         // The flag is masked again at bus_reset_work() scheduled by selfID event.
2228         if (event & OHCI1394_busReset)
2229                 reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_busReset);
2230
2231         if (event & OHCI1394_selfIDComplete) {
2232                 if (trace_self_id_complete_enabled()) {
2233                         u32 reg = reg_read(ohci, OHCI1394_SelfIDCount);
2234
2235                         trace_self_id_complete(ohci->card.index, reg, ohci->self_id,
2236                                                has_be_header_quirk(ohci));
2237                 }
2238                 queue_work(selfid_workqueue, &ohci->bus_reset_work);
2239         }
2240
2241         if (event & OHCI1394_RQPkt)
2242                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2243
2244         if (event & OHCI1394_RSPkt)
2245                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2246
2247         if (event & OHCI1394_reqTxComplete)
2248                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2249
2250         if (event & OHCI1394_respTxComplete)
2251                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2252
2253         if (event & OHCI1394_isochRx) {
2254                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2255                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2256
2257                 while (iso_event) {
2258                         i = ffs(iso_event) - 1;
2259                         fw_iso_context_schedule_flush_completions(&ohci->ir_context_list[i].base);
2260                         iso_event &= ~(1 << i);
2261                 }
2262         }
2263
2264         if (event & OHCI1394_isochTx) {
2265                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2266                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2267
2268                 while (iso_event) {
2269                         i = ffs(iso_event) - 1;
2270                         fw_iso_context_schedule_flush_completions(&ohci->it_context_list[i].base);
2271                         iso_event &= ~(1 << i);
2272                 }
2273         }
2274
2275         if (unlikely(event & OHCI1394_regAccessFail))
2276                 ohci_err(ohci, "register access failure\n");
2277
2278         if (unlikely(event & OHCI1394_postedWriteErr)) {
2279                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2280                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2281                 reg_write(ohci, OHCI1394_IntEventClear,
2282                           OHCI1394_postedWriteErr);
2283                 dev_err_ratelimited(ohci->card.device, "PCI posted write error\n");
2284         }
2285
2286         if (unlikely(event & OHCI1394_cycleTooLong)) {
2287                 dev_notice_ratelimited(ohci->card.device, "isochronous cycle too long\n");
2288                 reg_write(ohci, OHCI1394_LinkControlSet,
2289                           OHCI1394_LinkControl_cycleMaster);
2290         }
2291
2292         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2293                 /*
2294                  * We need to clear this event bit in order to make
2295                  * cycleMatch isochronous I/O work.  In theory we should
2296                  * stop active cycleMatch iso contexts now and restart
2297                  * them at least two cycles later.  (FIXME?)
2298                  */
2299                 dev_notice_ratelimited(ohci->card.device, "isochronous cycle inconsistent\n");
2300         }
2301
2302         if (unlikely(event & OHCI1394_unrecoverableError))
2303                 handle_dead_contexts(ohci);
2304
2305         if (event & OHCI1394_cycle64Seconds) {
2306                 guard(spinlock)(&ohci->lock);
2307                 update_bus_time(ohci);
2308         } else
2309                 flush_writes(ohci);
2310
2311         return IRQ_HANDLED;
2312 }
2313
2314 static int software_reset(struct fw_ohci *ohci)
2315 {
2316         u32 val;
2317         int i;
2318
2319         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2320         for (i = 0; i < 500; i++) {
2321                 val = reg_read(ohci, OHCI1394_HCControlSet);
2322                 if (!~val)
2323                         return -ENODEV; /* Card was ejected. */
2324
2325                 if (!(val & OHCI1394_HCControl_softReset))
2326                         return 0;
2327
2328                 msleep(1);
2329         }
2330
2331         return -EBUSY;
2332 }
2333
2334 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2335 {
2336         size_t size = length * 4;
2337
2338         memcpy(dest, src, size);
2339         if (size < CONFIG_ROM_SIZE)
2340                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2341 }
2342
2343 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2344 {
2345         bool enable_1394a;
2346         int ret, clear, set, offset;
2347
2348         /* Check if the driver should configure link and PHY. */
2349         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2350               OHCI1394_HCControl_programPhyEnable))
2351                 return 0;
2352
2353         /* Paranoia: check whether the PHY supports 1394a, too. */
2354         enable_1394a = false;
2355         ret = read_phy_reg(ohci, 2);
2356         if (ret < 0)
2357                 return ret;
2358         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2359                 ret = read_paged_phy_reg(ohci, 1, 8);
2360                 if (ret < 0)
2361                         return ret;
2362                 if (ret >= 1)
2363                         enable_1394a = true;
2364         }
2365
2366         if (ohci->quirks & QUIRK_NO_1394A)
2367                 enable_1394a = false;
2368
2369         /* Configure PHY and link consistently. */
2370         if (enable_1394a) {
2371                 clear = 0;
2372                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2373         } else {
2374                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2375                 set = 0;
2376         }
2377         ret = update_phy_reg(ohci, 5, clear, set);
2378         if (ret < 0)
2379                 return ret;
2380
2381         if (enable_1394a)
2382                 offset = OHCI1394_HCControlSet;
2383         else
2384                 offset = OHCI1394_HCControlClear;
2385         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2386
2387         /* Clean up: configuration has been taken care of. */
2388         reg_write(ohci, OHCI1394_HCControlClear,
2389                   OHCI1394_HCControl_programPhyEnable);
2390
2391         return 0;
2392 }
2393
2394 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2395 {
2396         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2397         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2398         int reg, i;
2399
2400         reg = read_phy_reg(ohci, 2);
2401         if (reg < 0)
2402                 return reg;
2403         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2404                 return 0;
2405
2406         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2407                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2408                 if (reg < 0)
2409                         return reg;
2410                 if (reg != id[i])
2411                         return 0;
2412         }
2413         return 1;
2414 }
2415
2416 static int ohci_enable(struct fw_card *card,
2417                        const __be32 *config_rom, size_t length)
2418 {
2419         struct fw_ohci *ohci = fw_ohci(card);
2420         u32 lps, version, irqs;
2421         int i, ret;
2422
2423         ret = software_reset(ohci);
2424         if (ret < 0) {
2425                 ohci_err(ohci, "failed to reset ohci card\n");
2426                 return ret;
2427         }
2428
2429         /*
2430          * Now enable LPS, which we need in order to start accessing
2431          * most of the registers.  In fact, on some cards (ALI M5251),
2432          * accessing registers in the SClk domain without LPS enabled
2433          * will lock up the machine.  Wait 50msec to make sure we have
2434          * full link enabled.  However, with some cards (well, at least
2435          * a JMicron PCIe card), we have to try again sometimes.
2436          *
2437          * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2438          * cannot actually use the phy at that time.  These need tens of
2439          * millisecods pause between LPS write and first phy access too.
2440          */
2441
2442         reg_write(ohci, OHCI1394_HCControlSet,
2443                   OHCI1394_HCControl_LPS |
2444                   OHCI1394_HCControl_postedWriteEnable);
2445         flush_writes(ohci);
2446
2447         for (lps = 0, i = 0; !lps && i < 3; i++) {
2448                 msleep(50);
2449                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2450                       OHCI1394_HCControl_LPS;
2451         }
2452
2453         if (!lps) {
2454                 ohci_err(ohci, "failed to set Link Power Status\n");
2455                 return -EIO;
2456         }
2457
2458         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2459                 ret = probe_tsb41ba3d(ohci);
2460                 if (ret < 0)
2461                         return ret;
2462                 if (ret)
2463                         ohci_notice(ohci, "local TSB41BA3D phy\n");
2464                 else
2465                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2466         }
2467
2468         reg_write(ohci, OHCI1394_HCControlClear,
2469                   OHCI1394_HCControl_noByteSwapData);
2470
2471         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2472         reg_write(ohci, OHCI1394_LinkControlSet,
2473                   OHCI1394_LinkControl_cycleTimerEnable |
2474                   OHCI1394_LinkControl_cycleMaster);
2475
2476         reg_write(ohci, OHCI1394_ATRetries,
2477                   OHCI1394_MAX_AT_REQ_RETRIES |
2478                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2479                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2480                   (200 << 16));
2481
2482         ohci->bus_time_running = false;
2483
2484         for (i = 0; i < 32; i++)
2485                 if (ohci->ir_context_support & (1 << i))
2486                         reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2487                                   IR_CONTEXT_MULTI_CHANNEL_MODE);
2488
2489         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2490         if (version >= OHCI_VERSION_1_1) {
2491                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2492                           0xfffffffe);
2493                 card->broadcast_channel_auto_allocated = true;
2494         }
2495
2496         /* Get implemented bits of the priority arbitration request counter. */
2497         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2498         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2499         reg_write(ohci, OHCI1394_FairnessControl, 0);
2500         card->priority_budget_implemented = ohci->pri_req_max != 0;
2501
2502         reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2503         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2504         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2505
2506         ret = configure_1394a_enhancements(ohci);
2507         if (ret < 0)
2508                 return ret;
2509
2510         /* Activate link_on bit and contender bit in our self ID packets.*/
2511         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2512         if (ret < 0)
2513                 return ret;
2514
2515         /*
2516          * When the link is not yet enabled, the atomic config rom
2517          * update mechanism described below in ohci_set_config_rom()
2518          * is not active.  We have to update ConfigRomHeader and
2519          * BusOptions manually, and the write to ConfigROMmap takes
2520          * effect immediately.  We tie this to the enabling of the
2521          * link, so we have a valid config rom before enabling - the
2522          * OHCI requires that ConfigROMhdr and BusOptions have valid
2523          * values before enabling.
2524          *
2525          * However, when the ConfigROMmap is written, some controllers
2526          * always read back quadlets 0 and 2 from the config rom to
2527          * the ConfigRomHeader and BusOptions registers on bus reset.
2528          * They shouldn't do that in this initial case where the link
2529          * isn't enabled.  This means we have to use the same
2530          * workaround here, setting the bus header to 0 and then write
2531          * the right values in the bus reset tasklet.
2532          */
2533
2534         if (config_rom) {
2535                 ohci->next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2536                                                             &ohci->next_config_rom_bus, GFP_KERNEL);
2537                 if (ohci->next_config_rom == NULL)
2538                         return -ENOMEM;
2539
2540                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2541         } else {
2542                 /*
2543                  * In the suspend case, config_rom is NULL, which
2544                  * means that we just reuse the old config rom.
2545                  */
2546                 ohci->next_config_rom = ohci->config_rom;
2547                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2548         }
2549
2550         ohci->next_header = ohci->next_config_rom[0];
2551         ohci->next_config_rom[0] = 0;
2552         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2553         reg_write(ohci, OHCI1394_BusOptions,
2554                   be32_to_cpu(ohci->next_config_rom[2]));
2555         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2556
2557         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2558
2559         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2560                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2561                 OHCI1394_isochTx | OHCI1394_isochRx |
2562                 OHCI1394_postedWriteErr |
2563                 OHCI1394_selfIDComplete |
2564                 OHCI1394_regAccessFail |
2565                 OHCI1394_cycleInconsistent |
2566                 OHCI1394_unrecoverableError |
2567                 OHCI1394_cycleTooLong |
2568                 OHCI1394_masterIntEnable |
2569                 OHCI1394_busReset;
2570         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2571
2572         reg_write(ohci, OHCI1394_HCControlSet,
2573                   OHCI1394_HCControl_linkEnable |
2574                   OHCI1394_HCControl_BIBimageValid);
2575
2576         reg_write(ohci, OHCI1394_LinkControlSet,
2577                   OHCI1394_LinkControl_rcvSelfID |
2578                   OHCI1394_LinkControl_rcvPhyPkt);
2579
2580         ar_context_run(&ohci->ar_request_ctx);
2581         ar_context_run(&ohci->ar_response_ctx);
2582
2583         flush_writes(ohci);
2584
2585         /* We are ready to go, reset bus to finish initialization. */
2586         fw_schedule_bus_reset(&ohci->card, false, true);
2587
2588         return 0;
2589 }
2590
2591 static int ohci_set_config_rom(struct fw_card *card,
2592                                const __be32 *config_rom, size_t length)
2593 {
2594         struct fw_ohci *ohci;
2595         __be32 *next_config_rom;
2596         dma_addr_t next_config_rom_bus;
2597
2598         ohci = fw_ohci(card);
2599
2600         /*
2601          * When the OHCI controller is enabled, the config rom update
2602          * mechanism is a bit tricky, but easy enough to use.  See
2603          * section 5.5.6 in the OHCI specification.
2604          *
2605          * The OHCI controller caches the new config rom address in a
2606          * shadow register (ConfigROMmapNext) and needs a bus reset
2607          * for the changes to take place.  When the bus reset is
2608          * detected, the controller loads the new values for the
2609          * ConfigRomHeader and BusOptions registers from the specified
2610          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2611          * shadow register. All automatically and atomically.
2612          *
2613          * Now, there's a twist to this story.  The automatic load of
2614          * ConfigRomHeader and BusOptions doesn't honor the
2615          * noByteSwapData bit, so with a be32 config rom, the
2616          * controller will load be32 values in to these registers
2617          * during the atomic update, even on little endian
2618          * architectures.  The workaround we use is to put a 0 in the
2619          * header quadlet; 0 is endian agnostic and means that the
2620          * config rom isn't ready yet.  In the bus reset tasklet we
2621          * then set up the real values for the two registers.
2622          *
2623          * We use ohci->lock to avoid racing with the code that sets
2624          * ohci->next_config_rom to NULL (see bus_reset_work).
2625          */
2626
2627         next_config_rom = dmam_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2628                                               &next_config_rom_bus, GFP_KERNEL);
2629         if (next_config_rom == NULL)
2630                 return -ENOMEM;
2631
2632         scoped_guard(spinlock_irq, &ohci->lock) {
2633                 // If there is not an already pending config_rom update, push our new allocation
2634                 // into the ohci->next_config_rom and then mark the local variable as null so that
2635                 // we won't deallocate the new buffer.
2636                 //
2637                 // OTOH, if there is a pending config_rom update, just use that buffer with the new
2638                 // config_rom data, and let this routine free the unused DMA allocation.
2639                 if (ohci->next_config_rom == NULL) {
2640                         ohci->next_config_rom = next_config_rom;
2641                         ohci->next_config_rom_bus = next_config_rom_bus;
2642                         next_config_rom = NULL;
2643                 }
2644
2645                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2646
2647                 ohci->next_header = config_rom[0];
2648                 ohci->next_config_rom[0] = 0;
2649
2650                 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2651         }
2652
2653         /* If we didn't use the DMA allocation, delete it. */
2654         if (next_config_rom != NULL) {
2655                 dmam_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, next_config_rom,
2656                                    next_config_rom_bus);
2657         }
2658
2659         /*
2660          * Now initiate a bus reset to have the changes take
2661          * effect. We clean up the old config rom memory and DMA
2662          * mappings in the bus reset tasklet, since the OHCI
2663          * controller could need to access it before the bus reset
2664          * takes effect.
2665          */
2666
2667         fw_schedule_bus_reset(&ohci->card, true, true);
2668
2669         return 0;
2670 }
2671
2672 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2673 {
2674         struct fw_ohci *ohci = fw_ohci(card);
2675
2676         at_context_transmit(&ohci->at_request_ctx, packet);
2677 }
2678
2679 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2680 {
2681         struct fw_ohci *ohci = fw_ohci(card);
2682
2683         at_context_transmit(&ohci->at_response_ctx, packet);
2684 }
2685
2686 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2687 {
2688         struct fw_ohci *ohci = fw_ohci(card);
2689         struct context *ctx = &ohci->at_request_ctx;
2690         struct driver_data *driver_data = packet->driver_data;
2691         int ret = -ENOENT;
2692
2693         tasklet_disable_in_atomic(&ctx->tasklet);
2694
2695         if (packet->ack != 0)
2696                 goto out;
2697
2698         if (packet->payload_mapped)
2699                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2700                                  packet->payload_length, DMA_TO_DEVICE);
2701
2702         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2703         driver_data->packet = NULL;
2704         packet->ack = RCODE_CANCELLED;
2705
2706         // Timestamping on behalf of the hardware.
2707         packet->timestamp = cycle_time_to_ohci_tstamp(get_cycle_time(ohci));
2708
2709         packet->callback(packet, &ohci->card, packet->ack);
2710         ret = 0;
2711  out:
2712         tasklet_enable(&ctx->tasklet);
2713
2714         return ret;
2715 }
2716
2717 static int ohci_enable_phys_dma(struct fw_card *card,
2718                                 int node_id, int generation)
2719 {
2720         struct fw_ohci *ohci = fw_ohci(card);
2721         int n, ret = 0;
2722
2723         if (param_remote_dma)
2724                 return 0;
2725
2726         /*
2727          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2728          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2729          */
2730
2731         guard(spinlock_irqsave)(&ohci->lock);
2732
2733         if (ohci->generation != generation)
2734                 return -ESTALE;
2735
2736         /*
2737          * Note, if the node ID contains a non-local bus ID, physical DMA is
2738          * enabled for _all_ nodes on remote buses.
2739          */
2740
2741         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2742         if (n < 32)
2743                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2744         else
2745                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2746
2747         flush_writes(ohci);
2748
2749         return ret;
2750 }
2751
2752 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2753 {
2754         struct fw_ohci *ohci = fw_ohci(card);
2755         u32 value;
2756
2757         switch (csr_offset) {
2758         case CSR_STATE_CLEAR:
2759         case CSR_STATE_SET:
2760                 if (ohci->is_root &&
2761                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2762                      OHCI1394_LinkControl_cycleMaster))
2763                         value = CSR_STATE_BIT_CMSTR;
2764                 else
2765                         value = 0;
2766                 if (ohci->csr_state_setclear_abdicate)
2767                         value |= CSR_STATE_BIT_ABDICATE;
2768
2769                 return value;
2770
2771         case CSR_NODE_IDS:
2772                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2773
2774         case CSR_CYCLE_TIME:
2775                 return get_cycle_time(ohci);
2776
2777         case CSR_BUS_TIME:
2778         {
2779                 // We might be called just after the cycle timer has wrapped around but just before
2780                 // the cycle64Seconds handler, so we better check here, too, if the bus time needs
2781                 // to be updated.
2782
2783                 guard(spinlock_irqsave)(&ohci->lock);
2784                 return update_bus_time(ohci);
2785         }
2786         case CSR_BUSY_TIMEOUT:
2787                 value = reg_read(ohci, OHCI1394_ATRetries);
2788                 return (value >> 4) & 0x0ffff00f;
2789
2790         case CSR_PRIORITY_BUDGET:
2791                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2792                         (ohci->pri_req_max << 8);
2793
2794         default:
2795                 WARN_ON(1);
2796                 return 0;
2797         }
2798 }
2799
2800 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2801 {
2802         struct fw_ohci *ohci = fw_ohci(card);
2803
2804         switch (csr_offset) {
2805         case CSR_STATE_CLEAR:
2806                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2807                         reg_write(ohci, OHCI1394_LinkControlClear,
2808                                   OHCI1394_LinkControl_cycleMaster);
2809                         flush_writes(ohci);
2810                 }
2811                 if (value & CSR_STATE_BIT_ABDICATE)
2812                         ohci->csr_state_setclear_abdicate = false;
2813                 break;
2814
2815         case CSR_STATE_SET:
2816                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2817                         reg_write(ohci, OHCI1394_LinkControlSet,
2818                                   OHCI1394_LinkControl_cycleMaster);
2819                         flush_writes(ohci);
2820                 }
2821                 if (value & CSR_STATE_BIT_ABDICATE)
2822                         ohci->csr_state_setclear_abdicate = true;
2823                 break;
2824
2825         case CSR_NODE_IDS:
2826                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2827                 flush_writes(ohci);
2828                 break;
2829
2830         case CSR_CYCLE_TIME:
2831                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2832                 reg_write(ohci, OHCI1394_IntEventSet,
2833                           OHCI1394_cycleInconsistent);
2834                 flush_writes(ohci);
2835                 break;
2836
2837         case CSR_BUS_TIME:
2838         {
2839                 guard(spinlock_irqsave)(&ohci->lock);
2840                 ohci->bus_time = (update_bus_time(ohci) & 0x40) | (value & ~0x7f);
2841                 break;
2842         }
2843         case CSR_BUSY_TIMEOUT:
2844                 value = (value & 0xf) | ((value & 0xf) << 4) |
2845                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2846                 reg_write(ohci, OHCI1394_ATRetries, value);
2847                 flush_writes(ohci);
2848                 break;
2849
2850         case CSR_PRIORITY_BUDGET:
2851                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2852                 flush_writes(ohci);
2853                 break;
2854
2855         default:
2856                 WARN_ON(1);
2857                 break;
2858         }
2859 }
2860
2861 static void flush_iso_completions(struct iso_context *ctx, enum fw_iso_context_completions_cause cause)
2862 {
2863         trace_isoc_inbound_single_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header,
2864                                               ctx->header_length);
2865         trace_isoc_outbound_completions(&ctx->base, ctx->last_timestamp, cause, ctx->header,
2866                                         ctx->header_length);
2867
2868         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2869                               ctx->header_length, ctx->header,
2870                               ctx->base.callback_data);
2871         ctx->header_length = 0;
2872 }
2873
2874 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2875 {
2876         u32 *ctx_hdr;
2877
2878         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2879                 if (ctx->base.drop_overflow_headers)
2880                         return;
2881                 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW);
2882         }
2883
2884         ctx_hdr = ctx->header + ctx->header_length;
2885         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2886
2887         /*
2888          * The two iso header quadlets are byteswapped to little
2889          * endian by the controller, but we want to present them
2890          * as big endian for consistency with the bus endianness.
2891          */
2892         if (ctx->base.header_size > 0)
2893                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2894         if (ctx->base.header_size > 4)
2895                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2896         if (ctx->base.header_size > 8)
2897                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2898         ctx->header_length += ctx->base.header_size;
2899 }
2900
2901 static int handle_ir_packet_per_buffer(struct context *context,
2902                                        struct descriptor *d,
2903                                        struct descriptor *last)
2904 {
2905         struct iso_context *ctx =
2906                 container_of(context, struct iso_context, context);
2907         struct descriptor *pd;
2908         u32 buffer_dma;
2909
2910         for (pd = d; pd <= last; pd++)
2911                 if (pd->transfer_status)
2912                         break;
2913         if (pd > last)
2914                 /* Descriptor(s) not done yet, stop iteration */
2915                 return 0;
2916
2917         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2918                 d++;
2919                 buffer_dma = le32_to_cpu(d->data_address);
2920                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2921                                               buffer_dma & PAGE_MASK,
2922                                               buffer_dma & ~PAGE_MASK,
2923                                               le16_to_cpu(d->req_count),
2924                                               DMA_FROM_DEVICE);
2925         }
2926
2927         copy_iso_headers(ctx, (u32 *) (last + 1));
2928
2929         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2930                 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_INTERRUPT);
2931
2932         return 1;
2933 }
2934
2935 /* d == last because each descriptor block is only a single descriptor. */
2936 static int handle_ir_buffer_fill(struct context *context,
2937                                  struct descriptor *d,
2938                                  struct descriptor *last)
2939 {
2940         struct iso_context *ctx =
2941                 container_of(context, struct iso_context, context);
2942         unsigned int req_count, res_count, completed;
2943         u32 buffer_dma;
2944
2945         req_count = le16_to_cpu(last->req_count);
2946         res_count = le16_to_cpu(READ_ONCE(last->res_count));
2947         completed = req_count - res_count;
2948         buffer_dma = le32_to_cpu(last->data_address);
2949
2950         if (completed > 0) {
2951                 ctx->mc_buffer_bus = buffer_dma;
2952                 ctx->mc_completed = completed;
2953         }
2954
2955         if (res_count != 0)
2956                 /* Descriptor(s) not done yet, stop iteration */
2957                 return 0;
2958
2959         dma_sync_single_range_for_cpu(context->ohci->card.device,
2960                                       buffer_dma & PAGE_MASK,
2961                                       buffer_dma & ~PAGE_MASK,
2962                                       completed, DMA_FROM_DEVICE);
2963
2964         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
2965                 trace_isoc_inbound_multiple_completions(&ctx->base, completed,
2966                                                         FW_ISO_CONTEXT_COMPLETIONS_CAUSE_INTERRUPT);
2967
2968                 ctx->base.callback.mc(&ctx->base,
2969                                       buffer_dma + completed,
2970                                       ctx->base.callback_data);
2971                 ctx->mc_completed = 0;
2972         }
2973
2974         return 1;
2975 }
2976
2977 static void flush_ir_buffer_fill(struct iso_context *ctx)
2978 {
2979         dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2980                                       ctx->mc_buffer_bus & PAGE_MASK,
2981                                       ctx->mc_buffer_bus & ~PAGE_MASK,
2982                                       ctx->mc_completed, DMA_FROM_DEVICE);
2983
2984         trace_isoc_inbound_multiple_completions(&ctx->base, ctx->mc_completed,
2985                                                 FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH);
2986
2987         ctx->base.callback.mc(&ctx->base,
2988                               ctx->mc_buffer_bus + ctx->mc_completed,
2989                               ctx->base.callback_data);
2990         ctx->mc_completed = 0;
2991 }
2992
2993 static inline void sync_it_packet_for_cpu(struct context *context,
2994                                           struct descriptor *pd)
2995 {
2996         __le16 control;
2997         u32 buffer_dma;
2998
2999         /* only packets beginning with OUTPUT_MORE* have data buffers */
3000         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
3001                 return;
3002
3003         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
3004         pd += 2;
3005
3006         /*
3007          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
3008          * data buffer is in the context program's coherent page and must not
3009          * be synced.
3010          */
3011         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
3012             (context->current_bus          & PAGE_MASK)) {
3013                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
3014                         return;
3015                 pd++;
3016         }
3017
3018         do {
3019                 buffer_dma = le32_to_cpu(pd->data_address);
3020                 dma_sync_single_range_for_cpu(context->ohci->card.device,
3021                                               buffer_dma & PAGE_MASK,
3022                                               buffer_dma & ~PAGE_MASK,
3023                                               le16_to_cpu(pd->req_count),
3024                                               DMA_TO_DEVICE);
3025                 control = pd->control;
3026                 pd++;
3027         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
3028 }
3029
3030 static int handle_it_packet(struct context *context,
3031                             struct descriptor *d,
3032                             struct descriptor *last)
3033 {
3034         struct iso_context *ctx =
3035                 container_of(context, struct iso_context, context);
3036         struct descriptor *pd;
3037         __be32 *ctx_hdr;
3038
3039         for (pd = d; pd <= last; pd++)
3040                 if (pd->transfer_status)
3041                         break;
3042         if (pd > last)
3043                 /* Descriptor(s) not done yet, stop iteration */
3044                 return 0;
3045
3046         sync_it_packet_for_cpu(context, d);
3047
3048         if (ctx->header_length + 4 > PAGE_SIZE) {
3049                 if (ctx->base.drop_overflow_headers)
3050                         return 1;
3051                 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_HEADER_OVERFLOW);
3052         }
3053
3054         ctx_hdr = ctx->header + ctx->header_length;
3055         ctx->last_timestamp = le16_to_cpu(last->res_count);
3056         /* Present this value as big-endian to match the receive code */
3057         *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
3058                                le16_to_cpu(pd->res_count));
3059         ctx->header_length += 4;
3060
3061         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
3062                 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_INTERRUPT);
3063
3064         return 1;
3065 }
3066
3067 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
3068 {
3069         u32 hi = channels >> 32, lo = channels;
3070
3071         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
3072         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
3073         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
3074         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
3075         ohci->mc_channels = channels;
3076 }
3077
3078 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
3079                                 int type, int channel, size_t header_size)
3080 {
3081         struct fw_ohci *ohci = fw_ohci(card);
3082         struct iso_context *ctx;
3083         descriptor_callback_t callback;
3084         u64 *channels;
3085         u32 *mask, regs;
3086         int index, ret = -EBUSY;
3087
3088         scoped_guard(spinlock_irq, &ohci->lock) {
3089                 switch (type) {
3090                 case FW_ISO_CONTEXT_TRANSMIT:
3091                         mask     = &ohci->it_context_mask;
3092                         callback = handle_it_packet;
3093                         index    = ffs(*mask) - 1;
3094                         if (index >= 0) {
3095                                 *mask &= ~(1 << index);
3096                                 regs = OHCI1394_IsoXmitContextBase(index);
3097                                 ctx  = &ohci->it_context_list[index];
3098                         }
3099                         break;
3100
3101                 case FW_ISO_CONTEXT_RECEIVE:
3102                         channels = &ohci->ir_context_channels;
3103                         mask     = &ohci->ir_context_mask;
3104                         callback = handle_ir_packet_per_buffer;
3105                         index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
3106                         if (index >= 0) {
3107                                 *channels &= ~(1ULL << channel);
3108                                 *mask     &= ~(1 << index);
3109                                 regs = OHCI1394_IsoRcvContextBase(index);
3110                                 ctx  = &ohci->ir_context_list[index];
3111                         }
3112                         break;
3113
3114                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3115                         mask     = &ohci->ir_context_mask;
3116                         callback = handle_ir_buffer_fill;
3117                         index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
3118                         if (index >= 0) {
3119                                 ohci->mc_allocated = true;
3120                                 *mask &= ~(1 << index);
3121                                 regs = OHCI1394_IsoRcvContextBase(index);
3122                                 ctx  = &ohci->ir_context_list[index];
3123                         }
3124                         break;
3125
3126                 default:
3127                         index = -1;
3128                         ret = -ENOSYS;
3129                 }
3130
3131                 if (index < 0)
3132                         return ERR_PTR(ret);
3133         }
3134
3135         memset(ctx, 0, sizeof(*ctx));
3136         ctx->header_length = 0;
3137         ctx->header = (void *) __get_free_page(GFP_KERNEL);
3138         if (ctx->header == NULL) {
3139                 ret = -ENOMEM;
3140                 goto out;
3141         }
3142         ret = context_init(&ctx->context, ohci, regs, callback);
3143         if (ret < 0)
3144                 goto out_with_header;
3145         fw_iso_context_init_work(&ctx->base, ohci_isoc_context_work);
3146
3147         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
3148                 set_multichannel_mask(ohci, 0);
3149                 ctx->mc_completed = 0;
3150         }
3151
3152         return &ctx->base;
3153
3154  out_with_header:
3155         free_page((unsigned long)ctx->header);
3156  out:
3157         scoped_guard(spinlock_irq, &ohci->lock) {
3158                 switch (type) {
3159                 case FW_ISO_CONTEXT_RECEIVE:
3160                         *channels |= 1ULL << channel;
3161                         break;
3162
3163                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3164                         ohci->mc_allocated = false;
3165                         break;
3166                 }
3167                 *mask |= 1 << index;
3168         }
3169
3170         return ERR_PTR(ret);
3171 }
3172
3173 static int ohci_start_iso(struct fw_iso_context *base,
3174                           s32 cycle, u32 sync, u32 tags)
3175 {
3176         struct iso_context *ctx = container_of(base, struct iso_context, base);
3177         struct fw_ohci *ohci = ctx->context.ohci;
3178         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
3179         int index;
3180
3181         /* the controller cannot start without any queued packets */
3182         if (ctx->context.last->branch_address == 0)
3183                 return -ENODATA;
3184
3185         switch (ctx->base.type) {
3186         case FW_ISO_CONTEXT_TRANSMIT:
3187                 index = ctx - ohci->it_context_list;
3188                 match = 0;
3189                 if (cycle >= 0)
3190                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
3191                                 (cycle & 0x7fff) << 16;
3192
3193                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3194                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
3195                 context_run(&ctx->context, match);
3196                 break;
3197
3198         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3199                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3200                 fallthrough;
3201         case FW_ISO_CONTEXT_RECEIVE:
3202                 index = ctx - ohci->ir_context_list;
3203                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3204                 if (cycle >= 0) {
3205                         match |= (cycle & 0x07fff) << 12;
3206                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3207                 }
3208
3209                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3210                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
3211                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
3212                 context_run(&ctx->context, control);
3213
3214                 ctx->sync = sync;
3215                 ctx->tags = tags;
3216
3217                 break;
3218         }
3219
3220         return 0;
3221 }
3222
3223 static int ohci_stop_iso(struct fw_iso_context *base)
3224 {
3225         struct fw_ohci *ohci = fw_ohci(base->card);
3226         struct iso_context *ctx = container_of(base, struct iso_context, base);
3227         int index;
3228
3229         switch (ctx->base.type) {
3230         case FW_ISO_CONTEXT_TRANSMIT:
3231                 index = ctx - ohci->it_context_list;
3232                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3233                 break;
3234
3235         case FW_ISO_CONTEXT_RECEIVE:
3236         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3237                 index = ctx - ohci->ir_context_list;
3238                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3239                 break;
3240         }
3241         flush_writes(ohci);
3242         context_stop(&ctx->context);
3243
3244         return 0;
3245 }
3246
3247 static void ohci_free_iso_context(struct fw_iso_context *base)
3248 {
3249         struct fw_ohci *ohci = fw_ohci(base->card);
3250         struct iso_context *ctx = container_of(base, struct iso_context, base);
3251         int index;
3252
3253         ohci_stop_iso(base);
3254         context_release(&ctx->context);
3255         free_page((unsigned long)ctx->header);
3256
3257         guard(spinlock_irqsave)(&ohci->lock);
3258
3259         switch (base->type) {
3260         case FW_ISO_CONTEXT_TRANSMIT:
3261                 index = ctx - ohci->it_context_list;
3262                 ohci->it_context_mask |= 1 << index;
3263                 break;
3264
3265         case FW_ISO_CONTEXT_RECEIVE:
3266                 index = ctx - ohci->ir_context_list;
3267                 ohci->ir_context_mask |= 1 << index;
3268                 ohci->ir_context_channels |= 1ULL << base->channel;
3269                 break;
3270
3271         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3272                 index = ctx - ohci->ir_context_list;
3273                 ohci->ir_context_mask |= 1 << index;
3274                 ohci->ir_context_channels |= ohci->mc_channels;
3275                 ohci->mc_channels = 0;
3276                 ohci->mc_allocated = false;
3277                 break;
3278         }
3279 }
3280
3281 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3282 {
3283         struct fw_ohci *ohci = fw_ohci(base->card);
3284
3285         switch (base->type) {
3286         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3287         {
3288                 guard(spinlock_irqsave)(&ohci->lock);
3289
3290                 // Don't allow multichannel to grab other contexts' channels.
3291                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3292                         *channels = ohci->ir_context_channels;
3293                         return -EBUSY;
3294                 } else {
3295                         set_multichannel_mask(ohci, *channels);
3296                         return 0;
3297                 }
3298         }
3299         default:
3300                 return -EINVAL;
3301         }
3302 }
3303
3304 static void __maybe_unused ohci_resume_iso_dma(struct fw_ohci *ohci)
3305 {
3306         int i;
3307         struct iso_context *ctx;
3308
3309         for (i = 0 ; i < ohci->n_ir ; i++) {
3310                 ctx = &ohci->ir_context_list[i];
3311                 if (ctx->context.running)
3312                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3313         }
3314
3315         for (i = 0 ; i < ohci->n_it ; i++) {
3316                 ctx = &ohci->it_context_list[i];
3317                 if (ctx->context.running)
3318                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3319         }
3320 }
3321
3322 static int queue_iso_transmit(struct iso_context *ctx,
3323                               struct fw_iso_packet *packet,
3324                               struct fw_iso_buffer *buffer,
3325                               unsigned long payload)
3326 {
3327         struct descriptor *d, *last, *pd;
3328         struct fw_iso_packet *p;
3329         __le32 *header;
3330         dma_addr_t d_bus, page_bus;
3331         u32 z, header_z, payload_z, irq;
3332         u32 payload_index, payload_end_index, next_page_index;
3333         int page, end_page, i, length, offset;
3334
3335         p = packet;
3336         payload_index = payload;
3337
3338         if (p->skip)
3339                 z = 1;
3340         else
3341                 z = 2;
3342         if (p->header_length > 0)
3343                 z++;
3344
3345         /* Determine the first page the payload isn't contained in. */
3346         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3347         if (p->payload_length > 0)
3348                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3349         else
3350                 payload_z = 0;
3351
3352         z += payload_z;
3353
3354         /* Get header size in number of descriptors. */
3355         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3356
3357         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3358         if (d == NULL)
3359                 return -ENOMEM;
3360
3361         if (!p->skip) {
3362                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3363                 d[0].req_count = cpu_to_le16(8);
3364                 /*
3365                  * Link the skip address to this descriptor itself.  This causes
3366                  * a context to skip a cycle whenever lost cycles or FIFO
3367                  * overruns occur, without dropping the data.  The application
3368                  * should then decide whether this is an error condition or not.
3369                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3370                  */
3371                 d[0].branch_address = cpu_to_le32(d_bus | z);
3372
3373                 header = (__le32 *) &d[1];
3374
3375                 ohci1394_it_data_set_speed(header, ctx->base.speed);
3376                 ohci1394_it_data_set_tag(header, p->tag);
3377                 ohci1394_it_data_set_channel(header, ctx->base.channel);
3378                 ohci1394_it_data_set_tcode(header, TCODE_STREAM_DATA);
3379                 ohci1394_it_data_set_sync(header, p->sy);
3380
3381                 ohci1394_it_data_set_data_length(header, p->header_length + p->payload_length);
3382         }
3383
3384         if (p->header_length > 0) {
3385                 d[2].req_count    = cpu_to_le16(p->header_length);
3386                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3387                 memcpy(&d[z], p->header, p->header_length);
3388         }
3389
3390         pd = d + z - payload_z;
3391         payload_end_index = payload_index + p->payload_length;
3392         for (i = 0; i < payload_z; i++) {
3393                 page               = payload_index >> PAGE_SHIFT;
3394                 offset             = payload_index & ~PAGE_MASK;
3395                 next_page_index    = (page + 1) << PAGE_SHIFT;
3396                 length             =
3397                         min(next_page_index, payload_end_index) - payload_index;
3398                 pd[i].req_count    = cpu_to_le16(length);
3399
3400                 page_bus = page_private(buffer->pages[page]);
3401                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3402
3403                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3404                                                  page_bus, offset, length,
3405                                                  DMA_TO_DEVICE);
3406
3407                 payload_index += length;
3408         }
3409
3410         if (p->interrupt)
3411                 irq = DESCRIPTOR_IRQ_ALWAYS;
3412         else
3413                 irq = DESCRIPTOR_NO_IRQ;
3414
3415         last = z == 2 ? d : d + z - 1;
3416         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3417                                      DESCRIPTOR_STATUS |
3418                                      DESCRIPTOR_BRANCH_ALWAYS |
3419                                      irq);
3420
3421         context_append(&ctx->context, d, z, header_z);
3422
3423         return 0;
3424 }
3425
3426 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3427                                        struct fw_iso_packet *packet,
3428                                        struct fw_iso_buffer *buffer,
3429                                        unsigned long payload)
3430 {
3431         struct device *device = ctx->context.ohci->card.device;
3432         struct descriptor *d, *pd;
3433         dma_addr_t d_bus, page_bus;
3434         u32 z, header_z, rest;
3435         int i, j, length;
3436         int page, offset, packet_count, header_size, payload_per_buffer;
3437
3438         /*
3439          * The OHCI controller puts the isochronous header and trailer in the
3440          * buffer, so we need at least 8 bytes.
3441          */
3442         packet_count = packet->header_length / ctx->base.header_size;
3443         header_size  = max(ctx->base.header_size, (size_t)8);
3444
3445         /* Get header size in number of descriptors. */
3446         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3447         page     = payload >> PAGE_SHIFT;
3448         offset   = payload & ~PAGE_MASK;
3449         payload_per_buffer = packet->payload_length / packet_count;
3450
3451         for (i = 0; i < packet_count; i++) {
3452                 /* d points to the header descriptor */
3453                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3454                 d = context_get_descriptors(&ctx->context,
3455                                 z + header_z, &d_bus);
3456                 if (d == NULL)
3457                         return -ENOMEM;
3458
3459                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3460                                               DESCRIPTOR_INPUT_MORE);
3461                 if (packet->skip && i == 0)
3462                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3463                 d->req_count    = cpu_to_le16(header_size);
3464                 d->res_count    = d->req_count;
3465                 d->transfer_status = 0;
3466                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3467
3468                 rest = payload_per_buffer;
3469                 pd = d;
3470                 for (j = 1; j < z; j++) {
3471                         pd++;
3472                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3473                                                   DESCRIPTOR_INPUT_MORE);
3474
3475                         if (offset + rest < PAGE_SIZE)
3476                                 length = rest;
3477                         else
3478                                 length = PAGE_SIZE - offset;
3479                         pd->req_count = cpu_to_le16(length);
3480                         pd->res_count = pd->req_count;
3481                         pd->transfer_status = 0;
3482
3483                         page_bus = page_private(buffer->pages[page]);
3484                         pd->data_address = cpu_to_le32(page_bus + offset);
3485
3486                         dma_sync_single_range_for_device(device, page_bus,
3487                                                          offset, length,
3488                                                          DMA_FROM_DEVICE);
3489
3490                         offset = (offset + length) & ~PAGE_MASK;
3491                         rest -= length;
3492                         if (offset == 0)
3493                                 page++;
3494                 }
3495                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3496                                           DESCRIPTOR_INPUT_LAST |
3497                                           DESCRIPTOR_BRANCH_ALWAYS);
3498                 if (packet->interrupt && i == packet_count - 1)
3499                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3500
3501                 context_append(&ctx->context, d, z, header_z);
3502         }
3503
3504         return 0;
3505 }
3506
3507 static int queue_iso_buffer_fill(struct iso_context *ctx,
3508                                  struct fw_iso_packet *packet,
3509                                  struct fw_iso_buffer *buffer,
3510                                  unsigned long payload)
3511 {
3512         struct descriptor *d;
3513         dma_addr_t d_bus, page_bus;
3514         int page, offset, rest, z, i, length;
3515
3516         page   = payload >> PAGE_SHIFT;
3517         offset = payload & ~PAGE_MASK;
3518         rest   = packet->payload_length;
3519
3520         /* We need one descriptor for each page in the buffer. */
3521         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3522
3523         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3524                 return -EFAULT;
3525
3526         for (i = 0; i < z; i++) {
3527                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3528                 if (d == NULL)
3529                         return -ENOMEM;
3530
3531                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3532                                          DESCRIPTOR_BRANCH_ALWAYS);
3533                 if (packet->skip && i == 0)
3534                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3535                 if (packet->interrupt && i == z - 1)
3536                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3537
3538                 if (offset + rest < PAGE_SIZE)
3539                         length = rest;
3540                 else
3541                         length = PAGE_SIZE - offset;
3542                 d->req_count = cpu_to_le16(length);
3543                 d->res_count = d->req_count;
3544                 d->transfer_status = 0;
3545
3546                 page_bus = page_private(buffer->pages[page]);
3547                 d->data_address = cpu_to_le32(page_bus + offset);
3548
3549                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3550                                                  page_bus, offset, length,
3551                                                  DMA_FROM_DEVICE);
3552
3553                 rest -= length;
3554                 offset = 0;
3555                 page++;
3556
3557                 context_append(&ctx->context, d, 1, 0);
3558         }
3559
3560         return 0;
3561 }
3562
3563 static int ohci_queue_iso(struct fw_iso_context *base,
3564                           struct fw_iso_packet *packet,
3565                           struct fw_iso_buffer *buffer,
3566                           unsigned long payload)
3567 {
3568         struct iso_context *ctx = container_of(base, struct iso_context, base);
3569
3570         guard(spinlock_irqsave)(&ctx->context.ohci->lock);
3571
3572         switch (base->type) {
3573         case FW_ISO_CONTEXT_TRANSMIT:
3574                 return queue_iso_transmit(ctx, packet, buffer, payload);
3575         case FW_ISO_CONTEXT_RECEIVE:
3576                 return queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3577         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3578                 return queue_iso_buffer_fill(ctx, packet, buffer, payload);
3579         default:
3580                 return -ENOSYS;
3581         }
3582 }
3583
3584 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3585 {
3586         struct context *ctx =
3587                         &container_of(base, struct iso_context, base)->context;
3588
3589         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3590 }
3591
3592 static int ohci_flush_iso_completions(struct fw_iso_context *base)
3593 {
3594         struct iso_context *ctx = container_of(base, struct iso_context, base);
3595         int ret = 0;
3596
3597         if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3598                 ohci_isoc_context_work(&base->work);
3599
3600                 switch (base->type) {
3601                 case FW_ISO_CONTEXT_TRANSMIT:
3602                 case FW_ISO_CONTEXT_RECEIVE:
3603                         if (ctx->header_length != 0)
3604                                 flush_iso_completions(ctx, FW_ISO_CONTEXT_COMPLETIONS_CAUSE_FLUSH);
3605                         break;
3606                 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3607                         if (ctx->mc_completed != 0)
3608                                 flush_ir_buffer_fill(ctx);
3609                         break;
3610                 default:
3611                         ret = -ENOSYS;
3612                 }
3613
3614                 clear_bit_unlock(0, &ctx->flushing_completions);
3615                 smp_mb__after_atomic();
3616         }
3617
3618         return ret;
3619 }
3620
3621 static const struct fw_card_driver ohci_driver = {
3622         .enable                 = ohci_enable,
3623         .read_phy_reg           = ohci_read_phy_reg,
3624         .update_phy_reg         = ohci_update_phy_reg,
3625         .set_config_rom         = ohci_set_config_rom,
3626         .send_request           = ohci_send_request,
3627         .send_response          = ohci_send_response,
3628         .cancel_packet          = ohci_cancel_packet,
3629         .enable_phys_dma        = ohci_enable_phys_dma,
3630         .read_csr               = ohci_read_csr,
3631         .write_csr              = ohci_write_csr,
3632
3633         .allocate_iso_context   = ohci_allocate_iso_context,
3634         .free_iso_context       = ohci_free_iso_context,
3635         .set_iso_channels       = ohci_set_iso_channels,
3636         .queue_iso              = ohci_queue_iso,
3637         .flush_queue_iso        = ohci_flush_queue_iso,
3638         .flush_iso_completions  = ohci_flush_iso_completions,
3639         .start_iso              = ohci_start_iso,
3640         .stop_iso               = ohci_stop_iso,
3641 };
3642
3643 #ifdef CONFIG_PPC_PMAC
3644 static void pmac_ohci_on(struct pci_dev *dev)
3645 {
3646         if (machine_is(powermac)) {
3647                 struct device_node *ofn = pci_device_to_OF_node(dev);
3648
3649                 if (ofn) {
3650                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3651                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3652                 }
3653         }
3654 }
3655
3656 static void pmac_ohci_off(struct pci_dev *dev)
3657 {
3658         if (machine_is(powermac)) {
3659                 struct device_node *ofn = pci_device_to_OF_node(dev);
3660
3661                 if (ofn) {
3662                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3663                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3664                 }
3665         }
3666 }
3667 #else
3668 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3669 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3670 #endif /* CONFIG_PPC_PMAC */
3671
3672 static void release_ohci(struct device *dev, void *data)
3673 {
3674         struct pci_dev *pdev = to_pci_dev(dev);
3675         struct fw_ohci *ohci = pci_get_drvdata(pdev);
3676
3677         pmac_ohci_off(pdev);
3678
3679         ar_context_release(&ohci->ar_response_ctx);
3680         ar_context_release(&ohci->ar_request_ctx);
3681
3682         dev_notice(dev, "removed fw-ohci device\n");
3683 }
3684
3685 static int pci_probe(struct pci_dev *dev,
3686                                const struct pci_device_id *ent)
3687 {
3688         struct fw_ohci *ohci;
3689         u32 bus_options, max_receive, link_speed, version;
3690         u64 guid;
3691         int i, flags, irq, err;
3692         size_t size;
3693
3694         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3695                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3696                 return -ENOSYS;
3697         }
3698
3699         ohci = devres_alloc(release_ohci, sizeof(*ohci), GFP_KERNEL);
3700         if (ohci == NULL)
3701                 return -ENOMEM;
3702         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3703         pci_set_drvdata(dev, ohci);
3704         pmac_ohci_on(dev);
3705         devres_add(&dev->dev, ohci);
3706
3707         err = pcim_enable_device(dev);
3708         if (err) {
3709                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3710                 return err;
3711         }
3712
3713         pci_set_master(dev);
3714         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3715
3716         spin_lock_init(&ohci->lock);
3717         mutex_init(&ohci->phy_reg_mutex);
3718
3719         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3720
3721         if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3722             pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3723                 ohci_err(ohci, "invalid MMIO resource\n");
3724                 return -ENXIO;
3725         }
3726
3727         ohci->registers = pcim_iomap_region(dev, 0, ohci_driver_name);
3728         if (IS_ERR(ohci->registers)) {
3729                 ohci_err(ohci, "request and map MMIO resource unavailable\n");
3730                 return -ENXIO;
3731         }
3732
3733         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3734                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3735                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3736                      ohci_quirks[i].device == dev->device) &&
3737                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3738                      ohci_quirks[i].revision >= dev->revision)) {
3739                         ohci->quirks = ohci_quirks[i].flags;
3740                         break;
3741                 }
3742         if (param_quirks)
3743                 ohci->quirks = param_quirks;
3744
3745         if (detect_vt630x_with_asm1083_on_amd_ryzen_machine(dev))
3746                 ohci->quirks |= QUIRK_REBOOT_BY_CYCLE_TIMER_READ;
3747
3748         /*
3749          * Because dma_alloc_coherent() allocates at least one page,
3750          * we save space by using a common buffer for the AR request/
3751          * response descriptors and the self IDs buffer.
3752          */
3753         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3754         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3755         ohci->misc_buffer = dmam_alloc_coherent(&dev->dev, PAGE_SIZE, &ohci->misc_buffer_bus,
3756                                                 GFP_KERNEL);
3757         if (!ohci->misc_buffer)
3758                 return -ENOMEM;
3759
3760         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3761                               OHCI1394_AsReqRcvContextControlSet);
3762         if (err < 0)
3763                 return err;
3764
3765         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3766                               OHCI1394_AsRspRcvContextControlSet);
3767         if (err < 0)
3768                 return err;
3769
3770         err = context_init(&ohci->at_request_ctx, ohci,
3771                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3772         if (err < 0)
3773                 return err;
3774
3775         err = context_init(&ohci->at_response_ctx, ohci,
3776                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3777         if (err < 0)
3778                 return err;
3779
3780         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3781         ohci->ir_context_channels = ~0ULL;
3782         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3783         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3784         ohci->ir_context_mask = ohci->ir_context_support;
3785         ohci->n_ir = hweight32(ohci->ir_context_mask);
3786         size = sizeof(struct iso_context) * ohci->n_ir;
3787         ohci->ir_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL);
3788         if (!ohci->ir_context_list)
3789                 return -ENOMEM;
3790
3791         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3792         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3793         /* JMicron JMB38x often shows 0 at first read, just ignore it */
3794         if (!ohci->it_context_support) {
3795                 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3796                 ohci->it_context_support = 0xf;
3797         }
3798         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3799         ohci->it_context_mask = ohci->it_context_support;
3800         ohci->n_it = hweight32(ohci->it_context_mask);
3801         size = sizeof(struct iso_context) * ohci->n_it;
3802         ohci->it_context_list = devm_kzalloc(&dev->dev, size, GFP_KERNEL);
3803         if (!ohci->it_context_list)
3804                 return -ENOMEM;
3805
3806         ohci->self_id     = ohci->misc_buffer     + PAGE_SIZE/2;
3807         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3808
3809         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3810         max_receive = (bus_options >> 12) & 0xf;
3811         link_speed = bus_options & 0x7;
3812         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3813                 reg_read(ohci, OHCI1394_GUIDLo);
3814
3815         flags = PCI_IRQ_INTX;
3816         if (!(ohci->quirks & QUIRK_NO_MSI))
3817                 flags |= PCI_IRQ_MSI;
3818         err = pci_alloc_irq_vectors(dev, 1, 1, flags);
3819         if (err < 0)
3820                 return err;
3821         irq = pci_irq_vector(dev, 0);
3822         if (irq < 0) {
3823                 err = irq;
3824                 goto fail_msi;
3825         }
3826
3827         err = request_threaded_irq(irq, irq_handler, NULL,
3828                                    pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, ohci_driver_name,
3829                                    ohci);
3830         if (err < 0) {
3831                 ohci_err(ohci, "failed to allocate interrupt %d\n", irq);
3832                 goto fail_msi;
3833         }
3834
3835         err = fw_card_add(&ohci->card, max_receive, link_speed, guid, ohci->n_it + ohci->n_ir);
3836         if (err)
3837                 goto fail_irq;
3838
3839         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3840         ohci_notice(ohci,
3841                     "added OHCI v%x.%x device as card %d, "
3842                     "%d IR + %d IT contexts, quirks 0x%x%s\n",
3843                     version >> 16, version & 0xff, ohci->card.index,
3844                     ohci->n_ir, ohci->n_it, ohci->quirks,
3845                     reg_read(ohci, OHCI1394_PhyUpperBound) ?
3846                         ", physUB" : "");
3847
3848         return 0;
3849
3850  fail_irq:
3851         free_irq(irq, ohci);
3852  fail_msi:
3853         pci_free_irq_vectors(dev);
3854
3855         return err;
3856 }
3857
3858 static void pci_remove(struct pci_dev *dev)
3859 {
3860         struct fw_ohci *ohci = pci_get_drvdata(dev);
3861         int irq;
3862
3863         /*
3864          * If the removal is happening from the suspend state, LPS won't be
3865          * enabled and host registers (eg., IntMaskClear) won't be accessible.
3866          */
3867         if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3868                 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3869                 flush_writes(ohci);
3870         }
3871         cancel_work_sync(&ohci->bus_reset_work);
3872         fw_core_remove_card(&ohci->card);
3873
3874         /*
3875          * FIXME: Fail all pending packets here, now that the upper
3876          * layers can't queue any more.
3877          */
3878
3879         software_reset(ohci);
3880
3881         irq = pci_irq_vector(dev, 0);
3882         if (irq >= 0)
3883                 free_irq(irq, ohci);
3884         pci_free_irq_vectors(dev);
3885
3886         dev_notice(&dev->dev, "removing fw-ohci device\n");
3887 }
3888
3889 static int __maybe_unused pci_suspend(struct device *dev)
3890 {
3891         struct pci_dev *pdev = to_pci_dev(dev);
3892         struct fw_ohci *ohci = pci_get_drvdata(pdev);
3893
3894         software_reset(ohci);
3895         pmac_ohci_off(pdev);
3896
3897         return 0;
3898 }
3899
3900
3901 static int __maybe_unused pci_resume(struct device *dev)
3902 {
3903         struct pci_dev *pdev = to_pci_dev(dev);
3904         struct fw_ohci *ohci = pci_get_drvdata(pdev);
3905         int err;
3906
3907         pmac_ohci_on(pdev);
3908
3909         /* Some systems don't setup GUID register on resume from ram  */
3910         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3911                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3912                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3913                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3914         }
3915
3916         err = ohci_enable(&ohci->card, NULL, 0);
3917         if (err)
3918                 return err;
3919
3920         ohci_resume_iso_dma(ohci);
3921
3922         return 0;
3923 }
3924
3925 static const struct pci_device_id pci_table[] = {
3926         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3927         { }
3928 };
3929
3930 MODULE_DEVICE_TABLE(pci, pci_table);
3931
3932 static SIMPLE_DEV_PM_OPS(pci_pm_ops, pci_suspend, pci_resume);
3933
3934 static struct pci_driver fw_ohci_pci_driver = {
3935         .name           = ohci_driver_name,
3936         .id_table       = pci_table,
3937         .probe          = pci_probe,
3938         .remove         = pci_remove,
3939         .driver.pm      = &pci_pm_ops,
3940 };
3941
3942 static int __init fw_ohci_init(void)
3943 {
3944         selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3945         if (!selfid_workqueue)
3946                 return -ENOMEM;
3947
3948         return pci_register_driver(&fw_ohci_pci_driver);
3949 }
3950
3951 static void __exit fw_ohci_cleanup(void)
3952 {
3953         pci_unregister_driver(&fw_ohci_pci_driver);
3954         destroy_workqueue(selfid_workqueue);
3955 }
3956
3957 module_init(fw_ohci_init);
3958 module_exit(fw_ohci_cleanup);
3959
3960 MODULE_AUTHOR("Kristian Hoegsberg <[email protected]>");
3961 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3962 MODULE_LICENSE("GPL");
3963
3964 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3965 MODULE_ALIAS("ohci1394");