drivers/clk/rockchip/clk-rk3328.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
   4  * Author: Elaine <[email protected]>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/io.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/syscore_ops.h>
  12 #include <dt-bindings/clock/rk3328-cru.h>
  13 #include "clk.h"
  14
  15 #define RK3328_GRF_SOC_CON4             0x410
  16 #define RK3328_GRF_SOC_STATUS0          0x480
  17 #define RK3328_GRF_MAC_CON1             0x904
  18 #define RK3328_GRF_MAC_CON2             0x908
  19
  20 enum rk3328_plls {
  21         apll, dpll, cpll, gpll, npll,
  22 };
  23
  24 static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
  25         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  26         RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
  27         RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
  28         RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
  29         RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
  30         RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
  31         RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
  32         RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
  33         RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
  34         RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
  35         RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
  36         RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
  37         RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
  38         RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
  39         RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
  40         RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
  41         RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
  42         RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  43         RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
  44         RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
  45         RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
  46         RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
  47         RK3036_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0),
  48         RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
  49         RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
  50         RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
  51         RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
  52         RK3036_PLL_RATE(900000000, 4, 300, 2, 1, 1, 0),
  53         RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
  54         RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
  55         RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
  56         RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  57         RK3036_PLL_RATE(800000000, 6, 400, 2, 1, 1, 0),
  58         RK3036_PLL_RATE(700000000, 6, 350, 2, 1, 1, 0),
  59         RK3036_PLL_RATE(696000000, 1, 58, 2, 1, 1, 0),
  60         RK3036_PLL_RATE(600000000, 1, 75, 3, 1, 1, 0),
  61         RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
  62         RK3036_PLL_RATE(504000000, 1, 63, 3, 1, 1, 0),
  63         RK3036_PLL_RATE(500000000, 6, 250, 2, 1, 1, 0),
  64         RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
  65         RK3036_PLL_RATE(312000000, 1, 52, 2, 2, 1, 0),
  66         RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
  67         RK3036_PLL_RATE(96000000, 1, 64, 4, 4, 1, 0),
  68         { /* sentinel */ },
  69 };
  70
  71 static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
  72         /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  73         RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
  74         /* vco = 1016064000 */
  75         RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
  76         /* vco = 983040000 */
  77         RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
  78         /* vco = 983040000 */
  79         RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
  80         /* vco = 860156000 */
  81         RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
  82         /* vco = 903168000 */
  83         RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
  84         /* vco = 819200000 */
  85         { /* sentinel */ },
  86 };
  87
  88 #define RK3328_DIV_ACLKM_MASK           0x7
  89 #define RK3328_DIV_ACLKM_SHIFT          4
  90 #define RK3328_DIV_PCLK_DBG_MASK        0xf
  91 #define RK3328_DIV_PCLK_DBG_SHIFT       0
  92
  93 #define RK3328_CLKSEL1(_aclk_core, _pclk_dbg)                           \
  94 {                                                                       \
  95         .reg = RK3328_CLKSEL_CON(1),                                    \
  96         .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK,         \
  97                              RK3328_DIV_ACLKM_SHIFT) |                  \
  98                HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK,       \
  99                              RK3328_DIV_PCLK_DBG_SHIFT),                \
 100 }
 101
 102 #define RK3328_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg)               \
 103 {                                                                       \
 104         .prate = _prate,                                                \
 105         .divs = {                                                       \
 106                 RK3328_CLKSEL1(_aclk_core, _pclk_dbg),                  \
 107         },                                                              \
 108 }
 109
 110 static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = {
 111         RK3328_CPUCLK_RATE(1800000000, 1, 7),
 112         RK3328_CPUCLK_RATE(1704000000, 1, 7),
 113         RK3328_CPUCLK_RATE(1608000000, 1, 7),
 114         RK3328_CPUCLK_RATE(1512000000, 1, 7),
 115         RK3328_CPUCLK_RATE(1488000000, 1, 5),
 116         RK3328_CPUCLK_RATE(1416000000, 1, 5),
 117         RK3328_CPUCLK_RATE(1392000000, 1, 5),
 118         RK3328_CPUCLK_RATE(1296000000, 1, 5),
 119         RK3328_CPUCLK_RATE(1200000000, 1, 5),
 120         RK3328_CPUCLK_RATE(1104000000, 1, 5),
 121         RK3328_CPUCLK_RATE(1008000000, 1, 5),
 122         RK3328_CPUCLK_RATE(912000000, 1, 5),
 123         RK3328_CPUCLK_RATE(816000000, 1, 3),
 124         RK3328_CPUCLK_RATE(696000000, 1, 3),
 125         RK3328_CPUCLK_RATE(600000000, 1, 3),
 126         RK3328_CPUCLK_RATE(408000000, 1, 1),
 127         RK3328_CPUCLK_RATE(312000000, 1, 1),
 128         RK3328_CPUCLK_RATE(216000000,  1, 1),
 129         RK3328_CPUCLK_RATE(96000000, 1, 1),
 130 };
 131
 132 static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
 133         .core_reg[0] = RK3328_CLKSEL_CON(0),
 134         .div_core_shift[0] = 0,
 135         .div_core_mask[0] = 0x1f,
 136         .num_cores = 1,
 137         .mux_core_alt = 1,
 138         .mux_core_main = 3,
 139         .mux_core_shift = 6,
 140         .mux_core_mask = 0x3,
 141 };
 142
 143 PNAME(mux_pll_p)                = { "xin24m" };
 144
 145 PNAME(mux_2plls_p)              = { "cpll", "gpll" };
 146 PNAME(mux_gpll_cpll_p)          = { "gpll", "cpll" };
 147 PNAME(mux_cpll_gpll_apll_p)     = { "cpll", "gpll", "apll" };
 148 PNAME(mux_2plls_xin24m_p)       = { "cpll", "gpll", "xin24m" };
 149 PNAME(mux_2plls_hdmiphy_p)      = { "cpll", "gpll",
 150                                     "dummy_hdmiphy" };
 151 PNAME(mux_4plls_p)              = { "cpll", "gpll",
 152                                     "dummy_hdmiphy",
 153                                     "usb480m" };
 154 PNAME(mux_2plls_u480m_p)        = { "cpll", "gpll",
 155                                     "usb480m" };
 156 PNAME(mux_2plls_24m_u480m_p)    = { "cpll", "gpll",
 157                                      "xin24m", "usb480m" };
 158
 159 PNAME(mux_ddrphy_p)             = { "dpll", "apll", "cpll" };
 160 PNAME(mux_armclk_p)             = { "apll_core",
 161                                     "gpll_core",
 162                                     "dpll_core",
 163                                     "npll_core"};
 164 PNAME(mux_hdmiphy_p)            = { "hdmi_phy", "xin24m" };
 165 PNAME(mux_usb480m_p)            = { "usb480m_phy",
 166                                     "xin24m" };
 167
 168 PNAME(mux_i2s0_p)               = { "clk_i2s0_div",
 169                                     "clk_i2s0_frac",
 170                                     "xin12m",
 171                                     "xin12m" };
 172 PNAME(mux_i2s1_p)               = { "clk_i2s1_div",
 173                                     "clk_i2s1_frac",
 174                                     "clkin_i2s1",
 175                                     "xin12m" };
 176 PNAME(mux_i2s2_p)               = { "clk_i2s2_div",
 177                                     "clk_i2s2_frac",
 178                                     "clkin_i2s2",
 179                                     "xin12m" };
 180 PNAME(mux_i2s1out_p)            = { "clk_i2s1", "xin12m"};
 181 PNAME(mux_i2s2out_p)            = { "clk_i2s2", "xin12m" };
 182 PNAME(mux_spdif_p)              = { "clk_spdif_div",
 183                                     "clk_spdif_frac",
 184                                     "xin12m",
 185                                     "xin12m" };
 186 PNAME(mux_uart0_p)              = { "clk_uart0_div",
 187                                     "clk_uart0_frac",
 188                                     "xin24m" };
 189 PNAME(mux_uart1_p)              = { "clk_uart1_div",
 190                                     "clk_uart1_frac",
 191                                     "xin24m" };
 192 PNAME(mux_uart2_p)              = { "clk_uart2_div",
 193                                     "clk_uart2_frac",
 194                                     "xin24m" };
 195
 196 PNAME(mux_sclk_cif_p)           = { "clk_cif_src",
 197                                     "xin24m" };
 198 PNAME(mux_dclk_lcdc_p)          = { "hdmiphy",
 199                                     "dclk_lcdc_src" };
 200 PNAME(mux_aclk_peri_pre_p)      = { "cpll_peri",
 201                                     "gpll_peri",
 202                                     "hdmiphy_peri" };
 203 PNAME(mux_ref_usb3otg_src_p)    = { "xin24m",
 204                                     "clk_usb3otg_ref" };
 205 PNAME(mux_xin24m_32k_p)         = { "xin24m",
 206                                     "clk_rtc32k" };
 207 PNAME(mux_mac2io_src_p)         = { "clk_mac2io_src",
 208                                     "gmac_clkin" };
 209 PNAME(mux_mac2phy_src_p)        = { "clk_mac2phy_src",
 210                                     "phy_50m_out" };
 211 PNAME(mux_mac2io_ext_p)         = { "clk_mac2io",
 212                                     "gmac_clkin" };
 213
 214 static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
 215         [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
 216                      0, RK3328_PLL_CON(0),
 217                      RK3328_MODE_CON, 0, 4, 0, rk3328_pll_frac_rates),
 218         [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
 219                      0, RK3328_PLL_CON(8),
 220                      RK3328_MODE_CON, 4, 3, 0, NULL),
 221         [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
 222                      0, RK3328_PLL_CON(16),
 223                      RK3328_MODE_CON, 8, 2, 0, rk3328_pll_rates),
 224         [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
 225                      0, RK3328_PLL_CON(24),
 226                      RK3328_MODE_CON, 12, 1, 0, rk3328_pll_frac_rates),
 227         [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
 228                      0, RK3328_PLL_CON(40),
 229                      RK3328_MODE_CON, 1, 0, 0, rk3328_pll_rates),
 230 };
 231
 232 #define MFLAGS CLK_MUX_HIWORD_MASK
 233 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 234 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 235
 236 static struct rockchip_clk_branch rk3328_i2s0_fracmux __initdata =
 237         MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
 238                         RK3328_CLKSEL_CON(6), 8, 2, MFLAGS);
 239
 240 static struct rockchip_clk_branch rk3328_i2s1_fracmux __initdata =
 241         MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
 242                         RK3328_CLKSEL_CON(8), 8, 2, MFLAGS);
 243
 244 static struct rockchip_clk_branch rk3328_i2s2_fracmux __initdata =
 245         MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
 246                         RK3328_CLKSEL_CON(10), 8, 2, MFLAGS);
 247
 248 static struct rockchip_clk_branch rk3328_spdif_fracmux __initdata =
 249         MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, CLK_SET_RATE_PARENT,
 250                         RK3328_CLKSEL_CON(12), 8, 2, MFLAGS);
 251
 252 static struct rockchip_clk_branch rk3328_uart0_fracmux __initdata =
 253         MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 254                         RK3328_CLKSEL_CON(14), 8, 2, MFLAGS);
 255
 256 static struct rockchip_clk_branch rk3328_uart1_fracmux __initdata =
 257         MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 258                         RK3328_CLKSEL_CON(16), 8, 2, MFLAGS);
 259
 260 static struct rockchip_clk_branch rk3328_uart2_fracmux __initdata =
 261         MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 262                         RK3328_CLKSEL_CON(18), 8, 2, MFLAGS);
 263
 264 static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 265         /*
 266          * Clock-Architecture Diagram 1
 267          */
 268
 269         DIV(0, "clk_24m", "xin24m", CLK_IGNORE_UNUSED,
 270                         RK3328_CLKSEL_CON(2), 8, 5, DFLAGS),
 271         COMPOSITE(SCLK_RTC32K, "clk_rtc32k", mux_2plls_xin24m_p, 0,
 272                         RK3328_CLKSEL_CON(38), 14, 2, MFLAGS, 0, 14, DFLAGS,
 273                         RK3328_CLKGATE_CON(0), 11, GFLAGS),
 274
 275         /* PD_MISC */
 276         MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
 277                         RK3328_MISC_CON, 13, 1, MFLAGS),
 278         MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
 279                         RK3328_MISC_CON, 15, 1, MFLAGS),
 280
 281         /*
 282          * Clock-Architecture Diagram 2
 283          */
 284
 285         /* PD_CORE */
 286         GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
 287                         RK3328_CLKGATE_CON(0), 0, GFLAGS),
 288         GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
 289                         RK3328_CLKGATE_CON(0), 2, GFLAGS),
 290         GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
 291                         RK3328_CLKGATE_CON(0), 1, GFLAGS),
 292         GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
 293                         RK3328_CLKGATE_CON(0), 12, GFLAGS),
 294         COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
 295                         RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 296                         RK3328_CLKGATE_CON(7), 0, GFLAGS),
 297         COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
 298                         RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 299                         RK3328_CLKGATE_CON(7), 1, GFLAGS),
 300         GATE(0, "aclk_core_niu", "aclk_core", 0,
 301                         RK3328_CLKGATE_CON(13), 0, GFLAGS),
 302         GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
 303                         RK3328_CLKGATE_CON(13), 1, GFLAGS),
 304
 305         GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
 306                         RK3328_CLKGATE_CON(7), 2, GFLAGS),
 307
 308         /* PD_GPU */
 309         COMPOSITE(0, "aclk_gpu_pre", mux_4plls_p, 0,
 310                         RK3328_CLKSEL_CON(44), 6, 2, MFLAGS, 0, 5, DFLAGS,
 311                         RK3328_CLKGATE_CON(6), 6, GFLAGS),
 312         GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
 313                         RK3328_CLKGATE_CON(14), 0, GFLAGS),
 314         GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
 315                         RK3328_CLKGATE_CON(14), 1, GFLAGS),
 316
 317         /* PD_DDR */
 318         COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 319                         RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 320                         RK3328_CLKGATE_CON(0), 4, GFLAGS),
 321         GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
 322                         RK3328_CLKGATE_CON(18), 6, GFLAGS),
 323         GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
 324                         RK3328_CLKGATE_CON(18), 5, GFLAGS),
 325         GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
 326                         RK3328_CLKGATE_CON(18), 4, GFLAGS),
 327         GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
 328                         RK3328_CLKGATE_CON(0), 6, GFLAGS),
 329
 330         COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
 331                         RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
 332                         RK3328_CLKGATE_CON(7), 4, GFLAGS),
 333         GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED,
 334                         RK3328_CLKGATE_CON(18), 1, GFLAGS),
 335         GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
 336                         RK3328_CLKGATE_CON(18), 2, GFLAGS),
 337         GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
 338                         RK3328_CLKGATE_CON(18), 3, GFLAGS),
 339         GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
 340                         RK3328_CLKGATE_CON(18), 7, GFLAGS),
 341         GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
 342                         RK3328_CLKGATE_CON(18), 9, GFLAGS),
 343
 344         /*
 345          * Clock-Architecture Diagram 3
 346          */
 347
 348         /* PD_BUS */
 349         COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
 350                         RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
 351                         RK3328_CLKGATE_CON(8), 0, GFLAGS),
 352         COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0,
 353                         RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
 354                         RK3328_CLKGATE_CON(8), 1, GFLAGS),
 355         COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0,
 356                         RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
 357                         RK3328_CLKGATE_CON(8), 2, GFLAGS),
 358         GATE(0, "pclk_bus", "pclk_bus_pre", 0,
 359                         RK3328_CLKGATE_CON(8), 3, GFLAGS),
 360         GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
 361                         RK3328_CLKGATE_CON(8), 4, GFLAGS),
 362
 363         COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
 364                         RK3328_CLKSEL_CON(21), 15, 1, MFLAGS, 8, 5, DFLAGS,
 365                         RK3328_CLKGATE_CON(2), 5, GFLAGS),
 366         GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
 367                         RK3328_CLKGATE_CON(17), 13, GFLAGS),
 368
 369         /* PD_I2S */
 370         COMPOSITE(0, "clk_i2s0_div", mux_2plls_p, 0,
 371                         RK3328_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
 372                         RK3328_CLKGATE_CON(1), 1, GFLAGS),
 373         COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
 374                         RK3328_CLKSEL_CON(7), 0,
 375                         RK3328_CLKGATE_CON(1), 2, GFLAGS,
 376                         &rk3328_i2s0_fracmux),
 377         GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
 378                         RK3328_CLKGATE_CON(1), 3, GFLAGS),
 379
 380         COMPOSITE(0, "clk_i2s1_div", mux_2plls_p, 0,
 381                         RK3328_CLKSEL_CON(8), 15, 1, MFLAGS, 0, 7, DFLAGS,
 382                         RK3328_CLKGATE_CON(1), 4, GFLAGS),
 383         COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
 384                         RK3328_CLKSEL_CON(9), 0,
 385                         RK3328_CLKGATE_CON(1), 5, GFLAGS,
 386                         &rk3328_i2s1_fracmux),
 387         GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
 388                         RK3328_CLKGATE_CON(1), 6, GFLAGS),
 389         COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
 390                         RK3328_CLKSEL_CON(8), 12, 1, MFLAGS,
 391                         RK3328_CLKGATE_CON(1), 7, GFLAGS),
 392
 393         COMPOSITE(0, "clk_i2s2_div", mux_2plls_p, 0,
 394                         RK3328_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 7, DFLAGS,
 395                         RK3328_CLKGATE_CON(1), 8, GFLAGS),
 396         COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
 397                         RK3328_CLKSEL_CON(11), 0,
 398                         RK3328_CLKGATE_CON(1), 9, GFLAGS,
 399                         &rk3328_i2s2_fracmux),
 400         GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
 401                         RK3328_CLKGATE_CON(1), 10, GFLAGS),
 402         COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
 403                         RK3328_CLKSEL_CON(10), 12, 1, MFLAGS,
 404                         RK3328_CLKGATE_CON(1), 11, GFLAGS),
 405
 406         COMPOSITE(0, "clk_spdif_div", mux_2plls_p, 0,
 407                         RK3328_CLKSEL_CON(12), 15, 1, MFLAGS, 0, 7, DFLAGS,
 408                         RK3328_CLKGATE_CON(1), 12, GFLAGS),
 409         COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
 410                         RK3328_CLKSEL_CON(13), 0,
 411                         RK3328_CLKGATE_CON(1), 13, GFLAGS,
 412                         &rk3328_spdif_fracmux),
 413
 414         /* PD_UART */
 415         COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
 416                         RK3328_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
 417                         RK3328_CLKGATE_CON(1), 14, GFLAGS),
 418         COMPOSITE(0, "clk_uart1_div", mux_2plls_u480m_p, 0,
 419                         RK3328_CLKSEL_CON(16), 12, 2, MFLAGS, 0, 7, DFLAGS,
 420                         RK3328_CLKGATE_CON(2), 0, GFLAGS),
 421         COMPOSITE(0, "clk_uart2_div", mux_2plls_u480m_p, 0,
 422                         RK3328_CLKSEL_CON(18), 12, 2, MFLAGS, 0, 7, DFLAGS,
 423                         RK3328_CLKGATE_CON(2), 2, GFLAGS),
 424         COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
 425                         RK3328_CLKSEL_CON(15), 0,
 426                         RK3328_CLKGATE_CON(1), 15, GFLAGS,
 427                         &rk3328_uart0_fracmux),
 428         COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
 429                         RK3328_CLKSEL_CON(17), 0,
 430                         RK3328_CLKGATE_CON(2), 1, GFLAGS,
 431                         &rk3328_uart1_fracmux),
 432         COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
 433                         RK3328_CLKSEL_CON(19), 0,
 434                         RK3328_CLKGATE_CON(2), 3, GFLAGS,
 435                         &rk3328_uart2_fracmux),
 436
 437         /*
 438          * Clock-Architecture Diagram 4
 439          */
 440
 441         COMPOSITE(SCLK_I2C0, "clk_i2c0", mux_2plls_p, 0,
 442                         RK3328_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 7, DFLAGS,
 443                         RK3328_CLKGATE_CON(2), 9, GFLAGS),
 444         COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_2plls_p, 0,
 445                         RK3328_CLKSEL_CON(34), 15, 1, MFLAGS, 8, 7, DFLAGS,
 446                         RK3328_CLKGATE_CON(2), 10, GFLAGS),
 447         COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_2plls_p, 0,
 448                         RK3328_CLKSEL_CON(35), 7, 1, MFLAGS, 0, 7, DFLAGS,
 449                         RK3328_CLKGATE_CON(2), 11, GFLAGS),
 450         COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_2plls_p, 0,
 451                         RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
 452                         RK3328_CLKGATE_CON(2), 12, GFLAGS),
 453         COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
 454                         RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
 455                         RK3328_CLKGATE_CON(2), 4, GFLAGS),
 456         COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
 457                         RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
 458                         RK3328_CLKGATE_CON(2), 6, GFLAGS),
 459         COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "clk_24m", 0,
 460                         RK3328_CLKSEL_CON(23), 0, 10, DFLAGS,
 461                         RK3328_CLKGATE_CON(2), 14, GFLAGS),
 462         COMPOSITE(SCLK_SPI, "clk_spi", mux_2plls_p, 0,
 463                         RK3328_CLKSEL_CON(24), 7, 1, MFLAGS, 0, 7, DFLAGS,
 464                         RK3328_CLKGATE_CON(2), 7, GFLAGS),
 465         COMPOSITE(SCLK_PWM, "clk_pwm", mux_2plls_p, 0,
 466                         RK3328_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 7, DFLAGS,
 467                         RK3328_CLKGATE_CON(2), 8, GFLAGS),
 468         COMPOSITE(SCLK_OTP, "clk_otp", mux_2plls_xin24m_p, 0,
 469                         RK3328_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 6, DFLAGS,
 470                         RK3328_CLKGATE_CON(3), 8, GFLAGS),
 471         COMPOSITE(SCLK_EFUSE, "clk_efuse", mux_2plls_xin24m_p, 0,
 472                         RK3328_CLKSEL_CON(5), 14, 2, MFLAGS, 8, 5, DFLAGS,
 473                         RK3328_CLKGATE_CON(2), 13, GFLAGS),
 474         COMPOSITE(SCLK_PDM, "clk_pdm", mux_cpll_gpll_apll_p, CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
 475                         RK3328_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
 476                         RK3328_CLKGATE_CON(2), 15, GFLAGS),
 477
 478         GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
 479                         RK3328_CLKGATE_CON(8), 5, GFLAGS),
 480         GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
 481                         RK3328_CLKGATE_CON(8), 6, GFLAGS),
 482         GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
 483                         RK3328_CLKGATE_CON(8), 7, GFLAGS),
 484         GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
 485                         RK3328_CLKGATE_CON(8), 8, GFLAGS),
 486         GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
 487                         RK3328_CLKGATE_CON(8), 9, GFLAGS),
 488         GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
 489                         RK3328_CLKGATE_CON(8), 10, GFLAGS),
 490
 491         COMPOSITE(SCLK_WIFI, "clk_wifi", mux_2plls_u480m_p, 0,
 492                         RK3328_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 6, DFLAGS,
 493                         RK3328_CLKGATE_CON(0), 10, GFLAGS),
 494
 495         /*
 496          * Clock-Architecture Diagram 5
 497          */
 498
 499         /* PD_VIDEO */
 500         COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_4plls_p, 0,
 501                         RK3328_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
 502                         RK3328_CLKGATE_CON(6), 0, GFLAGS),
 503         FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
 504                         RK3328_CLKGATE_CON(11), 0, GFLAGS),
 505         GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", CLK_SET_RATE_PARENT,
 506                         RK3328_CLKGATE_CON(24), 0, GFLAGS),
 507         GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
 508                         RK3328_CLKGATE_CON(24), 1, GFLAGS),
 509         GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0,
 510                         RK3328_CLKGATE_CON(24), 2, GFLAGS),
 511         GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0,
 512                         RK3328_CLKGATE_CON(24), 3, GFLAGS),
 513
 514         COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
 515                         RK3328_CLKSEL_CON(48), 14, 2, MFLAGS, 8, 5, DFLAGS,
 516                         RK3328_CLKGATE_CON(6), 1, GFLAGS),
 517
 518         COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_4plls_p, 0,
 519                         RK3328_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
 520                         RK3328_CLKGATE_CON(6), 2, GFLAGS),
 521
 522         COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_4plls_p, 0,
 523                         RK3328_CLKSEL_CON(50), 6, 2, MFLAGS, 0, 5, DFLAGS,
 524                         RK3328_CLKGATE_CON(6), 5, GFLAGS),
 525         FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
 526                         RK3328_CLKGATE_CON(11), 8, GFLAGS),
 527         GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", CLK_SET_RATE_PARENT,
 528                         RK3328_CLKGATE_CON(23), 0, GFLAGS),
 529         GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
 530                         RK3328_CLKGATE_CON(23), 1, GFLAGS),
 531         GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
 532                         RK3328_CLKGATE_CON(23), 2, GFLAGS),
 533         GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
 534                         RK3328_CLKGATE_CON(23), 3, GFLAGS),
 535
 536         COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
 537                         RK3328_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
 538                         RK3328_CLKGATE_CON(6), 3, GFLAGS),
 539         FACTOR_GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 0, 1, 4,
 540                         RK3328_CLKGATE_CON(11), 4, GFLAGS),
 541         GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
 542                         RK3328_CLKGATE_CON(25), 0, GFLAGS),
 543         GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
 544                         RK3328_CLKGATE_CON(25), 1, GFLAGS),
 545         GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
 546                         RK3328_CLKGATE_CON(25), 2, GFLAGS),
 547         GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
 548                         RK3328_CLKGATE_CON(25), 3, GFLAGS),
 549         GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
 550                         RK3328_CLKGATE_CON(25), 4, GFLAGS),
 551         GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
 552                         RK3328_CLKGATE_CON(25), 5, GFLAGS),
 553         GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
 554                         RK3328_CLKGATE_CON(25), 6, GFLAGS),
 555
 556         COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
 557                         RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
 558                         RK3328_CLKGATE_CON(6), 4, GFLAGS),
 559
 560         COMPOSITE(SCLK_VENC_DSP, "sclk_venc_dsp", mux_4plls_p, 0,
 561                         RK3328_CLKSEL_CON(52), 14, 2, MFLAGS, 8, 5, DFLAGS,
 562                         RK3328_CLKGATE_CON(6), 7, GFLAGS),
 563
 564         /*
 565          * Clock-Architecture Diagram 6
 566          */
 567
 568         /* PD_VIO */
 569         COMPOSITE(ACLK_VIO_PRE, "aclk_vio_pre", mux_4plls_p, 0,
 570                         RK3328_CLKSEL_CON(37), 6, 2, MFLAGS, 0, 5, DFLAGS,
 571                         RK3328_CLKGATE_CON(5), 2, GFLAGS),
 572         DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0,
 573                         RK3328_CLKSEL_CON(37), 8, 5, DFLAGS),
 574
 575         COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", mux_4plls_p, 0,
 576                         RK3328_CLKSEL_CON(36), 14, 2, MFLAGS, 8, 5, DFLAGS,
 577                         RK3328_CLKGATE_CON(5), 0, GFLAGS),
 578         COMPOSITE(SCLK_RGA, "clk_rga", mux_4plls_p, 0,
 579                         RK3328_CLKSEL_CON(36), 6, 2, MFLAGS, 0, 5, DFLAGS,
 580                         RK3328_CLKGATE_CON(5), 1, GFLAGS),
 581         COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
 582                         RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
 583                         RK3328_CLKGATE_CON(5), 5, GFLAGS),
 584         GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
 585                         RK3328_CLKGATE_CON(5), 4, GFLAGS),
 586
 587         COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
 588                         RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
 589                         RK3328_CLKGATE_CON(5), 3, GFLAGS),
 590         COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
 591                         RK3328_CLKSEL_CON(42), 5, 1, MFLAGS, 0, 5, DFLAGS),
 592
 593         COMPOSITE(DCLK_LCDC_SRC, "dclk_lcdc_src", mux_gpll_cpll_p, 0,
 594                         RK3328_CLKSEL_CON(40), 0, 1, MFLAGS, 8, 8, DFLAGS,
 595                         RK3328_CLKGATE_CON(5), 6, GFLAGS),
 596         DIV(DCLK_HDMIPHY, "dclk_hdmiphy", "dclk_lcdc_src", 0,
 597                         RK3328_CLKSEL_CON(40), 3, 3, DFLAGS),
 598         MUX(DCLK_LCDC, "dclk_lcdc", mux_dclk_lcdc_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
 599                         RK3328_CLKSEL_CON(40), 1, 1, MFLAGS),
 600
 601         /*
 602          * Clock-Architecture Diagram 7
 603          */
 604
 605         /* PD_PERI */
 606         GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
 607                         RK3328_CLKGATE_CON(4), 0, GFLAGS),
 608         GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
 609                         RK3328_CLKGATE_CON(4), 1, GFLAGS),
 610         GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
 611                         RK3328_CLKGATE_CON(4), 2, GFLAGS),
 612         COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0,
 613                         RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
 614         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
 615                         RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
 616                         RK3328_CLKGATE_CON(10), 2, GFLAGS),
 617         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
 618                         RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
 619                         RK3328_CLKGATE_CON(10), 1, GFLAGS),
 620         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
 621                         RK3328_CLKGATE_CON(10), 0, GFLAGS),
 622
 623         COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
 624                         RK3328_CLKSEL_CON(30), 8, 2, MFLAGS, 0, 8, DFLAGS,
 625                         RK3328_CLKGATE_CON(4), 3, GFLAGS),
 626
 627         COMPOSITE(SCLK_SDIO, "clk_sdio", mux_2plls_24m_u480m_p, 0,
 628                         RK3328_CLKSEL_CON(31), 8, 2, MFLAGS, 0, 8, DFLAGS,
 629                         RK3328_CLKGATE_CON(4), 4, GFLAGS),
 630
 631         COMPOSITE(SCLK_EMMC, "clk_emmc", mux_2plls_24m_u480m_p, 0,
 632                         RK3328_CLKSEL_CON(32), 8, 2, MFLAGS, 0, 8, DFLAGS,
 633                         RK3328_CLKGATE_CON(4), 5, GFLAGS),
 634
 635         COMPOSITE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", mux_2plls_24m_u480m_p, 0,
 636                         RK3328_CLKSEL_CON(43), 8, 2, MFLAGS, 0, 8, DFLAGS,
 637                         RK3328_CLKGATE_CON(4), 10, GFLAGS),
 638
 639         COMPOSITE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", mux_2plls_p, 0,
 640                         RK3328_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 7, DFLAGS,
 641                         RK3328_CLKGATE_CON(4), 9, GFLAGS),
 642
 643         MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_src_p, CLK_SET_RATE_PARENT,
 644                         RK3328_CLKSEL_CON(45), 8, 1, MFLAGS),
 645
 646         GATE(SCLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
 647                         RK3328_CLKGATE_CON(4), 7, GFLAGS),
 648
 649         COMPOSITE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
 650                         RK3328_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 10, DFLAGS,
 651                         RK3328_CLKGATE_CON(4), 8, GFLAGS),
 652
 653         /*
 654          * Clock-Architecture Diagram 8
 655          */
 656
 657         /* PD_GMAC */
 658         COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
 659                         RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
 660                         RK3328_CLKGATE_CON(3), 2, GFLAGS),
 661         COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
 662                         RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
 663                         RK3328_CLKGATE_CON(9), 0, GFLAGS),
 664
 665         COMPOSITE(SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_p, 0,
 666                         RK3328_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 5, DFLAGS,
 667                         RK3328_CLKGATE_CON(3), 1, GFLAGS),
 668         GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0,
 669                         RK3328_CLKGATE_CON(9), 7, GFLAGS),
 670         GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0,
 671                         RK3328_CLKGATE_CON(9), 4, GFLAGS),
 672         GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0,
 673                         RK3328_CLKGATE_CON(9), 5, GFLAGS),
 674         GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0,
 675                         RK3328_CLKGATE_CON(9), 6, GFLAGS),
 676         COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
 677                         RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
 678                         RK3328_CLKGATE_CON(3), 5, GFLAGS),
 679         MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
 680                         RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
 681         MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
 682                         RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
 683
 684         COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
 685                         RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
 686                         RK3328_CLKGATE_CON(3), 0, GFLAGS),
 687         GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0,
 688                         RK3328_CLKGATE_CON(9), 3, GFLAGS),
 689         GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0,
 690                         RK3328_CLKGATE_CON(9), 1, GFLAGS),
 691         COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
 692                         RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
 693                         RK3328_CLKGATE_CON(9), 2, GFLAGS),
 694         MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
 695                         RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
 696
 697         FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
 698
 699         /*
 700          * Clock-Architecture Diagram 9
 701          */
 702
 703         /* PD_VOP */
 704         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
 705         GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS),
 706         GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
 707         GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS),
 708
 709         GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
 710         GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
 711         GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
 712         GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS),
 713
 714         GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
 715         GATE(0, "hclk_vop_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 5, GFLAGS),
 716         GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
 717         GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
 718         GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
 719         GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),
 720         GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS),
 721         GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS),
 722         GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
 723         GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),
 724         GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
 725         GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
 726
 727         /* PD_PERI */
 728         GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
 729         GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
 730
 731         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
 732         GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
 733         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 2, GFLAGS),
 734         GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 15, GFLAGS),
 735         GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
 736         GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
 737         GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
 738         GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),
 739         GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS),
 740         GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS),
 741
 742         /* PD_GMAC */
 743         GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
 744         GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
 745         GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS),
 746         GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
 747         GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
 748         GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS),
 749
 750         /* PD_BUS */
 751         GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS),
 752         GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
 753         GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
 754         GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
 755         GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
 756
 757         GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS),
 758         GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
 759         GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
 760         GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
 761         GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 6, GFLAGS),
 762         GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
 763         GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
 764         GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
 765         GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS),
 766         GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
 767
 768         GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS),
 769         GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
 770         GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
 771         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
 772         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
 773         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
 774         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
 775         GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS),
 776         GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
 777         GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
 778         GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
 779         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 7, GFLAGS),
 780         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 8, GFLAGS),
 781         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 9, GFLAGS),
 782         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
 783         GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
 784         GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
 785         GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
 786         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
 787         GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
 788         GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
 789         GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
 790         GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
 791         GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
 792         GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
 793         GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
 794
 795         /* Watchdog pclk is controlled from the secure GRF */
 796         SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
 797
 798         GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
 799         GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
 800         GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
 801         GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
 802         GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
 803         GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
 804         GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
 805         GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
 806         GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),
 807
 808         /* PD_MMC */
 809         MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
 810             RK3328_SDMMC_CON0, 1),
 811         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
 812             RK3328_SDMMC_CON1, 1),
 813
 814         MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
 815             RK3328_SDIO_CON0, 1),
 816         MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
 817             RK3328_SDIO_CON1, 1),
 818
 819         MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
 820             RK3328_EMMC_CON0, 1),
 821         MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
 822             RK3328_EMMC_CON1, 1),
 823
 824         MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
 825             RK3328_SDMMC_EXT_CON0, 1),
 826         MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
 827             RK3328_SDMMC_EXT_CON1, 1),
 828 };
 829
 830 static const char *const rk3328_critical_clocks[] __initconst = {
 831         "aclk_bus",
 832         "aclk_bus_niu",
 833         "pclk_bus",
 834         "pclk_bus_niu",
 835         "hclk_bus",
 836         "hclk_bus_niu",
 837         "aclk_peri",
 838         "hclk_peri",
 839         "hclk_peri_niu",
 840         "pclk_peri",
 841         "pclk_peri_niu",
 842         "pclk_dbg",
 843         "aclk_core_niu",
 844         "aclk_gic400",
 845         "aclk_intmem",
 846         "hclk_rom",
 847         "pclk_grf",
 848         "pclk_cru",
 849         "pclk_sgrf",
 850         "pclk_timer0",
 851         "clk_timer0",
 852         "pclk_ddr_msch",
 853         "pclk_ddr_mon",
 854         "pclk_ddr_grf",
 855         "clk_ddrupctl",
 856         "clk_ddrmsch",
 857         "hclk_ahb1tom",
 858         "clk_jtag",
 859         "pclk_ddrphy",
 860         "pclk_pmu",
 861         "hclk_otg_pmu",
 862         "aclk_rga_niu",
 863         "pclk_vio_h2p",
 864         "hclk_vio_h2p",
 865         "aclk_vio_niu",
 866         "hclk_vio_niu",
 867         "aclk_vop_niu",
 868         "hclk_vop_niu",
 869         "aclk_gpu_niu",
 870         "aclk_rkvdec_niu",
 871         "hclk_rkvdec_niu",
 872         "aclk_vpu_niu",
 873         "hclk_vpu_niu",
 874         "aclk_rkvenc_niu",
 875         "hclk_rkvenc_niu",
 876         "aclk_gmac_niu",
 877         "pclk_gmac_niu",
 878         "pclk_phy_niu",
 879 };
 880
 881 static void __init rk3328_clk_init(struct device_node *np)
 882 {
 883         struct rockchip_clk_provider *ctx;
 884         unsigned long clk_nr_clks;
 885         void __iomem *reg_base;
 886
 887         reg_base = of_iomap(np, 0);
 888         if (!reg_base) {
 889                 pr_err("%s: could not map cru region\n", __func__);
 890                 return;
 891         }
 892
 893         clk_nr_clks = rockchip_clk_find_max_clk_id(rk3328_clk_branches,
 894                                                    ARRAY_SIZE(rk3328_clk_branches)) + 1;
 895         ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
 896         if (IS_ERR(ctx)) {
 897                 pr_err("%s: rockchip clk init failed\n", __func__);
 898                 iounmap(reg_base);
 899                 return;
 900         }
 901
 902         rockchip_clk_register_plls(ctx, rk3328_pll_clks,
 903                                    ARRAY_SIZE(rk3328_pll_clks),
 904                                    RK3328_GRF_SOC_STATUS0);
 905         rockchip_clk_register_branches(ctx, rk3328_clk_branches,
 906                                        ARRAY_SIZE(rk3328_clk_branches));
 907         rockchip_clk_protect_critical(rk3328_critical_clocks,
 908                                       ARRAY_SIZE(rk3328_critical_clocks));
 909
 910         rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
 911                                      mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 912                                      &rk3328_cpuclk_data, rk3328_cpuclk_rates,
 913                                      ARRAY_SIZE(rk3328_cpuclk_rates));
 914
 915         rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
 916                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 917
 918         rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
 919
 920         rockchip_clk_of_add_provider(np, ctx);
 921 }
 922 CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);