drivers/clk/qcom/mmcc-msm8960.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/delay.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/property.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset-controller.h>
  18
  19 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
  20 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
  21
  22 #include "common.h"
  23 #include "clk-regmap.h"
  24 #include "clk-pll.h"
  25 #include "clk-rcg.h"
  26 #include "clk-branch.h"
  27 #include "reset.h"
  28
  29 enum {
  30         P_PXO,
  31         P_PLL8,
  32         P_PLL2,
  33         P_PLL3,
  34         P_PLL15,
  35         P_HDMI_PLL,
  36         P_DSI1_PLL_DSICLK,
  37         P_DSI2_PLL_DSICLK,
  38         P_DSI1_PLL_BYTECLK,
  39         P_DSI2_PLL_BYTECLK,
  40         P_LVDS_PLL,
  41 };
  42
  43 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
  44
  45 static struct clk_pll pll2 = {
  46         .l_reg = 0x320,
  47         .m_reg = 0x324,
  48         .n_reg = 0x328,
  49         .config_reg = 0x32c,
  50         .mode_reg = 0x31c,
  51         .status_reg = 0x334,
  52         .status_bit = 16,
  53         .clkr.hw.init = &(struct clk_init_data){
  54                 .name = "pll2",
  55                 .parent_data = (const struct clk_parent_data[]){
  56                         { .fw_name = "pxo", .name = "pxo_board" },
  57                 },
  58                 .num_parents = 1,
  59                 .ops = &clk_pll_ops,
  60         },
  61 };
  62
  63 static struct clk_pll pll15 = {
  64         .l_reg = 0x33c,
  65         .m_reg = 0x340,
  66         .n_reg = 0x344,
  67         .config_reg = 0x348,
  68         .mode_reg = 0x338,
  69         .status_reg = 0x350,
  70         .status_bit = 16,
  71         .clkr.hw.init = &(struct clk_init_data){
  72                 .name = "pll15",
  73                 .parent_data = (const struct clk_parent_data[]){
  74                         { .fw_name = "pxo", .name = "pxo_board" },
  75                 },
  76                 .num_parents = 1,
  77                 .ops = &clk_pll_ops,
  78         },
  79 };
  80
  81 static const struct pll_config pll15_config = {
  82         .l = 33,
  83         .m = 1,
  84         .n = 3,
  85         .vco_val = 0x2 << 16,
  86         .vco_mask = 0x3 << 16,
  87         .pre_div_val = 0x0,
  88         .pre_div_mask = BIT(19),
  89         .post_div_val = 0x0,
  90         .post_div_mask = 0x3 << 20,
  91         .mn_ena_mask = BIT(22),
  92         .main_output_mask = BIT(23),
  93 };
  94
  95 static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
  96         { P_PXO, 0 },
  97         { P_PLL8, 2 },
  98         { P_PLL2, 1 }
  99 };
 100
 101 static const struct clk_parent_data mmcc_pxo_pll8_pll2[] = {
 102         { .fw_name = "pxo", .name = "pxo_board" },
 103         { .fw_name = "pll8_vote", .name = "pll8_vote" },
 104         { .hw = &pll2.clkr.hw },
 105 };
 106
 107 static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
 108         { P_PXO, 0 },
 109         { P_PLL8, 2 },
 110         { P_PLL2, 1 },
 111         { P_PLL3, 3 }
 112 };
 113
 114 static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll15[] = {
 115         { .fw_name = "pxo", .name = "pxo_board" },
 116         { .fw_name = "pll8_vote", .name = "pll8_vote" },
 117         { .hw = &pll2.clkr.hw },
 118         { .hw = &pll15.clkr.hw },
 119 };
 120
 121 static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
 122         { P_PXO, 0 },
 123         { P_PLL8, 2 },
 124         { P_PLL2, 1 },
 125         { P_PLL15, 3 }
 126 };
 127
 128 static const struct clk_parent_data mmcc_pxo_pll8_pll2_pll3[] = {
 129         { .fw_name = "pxo", .name = "pxo_board" },
 130         { .fw_name = "pll8_vote", .name = "pll8_vote" },
 131         { .hw = &pll2.clkr.hw },
 132         { .fw_name = "pll3", .name = "pll3" },
 133 };
 134
 135 static const struct parent_map mmcc_pxo_dsi2_dsi1_map[] = {
 136         { P_PXO, 0 },
 137         { P_DSI2_PLL_DSICLK, 1 },
 138         { P_DSI1_PLL_DSICLK, 3 },
 139 };
 140
 141 static const struct clk_parent_data mmcc_pxo_dsi2_dsi1[] = {
 142         { .fw_name = "pxo", .name = "pxo_board" },
 143         { .fw_name = "dsi2pll", .name = "dsi2pll" },
 144         { .fw_name = "dsi1pll", .name = "dsi1pll" },
 145 };
 146
 147 static const struct parent_map mmcc_pxo_dsi2_dsi1_lvds_map[] = {
 148         { P_PXO, 0 },
 149         { P_DSI2_PLL_DSICLK, 1 },
 150         { P_LVDS_PLL, 2 },
 151         { P_DSI1_PLL_DSICLK, 3 },
 152 };
 153
 154 static const struct clk_parent_data mmcc_pxo_dsi2_dsi1_lvds[] = {
 155         { .fw_name = "pxo", .name = "pxo_board" },
 156         { .fw_name = "dsi2pll", .name = "dsi2pll" },
 157         { .fw_name = "lvdspll", .name = "mpd4_lvds_pll" },
 158         { .fw_name = "dsi1pll", .name = "dsi1pll" },
 159 };
 160
 161 static const struct parent_map mmcc_pxo_dsi1_dsi2_byte_map[] = {
 162         { P_PXO, 0 },
 163         { P_DSI1_PLL_BYTECLK, 1 },
 164         { P_DSI2_PLL_BYTECLK, 2 },
 165 };
 166
 167 static const struct clk_parent_data mmcc_pxo_dsi1_dsi2_byte[] = {
 168         { .fw_name = "pxo", .name = "pxo_board" },
 169         { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" },
 170         { .fw_name = "dsi2pllbyte", .name = "dsi2pllbyte" },
 171 };
 172
 173 static const struct freq_tbl clk_tbl_cam[] = {
 174         {   6000000, P_PLL8, 4, 1, 16 },
 175         {   8000000, P_PLL8, 4, 1, 12 },
 176         {  12000000, P_PLL8, 4, 1,  8 },
 177         {  16000000, P_PLL8, 4, 1,  6 },
 178         {  19200000, P_PLL8, 4, 1,  5 },
 179         {  24000000, P_PLL8, 4, 1,  4 },
 180         {  32000000, P_PLL8, 4, 1,  3 },
 181         {  48000000, P_PLL8, 4, 1,  2 },
 182         {  64000000, P_PLL8, 3, 1,  2 },
 183         {  96000000, P_PLL8, 4, 0,  0 },
 184         { 128000000, P_PLL8, 3, 0,  0 },
 185         { }
 186 };
 187
 188 static struct clk_rcg camclk0_src = {
 189         .ns_reg = 0x0148,
 190         .md_reg = 0x0144,
 191         .mn = {
 192                 .mnctr_en_bit = 5,
 193                 .mnctr_reset_bit = 8,
 194                 .reset_in_cc = true,
 195                 .mnctr_mode_shift = 6,
 196                 .n_val_shift = 24,
 197                 .m_val_shift = 8,
 198                 .width = 8,
 199         },
 200         .p = {
 201                 .pre_div_shift = 14,
 202                 .pre_div_width = 2,
 203         },
 204         .s = {
 205                 .src_sel_shift = 0,
 206                 .parent_map = mmcc_pxo_pll8_pll2_map,
 207         },
 208         .freq_tbl = clk_tbl_cam,
 209         .clkr = {
 210                 .enable_reg = 0x0140,
 211                 .enable_mask = BIT(2),
 212                 .hw.init = &(struct clk_init_data){
 213                         .name = "camclk0_src",
 214                         .parent_data = mmcc_pxo_pll8_pll2,
 215                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 216                         .ops = &clk_rcg_ops,
 217                 },
 218         },
 219 };
 220
 221 static struct clk_branch camclk0_clk = {
 222         .halt_reg = 0x01e8,
 223         .halt_bit = 15,
 224         .clkr = {
 225                 .enable_reg = 0x0140,
 226                 .enable_mask = BIT(0),
 227                 .hw.init = &(struct clk_init_data){
 228                         .name = "camclk0_clk",
 229                         .parent_hws = (const struct clk_hw*[]){
 230                                 &camclk0_src.clkr.hw
 231                         },
 232                         .num_parents = 1,
 233                         .ops = &clk_branch_ops,
 234                 },
 235         },
 236
 237 };
 238
 239 static struct clk_rcg camclk1_src = {
 240         .ns_reg = 0x015c,
 241         .md_reg = 0x0158,
 242         .mn = {
 243                 .mnctr_en_bit = 5,
 244                 .mnctr_reset_bit = 8,
 245                 .reset_in_cc = true,
 246                 .mnctr_mode_shift = 6,
 247                 .n_val_shift = 24,
 248                 .m_val_shift = 8,
 249                 .width = 8,
 250         },
 251         .p = {
 252                 .pre_div_shift = 14,
 253                 .pre_div_width = 2,
 254         },
 255         .s = {
 256                 .src_sel_shift = 0,
 257                 .parent_map = mmcc_pxo_pll8_pll2_map,
 258         },
 259         .freq_tbl = clk_tbl_cam,
 260         .clkr = {
 261                 .enable_reg = 0x0154,
 262                 .enable_mask = BIT(2),
 263                 .hw.init = &(struct clk_init_data){
 264                         .name = "camclk1_src",
 265                         .parent_data = mmcc_pxo_pll8_pll2,
 266                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 267                         .ops = &clk_rcg_ops,
 268                 },
 269         },
 270 };
 271
 272 static struct clk_branch camclk1_clk = {
 273         .halt_reg = 0x01e8,
 274         .halt_bit = 16,
 275         .clkr = {
 276                 .enable_reg = 0x0154,
 277                 .enable_mask = BIT(0),
 278                 .hw.init = &(struct clk_init_data){
 279                         .name = "camclk1_clk",
 280                         .parent_hws = (const struct clk_hw*[]){
 281                                 &camclk1_src.clkr.hw
 282                         },
 283                         .num_parents = 1,
 284                         .ops = &clk_branch_ops,
 285                 },
 286         },
 287
 288 };
 289
 290 static struct clk_rcg camclk2_src = {
 291         .ns_reg = 0x0228,
 292         .md_reg = 0x0224,
 293         .mn = {
 294                 .mnctr_en_bit = 5,
 295                 .mnctr_reset_bit = 8,
 296                 .reset_in_cc = true,
 297                 .mnctr_mode_shift = 6,
 298                 .n_val_shift = 24,
 299                 .m_val_shift = 8,
 300                 .width = 8,
 301         },
 302         .p = {
 303                 .pre_div_shift = 14,
 304                 .pre_div_width = 2,
 305         },
 306         .s = {
 307                 .src_sel_shift = 0,
 308                 .parent_map = mmcc_pxo_pll8_pll2_map,
 309         },
 310         .freq_tbl = clk_tbl_cam,
 311         .clkr = {
 312                 .enable_reg = 0x0220,
 313                 .enable_mask = BIT(2),
 314                 .hw.init = &(struct clk_init_data){
 315                         .name = "camclk2_src",
 316                         .parent_data = mmcc_pxo_pll8_pll2,
 317                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 318                         .ops = &clk_rcg_ops,
 319                 },
 320         },
 321 };
 322
 323 static struct clk_branch camclk2_clk = {
 324         .halt_reg = 0x01e8,
 325         .halt_bit = 16,
 326         .clkr = {
 327                 .enable_reg = 0x0220,
 328                 .enable_mask = BIT(0),
 329                 .hw.init = &(struct clk_init_data){
 330                         .name = "camclk2_clk",
 331                         .parent_hws = (const struct clk_hw*[]){
 332                                 &camclk2_src.clkr.hw
 333                         },
 334                         .num_parents = 1,
 335                         .ops = &clk_branch_ops,
 336                 },
 337         },
 338
 339 };
 340
 341 static const struct freq_tbl clk_tbl_csi[] = {
 342         {  27000000, P_PXO,  1, 0, 0 },
 343         {  85330000, P_PLL8, 1, 2, 9 },
 344         { 177780000, P_PLL2, 1, 2, 9 },
 345         { }
 346 };
 347
 348 static struct clk_rcg csi0_src = {
 349         .ns_reg = 0x0048,
 350         .md_reg = 0x0044,
 351         .mn = {
 352                 .mnctr_en_bit = 5,
 353                 .mnctr_reset_bit = 7,
 354                 .mnctr_mode_shift = 6,
 355                 .n_val_shift = 24,
 356                 .m_val_shift = 8,
 357                 .width = 8,
 358         },
 359         .p = {
 360                 .pre_div_shift = 14,
 361                 .pre_div_width = 2,
 362         },
 363         .s = {
 364                 .src_sel_shift = 0,
 365                 .parent_map = mmcc_pxo_pll8_pll2_map,
 366         },
 367         .freq_tbl = clk_tbl_csi,
 368         .clkr = {
 369                 .enable_reg = 0x0040,
 370                 .enable_mask = BIT(2),
 371                 .hw.init = &(struct clk_init_data){
 372                         .name = "csi0_src",
 373                         .parent_data = mmcc_pxo_pll8_pll2,
 374                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 375                         .ops = &clk_rcg_ops,
 376                 },
 377         },
 378 };
 379
 380 static struct clk_branch csi0_clk = {
 381         .halt_reg = 0x01cc,
 382         .halt_bit = 13,
 383         .clkr = {
 384                 .enable_reg = 0x0040,
 385                 .enable_mask = BIT(0),
 386                 .hw.init = &(struct clk_init_data){
 387                         .parent_hws = (const struct clk_hw*[]){
 388                                 &csi0_src.clkr.hw
 389                         },
 390                         .num_parents = 1,
 391                         .name = "csi0_clk",
 392                         .ops = &clk_branch_ops,
 393                         .flags = CLK_SET_RATE_PARENT,
 394                 },
 395         },
 396 };
 397
 398 static struct clk_branch csi0_phy_clk = {
 399         .halt_reg = 0x01e8,
 400         .halt_bit = 9,
 401         .clkr = {
 402                 .enable_reg = 0x0040,
 403                 .enable_mask = BIT(8),
 404                 .hw.init = &(struct clk_init_data){
 405                         .parent_hws = (const struct clk_hw*[]){
 406                                 &csi0_src.clkr.hw
 407                         },
 408                         .num_parents = 1,
 409                         .name = "csi0_phy_clk",
 410                         .ops = &clk_branch_ops,
 411                         .flags = CLK_SET_RATE_PARENT,
 412                 },
 413         },
 414 };
 415
 416 static struct clk_rcg csi1_src = {
 417         .ns_reg = 0x0010,
 418         .md_reg = 0x0028,
 419         .mn = {
 420                 .mnctr_en_bit = 5,
 421                 .mnctr_reset_bit = 7,
 422                 .mnctr_mode_shift = 6,
 423                 .n_val_shift = 24,
 424                 .m_val_shift = 8,
 425                 .width = 8,
 426         },
 427         .p = {
 428                 .pre_div_shift = 14,
 429                 .pre_div_width = 2,
 430         },
 431         .s = {
 432                 .src_sel_shift = 0,
 433                 .parent_map = mmcc_pxo_pll8_pll2_map,
 434         },
 435         .freq_tbl = clk_tbl_csi,
 436         .clkr = {
 437                 .enable_reg = 0x0024,
 438                 .enable_mask = BIT(2),
 439                 .hw.init = &(struct clk_init_data){
 440                         .name = "csi1_src",
 441                         .parent_data = mmcc_pxo_pll8_pll2,
 442                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 443                         .ops = &clk_rcg_ops,
 444                 },
 445         },
 446 };
 447
 448 static struct clk_branch csi1_clk = {
 449         .halt_reg = 0x01cc,
 450         .halt_bit = 14,
 451         .clkr = {
 452                 .enable_reg = 0x0024,
 453                 .enable_mask = BIT(0),
 454                 .hw.init = &(struct clk_init_data){
 455                         .parent_hws = (const struct clk_hw*[]){
 456                                 &csi1_src.clkr.hw
 457                         },
 458                         .num_parents = 1,
 459                         .name = "csi1_clk",
 460                         .ops = &clk_branch_ops,
 461                         .flags = CLK_SET_RATE_PARENT,
 462                 },
 463         },
 464 };
 465
 466 static struct clk_branch csi1_phy_clk = {
 467         .halt_reg = 0x01e8,
 468         .halt_bit = 10,
 469         .clkr = {
 470                 .enable_reg = 0x0024,
 471                 .enable_mask = BIT(8),
 472                 .hw.init = &(struct clk_init_data){
 473                         .parent_hws = (const struct clk_hw*[]){
 474                                 &csi1_src.clkr.hw
 475                         },
 476                         .num_parents = 1,
 477                         .name = "csi1_phy_clk",
 478                         .ops = &clk_branch_ops,
 479                         .flags = CLK_SET_RATE_PARENT,
 480                 },
 481         },
 482 };
 483
 484 static struct clk_rcg csi2_src = {
 485         .ns_reg = 0x0234,
 486         .md_reg = 0x022c,
 487         .mn = {
 488                 .mnctr_en_bit = 5,
 489                 .mnctr_reset_bit = 7,
 490                 .mnctr_mode_shift = 6,
 491                 .n_val_shift = 24,
 492                 .m_val_shift = 8,
 493                 .width = 8,
 494         },
 495         .p = {
 496                 .pre_div_shift = 14,
 497                 .pre_div_width = 2,
 498         },
 499         .s = {
 500                 .src_sel_shift = 0,
 501                 .parent_map = mmcc_pxo_pll8_pll2_map,
 502         },
 503         .freq_tbl = clk_tbl_csi,
 504         .clkr = {
 505                 .enable_reg = 0x022c,
 506                 .enable_mask = BIT(2),
 507                 .hw.init = &(struct clk_init_data){
 508                         .name = "csi2_src",
 509                         .parent_data = mmcc_pxo_pll8_pll2,
 510                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 511                         .ops = &clk_rcg_ops,
 512                 },
 513         },
 514 };
 515
 516 static struct clk_branch csi2_clk = {
 517         .halt_reg = 0x01cc,
 518         .halt_bit = 29,
 519         .clkr = {
 520                 .enable_reg = 0x022c,
 521                 .enable_mask = BIT(0),
 522                 .hw.init = &(struct clk_init_data){
 523                         .parent_hws = (const struct clk_hw*[]){
 524                                 &csi2_src.clkr.hw
 525                         },
 526                         .num_parents = 1,
 527                         .name = "csi2_clk",
 528                         .ops = &clk_branch_ops,
 529                         .flags = CLK_SET_RATE_PARENT,
 530                 },
 531         },
 532 };
 533
 534 static struct clk_branch csi2_phy_clk = {
 535         .halt_reg = 0x01e8,
 536         .halt_bit = 29,
 537         .clkr = {
 538                 .enable_reg = 0x022c,
 539                 .enable_mask = BIT(8),
 540                 .hw.init = &(struct clk_init_data){
 541                         .parent_hws = (const struct clk_hw*[]){
 542                                 &csi2_src.clkr.hw
 543                         },
 544                         .num_parents = 1,
 545                         .name = "csi2_phy_clk",
 546                         .ops = &clk_branch_ops,
 547                         .flags = CLK_SET_RATE_PARENT,
 548                 },
 549         },
 550 };
 551
 552 struct clk_pix_rdi {
 553         u32 s_reg;
 554         u32 s_mask;
 555         u32 s2_reg;
 556         u32 s2_mask;
 557         struct clk_regmap clkr;
 558 };
 559
 560 #define to_clk_pix_rdi(_hw) \
 561         container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
 562
 563 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
 564 {
 565         int i;
 566         int ret = 0;
 567         u32 val;
 568         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 569         int num_parents = clk_hw_get_num_parents(hw);
 570
 571         /*
 572          * These clocks select three inputs via two muxes. One mux selects
 573          * between csi0 and csi1 and the second mux selects between that mux's
 574          * output and csi2. The source and destination selections for each
 575          * mux must be clocking for the switch to succeed so just turn on
 576          * all three sources because it's easier than figuring out what source
 577          * needs to be on at what time.
 578          */
 579         for (i = 0; i < num_parents; i++) {
 580                 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 581                 ret = clk_prepare_enable(p->clk);
 582                 if (ret)
 583                         goto err;
 584         }
 585
 586         if (index == 2)
 587                 val = rdi->s2_mask;
 588         else
 589                 val = 0;
 590         regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
 591         /*
 592          * Wait at least 6 cycles of slowest clock
 593          * for the glitch-free MUX to fully switch sources.
 594          */
 595         udelay(1);
 596
 597         if (index == 1)
 598                 val = rdi->s_mask;
 599         else
 600                 val = 0;
 601         regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
 602         /*
 603          * Wait at least 6 cycles of slowest clock
 604          * for the glitch-free MUX to fully switch sources.
 605          */
 606         udelay(1);
 607
 608 err:
 609         for (i--; i >= 0; i--) {
 610                 struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
 611                 clk_disable_unprepare(p->clk);
 612         }
 613
 614         return ret;
 615 }
 616
 617 static u8 pix_rdi_get_parent(struct clk_hw *hw)
 618 {
 619         u32 val;
 620         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 621
 622
 623         regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
 624         if (val & rdi->s2_mask)
 625                 return 2;
 626
 627         regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
 628         if (val & rdi->s_mask)
 629                 return 1;
 630
 631         return 0;
 632 }
 633
 634 static const struct clk_ops clk_ops_pix_rdi = {
 635         .enable = clk_enable_regmap,
 636         .disable = clk_disable_regmap,
 637         .set_parent = pix_rdi_set_parent,
 638         .get_parent = pix_rdi_get_parent,
 639         .determine_rate = __clk_mux_determine_rate,
 640 };
 641
 642 static const struct clk_hw *pix_rdi_parents[] = {
 643         &csi0_clk.clkr.hw,
 644         &csi1_clk.clkr.hw,
 645         &csi2_clk.clkr.hw,
 646 };
 647
 648 static struct clk_pix_rdi csi_pix_clk = {
 649         .s_reg = 0x0058,
 650         .s_mask = BIT(25),
 651         .s2_reg = 0x0238,
 652         .s2_mask = BIT(13),
 653         .clkr = {
 654                 .enable_reg = 0x0058,
 655                 .enable_mask = BIT(26),
 656                 .hw.init = &(struct clk_init_data){
 657                         .name = "csi_pix_clk",
 658                         .parent_hws = pix_rdi_parents,
 659                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 660                         .ops = &clk_ops_pix_rdi,
 661                 },
 662         },
 663 };
 664
 665 static struct clk_pix_rdi csi_pix1_clk = {
 666         .s_reg = 0x0238,
 667         .s_mask = BIT(8),
 668         .s2_reg = 0x0238,
 669         .s2_mask = BIT(9),
 670         .clkr = {
 671                 .enable_reg = 0x0238,
 672                 .enable_mask = BIT(10),
 673                 .hw.init = &(struct clk_init_data){
 674                         .name = "csi_pix1_clk",
 675                         .parent_hws = pix_rdi_parents,
 676                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 677                         .ops = &clk_ops_pix_rdi,
 678                 },
 679         },
 680 };
 681
 682 static struct clk_pix_rdi csi_rdi_clk = {
 683         .s_reg = 0x0058,
 684         .s_mask = BIT(12),
 685         .s2_reg = 0x0238,
 686         .s2_mask = BIT(12),
 687         .clkr = {
 688                 .enable_reg = 0x0058,
 689                 .enable_mask = BIT(13),
 690                 .hw.init = &(struct clk_init_data){
 691                         .name = "csi_rdi_clk",
 692                         .parent_hws = pix_rdi_parents,
 693                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 694                         .ops = &clk_ops_pix_rdi,
 695                 },
 696         },
 697 };
 698
 699 static struct clk_pix_rdi csi_rdi1_clk = {
 700         .s_reg = 0x0238,
 701         .s_mask = BIT(0),
 702         .s2_reg = 0x0238,
 703         .s2_mask = BIT(1),
 704         .clkr = {
 705                 .enable_reg = 0x0238,
 706                 .enable_mask = BIT(2),
 707                 .hw.init = &(struct clk_init_data){
 708                         .name = "csi_rdi1_clk",
 709                         .parent_hws = pix_rdi_parents,
 710                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 711                         .ops = &clk_ops_pix_rdi,
 712                 },
 713         },
 714 };
 715
 716 static struct clk_pix_rdi csi_rdi2_clk = {
 717         .s_reg = 0x0238,
 718         .s_mask = BIT(4),
 719         .s2_reg = 0x0238,
 720         .s2_mask = BIT(5),
 721         .clkr = {
 722                 .enable_reg = 0x0238,
 723                 .enable_mask = BIT(6),
 724                 .hw.init = &(struct clk_init_data){
 725                         .name = "csi_rdi2_clk",
 726                         .parent_hws = pix_rdi_parents,
 727                         .num_parents = ARRAY_SIZE(pix_rdi_parents),
 728                         .ops = &clk_ops_pix_rdi,
 729                 },
 730         },
 731 };
 732
 733 static const struct freq_tbl clk_tbl_csiphytimer[] = {
 734         {  85330000, P_PLL8, 1, 2, 9 },
 735         { 177780000, P_PLL2, 1, 2, 9 },
 736         { }
 737 };
 738
 739 static struct clk_rcg csiphytimer_src = {
 740         .ns_reg = 0x0168,
 741         .md_reg = 0x0164,
 742         .mn = {
 743                 .mnctr_en_bit = 5,
 744                 .mnctr_reset_bit = 8,
 745                 .reset_in_cc = true,
 746                 .mnctr_mode_shift = 6,
 747                 .n_val_shift = 24,
 748                 .m_val_shift = 8,
 749                 .width = 8,
 750         },
 751         .p = {
 752                 .pre_div_shift = 14,
 753                 .pre_div_width = 2,
 754         },
 755         .s = {
 756                 .src_sel_shift = 0,
 757                 .parent_map = mmcc_pxo_pll8_pll2_map,
 758         },
 759         .freq_tbl = clk_tbl_csiphytimer,
 760         .clkr = {
 761                 .enable_reg = 0x0160,
 762                 .enable_mask = BIT(2),
 763                 .hw.init = &(struct clk_init_data){
 764                         .name = "csiphytimer_src",
 765                         .parent_data = mmcc_pxo_pll8_pll2,
 766                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 767                         .ops = &clk_rcg_ops,
 768                 },
 769         },
 770 };
 771
 772 static struct clk_branch csiphy0_timer_clk = {
 773         .halt_reg = 0x01e8,
 774         .halt_bit = 17,
 775         .clkr = {
 776                 .enable_reg = 0x0160,
 777                 .enable_mask = BIT(0),
 778                 .hw.init = &(struct clk_init_data){
 779                         .parent_hws = (const struct clk_hw*[]){
 780                                 &csiphytimer_src.clkr.hw,
 781                         },
 782                         .num_parents = 1,
 783                         .name = "csiphy0_timer_clk",
 784                         .ops = &clk_branch_ops,
 785                         .flags = CLK_SET_RATE_PARENT,
 786                 },
 787         },
 788 };
 789
 790 static struct clk_branch csiphy1_timer_clk = {
 791         .halt_reg = 0x01e8,
 792         .halt_bit = 18,
 793         .clkr = {
 794                 .enable_reg = 0x0160,
 795                 .enable_mask = BIT(9),
 796                 .hw.init = &(struct clk_init_data){
 797                         .parent_hws = (const struct clk_hw*[]){
 798                                 &csiphytimer_src.clkr.hw,
 799                         },
 800                         .num_parents = 1,
 801                         .name = "csiphy1_timer_clk",
 802                         .ops = &clk_branch_ops,
 803                         .flags = CLK_SET_RATE_PARENT,
 804                 },
 805         },
 806 };
 807
 808 static struct clk_branch csiphy2_timer_clk = {
 809         .halt_reg = 0x01e8,
 810         .halt_bit = 30,
 811         .clkr = {
 812                 .enable_reg = 0x0160,
 813                 .enable_mask = BIT(11),
 814                 .hw.init = &(struct clk_init_data){
 815                         .parent_hws = (const struct clk_hw*[]){
 816                                 &csiphytimer_src.clkr.hw,
 817                         },
 818                         .num_parents = 1,
 819                         .name = "csiphy2_timer_clk",
 820                         .ops = &clk_branch_ops,
 821                         .flags = CLK_SET_RATE_PARENT,
 822                 },
 823         },
 824 };
 825
 826 static const struct freq_tbl clk_tbl_gfx2d[] = {
 827         F_MN( 27000000, P_PXO,  1,  0),
 828         F_MN( 48000000, P_PLL8, 1,  8),
 829         F_MN( 54857000, P_PLL8, 1,  7),
 830         F_MN( 64000000, P_PLL8, 1,  6),
 831         F_MN( 76800000, P_PLL8, 1,  5),
 832         F_MN( 96000000, P_PLL8, 1,  4),
 833         F_MN(128000000, P_PLL8, 1,  3),
 834         F_MN(145455000, P_PLL2, 2, 11),
 835         F_MN(160000000, P_PLL2, 1,  5),
 836         F_MN(177778000, P_PLL2, 2,  9),
 837         F_MN(200000000, P_PLL2, 1,  4),
 838         F_MN(228571000, P_PLL2, 2,  7),
 839         { }
 840 };
 841
 842 static struct clk_dyn_rcg gfx2d0_src = {
 843         .ns_reg[0] = 0x0070,
 844         .ns_reg[1] = 0x0070,
 845         .md_reg[0] = 0x0064,
 846         .md_reg[1] = 0x0068,
 847         .bank_reg = 0x0060,
 848         .mn[0] = {
 849                 .mnctr_en_bit = 8,
 850                 .mnctr_reset_bit = 25,
 851                 .mnctr_mode_shift = 9,
 852                 .n_val_shift = 20,
 853                 .m_val_shift = 4,
 854                 .width = 4,
 855         },
 856         .mn[1] = {
 857                 .mnctr_en_bit = 5,
 858                 .mnctr_reset_bit = 24,
 859                 .mnctr_mode_shift = 6,
 860                 .n_val_shift = 16,
 861                 .m_val_shift = 4,
 862                 .width = 4,
 863         },
 864         .s[0] = {
 865                 .src_sel_shift = 3,
 866                 .parent_map = mmcc_pxo_pll8_pll2_map,
 867         },
 868         .s[1] = {
 869                 .src_sel_shift = 0,
 870                 .parent_map = mmcc_pxo_pll8_pll2_map,
 871         },
 872         .mux_sel_bit = 11,
 873         .freq_tbl = clk_tbl_gfx2d,
 874         .clkr = {
 875                 .enable_reg = 0x0060,
 876                 .enable_mask = BIT(2),
 877                 .hw.init = &(struct clk_init_data){
 878                         .name = "gfx2d0_src",
 879                         .parent_data = mmcc_pxo_pll8_pll2,
 880                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 881                         .ops = &clk_dyn_rcg_ops,
 882                 },
 883         },
 884 };
 885
 886 static struct clk_branch gfx2d0_clk = {
 887         .halt_reg = 0x01c8,
 888         .halt_bit = 9,
 889         .clkr = {
 890                 .enable_reg = 0x0060,
 891                 .enable_mask = BIT(0),
 892                 .hw.init = &(struct clk_init_data){
 893                         .name = "gfx2d0_clk",
 894                         .parent_hws = (const struct clk_hw*[]){
 895                                 &gfx2d0_src.clkr.hw
 896                         },
 897                         .num_parents = 1,
 898                         .ops = &clk_branch_ops,
 899                         .flags = CLK_SET_RATE_PARENT,
 900                 },
 901         },
 902 };
 903
 904 static struct clk_dyn_rcg gfx2d1_src = {
 905         .ns_reg[0] = 0x007c,
 906         .ns_reg[1] = 0x007c,
 907         .md_reg[0] = 0x0078,
 908         .md_reg[1] = 0x006c,
 909         .bank_reg = 0x0074,
 910         .mn[0] = {
 911                 .mnctr_en_bit = 8,
 912                 .mnctr_reset_bit = 25,
 913                 .mnctr_mode_shift = 9,
 914                 .n_val_shift = 20,
 915                 .m_val_shift = 4,
 916                 .width = 4,
 917         },
 918         .mn[1] = {
 919                 .mnctr_en_bit = 5,
 920                 .mnctr_reset_bit = 24,
 921                 .mnctr_mode_shift = 6,
 922                 .n_val_shift = 16,
 923                 .m_val_shift = 4,
 924                 .width = 4,
 925         },
 926         .s[0] = {
 927                 .src_sel_shift = 3,
 928                 .parent_map = mmcc_pxo_pll8_pll2_map,
 929         },
 930         .s[1] = {
 931                 .src_sel_shift = 0,
 932                 .parent_map = mmcc_pxo_pll8_pll2_map,
 933         },
 934         .mux_sel_bit = 11,
 935         .freq_tbl = clk_tbl_gfx2d,
 936         .clkr = {
 937                 .enable_reg = 0x0074,
 938                 .enable_mask = BIT(2),
 939                 .hw.init = &(struct clk_init_data){
 940                         .name = "gfx2d1_src",
 941                         .parent_data = mmcc_pxo_pll8_pll2,
 942                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
 943                         .ops = &clk_dyn_rcg_ops,
 944                 },
 945         },
 946 };
 947
 948 static struct clk_branch gfx2d1_clk = {
 949         .halt_reg = 0x01c8,
 950         .halt_bit = 14,
 951         .clkr = {
 952                 .enable_reg = 0x0074,
 953                 .enable_mask = BIT(0),
 954                 .hw.init = &(struct clk_init_data){
 955                         .name = "gfx2d1_clk",
 956                         .parent_hws = (const struct clk_hw*[]){
 957                                 &gfx2d1_src.clkr.hw
 958                         },
 959                         .num_parents = 1,
 960                         .ops = &clk_branch_ops,
 961                         .flags = CLK_SET_RATE_PARENT,
 962                 },
 963         },
 964 };
 965
 966 static const struct freq_tbl clk_tbl_gfx3d[] = {
 967         F_MN( 27000000, P_PXO,  1,  0),
 968         F_MN( 48000000, P_PLL8, 1,  8),
 969         F_MN( 54857000, P_PLL8, 1,  7),
 970         F_MN( 64000000, P_PLL8, 1,  6),
 971         F_MN( 76800000, P_PLL8, 1,  5),
 972         F_MN( 96000000, P_PLL8, 1,  4),
 973         F_MN(128000000, P_PLL8, 1,  3),
 974         F_MN(145455000, P_PLL2, 2, 11),
 975         F_MN(160000000, P_PLL2, 1,  5),
 976         F_MN(177778000, P_PLL2, 2,  9),
 977         F_MN(200000000, P_PLL2, 1,  4),
 978         F_MN(228571000, P_PLL2, 2,  7),
 979         F_MN(266667000, P_PLL2, 1,  3),
 980         F_MN(300000000, P_PLL3, 1,  4),
 981         F_MN(320000000, P_PLL2, 2,  5),
 982         F_MN(400000000, P_PLL2, 1,  2),
 983         { }
 984 };
 985
 986 static const struct freq_tbl clk_tbl_gfx3d_8064[] = {
 987         F_MN( 27000000, P_PXO,   0,  0),
 988         F_MN( 48000000, P_PLL8,  1,  8),
 989         F_MN( 54857000, P_PLL8,  1,  7),
 990         F_MN( 64000000, P_PLL8,  1,  6),
 991         F_MN( 76800000, P_PLL8,  1,  5),
 992         F_MN( 96000000, P_PLL8,  1,  4),
 993         F_MN(128000000, P_PLL8,  1,  3),
 994         F_MN(145455000, P_PLL2,  2, 11),
 995         F_MN(160000000, P_PLL2,  1,  5),
 996         F_MN(177778000, P_PLL2,  2,  9),
 997         F_MN(192000000, P_PLL8,  1,  2),
 998         F_MN(200000000, P_PLL2,  1,  4),
 999         F_MN(228571000, P_PLL2,  2,  7),
1000         F_MN(266667000, P_PLL2,  1,  3),
1001         F_MN(320000000, P_PLL2,  2,  5),
1002         F_MN(400000000, P_PLL2,  1,  2),
1003         F_MN(450000000, P_PLL15, 1,  2),
1004         { }
1005 };
1006
1007 static struct clk_dyn_rcg gfx3d_src = {
1008         .ns_reg[0] = 0x008c,
1009         .ns_reg[1] = 0x008c,
1010         .md_reg[0] = 0x0084,
1011         .md_reg[1] = 0x0088,
1012         .bank_reg = 0x0080,
1013         .mn[0] = {
1014                 .mnctr_en_bit = 8,
1015                 .mnctr_reset_bit = 25,
1016                 .mnctr_mode_shift = 9,
1017                 .n_val_shift = 18,
1018                 .m_val_shift = 4,
1019                 .width = 4,
1020         },
1021         .mn[1] = {
1022                 .mnctr_en_bit = 5,
1023                 .mnctr_reset_bit = 24,
1024                 .mnctr_mode_shift = 6,
1025                 .n_val_shift = 14,
1026                 .m_val_shift = 4,
1027                 .width = 4,
1028         },
1029         .s[0] = {
1030                 .src_sel_shift = 3,
1031                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
1032         },
1033         .s[1] = {
1034                 .src_sel_shift = 0,
1035                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
1036         },
1037         .mux_sel_bit = 11,
1038         .freq_tbl = clk_tbl_gfx3d,
1039         .clkr = {
1040                 .enable_reg = 0x0080,
1041                 .enable_mask = BIT(2),
1042                 .hw.init = &(struct clk_init_data){
1043                         .name = "gfx3d_src",
1044                         .parent_data = mmcc_pxo_pll8_pll2_pll3,
1045                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll3),
1046                         .ops = &clk_dyn_rcg_ops,
1047                 },
1048         },
1049 };
1050
1051 static const struct clk_init_data gfx3d_8064_init = {
1052         .name = "gfx3d_src",
1053         .parent_data = mmcc_pxo_pll8_pll2_pll15,
1054         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2_pll15),
1055         .ops = &clk_dyn_rcg_ops,
1056 };
1057
1058 static struct clk_branch gfx3d_clk = {
1059         .halt_reg = 0x01c8,
1060         .halt_bit = 4,
1061         .clkr = {
1062                 .enable_reg = 0x0080,
1063                 .enable_mask = BIT(0),
1064                 .hw.init = &(struct clk_init_data){
1065                         .name = "gfx3d_clk",
1066                         .parent_hws = (const struct clk_hw*[]){
1067                                 &gfx3d_src.clkr.hw
1068                         },
1069                         .num_parents = 1,
1070                         .ops = &clk_branch_ops,
1071                         .flags = CLK_SET_RATE_PARENT,
1072                 },
1073         },
1074 };
1075
1076 static const struct freq_tbl clk_tbl_vcap[] = {
1077         F_MN( 27000000, P_PXO,  0,  0),
1078         F_MN( 54860000, P_PLL8, 1,  7),
1079         F_MN( 64000000, P_PLL8, 1,  6),
1080         F_MN( 76800000, P_PLL8, 1,  5),
1081         F_MN(128000000, P_PLL8, 1,  3),
1082         F_MN(160000000, P_PLL2, 1,  5),
1083         F_MN(200000000, P_PLL2, 1,  4),
1084         { }
1085 };
1086
1087 static struct clk_dyn_rcg vcap_src = {
1088         .ns_reg[0] = 0x021c,
1089         .ns_reg[1] = 0x021c,
1090         .md_reg[0] = 0x01ec,
1091         .md_reg[1] = 0x0218,
1092         .bank_reg = 0x0178,
1093         .mn[0] = {
1094                 .mnctr_en_bit = 8,
1095                 .mnctr_reset_bit = 23,
1096                 .mnctr_mode_shift = 9,
1097                 .n_val_shift = 18,
1098                 .m_val_shift = 4,
1099                 .width = 4,
1100         },
1101         .mn[1] = {
1102                 .mnctr_en_bit = 5,
1103                 .mnctr_reset_bit = 22,
1104                 .mnctr_mode_shift = 6,
1105                 .n_val_shift = 14,
1106                 .m_val_shift = 4,
1107                 .width = 4,
1108         },
1109         .s[0] = {
1110                 .src_sel_shift = 3,
1111                 .parent_map = mmcc_pxo_pll8_pll2_map,
1112         },
1113         .s[1] = {
1114                 .src_sel_shift = 0,
1115                 .parent_map = mmcc_pxo_pll8_pll2_map,
1116         },
1117         .mux_sel_bit = 11,
1118         .freq_tbl = clk_tbl_vcap,
1119         .clkr = {
1120                 .enable_reg = 0x0178,
1121                 .enable_mask = BIT(2),
1122                 .hw.init = &(struct clk_init_data){
1123                         .name = "vcap_src",
1124                         .parent_data = mmcc_pxo_pll8_pll2,
1125                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1126                         .ops = &clk_dyn_rcg_ops,
1127                 },
1128         },
1129 };
1130
1131 static struct clk_branch vcap_clk = {
1132         .halt_reg = 0x0240,
1133         .halt_bit = 15,
1134         .clkr = {
1135                 .enable_reg = 0x0178,
1136                 .enable_mask = BIT(0),
1137                 .hw.init = &(struct clk_init_data){
1138                         .name = "vcap_clk",
1139                         .parent_hws = (const struct clk_hw*[]){
1140                                 &vcap_src.clkr.hw
1141                         },
1142                         .num_parents = 1,
1143                         .ops = &clk_branch_ops,
1144                         .flags = CLK_SET_RATE_PARENT,
1145                 },
1146         },
1147 };
1148
1149 static struct clk_branch vcap_npl_clk = {
1150         .halt_reg = 0x0240,
1151         .halt_bit = 25,
1152         .clkr = {
1153                 .enable_reg = 0x0178,
1154                 .enable_mask = BIT(13),
1155                 .hw.init = &(struct clk_init_data){
1156                         .name = "vcap_npl_clk",
1157                         .parent_hws = (const struct clk_hw*[]){
1158                                 &vcap_src.clkr.hw
1159                         },
1160                         .num_parents = 1,
1161                         .ops = &clk_branch_ops,
1162                         .flags = CLK_SET_RATE_PARENT,
1163                 },
1164         },
1165 };
1166
1167 static const struct freq_tbl clk_tbl_ijpeg[] = {
1168         {  27000000, P_PXO,  1, 0,  0 },
1169         {  36570000, P_PLL8, 1, 2, 21 },
1170         {  54860000, P_PLL8, 7, 0,  0 },
1171         {  96000000, P_PLL8, 4, 0,  0 },
1172         { 109710000, P_PLL8, 1, 2,  7 },
1173         { 128000000, P_PLL8, 3, 0,  0 },
1174         { 153600000, P_PLL8, 1, 2,  5 },
1175         { 200000000, P_PLL2, 4, 0,  0 },
1176         { 228571000, P_PLL2, 1, 2,  7 },
1177         { 266667000, P_PLL2, 1, 1,  3 },
1178         { 320000000, P_PLL2, 1, 2,  5 },
1179         { }
1180 };
1181
1182 static struct clk_rcg ijpeg_src = {
1183         .ns_reg = 0x00a0,
1184         .md_reg = 0x009c,
1185         .mn = {
1186                 .mnctr_en_bit = 5,
1187                 .mnctr_reset_bit = 7,
1188                 .mnctr_mode_shift = 6,
1189                 .n_val_shift = 16,
1190                 .m_val_shift = 8,
1191                 .width = 8,
1192         },
1193         .p = {
1194                 .pre_div_shift = 12,
1195                 .pre_div_width = 2,
1196         },
1197         .s = {
1198                 .src_sel_shift = 0,
1199                 .parent_map = mmcc_pxo_pll8_pll2_map,
1200         },
1201         .freq_tbl = clk_tbl_ijpeg,
1202         .clkr = {
1203                 .enable_reg = 0x0098,
1204                 .enable_mask = BIT(2),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "ijpeg_src",
1207                         .parent_data = mmcc_pxo_pll8_pll2,
1208                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1209                         .ops = &clk_rcg_ops,
1210                 },
1211         },
1212 };
1213
1214 static struct clk_branch ijpeg_clk = {
1215         .halt_reg = 0x01c8,
1216         .halt_bit = 24,
1217         .clkr = {
1218                 .enable_reg = 0x0098,
1219                 .enable_mask = BIT(0),
1220                 .hw.init = &(struct clk_init_data){
1221                         .name = "ijpeg_clk",
1222                         .parent_hws = (const struct clk_hw*[]){
1223                                 &ijpeg_src.clkr.hw
1224                         },
1225                         .num_parents = 1,
1226                         .ops = &clk_branch_ops,
1227                         .flags = CLK_SET_RATE_PARENT,
1228                 },
1229         },
1230 };
1231
1232 static const struct freq_tbl clk_tbl_jpegd[] = {
1233         {  64000000, P_PLL8, 6 },
1234         {  76800000, P_PLL8, 5 },
1235         {  96000000, P_PLL8, 4 },
1236         { 160000000, P_PLL2, 5 },
1237         { 200000000, P_PLL2, 4 },
1238         { }
1239 };
1240
1241 static struct clk_rcg jpegd_src = {
1242         .ns_reg = 0x00ac,
1243         .p = {
1244                 .pre_div_shift = 12,
1245                 .pre_div_width = 4,
1246         },
1247         .s = {
1248                 .src_sel_shift = 0,
1249                 .parent_map = mmcc_pxo_pll8_pll2_map,
1250         },
1251         .freq_tbl = clk_tbl_jpegd,
1252         .clkr = {
1253                 .enable_reg = 0x00a4,
1254                 .enable_mask = BIT(2),
1255                 .hw.init = &(struct clk_init_data){
1256                         .name = "jpegd_src",
1257                         .parent_data = mmcc_pxo_pll8_pll2,
1258                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1259                         .ops = &clk_rcg_ops,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch jpegd_clk = {
1265         .halt_reg = 0x01c8,
1266         .halt_bit = 19,
1267         .clkr = {
1268                 .enable_reg = 0x00a4,
1269                 .enable_mask = BIT(0),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "jpegd_clk",
1272                         .parent_hws = (const struct clk_hw*[]){
1273                                 &jpegd_src.clkr.hw
1274                         },
1275                         .num_parents = 1,
1276                         .ops = &clk_branch_ops,
1277                         .flags = CLK_SET_RATE_PARENT,
1278                 },
1279         },
1280 };
1281
1282 static const struct freq_tbl clk_tbl_mdp[] = {
1283         {   9600000, P_PLL8, 1, 1, 40 },
1284         {  13710000, P_PLL8, 1, 1, 28 },
1285         {  27000000, P_PXO,  1, 0,  0 },
1286         {  29540000, P_PLL8, 1, 1, 13 },
1287         {  34910000, P_PLL8, 1, 1, 11 },
1288         {  38400000, P_PLL8, 1, 1, 10 },
1289         {  59080000, P_PLL8, 1, 2, 13 },
1290         {  76800000, P_PLL8, 1, 1,  5 },
1291         {  85330000, P_PLL8, 1, 2,  9 },
1292         {  96000000, P_PLL8, 1, 1,  4 },
1293         { 128000000, P_PLL8, 1, 1,  3 },
1294         { 160000000, P_PLL2, 1, 1,  5 },
1295         { 177780000, P_PLL2, 1, 2,  9 },
1296         { 200000000, P_PLL2, 1, 1,  4 },
1297         { 228571000, P_PLL2, 1, 2,  7 },
1298         { 266667000, P_PLL2, 1, 1,  3 },
1299         { }
1300 };
1301
1302 static struct clk_dyn_rcg mdp_src = {
1303         .ns_reg[0] = 0x00d0,
1304         .ns_reg[1] = 0x00d0,
1305         .md_reg[0] = 0x00c4,
1306         .md_reg[1] = 0x00c8,
1307         .bank_reg = 0x00c0,
1308         .mn[0] = {
1309                 .mnctr_en_bit = 8,
1310                 .mnctr_reset_bit = 31,
1311                 .mnctr_mode_shift = 9,
1312                 .n_val_shift = 22,
1313                 .m_val_shift = 8,
1314                 .width = 8,
1315         },
1316         .mn[1] = {
1317                 .mnctr_en_bit = 5,
1318                 .mnctr_reset_bit = 30,
1319                 .mnctr_mode_shift = 6,
1320                 .n_val_shift = 14,
1321                 .m_val_shift = 8,
1322                 .width = 8,
1323         },
1324         .s[0] = {
1325                 .src_sel_shift = 3,
1326                 .parent_map = mmcc_pxo_pll8_pll2_map,
1327         },
1328         .s[1] = {
1329                 .src_sel_shift = 0,
1330                 .parent_map = mmcc_pxo_pll8_pll2_map,
1331         },
1332         .mux_sel_bit = 11,
1333         .freq_tbl = clk_tbl_mdp,
1334         .clkr = {
1335                 .enable_reg = 0x00c0,
1336                 .enable_mask = BIT(2),
1337                 .hw.init = &(struct clk_init_data){
1338                         .name = "mdp_src",
1339                         .parent_data = mmcc_pxo_pll8_pll2,
1340                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1341                         .ops = &clk_dyn_rcg_ops,
1342                 },
1343         },
1344 };
1345
1346 static struct clk_branch mdp_clk = {
1347         .halt_reg = 0x01d0,
1348         .halt_bit = 10,
1349         .clkr = {
1350                 .enable_reg = 0x00c0,
1351                 .enable_mask = BIT(0),
1352                 .hw.init = &(struct clk_init_data){
1353                         .name = "mdp_clk",
1354                         .parent_hws = (const struct clk_hw*[]){
1355                                 &mdp_src.clkr.hw
1356                         },
1357                         .num_parents = 1,
1358                         .ops = &clk_branch_ops,
1359                         .flags = CLK_SET_RATE_PARENT,
1360                 },
1361         },
1362 };
1363
1364 static struct clk_branch mdp_lut_clk = {
1365         .halt_reg = 0x01e8,
1366         .halt_bit = 13,
1367         .clkr = {
1368                 .enable_reg = 0x016c,
1369                 .enable_mask = BIT(0),
1370                 .hw.init = &(struct clk_init_data){
1371                         .parent_hws = (const struct clk_hw*[]){
1372                                 &mdp_src.clkr.hw
1373                         },
1374                         .num_parents = 1,
1375                         .name = "mdp_lut_clk",
1376                         .ops = &clk_branch_ops,
1377                         .flags = CLK_SET_RATE_PARENT,
1378                 },
1379         },
1380 };
1381
1382 static struct clk_branch mdp_vsync_clk = {
1383         .halt_reg = 0x01cc,
1384         .halt_bit = 22,
1385         .clkr = {
1386                 .enable_reg = 0x0058,
1387                 .enable_mask = BIT(6),
1388                 .hw.init = &(struct clk_init_data){
1389                         .name = "mdp_vsync_clk",
1390                         .parent_data = (const struct clk_parent_data[]){
1391                                 { .fw_name = "pxo", .name = "pxo_board" },
1392                         },
1393                         .num_parents = 1,
1394                         .ops = &clk_branch_ops
1395                 },
1396         },
1397 };
1398
1399 static const struct freq_tbl clk_tbl_rot[] = {
1400         {  27000000, P_PXO,   1 },
1401         {  29540000, P_PLL8, 13 },
1402         {  32000000, P_PLL8, 12 },
1403         {  38400000, P_PLL8, 10 },
1404         {  48000000, P_PLL8,  8 },
1405         {  54860000, P_PLL8,  7 },
1406         {  64000000, P_PLL8,  6 },
1407         {  76800000, P_PLL8,  5 },
1408         {  96000000, P_PLL8,  4 },
1409         { 100000000, P_PLL2,  8 },
1410         { 114290000, P_PLL2,  7 },
1411         { 133330000, P_PLL2,  6 },
1412         { 160000000, P_PLL2,  5 },
1413         { 200000000, P_PLL2,  4 },
1414         { }
1415 };
1416
1417 static struct clk_dyn_rcg rot_src = {
1418         .ns_reg[0] = 0x00e8,
1419         .ns_reg[1] = 0x00e8,
1420         .bank_reg = 0x00e8,
1421         .p[0] = {
1422                 .pre_div_shift = 22,
1423                 .pre_div_width = 4,
1424         },
1425         .p[1] = {
1426                 .pre_div_shift = 26,
1427                 .pre_div_width = 4,
1428         },
1429         .s[0] = {
1430                 .src_sel_shift = 16,
1431                 .parent_map = mmcc_pxo_pll8_pll2_map,
1432         },
1433         .s[1] = {
1434                 .src_sel_shift = 19,
1435                 .parent_map = mmcc_pxo_pll8_pll2_map,
1436         },
1437         .mux_sel_bit = 30,
1438         .freq_tbl = clk_tbl_rot,
1439         .clkr = {
1440                 .enable_reg = 0x00e0,
1441                 .enable_mask = BIT(2),
1442                 .hw.init = &(struct clk_init_data){
1443                         .name = "rot_src",
1444                         .parent_data = mmcc_pxo_pll8_pll2,
1445                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1446                         .ops = &clk_dyn_rcg_ops,
1447                 },
1448         },
1449 };
1450
1451 static struct clk_branch rot_clk = {
1452         .halt_reg = 0x01d0,
1453         .halt_bit = 15,
1454         .clkr = {
1455                 .enable_reg = 0x00e0,
1456                 .enable_mask = BIT(0),
1457                 .hw.init = &(struct clk_init_data){
1458                         .name = "rot_clk",
1459                         .parent_hws = (const struct clk_hw*[]){
1460                                 &rot_src.clkr.hw
1461                         },
1462                         .num_parents = 1,
1463                         .ops = &clk_branch_ops,
1464                         .flags = CLK_SET_RATE_PARENT,
1465                 },
1466         },
1467 };
1468
1469 static const struct parent_map mmcc_pxo_hdmi_map[] = {
1470         { P_PXO, 0 },
1471         { P_HDMI_PLL, 3 }
1472 };
1473
1474 static const struct clk_parent_data mmcc_pxo_hdmi[] = {
1475         { .fw_name = "pxo", .name = "pxo_board" },
1476         { .fw_name = "hdmipll", .name = "hdmi_pll" },
1477 };
1478
1479 static const struct freq_tbl clk_tbl_tv[] = {
1480         {  .src = P_HDMI_PLL, .pre_div = 1 },
1481         { }
1482 };
1483
1484 static struct clk_rcg tv_src = {
1485         .ns_reg = 0x00f4,
1486         .md_reg = 0x00f0,
1487         .mn = {
1488                 .mnctr_en_bit = 5,
1489                 .mnctr_reset_bit = 7,
1490                 .mnctr_mode_shift = 6,
1491                 .n_val_shift = 16,
1492                 .m_val_shift = 8,
1493                 .width = 8,
1494         },
1495         .p = {
1496                 .pre_div_shift = 14,
1497                 .pre_div_width = 2,
1498         },
1499         .s = {
1500                 .src_sel_shift = 0,
1501                 .parent_map = mmcc_pxo_hdmi_map,
1502         },
1503         .freq_tbl = clk_tbl_tv,
1504         .clkr = {
1505                 .enable_reg = 0x00ec,
1506                 .enable_mask = BIT(2),
1507                 .hw.init = &(struct clk_init_data){
1508                         .name = "tv_src",
1509                         .parent_data = mmcc_pxo_hdmi,
1510                         .num_parents = ARRAY_SIZE(mmcc_pxo_hdmi),
1511                         .ops = &clk_rcg_bypass_ops,
1512                         .flags = CLK_SET_RATE_PARENT,
1513                 },
1514         },
1515 };
1516
1517 static struct clk_branch tv_enc_clk = {
1518         .halt_reg = 0x01d4,
1519         .halt_bit = 9,
1520         .clkr = {
1521                 .enable_reg = 0x00ec,
1522                 .enable_mask = BIT(8),
1523                 .hw.init = &(struct clk_init_data){
1524                         .parent_hws = (const struct clk_hw*[]){
1525                                 &tv_src.clkr.hw,
1526                         },
1527                         .num_parents = 1,
1528                         .name = "tv_enc_clk",
1529                         .ops = &clk_branch_ops,
1530                         .flags = CLK_SET_RATE_PARENT,
1531                 },
1532         },
1533 };
1534
1535 static struct clk_branch tv_dac_clk = {
1536         .halt_reg = 0x01d4,
1537         .halt_bit = 10,
1538         .clkr = {
1539                 .enable_reg = 0x00ec,
1540                 .enable_mask = BIT(10),
1541                 .hw.init = &(struct clk_init_data){
1542                         .parent_hws = (const struct clk_hw*[]){
1543                                 &tv_src.clkr.hw,
1544                         },
1545                         .num_parents = 1,
1546                         .name = "tv_dac_clk",
1547                         .ops = &clk_branch_ops,
1548                         .flags = CLK_SET_RATE_PARENT,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_branch mdp_tv_clk = {
1554         .halt_reg = 0x01d4,
1555         .halt_bit = 12,
1556         .clkr = {
1557                 .enable_reg = 0x00ec,
1558                 .enable_mask = BIT(0),
1559                 .hw.init = &(struct clk_init_data){
1560                         .parent_hws = (const struct clk_hw*[]){
1561                                 &tv_src.clkr.hw,
1562                         },
1563                         .num_parents = 1,
1564                         .name = "mdp_tv_clk",
1565                         .ops = &clk_branch_ops,
1566                         .flags = CLK_SET_RATE_PARENT,
1567                 },
1568         },
1569 };
1570
1571 static struct clk_branch hdmi_tv_clk = {
1572         .halt_reg = 0x01d4,
1573         .halt_bit = 11,
1574         .clkr = {
1575                 .enable_reg = 0x00ec,
1576                 .enable_mask = BIT(12),
1577                 .hw.init = &(struct clk_init_data){
1578                         .parent_hws = (const struct clk_hw*[]){
1579                                 &tv_src.clkr.hw,
1580                         },
1581                         .num_parents = 1,
1582                         .name = "hdmi_tv_clk",
1583                         .ops = &clk_branch_ops,
1584                         .flags = CLK_SET_RATE_PARENT,
1585                 },
1586         },
1587 };
1588
1589 static struct clk_branch rgb_tv_clk = {
1590         .halt_reg = 0x0240,
1591         .halt_bit = 27,
1592         .clkr = {
1593                 .enable_reg = 0x0124,
1594                 .enable_mask = BIT(14),
1595                 .hw.init = &(struct clk_init_data){
1596                         .parent_hws = (const struct clk_hw*[]){
1597                                 &tv_src.clkr.hw,
1598                         },
1599                         .num_parents = 1,
1600                         .name = "rgb_tv_clk",
1601                         .ops = &clk_branch_ops,
1602                         .flags = CLK_SET_RATE_PARENT,
1603                 },
1604         },
1605 };
1606
1607 static struct clk_branch npl_tv_clk = {
1608         .halt_reg = 0x0240,
1609         .halt_bit = 26,
1610         .clkr = {
1611                 .enable_reg = 0x0124,
1612                 .enable_mask = BIT(16),
1613                 .hw.init = &(struct clk_init_data){
1614                         .parent_hws = (const struct clk_hw*[]){
1615                                 &tv_src.clkr.hw,
1616                         },
1617                         .num_parents = 1,
1618                         .name = "npl_tv_clk",
1619                         .ops = &clk_branch_ops,
1620                         .flags = CLK_SET_RATE_PARENT,
1621                 },
1622         },
1623 };
1624
1625 static struct clk_branch hdmi_app_clk = {
1626         .halt_reg = 0x01cc,
1627         .halt_bit = 25,
1628         .clkr = {
1629                 .enable_reg = 0x005c,
1630                 .enable_mask = BIT(11),
1631                 .hw.init = &(struct clk_init_data){
1632                         .parent_data = (const struct clk_parent_data[]){
1633                                 { .fw_name = "pxo", .name = "pxo_board" },
1634                         },
1635                         .num_parents = 1,
1636                         .name = "hdmi_app_clk",
1637                         .ops = &clk_branch_ops,
1638                 },
1639         },
1640 };
1641
1642 static const struct freq_tbl clk_tbl_vcodec[] = {
1643         F_MN( 27000000, P_PXO,  1,  0),
1644         F_MN( 32000000, P_PLL8, 1, 12),
1645         F_MN( 48000000, P_PLL8, 1,  8),
1646         F_MN( 54860000, P_PLL8, 1,  7),
1647         F_MN( 96000000, P_PLL8, 1,  4),
1648         F_MN(133330000, P_PLL2, 1,  6),
1649         F_MN(200000000, P_PLL2, 1,  4),
1650         F_MN(228570000, P_PLL2, 2,  7),
1651         F_MN(266670000, P_PLL2, 1,  3),
1652         { }
1653 };
1654
1655 static struct clk_dyn_rcg vcodec_src = {
1656         .ns_reg[0] = 0x0100,
1657         .ns_reg[1] = 0x0100,
1658         .md_reg[0] = 0x00fc,
1659         .md_reg[1] = 0x0128,
1660         .bank_reg = 0x00f8,
1661         .mn[0] = {
1662                 .mnctr_en_bit = 5,
1663                 .mnctr_reset_bit = 31,
1664                 .mnctr_mode_shift = 6,
1665                 .n_val_shift = 11,
1666                 .m_val_shift = 8,
1667                 .width = 8,
1668         },
1669         .mn[1] = {
1670                 .mnctr_en_bit = 10,
1671                 .mnctr_reset_bit = 30,
1672                 .mnctr_mode_shift = 11,
1673                 .n_val_shift = 19,
1674                 .m_val_shift = 8,
1675                 .width = 8,
1676         },
1677         .s[0] = {
1678                 .src_sel_shift = 27,
1679                 .parent_map = mmcc_pxo_pll8_pll2_map,
1680         },
1681         .s[1] = {
1682                 .src_sel_shift = 0,
1683                 .parent_map = mmcc_pxo_pll8_pll2_map,
1684         },
1685         .mux_sel_bit = 13,
1686         .freq_tbl = clk_tbl_vcodec,
1687         .clkr = {
1688                 .enable_reg = 0x00f8,
1689                 .enable_mask = BIT(2),
1690                 .hw.init = &(struct clk_init_data){
1691                         .name = "vcodec_src",
1692                         .parent_data = mmcc_pxo_pll8_pll2,
1693                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1694                         .ops = &clk_dyn_rcg_ops,
1695                 },
1696         },
1697 };
1698
1699 static struct clk_branch vcodec_clk = {
1700         .halt_reg = 0x01d0,
1701         .halt_bit = 29,
1702         .clkr = {
1703                 .enable_reg = 0x00f8,
1704                 .enable_mask = BIT(0),
1705                 .hw.init = &(struct clk_init_data){
1706                         .name = "vcodec_clk",
1707                         .parent_hws = (const struct clk_hw*[]){
1708                                 &vcodec_src.clkr.hw
1709                         },
1710                         .num_parents = 1,
1711                         .ops = &clk_branch_ops,
1712                         .flags = CLK_SET_RATE_PARENT,
1713                 },
1714         },
1715 };
1716
1717 static const struct freq_tbl clk_tbl_vpe[] = {
1718         {  27000000, P_PXO,   1 },
1719         {  34909000, P_PLL8, 11 },
1720         {  38400000, P_PLL8, 10 },
1721         {  64000000, P_PLL8,  6 },
1722         {  76800000, P_PLL8,  5 },
1723         {  96000000, P_PLL8,  4 },
1724         { 100000000, P_PLL2,  8 },
1725         { 160000000, P_PLL2,  5 },
1726         { }
1727 };
1728
1729 static struct clk_rcg vpe_src = {
1730         .ns_reg = 0x0118,
1731         .p = {
1732                 .pre_div_shift = 12,
1733                 .pre_div_width = 4,
1734         },
1735         .s = {
1736                 .src_sel_shift = 0,
1737                 .parent_map = mmcc_pxo_pll8_pll2_map,
1738         },
1739         .freq_tbl = clk_tbl_vpe,
1740         .clkr = {
1741                 .enable_reg = 0x0110,
1742                 .enable_mask = BIT(2),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "vpe_src",
1745                         .parent_data = mmcc_pxo_pll8_pll2,
1746                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1747                         .ops = &clk_rcg_ops,
1748                 },
1749         },
1750 };
1751
1752 static struct clk_branch vpe_clk = {
1753         .halt_reg = 0x01c8,
1754         .halt_bit = 28,
1755         .clkr = {
1756                 .enable_reg = 0x0110,
1757                 .enable_mask = BIT(0),
1758                 .hw.init = &(struct clk_init_data){
1759                         .name = "vpe_clk",
1760                         .parent_hws = (const struct clk_hw*[]){
1761                                 &vpe_src.clkr.hw
1762                         },
1763                         .num_parents = 1,
1764                         .ops = &clk_branch_ops,
1765                         .flags = CLK_SET_RATE_PARENT,
1766                 },
1767         },
1768 };
1769
1770 static const struct freq_tbl clk_tbl_vfe[] = {
1771         {  13960000, P_PLL8,  1, 2, 55 },
1772         {  27000000, P_PXO,   1, 0,  0 },
1773         {  36570000, P_PLL8,  1, 2, 21 },
1774         {  38400000, P_PLL8,  2, 1,  5 },
1775         {  45180000, P_PLL8,  1, 2, 17 },
1776         {  48000000, P_PLL8,  2, 1,  4 },
1777         {  54860000, P_PLL8,  1, 1,  7 },
1778         {  64000000, P_PLL8,  2, 1,  3 },
1779         {  76800000, P_PLL8,  1, 1,  5 },
1780         {  96000000, P_PLL8,  2, 1,  2 },
1781         { 109710000, P_PLL8,  1, 2,  7 },
1782         { 128000000, P_PLL8,  1, 1,  3 },
1783         { 153600000, P_PLL8,  1, 2,  5 },
1784         { 200000000, P_PLL2,  2, 1,  2 },
1785         { 228570000, P_PLL2,  1, 2,  7 },
1786         { 266667000, P_PLL2,  1, 1,  3 },
1787         { 320000000, P_PLL2,  1, 2,  5 },
1788         { }
1789 };
1790
1791 static struct clk_rcg vfe_src = {
1792         .ns_reg = 0x0108,
1793         .mn = {
1794                 .mnctr_en_bit = 5,
1795                 .mnctr_reset_bit = 7,
1796                 .mnctr_mode_shift = 6,
1797                 .n_val_shift = 16,
1798                 .m_val_shift = 8,
1799                 .width = 8,
1800         },
1801         .p = {
1802                 .pre_div_shift = 10,
1803                 .pre_div_width = 1,
1804         },
1805         .s = {
1806                 .src_sel_shift = 0,
1807                 .parent_map = mmcc_pxo_pll8_pll2_map,
1808         },
1809         .freq_tbl = clk_tbl_vfe,
1810         .clkr = {
1811                 .enable_reg = 0x0104,
1812                 .enable_mask = BIT(2),
1813                 .hw.init = &(struct clk_init_data){
1814                         .name = "vfe_src",
1815                         .parent_data = mmcc_pxo_pll8_pll2,
1816                         .num_parents = ARRAY_SIZE(mmcc_pxo_pll8_pll2),
1817                         .ops = &clk_rcg_ops,
1818                 },
1819         },
1820 };
1821
1822 static struct clk_branch vfe_clk = {
1823         .halt_reg = 0x01cc,
1824         .halt_bit = 6,
1825         .clkr = {
1826                 .enable_reg = 0x0104,
1827                 .enable_mask = BIT(0),
1828                 .hw.init = &(struct clk_init_data){
1829                         .name = "vfe_clk",
1830                         .parent_hws = (const struct clk_hw*[]){
1831                                 &vfe_src.clkr.hw
1832                         },
1833                         .num_parents = 1,
1834                         .ops = &clk_branch_ops,
1835                         .flags = CLK_SET_RATE_PARENT,
1836                 },
1837         },
1838 };
1839
1840 static struct clk_branch vfe_csi_clk = {
1841         .halt_reg = 0x01cc,
1842         .halt_bit = 8,
1843         .clkr = {
1844                 .enable_reg = 0x0104,
1845                 .enable_mask = BIT(12),
1846                 .hw.init = &(struct clk_init_data){
1847                         .parent_hws = (const struct clk_hw*[]){
1848                                 &vfe_src.clkr.hw
1849                         },
1850                         .num_parents = 1,
1851                         .name = "vfe_csi_clk",
1852                         .ops = &clk_branch_ops,
1853                         .flags = CLK_SET_RATE_PARENT,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_branch gmem_axi_clk = {
1859         .halt_reg = 0x01d8,
1860         .halt_bit = 6,
1861         .clkr = {
1862                 .enable_reg = 0x0018,
1863                 .enable_mask = BIT(24),
1864                 .hw.init = &(struct clk_init_data){
1865                         .name = "gmem_axi_clk",
1866                         .ops = &clk_branch_ops,
1867                 },
1868         },
1869 };
1870
1871 static struct clk_branch ijpeg_axi_clk = {
1872         .hwcg_reg = 0x0018,
1873         .hwcg_bit = 11,
1874         .halt_reg = 0x01d8,
1875         .halt_bit = 4,
1876         .clkr = {
1877                 .enable_reg = 0x0018,
1878                 .enable_mask = BIT(21),
1879                 .hw.init = &(struct clk_init_data){
1880                         .name = "ijpeg_axi_clk",
1881                         .ops = &clk_branch_ops,
1882                 },
1883         },
1884 };
1885
1886 static struct clk_branch mmss_imem_axi_clk = {
1887         .hwcg_reg = 0x0018,
1888         .hwcg_bit = 15,
1889         .halt_reg = 0x01d8,
1890         .halt_bit = 7,
1891         .clkr = {
1892                 .enable_reg = 0x0018,
1893                 .enable_mask = BIT(22),
1894                 .hw.init = &(struct clk_init_data){
1895                         .name = "mmss_imem_axi_clk",
1896                         .ops = &clk_branch_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch jpegd_axi_clk = {
1902         .halt_reg = 0x01d8,
1903         .halt_bit = 5,
1904         .clkr = {
1905                 .enable_reg = 0x0018,
1906                 .enable_mask = BIT(25),
1907                 .hw.init = &(struct clk_init_data){
1908                         .name = "jpegd_axi_clk",
1909                         .ops = &clk_branch_ops,
1910                 },
1911         },
1912 };
1913
1914 static struct clk_branch vcodec_axi_b_clk = {
1915         .hwcg_reg = 0x0114,
1916         .hwcg_bit = 22,
1917         .halt_reg = 0x01e8,
1918         .halt_bit = 25,
1919         .clkr = {
1920                 .enable_reg = 0x0114,
1921                 .enable_mask = BIT(23),
1922                 .hw.init = &(struct clk_init_data){
1923                         .name = "vcodec_axi_b_clk",
1924                         .ops = &clk_branch_ops,
1925                 },
1926         },
1927 };
1928
1929 static struct clk_branch vcodec_axi_a_clk = {
1930         .hwcg_reg = 0x0114,
1931         .hwcg_bit = 24,
1932         .halt_reg = 0x01e8,
1933         .halt_bit = 26,
1934         .clkr = {
1935                 .enable_reg = 0x0114,
1936                 .enable_mask = BIT(25),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "vcodec_axi_a_clk",
1939                         .ops = &clk_branch_ops,
1940                 },
1941         },
1942 };
1943
1944 static struct clk_branch vcodec_axi_clk = {
1945         .hwcg_reg = 0x0018,
1946         .hwcg_bit = 13,
1947         .halt_reg = 0x01d8,
1948         .halt_bit = 3,
1949         .clkr = {
1950                 .enable_reg = 0x0018,
1951                 .enable_mask = BIT(19),
1952                 .hw.init = &(struct clk_init_data){
1953                         .name = "vcodec_axi_clk",
1954                         .ops = &clk_branch_ops,
1955                 },
1956         },
1957 };
1958
1959 static struct clk_branch vfe_axi_clk = {
1960         .halt_reg = 0x01d8,
1961         .halt_bit = 0,
1962         .clkr = {
1963                 .enable_reg = 0x0018,
1964                 .enable_mask = BIT(18),
1965                 .hw.init = &(struct clk_init_data){
1966                         .name = "vfe_axi_clk",
1967                         .ops = &clk_branch_ops,
1968                 },
1969         },
1970 };
1971
1972 static struct clk_branch mdp_axi_clk = {
1973         .hwcg_reg = 0x0018,
1974         .hwcg_bit = 16,
1975         .halt_reg = 0x01d8,
1976         .halt_bit = 8,
1977         .clkr = {
1978                 .enable_reg = 0x0018,
1979                 .enable_mask = BIT(23),
1980                 .hw.init = &(struct clk_init_data){
1981                         .name = "mdp_axi_clk",
1982                         .ops = &clk_branch_ops,
1983                 },
1984         },
1985 };
1986
1987 static struct clk_branch rot_axi_clk = {
1988         .hwcg_reg = 0x0020,
1989         .hwcg_bit = 25,
1990         .halt_reg = 0x01d8,
1991         .halt_bit = 2,
1992         .clkr = {
1993                 .enable_reg = 0x0020,
1994                 .enable_mask = BIT(24),
1995                 .hw.init = &(struct clk_init_data){
1996                         .name = "rot_axi_clk",
1997                         .ops = &clk_branch_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch vcap_axi_clk = {
2003         .halt_reg = 0x0240,
2004         .halt_bit = 20,
2005         .hwcg_reg = 0x0244,
2006         .hwcg_bit = 11,
2007         .clkr = {
2008                 .enable_reg = 0x0244,
2009                 .enable_mask = BIT(12),
2010                 .hw.init = &(struct clk_init_data){
2011                         .name = "vcap_axi_clk",
2012                         .ops = &clk_branch_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch vpe_axi_clk = {
2018         .hwcg_reg = 0x0020,
2019         .hwcg_bit = 27,
2020         .halt_reg = 0x01d8,
2021         .halt_bit = 1,
2022         .clkr = {
2023                 .enable_reg = 0x0020,
2024                 .enable_mask = BIT(26),
2025                 .hw.init = &(struct clk_init_data){
2026                         .name = "vpe_axi_clk",
2027                         .ops = &clk_branch_ops,
2028                 },
2029         },
2030 };
2031
2032 static struct clk_branch gfx3d_axi_clk = {
2033         .hwcg_reg = 0x0244,
2034         .hwcg_bit = 24,
2035         .halt_reg = 0x0240,
2036         .halt_bit = 30,
2037         .clkr = {
2038                 .enable_reg = 0x0244,
2039                 .enable_mask = BIT(25),
2040                 .hw.init = &(struct clk_init_data){
2041                         .name = "gfx3d_axi_clk",
2042                         .ops = &clk_branch_ops,
2043                 },
2044         },
2045 };
2046
2047 static struct clk_branch amp_ahb_clk = {
2048         .halt_reg = 0x01dc,
2049         .halt_bit = 18,
2050         .clkr = {
2051                 .enable_reg = 0x0008,
2052                 .enable_mask = BIT(24),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "amp_ahb_clk",
2055                         .ops = &clk_branch_ops,
2056                 },
2057         },
2058 };
2059
2060 static struct clk_branch csi_ahb_clk = {
2061         .halt_reg = 0x01dc,
2062         .halt_bit = 16,
2063         .clkr = {
2064                 .enable_reg = 0x0008,
2065                 .enable_mask = BIT(7),
2066                 .hw.init = &(struct clk_init_data){
2067                         .name = "csi_ahb_clk",
2068                         .ops = &clk_branch_ops,
2069                 },
2070         },
2071 };
2072
2073 static struct clk_branch dsi_m_ahb_clk = {
2074         .halt_reg = 0x01dc,
2075         .halt_bit = 19,
2076         .clkr = {
2077                 .enable_reg = 0x0008,
2078                 .enable_mask = BIT(9),
2079                 .hw.init = &(struct clk_init_data){
2080                         .name = "dsi_m_ahb_clk",
2081                         .ops = &clk_branch_ops,
2082                 },
2083         },
2084 };
2085
2086 static struct clk_branch dsi_s_ahb_clk = {
2087         .hwcg_reg = 0x0038,
2088         .hwcg_bit = 20,
2089         .halt_reg = 0x01dc,
2090         .halt_bit = 21,
2091         .clkr = {
2092                 .enable_reg = 0x0008,
2093                 .enable_mask = BIT(18),
2094                 .hw.init = &(struct clk_init_data){
2095                         .name = "dsi_s_ahb_clk",
2096                         .ops = &clk_branch_ops,
2097                 },
2098         },
2099 };
2100
2101 static struct clk_branch dsi2_m_ahb_clk = {
2102         .halt_reg = 0x01d8,
2103         .halt_bit = 18,
2104         .clkr = {
2105                 .enable_reg = 0x0008,
2106                 .enable_mask = BIT(17),
2107                 .hw.init = &(struct clk_init_data){
2108                         .name = "dsi2_m_ahb_clk",
2109                         .ops = &clk_branch_ops,
2110                 },
2111         },
2112 };
2113
2114 static struct clk_branch dsi2_s_ahb_clk = {
2115         .hwcg_reg = 0x0038,
2116         .hwcg_bit = 15,
2117         .halt_reg = 0x01dc,
2118         .halt_bit = 20,
2119         .clkr = {
2120                 .enable_reg = 0x0008,
2121                 .enable_mask = BIT(22),
2122                 .hw.init = &(struct clk_init_data){
2123                         .name = "dsi2_s_ahb_clk",
2124                         .ops = &clk_branch_ops,
2125                 },
2126         },
2127 };
2128
2129 static struct clk_rcg dsi1_src = {
2130         .ns_reg = 0x0054,
2131         .md_reg = 0x0050,
2132         .mn = {
2133                 .mnctr_en_bit = 5,
2134                 .mnctr_reset_bit = 7,
2135                 .mnctr_mode_shift = 6,
2136                 .n_val_shift = 24,
2137                 .m_val_shift = 8,
2138                 .width = 8,
2139         },
2140         .p = {
2141                 .pre_div_shift = 14,
2142                 .pre_div_width = 2,
2143         },
2144         .s = {
2145                 .src_sel_shift = 0,
2146                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2147         },
2148         .clkr = {
2149                 .enable_reg = 0x004c,
2150                 .enable_mask = BIT(2),
2151                 .hw.init = &(struct clk_init_data){
2152                         .name = "dsi1_src",
2153                         .parent_data = mmcc_pxo_dsi2_dsi1,
2154                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2155                         .ops = &clk_rcg_bypass2_ops,
2156                         .flags = CLK_SET_RATE_PARENT,
2157                 },
2158         },
2159 };
2160
2161 static struct clk_branch dsi1_clk = {
2162         .halt_reg = 0x01d0,
2163         .halt_bit = 2,
2164         .clkr = {
2165                 .enable_reg = 0x004c,
2166                 .enable_mask = BIT(0),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "dsi1_clk",
2169                         .parent_hws = (const struct clk_hw*[]){
2170                                 &dsi1_src.clkr.hw
2171                         },
2172                         .num_parents = 1,
2173                         .ops = &clk_branch_ops,
2174                         .flags = CLK_SET_RATE_PARENT,
2175                 },
2176         },
2177 };
2178
2179 static struct clk_rcg dsi2_src = {
2180         .ns_reg = 0x012c,
2181         .md_reg = 0x00a8,
2182         .mn = {
2183                 .mnctr_en_bit = 5,
2184                 .mnctr_reset_bit = 7,
2185                 .mnctr_mode_shift = 6,
2186                 .n_val_shift = 24,
2187                 .m_val_shift = 8,
2188                 .width = 8,
2189         },
2190         .p = {
2191                 .pre_div_shift = 14,
2192                 .pre_div_width = 2,
2193         },
2194         .s = {
2195                 .src_sel_shift = 0,
2196                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2197         },
2198         .clkr = {
2199                 .enable_reg = 0x003c,
2200                 .enable_mask = BIT(2),
2201                 .hw.init = &(struct clk_init_data){
2202                         .name = "dsi2_src",
2203                         .parent_data = mmcc_pxo_dsi2_dsi1,
2204                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2205                         .ops = &clk_rcg_bypass2_ops,
2206                         .flags = CLK_SET_RATE_PARENT,
2207                 },
2208         },
2209 };
2210
2211 static struct clk_branch dsi2_clk = {
2212         .halt_reg = 0x01d0,
2213         .halt_bit = 20,
2214         .clkr = {
2215                 .enable_reg = 0x003c,
2216                 .enable_mask = BIT(0),
2217                 .hw.init = &(struct clk_init_data){
2218                         .name = "dsi2_clk",
2219                         .parent_hws = (const struct clk_hw*[]){
2220                                 &dsi2_src.clkr.hw
2221                         },
2222                         .num_parents = 1,
2223                         .ops = &clk_branch_ops,
2224                         .flags = CLK_SET_RATE_PARENT,
2225                 },
2226         },
2227 };
2228
2229 static struct clk_rcg dsi1_byte_src = {
2230         .ns_reg = 0x00b0,
2231         .p = {
2232                 .pre_div_shift = 12,
2233                 .pre_div_width = 4,
2234         },
2235         .s = {
2236                 .src_sel_shift = 0,
2237                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2238         },
2239         .clkr = {
2240                 .enable_reg = 0x0090,
2241                 .enable_mask = BIT(2),
2242                 .hw.init = &(struct clk_init_data){
2243                         .name = "dsi1_byte_src",
2244                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2245                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2246                         .ops = &clk_rcg_bypass2_ops,
2247                         .flags = CLK_SET_RATE_PARENT,
2248                 },
2249         },
2250 };
2251
2252 static struct clk_branch dsi1_byte_clk = {
2253         .halt_reg = 0x01cc,
2254         .halt_bit = 21,
2255         .clkr = {
2256                 .enable_reg = 0x0090,
2257                 .enable_mask = BIT(0),
2258                 .hw.init = &(struct clk_init_data){
2259                         .name = "dsi1_byte_clk",
2260                         .parent_hws = (const struct clk_hw*[]){
2261                                 &dsi1_byte_src.clkr.hw
2262                         },
2263                         .num_parents = 1,
2264                         .ops = &clk_branch_ops,
2265                         .flags = CLK_SET_RATE_PARENT,
2266                 },
2267         },
2268 };
2269
2270 static struct clk_rcg dsi2_byte_src = {
2271         .ns_reg = 0x012c,
2272         .p = {
2273                 .pre_div_shift = 12,
2274                 .pre_div_width = 4,
2275         },
2276         .s = {
2277                 .src_sel_shift = 0,
2278                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2279         },
2280         .clkr = {
2281                 .enable_reg = 0x0130,
2282                 .enable_mask = BIT(2),
2283                 .hw.init = &(struct clk_init_data){
2284                         .name = "dsi2_byte_src",
2285                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2286                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2287                         .ops = &clk_rcg_bypass2_ops,
2288                         .flags = CLK_SET_RATE_PARENT,
2289                 },
2290         },
2291 };
2292
2293 static struct clk_branch dsi2_byte_clk = {
2294         .halt_reg = 0x01cc,
2295         .halt_bit = 20,
2296         .clkr = {
2297                 .enable_reg = 0x00b4,
2298                 .enable_mask = BIT(0),
2299                 .hw.init = &(struct clk_init_data){
2300                         .name = "dsi2_byte_clk",
2301                         .parent_hws = (const struct clk_hw*[]){
2302                                 &dsi2_byte_src.clkr.hw
2303                         },
2304                         .num_parents = 1,
2305                         .ops = &clk_branch_ops,
2306                         .flags = CLK_SET_RATE_PARENT,
2307                 },
2308         },
2309 };
2310
2311 static struct clk_rcg dsi1_esc_src = {
2312         .ns_reg = 0x0011c,
2313         .p = {
2314                 .pre_div_shift = 12,
2315                 .pre_div_width = 4,
2316         },
2317         .s = {
2318                 .src_sel_shift = 0,
2319                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2320         },
2321         .clkr = {
2322                 .enable_reg = 0x00cc,
2323                 .enable_mask = BIT(2),
2324                 .hw.init = &(struct clk_init_data){
2325                         .name = "dsi1_esc_src",
2326                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2327                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2328                         .ops = &clk_rcg_esc_ops,
2329                 },
2330         },
2331 };
2332
2333 static struct clk_branch dsi1_esc_clk = {
2334         .halt_reg = 0x01e8,
2335         .halt_bit = 1,
2336         .clkr = {
2337                 .enable_reg = 0x00cc,
2338                 .enable_mask = BIT(0),
2339                 .hw.init = &(struct clk_init_data){
2340                         .name = "dsi1_esc_clk",
2341                         .parent_hws = (const struct clk_hw*[]){
2342                                 &dsi1_esc_src.clkr.hw
2343                         },
2344                         .num_parents = 1,
2345                         .ops = &clk_branch_ops,
2346                         .flags = CLK_SET_RATE_PARENT,
2347                 },
2348         },
2349 };
2350
2351 static struct clk_rcg dsi2_esc_src = {
2352         .ns_reg = 0x0150,
2353         .p = {
2354                 .pre_div_shift = 12,
2355                 .pre_div_width = 4,
2356         },
2357         .s = {
2358                 .src_sel_shift = 0,
2359                 .parent_map = mmcc_pxo_dsi1_dsi2_byte_map,
2360         },
2361         .clkr = {
2362                 .enable_reg = 0x013c,
2363                 .enable_mask = BIT(2),
2364                 .hw.init = &(struct clk_init_data){
2365                         .name = "dsi2_esc_src",
2366                         .parent_data = mmcc_pxo_dsi1_dsi2_byte,
2367                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi1_dsi2_byte),
2368                         .ops = &clk_rcg_esc_ops,
2369                 },
2370         },
2371 };
2372
2373 static struct clk_branch dsi2_esc_clk = {
2374         .halt_reg = 0x01e8,
2375         .halt_bit = 3,
2376         .clkr = {
2377                 .enable_reg = 0x013c,
2378                 .enable_mask = BIT(0),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "dsi2_esc_clk",
2381                         .parent_hws = (const struct clk_hw*[]){
2382                                 &dsi2_esc_src.clkr.hw
2383                         },
2384                         .num_parents = 1,
2385                         .ops = &clk_branch_ops,
2386                         .flags = CLK_SET_RATE_PARENT,
2387                 },
2388         },
2389 };
2390
2391 static struct clk_rcg dsi1_pixel_src = {
2392         .ns_reg = 0x0138,
2393         .md_reg = 0x0134,
2394         .mn = {
2395                 .mnctr_en_bit = 5,
2396                 .mnctr_reset_bit = 7,
2397                 .mnctr_mode_shift = 6,
2398                 .n_val_shift = 16,
2399                 .m_val_shift = 8,
2400                 .width = 8,
2401         },
2402         .p = {
2403                 .pre_div_shift = 12,
2404                 .pre_div_width = 4,
2405         },
2406         .s = {
2407                 .src_sel_shift = 0,
2408                 .parent_map = mmcc_pxo_dsi2_dsi1_map,
2409         },
2410         .clkr = {
2411                 .enable_reg = 0x0130,
2412                 .enable_mask = BIT(2),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "dsi1_pixel_src",
2415                         .parent_data = mmcc_pxo_dsi2_dsi1,
2416                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1),
2417                         .ops = &clk_rcg_pixel_ops,
2418                 },
2419         },
2420 };
2421
2422 static struct clk_branch dsi1_pixel_clk = {
2423         .halt_reg = 0x01d0,
2424         .halt_bit = 6,
2425         .clkr = {
2426                 .enable_reg = 0x0130,
2427                 .enable_mask = BIT(0),
2428                 .hw.init = &(struct clk_init_data){
2429                         .name = "mdp_pclk1_clk",
2430                         .parent_hws = (const struct clk_hw*[]){
2431                                 &dsi1_pixel_src.clkr.hw
2432                         },
2433                         .num_parents = 1,
2434                         .ops = &clk_branch_ops,
2435                         .flags = CLK_SET_RATE_PARENT,
2436                 },
2437         },
2438 };
2439
2440 static struct clk_rcg dsi2_pixel_src = {
2441         .ns_reg = 0x00e4,
2442         .md_reg = 0x00b8,
2443         .mn = {
2444                 .mnctr_en_bit = 5,
2445                 .mnctr_reset_bit = 7,
2446                 .mnctr_mode_shift = 6,
2447                 .n_val_shift = 16,
2448                 .m_val_shift = 8,
2449                 .width = 8,
2450         },
2451         .p = {
2452                 .pre_div_shift = 12,
2453                 .pre_div_width = 4,
2454         },
2455         .s = {
2456                 .src_sel_shift = 0,
2457                 .parent_map = mmcc_pxo_dsi2_dsi1_lvds_map,
2458         },
2459         .clkr = {
2460                 .enable_reg = 0x0094,
2461                 .enable_mask = BIT(2),
2462                 .hw.init = &(struct clk_init_data){
2463                         .name = "dsi2_pixel_src",
2464                         .parent_data = mmcc_pxo_dsi2_dsi1_lvds,
2465                         .num_parents = ARRAY_SIZE(mmcc_pxo_dsi2_dsi1_lvds),
2466                         .ops = &clk_rcg_pixel_ops,
2467                 },
2468         },
2469 };
2470
2471 static struct clk_branch dsi2_pixel_lvds_src = {
2472         .clkr = {
2473                 .enable_reg = 0x0094,
2474                 .enable_mask = BIT(0),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "dsi2_pixel_lvds_src",
2477                         .parent_hws = (const struct clk_hw*[]){
2478                                 &dsi2_pixel_src.clkr.hw
2479                         },
2480                         .num_parents = 1,
2481                         .ops = &clk_branch_simple_ops,
2482                         .flags = CLK_SET_RATE_PARENT,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch dsi2_pixel_clk = {
2488         .halt_reg = 0x01d0,
2489         .halt_bit = 19,
2490         .clkr = {
2491                 .enable_reg = 0x0094,
2492                 .enable_mask = 0,
2493                 .hw.init = &(struct clk_init_data){
2494                         .name = "mdp_pclk2_clk",
2495                         .parent_hws = (const struct clk_hw*[]){
2496                                 &dsi2_pixel_src.clkr.hw
2497                         },
2498                         .num_parents = 1,
2499                         .ops = &clk_branch_ops,
2500                         .flags = CLK_SET_RATE_PARENT,
2501                 },
2502         },
2503 };
2504
2505 static struct clk_branch lvds_clk = {
2506         .halt_reg = 0x024c,
2507         .halt_bit = 6,
2508         .clkr = {
2509                 .enable_reg = 0x0264,
2510                 .enable_mask = BIT(1),
2511                 .hw.init = &(struct clk_init_data){
2512                         .name = "mdp_lvds_clk",
2513                         .parent_hws = (const struct clk_hw*[]){
2514                                 &dsi2_pixel_lvds_src.clkr.hw
2515                         },
2516                         .num_parents = 1,
2517                         .ops = &clk_branch_ops,
2518                         .flags = CLK_SET_RATE_PARENT,
2519                 },
2520         },
2521 };
2522
2523 static struct clk_branch gfx2d0_ahb_clk = {
2524         .hwcg_reg = 0x0038,
2525         .hwcg_bit = 28,
2526         .halt_reg = 0x01dc,
2527         .halt_bit = 2,
2528         .clkr = {
2529                 .enable_reg = 0x0008,
2530                 .enable_mask = BIT(19),
2531                 .hw.init = &(struct clk_init_data){
2532                         .name = "gfx2d0_ahb_clk",
2533                         .ops = &clk_branch_ops,
2534                 },
2535         },
2536 };
2537
2538 static struct clk_branch gfx2d1_ahb_clk = {
2539         .hwcg_reg = 0x0038,
2540         .hwcg_bit = 29,
2541         .halt_reg = 0x01dc,
2542         .halt_bit = 3,
2543         .clkr = {
2544                 .enable_reg = 0x0008,
2545                 .enable_mask = BIT(2),
2546                 .hw.init = &(struct clk_init_data){
2547                         .name = "gfx2d1_ahb_clk",
2548                         .ops = &clk_branch_ops,
2549                 },
2550         },
2551 };
2552
2553 static struct clk_branch gfx3d_ahb_clk = {
2554         .hwcg_reg = 0x0038,
2555         .hwcg_bit = 27,
2556         .halt_reg = 0x01dc,
2557         .halt_bit = 4,
2558         .clkr = {
2559                 .enable_reg = 0x0008,
2560                 .enable_mask = BIT(3),
2561                 .hw.init = &(struct clk_init_data){
2562                         .name = "gfx3d_ahb_clk",
2563                         .ops = &clk_branch_ops,
2564                 },
2565         },
2566 };
2567
2568 static struct clk_branch hdmi_m_ahb_clk = {
2569         .hwcg_reg = 0x0038,
2570         .hwcg_bit = 21,
2571         .halt_reg = 0x01dc,
2572         .halt_bit = 5,
2573         .clkr = {
2574                 .enable_reg = 0x0008,
2575                 .enable_mask = BIT(14),
2576                 .hw.init = &(struct clk_init_data){
2577                         .name = "hdmi_m_ahb_clk",
2578                         .ops = &clk_branch_ops,
2579                 },
2580         },
2581 };
2582
2583 static struct clk_branch hdmi_s_ahb_clk = {
2584         .hwcg_reg = 0x0038,
2585         .hwcg_bit = 22,
2586         .halt_reg = 0x01dc,
2587         .halt_bit = 6,
2588         .clkr = {
2589                 .enable_reg = 0x0008,
2590                 .enable_mask = BIT(4),
2591                 .hw.init = &(struct clk_init_data){
2592                         .name = "hdmi_s_ahb_clk",
2593                         .ops = &clk_branch_ops,
2594                 },
2595         },
2596 };
2597
2598 static struct clk_branch ijpeg_ahb_clk = {
2599         .halt_reg = 0x01dc,
2600         .halt_bit = 9,
2601         .clkr = {
2602                 .enable_reg = 0x0008,
2603                 .enable_mask = BIT(5),
2604                 .hw.init = &(struct clk_init_data){
2605                         .name = "ijpeg_ahb_clk",
2606                         .ops = &clk_branch_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch mmss_imem_ahb_clk = {
2612         .hwcg_reg = 0x0038,
2613         .hwcg_bit = 12,
2614         .halt_reg = 0x01dc,
2615         .halt_bit = 10,
2616         .clkr = {
2617                 .enable_reg = 0x0008,
2618                 .enable_mask = BIT(6),
2619                 .hw.init = &(struct clk_init_data){
2620                         .name = "mmss_imem_ahb_clk",
2621                         .ops = &clk_branch_ops,
2622                 },
2623         },
2624 };
2625
2626 static struct clk_branch jpegd_ahb_clk = {
2627         .halt_reg = 0x01dc,
2628         .halt_bit = 7,
2629         .clkr = {
2630                 .enable_reg = 0x0008,
2631                 .enable_mask = BIT(21),
2632                 .hw.init = &(struct clk_init_data){
2633                         .name = "jpegd_ahb_clk",
2634                         .ops = &clk_branch_ops,
2635                 },
2636         },
2637 };
2638
2639 static struct clk_branch mdp_ahb_clk = {
2640         .halt_reg = 0x01dc,
2641         .halt_bit = 11,
2642         .clkr = {
2643                 .enable_reg = 0x0008,
2644                 .enable_mask = BIT(10),
2645                 .hw.init = &(struct clk_init_data){
2646                         .name = "mdp_ahb_clk",
2647                         .ops = &clk_branch_ops,
2648                 },
2649         },
2650 };
2651
2652 static struct clk_branch rot_ahb_clk = {
2653         .halt_reg = 0x01dc,
2654         .halt_bit = 13,
2655         .clkr = {
2656                 .enable_reg = 0x0008,
2657                 .enable_mask = BIT(12),
2658                 .hw.init = &(struct clk_init_data){
2659                         .name = "rot_ahb_clk",
2660                         .ops = &clk_branch_ops,
2661                 },
2662         },
2663 };
2664
2665 static struct clk_branch smmu_ahb_clk = {
2666         .hwcg_reg = 0x0008,
2667         .hwcg_bit = 26,
2668         .halt_reg = 0x01dc,
2669         .halt_bit = 22,
2670         .clkr = {
2671                 .enable_reg = 0x0008,
2672                 .enable_mask = BIT(15),
2673                 .hw.init = &(struct clk_init_data){
2674                         .name = "smmu_ahb_clk",
2675                         .ops = &clk_branch_ops,
2676                 },
2677         },
2678 };
2679
2680 static struct clk_branch tv_enc_ahb_clk = {
2681         .halt_reg = 0x01dc,
2682         .halt_bit = 23,
2683         .clkr = {
2684                 .enable_reg = 0x0008,
2685                 .enable_mask = BIT(25),
2686                 .hw.init = &(struct clk_init_data){
2687                         .name = "tv_enc_ahb_clk",
2688                         .ops = &clk_branch_ops,
2689                 },
2690         },
2691 };
2692
2693 static struct clk_branch vcap_ahb_clk = {
2694         .halt_reg = 0x0240,
2695         .halt_bit = 23,
2696         .clkr = {
2697                 .enable_reg = 0x0248,
2698                 .enable_mask = BIT(1),
2699                 .hw.init = &(struct clk_init_data){
2700                         .name = "vcap_ahb_clk",
2701                         .ops = &clk_branch_ops,
2702                 },
2703         },
2704 };
2705
2706 static struct clk_branch vcodec_ahb_clk = {
2707         .hwcg_reg = 0x0038,
2708         .hwcg_bit = 26,
2709         .halt_reg = 0x01dc,
2710         .halt_bit = 12,
2711         .clkr = {
2712                 .enable_reg = 0x0008,
2713                 .enable_mask = BIT(11),
2714                 .hw.init = &(struct clk_init_data){
2715                         .name = "vcodec_ahb_clk",
2716                         .ops = &clk_branch_ops,
2717                 },
2718         },
2719 };
2720
2721 static struct clk_branch vfe_ahb_clk = {
2722         .halt_reg = 0x01dc,
2723         .halt_bit = 14,
2724         .clkr = {
2725                 .enable_reg = 0x0008,
2726                 .enable_mask = BIT(13),
2727                 .hw.init = &(struct clk_init_data){
2728                         .name = "vfe_ahb_clk",
2729                         .ops = &clk_branch_ops,
2730                 },
2731         },
2732 };
2733
2734 static struct clk_branch vpe_ahb_clk = {
2735         .halt_reg = 0x01dc,
2736         .halt_bit = 15,
2737         .clkr = {
2738                 .enable_reg = 0x0008,
2739                 .enable_mask = BIT(16),
2740                 .hw.init = &(struct clk_init_data){
2741                         .name = "vpe_ahb_clk",
2742                         .ops = &clk_branch_ops,
2743                 },
2744         },
2745 };
2746
2747 static struct clk_regmap *mmcc_msm8960_clks[] = {
2748         [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2749         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2750         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2751         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2752         [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2753         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2754         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2755         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2756         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2757         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2758         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2759         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2760         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2761         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2762         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2763         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2764         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2765         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2766         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2767         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2768         [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2769         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2770         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2771         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2772         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2773         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2774         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2775         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2776         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2777         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2778         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2779         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2780         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2781         [CSI0_SRC] = &csi0_src.clkr,
2782         [CSI0_CLK] = &csi0_clk.clkr,
2783         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2784         [CSI1_SRC] = &csi1_src.clkr,
2785         [CSI1_CLK] = &csi1_clk.clkr,
2786         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2787         [CSI2_SRC] = &csi2_src.clkr,
2788         [CSI2_CLK] = &csi2_clk.clkr,
2789         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2790         [DSI_SRC] = &dsi1_src.clkr,
2791         [DSI_CLK] = &dsi1_clk.clkr,
2792         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2793         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2794         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2795         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2796         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2797         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2798         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2799         [GFX2D0_SRC] = &gfx2d0_src.clkr,
2800         [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2801         [GFX2D1_SRC] = &gfx2d1_src.clkr,
2802         [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2803         [GFX3D_SRC] = &gfx3d_src.clkr,
2804         [GFX3D_CLK] = &gfx3d_clk.clkr,
2805         [IJPEG_SRC] = &ijpeg_src.clkr,
2806         [IJPEG_CLK] = &ijpeg_clk.clkr,
2807         [JPEGD_SRC] = &jpegd_src.clkr,
2808         [JPEGD_CLK] = &jpegd_clk.clkr,
2809         [MDP_SRC] = &mdp_src.clkr,
2810         [MDP_CLK] = &mdp_clk.clkr,
2811         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2812         [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2813         [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2814         [DSI2_SRC] = &dsi2_src.clkr,
2815         [DSI2_CLK] = &dsi2_clk.clkr,
2816         [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2817         [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2818         [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2819         [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2820         [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
2821         [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
2822         [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
2823         [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
2824         [ROT_SRC] = &rot_src.clkr,
2825         [ROT_CLK] = &rot_clk.clkr,
2826         [TV_ENC_CLK] = &tv_enc_clk.clkr,
2827         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2828         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2829         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2830         [TV_SRC] = &tv_src.clkr,
2831         [VCODEC_SRC] = &vcodec_src.clkr,
2832         [VCODEC_CLK] = &vcodec_clk.clkr,
2833         [VFE_SRC] = &vfe_src.clkr,
2834         [VFE_CLK] = &vfe_clk.clkr,
2835         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2836         [VPE_SRC] = &vpe_src.clkr,
2837         [VPE_CLK] = &vpe_clk.clkr,
2838         [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
2839         [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
2840         [CAMCLK0_SRC] = &camclk0_src.clkr,
2841         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2842         [CAMCLK1_SRC] = &camclk1_src.clkr,
2843         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2844         [CAMCLK2_SRC] = &camclk2_src.clkr,
2845         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2846         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2847         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2848         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2849         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2850         [PLL2] = &pll2.clkr,
2851         [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr,
2852         [LVDS_CLK] = &lvds_clk.clkr,
2853 };
2854
2855 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2856         [VPE_AXI_RESET] = { 0x0208, 15 },
2857         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2858         [MPD_AXI_RESET] = { 0x0208, 13 },
2859         [VFE_AXI_RESET] = { 0x0208, 9 },
2860         [SP_AXI_RESET] = { 0x0208, 8 },
2861         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2862         [ROT_AXI_RESET] = { 0x0208, 6 },
2863         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2864         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2865         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2866         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2867         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2868         [FAB_S0_AXI_RESET] = { 0x0208 },
2869         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2870         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2871         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2872         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2873         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2874         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2875         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2876         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2877         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2878         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2879         [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2880         [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2881         [APU_AHB_RESET] = { 0x020c, 18 },
2882         [CSI_AHB_RESET] = { 0x020c, 17 },
2883         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2884         [VPE_AHB_RESET] = { 0x020c, 14 },
2885         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2886         [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2887         [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2888         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2889         [HDMI_AHB_RESET] = { 0x020c, 9 },
2890         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2891         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2892         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2893         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2894         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2895         [MDP_AHB_RESET] = { 0x020c, 3 },
2896         [ROT_AHB_RESET] = { 0x020c, 2 },
2897         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2898         [VFE_AHB_RESET] = { 0x020c, 0 },
2899         [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2900         [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2901         [CSIPHY2_RESET] = { 0x0210, 29 },
2902         [CSI_PIX1_RESET] = { 0x0210, 28 },
2903         [CSIPHY0_RESET] = { 0x0210, 27 },
2904         [CSIPHY1_RESET] = { 0x0210, 26 },
2905         [DSI2_RESET] = { 0x0210, 25 },
2906         [VFE_CSI_RESET] = { 0x0210, 24 },
2907         [MDP_RESET] = { 0x0210, 21 },
2908         [AMP_RESET] = { 0x0210, 20 },
2909         [JPEGD_RESET] = { 0x0210, 19 },
2910         [CSI1_RESET] = { 0x0210, 18 },
2911         [VPE_RESET] = { 0x0210, 17 },
2912         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2913         [VFE_RESET] = { 0x0210, 15 },
2914         [GFX2D0_RESET] = { 0x0210, 14 },
2915         [GFX2D1_RESET] = { 0x0210, 13 },
2916         [GFX3D_RESET] = { 0x0210, 12 },
2917         [HDMI_RESET] = { 0x0210, 11 },
2918         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2919         [IJPEG_RESET] = { 0x0210, 9 },
2920         [CSI0_RESET] = { 0x0210, 8 },
2921         [DSI_RESET] = { 0x0210, 7 },
2922         [VCODEC_RESET] = { 0x0210, 6 },
2923         [MDP_TV_RESET] = { 0x0210, 4 },
2924         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2925         [ROT_RESET] = { 0x0210, 2 },
2926         [TV_HDMI_RESET] = { 0x0210, 1 },
2927         [TV_ENC_RESET] = { 0x0210 },
2928         [CSI2_RESET] = { 0x0214, 2 },
2929         [CSI_RDI1_RESET] = { 0x0214, 1 },
2930         [CSI_RDI2_RESET] = { 0x0214 },
2931 };
2932
2933 static struct clk_regmap *mmcc_apq8064_clks[] = {
2934         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2935         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2936         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2937         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2938         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2939         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2940         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2941         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2942         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2943         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2944         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2945         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2946         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2947         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2948         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2949         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2950         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2951         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2952         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2953         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2954         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2955         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2956         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2957         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2958         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2959         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2960         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2961         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2962         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2963         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2964         [CSI0_SRC] = &csi0_src.clkr,
2965         [CSI0_CLK] = &csi0_clk.clkr,
2966         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2967         [CSI1_SRC] = &csi1_src.clkr,
2968         [CSI1_CLK] = &csi1_clk.clkr,
2969         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2970         [CSI2_SRC] = &csi2_src.clkr,
2971         [CSI2_CLK] = &csi2_clk.clkr,
2972         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2973         [DSI_SRC] = &dsi1_src.clkr,
2974         [DSI_CLK] = &dsi1_clk.clkr,
2975         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2976         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2977         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2978         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2979         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2980         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2981         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2982         [GFX3D_SRC] = &gfx3d_src.clkr,
2983         [GFX3D_CLK] = &gfx3d_clk.clkr,
2984         [IJPEG_SRC] = &ijpeg_src.clkr,
2985         [IJPEG_CLK] = &ijpeg_clk.clkr,
2986         [JPEGD_SRC] = &jpegd_src.clkr,
2987         [JPEGD_CLK] = &jpegd_clk.clkr,
2988         [MDP_SRC] = &mdp_src.clkr,
2989         [MDP_CLK] = &mdp_clk.clkr,
2990         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2991         [DSI2_PIXEL_SRC] = &dsi2_pixel_src.clkr,
2992         [DSI2_PIXEL_CLK] = &dsi2_pixel_clk.clkr,
2993         [DSI2_SRC] = &dsi2_src.clkr,
2994         [DSI2_CLK] = &dsi2_clk.clkr,
2995         [DSI1_BYTE_SRC] = &dsi1_byte_src.clkr,
2996         [DSI1_BYTE_CLK] = &dsi1_byte_clk.clkr,
2997         [DSI2_BYTE_SRC] = &dsi2_byte_src.clkr,
2998         [DSI2_BYTE_CLK] = &dsi2_byte_clk.clkr,
2999         [DSI1_ESC_SRC] = &dsi1_esc_src.clkr,
3000         [DSI1_ESC_CLK] = &dsi1_esc_clk.clkr,
3001         [DSI2_ESC_SRC] = &dsi2_esc_src.clkr,
3002         [DSI2_ESC_CLK] = &dsi2_esc_clk.clkr,
3003         [ROT_SRC] = &rot_src.clkr,
3004         [ROT_CLK] = &rot_clk.clkr,
3005         [TV_DAC_CLK] = &tv_dac_clk.clkr,
3006         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
3007         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
3008         [TV_SRC] = &tv_src.clkr,
3009         [VCODEC_SRC] = &vcodec_src.clkr,
3010         [VCODEC_CLK] = &vcodec_clk.clkr,
3011         [VFE_SRC] = &vfe_src.clkr,
3012         [VFE_CLK] = &vfe_clk.clkr,
3013         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
3014         [VPE_SRC] = &vpe_src.clkr,
3015         [VPE_CLK] = &vpe_clk.clkr,
3016         [DSI_PIXEL_SRC] = &dsi1_pixel_src.clkr,
3017         [DSI_PIXEL_CLK] = &dsi1_pixel_clk.clkr,
3018         [CAMCLK0_SRC] = &camclk0_src.clkr,
3019         [CAMCLK0_CLK] = &camclk0_clk.clkr,
3020         [CAMCLK1_SRC] = &camclk1_src.clkr,
3021         [CAMCLK1_CLK] = &camclk1_clk.clkr,
3022         [CAMCLK2_SRC] = &camclk2_src.clkr,
3023         [CAMCLK2_CLK] = &camclk2_clk.clkr,
3024         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
3025         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
3026         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
3027         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
3028         [PLL2] = &pll2.clkr,
3029         [RGB_TV_CLK] = &rgb_tv_clk.clkr,
3030         [NPL_TV_CLK] = &npl_tv_clk.clkr,
3031         [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
3032         [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
3033         [VCAP_SRC] = &vcap_src.clkr,
3034         [VCAP_CLK] = &vcap_clk.clkr,
3035         [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
3036         [PLL15] = &pll15.clkr,
3037         [DSI2_PIXEL_LVDS_SRC] = &dsi2_pixel_lvds_src.clkr,
3038         [LVDS_CLK] = &lvds_clk.clkr,
3039 };
3040
3041 static const struct qcom_reset_map mmcc_apq8064_resets[] = {
3042         [GFX3D_AXI_RESET] = { 0x0208, 17 },
3043         [VCAP_AXI_RESET] = { 0x0208, 16 },
3044         [VPE_AXI_RESET] = { 0x0208, 15 },
3045         [IJPEG_AXI_RESET] = { 0x0208, 14 },
3046         [MPD_AXI_RESET] = { 0x0208, 13 },
3047         [VFE_AXI_RESET] = { 0x0208, 9 },
3048         [SP_AXI_RESET] = { 0x0208, 8 },
3049         [VCODEC_AXI_RESET] = { 0x0208, 7 },
3050         [ROT_AXI_RESET] = { 0x0208, 6 },
3051         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
3052         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
3053         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
3054         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
3055         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
3056         [FAB_S0_AXI_RESET] = { 0x0208 },
3057         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
3058         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
3059         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
3060         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
3061         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
3062         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
3063         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
3064         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
3065         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
3066         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
3067         [APU_AHB_RESET] = { 0x020c, 18 },
3068         [CSI_AHB_RESET] = { 0x020c, 17 },
3069         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
3070         [VPE_AHB_RESET] = { 0x020c, 14 },
3071         [FABRIC_AHB_RESET] = { 0x020c, 13 },
3072         [GFX3D_AHB_RESET] = { 0x020c, 10 },
3073         [HDMI_AHB_RESET] = { 0x020c, 9 },
3074         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
3075         [IJPEG_AHB_RESET] = { 0x020c, 7 },
3076         [DSI_M_AHB_RESET] = { 0x020c, 6 },
3077         [DSI_S_AHB_RESET] = { 0x020c, 5 },
3078         [JPEGD_AHB_RESET] = { 0x020c, 4 },
3079         [MDP_AHB_RESET] = { 0x020c, 3 },
3080         [ROT_AHB_RESET] = { 0x020c, 2 },
3081         [VCODEC_AHB_RESET] = { 0x020c, 1 },
3082         [VFE_AHB_RESET] = { 0x020c, 0 },
3083         [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
3084         [VCAP_AHB_RESET] = { 0x0200, 2 },
3085         [DSI2_M_AHB_RESET] = { 0x0200, 1 },
3086         [DSI2_S_AHB_RESET] = { 0x0200, 0 },
3087         [CSIPHY2_RESET] = { 0x0210, 31 },
3088         [CSI_PIX1_RESET] = { 0x0210, 30 },
3089         [CSIPHY0_RESET] = { 0x0210, 29 },
3090         [CSIPHY1_RESET] = { 0x0210, 28 },
3091         [CSI_RDI_RESET] = { 0x0210, 27 },
3092         [CSI_PIX_RESET] = { 0x0210, 26 },
3093         [DSI2_RESET] = { 0x0210, 25 },
3094         [VFE_CSI_RESET] = { 0x0210, 24 },
3095         [MDP_RESET] = { 0x0210, 21 },
3096         [AMP_RESET] = { 0x0210, 20 },
3097         [JPEGD_RESET] = { 0x0210, 19 },
3098         [CSI1_RESET] = { 0x0210, 18 },
3099         [VPE_RESET] = { 0x0210, 17 },
3100         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
3101         [VFE_RESET] = { 0x0210, 15 },
3102         [GFX3D_RESET] = { 0x0210, 12 },
3103         [HDMI_RESET] = { 0x0210, 11 },
3104         [MMSS_IMEM_RESET] = { 0x0210, 10 },
3105         [IJPEG_RESET] = { 0x0210, 9 },
3106         [CSI0_RESET] = { 0x0210, 8 },
3107         [DSI_RESET] = { 0x0210, 7 },
3108         [VCODEC_RESET] = { 0x0210, 6 },
3109         [MDP_TV_RESET] = { 0x0210, 4 },
3110         [MDP_VSYNC_RESET] = { 0x0210, 3 },
3111         [ROT_RESET] = { 0x0210, 2 },
3112         [TV_HDMI_RESET] = { 0x0210, 1 },
3113         [VCAP_NPL_RESET] = { 0x0214, 4 },
3114         [VCAP_RESET] = { 0x0214, 3 },
3115         [CSI2_RESET] = { 0x0214, 2 },
3116         [CSI_RDI1_RESET] = { 0x0214, 1 },
3117         [CSI_RDI2_RESET] = { 0x0214 },
3118 };
3119
3120 static const struct regmap_config mmcc_msm8960_regmap_config = {
3121         .reg_bits       = 32,
3122         .reg_stride     = 4,
3123         .val_bits       = 32,
3124         .max_register   = 0x334,
3125         .fast_io        = true,
3126 };
3127
3128 static const struct regmap_config mmcc_apq8064_regmap_config = {
3129         .reg_bits       = 32,
3130         .reg_stride     = 4,
3131         .val_bits       = 32,
3132         .max_register   = 0x350,
3133         .fast_io        = true,
3134 };
3135
3136 static const struct qcom_cc_desc mmcc_msm8960_desc = {
3137         .config = &mmcc_msm8960_regmap_config,
3138         .clks = mmcc_msm8960_clks,
3139         .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
3140         .resets = mmcc_msm8960_resets,
3141         .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
3142 };
3143
3144 static const struct qcom_cc_desc mmcc_apq8064_desc = {
3145         .config = &mmcc_apq8064_regmap_config,
3146         .clks = mmcc_apq8064_clks,
3147         .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
3148         .resets = mmcc_apq8064_resets,
3149         .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
3150 };
3151
3152 static const struct of_device_id mmcc_msm8960_match_table[] = {
3153         { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
3154         { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
3155         { }
3156 };
3157 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
3158
3159 static int mmcc_msm8960_probe(struct platform_device *pdev)
3160 {
3161         struct regmap *regmap;
3162         struct device *dev = &pdev->dev;
3163         const struct qcom_cc_desc *desc = device_get_match_data(dev);
3164
3165         if (desc == &mmcc_apq8064_desc) {
3166                 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
3167                 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
3168                 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3169                 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
3170         }
3171
3172         regmap = qcom_cc_map(pdev, desc);
3173         if (IS_ERR(regmap))
3174                 return PTR_ERR(regmap);
3175
3176         clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
3177
3178         return qcom_cc_really_probe(&pdev->dev, desc, regmap);
3179 }
3180
3181 static struct platform_driver mmcc_msm8960_driver = {
3182         .probe          = mmcc_msm8960_probe,
3183         .driver         = {
3184                 .name   = "mmcc-msm8960",
3185                 .of_match_table = mmcc_msm8960_match_table,
3186         },
3187 };
3188
3189 module_platform_driver(mmcc_msm8960_driver);
3190
3191 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
3192 MODULE_LICENSE("GPL v2");
3193 MODULE_ALIAS("platform:mmcc-msm8960");