drivers/clk/qcom/gcc-sdm845.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset-controller.h>
  15
  16 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  17
  18 #include "common.h"
  19 #include "clk-regmap.h"
  20 #include "clk-pll.h"
  21 #include "clk-rcg.h"
  22 #include "clk-branch.h"
  23 #include "clk-alpha-pll.h"
  24 #include "gdsc.h"
  25 #include "reset.h"
  26
  27 enum {
  28         P_BI_TCXO,
  29         P_AUD_REF_CLK,
  30         P_GPLL0_OUT_EVEN,
  31         P_GPLL0_OUT_MAIN,
  32         P_GPLL4_OUT_MAIN,
  33         P_GPLL6_OUT_MAIN,
  34         P_SLEEP_CLK,
  35 };
  36
  37 static struct clk_alpha_pll gpll0 = {
  38         .offset = 0x0,
  39         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  40         .clkr = {
  41                 .enable_reg = 0x52000,
  42                 .enable_mask = BIT(0),
  43                 .hw.init = &(struct clk_init_data){
  44                         .name = "gpll0",
  45                         .parent_data = &(const struct clk_parent_data){
  46                                 .fw_name = "bi_tcxo", .name = "bi_tcxo",
  47                         },
  48                         .num_parents = 1,
  49                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  50                 },
  51         },
  52 };
  53
  54 static struct clk_alpha_pll gpll4 = {
  55         .offset = 0x76000,
  56         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  57         .clkr = {
  58                 .enable_reg = 0x52000,
  59                 .enable_mask = BIT(4),
  60                 .hw.init = &(struct clk_init_data){
  61                         .name = "gpll4",
  62                         .parent_data = &(const struct clk_parent_data){
  63                                 .fw_name = "bi_tcxo", .name = "bi_tcxo",
  64                         },
  65                         .num_parents = 1,
  66                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  67                 },
  68         },
  69 };
  70
  71 static struct clk_alpha_pll gpll6 = {
  72         .offset = 0x13000,
  73         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  74         .clkr = {
  75                 .enable_reg = 0x52000,
  76                 .enable_mask = BIT(6),
  77                 .hw.init = &(struct clk_init_data){
  78                         .name = "gpll6",
  79                         .parent_data = &(const struct clk_parent_data){
  80                                 .fw_name = "bi_tcxo", .name = "bi_tcxo",
  81                         },
  82                         .num_parents = 1,
  83                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  84                 },
  85         },
  86 };
  87
  88 static const struct clk_div_table post_div_table_fabia_even[] = {
  89         { 0x0, 1 },
  90         { 0x1, 2 },
  91         { 0x3, 4 },
  92         { 0x7, 8 },
  93         { }
  94 };
  95
  96 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  97         .offset = 0x0,
  98         .post_div_shift = 8,
  99         .post_div_table = post_div_table_fabia_even,
 100         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 101         .width = 4,
 102         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 103         .clkr.hw.init = &(struct clk_init_data){
 104                 .name = "gpll0_out_even",
 105                 .parent_hws = (const struct clk_hw*[]){
 106                         &gpll0.clkr.hw,
 107                 },
 108                 .num_parents = 1,
 109                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 110         },
 111 };
 112
 113 static const struct parent_map gcc_parent_map_0[] = {
 114         { P_BI_TCXO, 0 },
 115         { P_GPLL0_OUT_MAIN, 1 },
 116         { P_GPLL0_OUT_EVEN, 6 },
 117 };
 118
 119 static const struct clk_parent_data gcc_parent_data_0[] = {
 120         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 121         { .hw = &gpll0.clkr.hw },
 122         { .hw = &gpll0_out_even.clkr.hw },
 123 };
 124
 125 static const struct parent_map gcc_parent_map_1[] = {
 126         { P_BI_TCXO, 0 },
 127         { P_GPLL0_OUT_MAIN, 1 },
 128         { P_SLEEP_CLK, 5 },
 129         { P_GPLL0_OUT_EVEN, 6 },
 130 };
 131
 132 static const struct clk_parent_data gcc_parent_data_1[] = {
 133         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 134         { .hw = &gpll0.clkr.hw },
 135         { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
 136         { .hw = &gpll0_out_even.clkr.hw },
 137 };
 138
 139 static const struct parent_map gcc_parent_map_2[] = {
 140         { P_BI_TCXO, 0 },
 141         { P_SLEEP_CLK, 5 },
 142 };
 143
 144 static const struct clk_parent_data gcc_parent_data_2[] = {
 145         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 146         { .fw_name = "sleep_clk", .name = "core_pi_sleep_clk" },
 147 };
 148
 149 static const struct parent_map gcc_parent_map_3[] = {
 150         { P_BI_TCXO, 0 },
 151         { P_GPLL0_OUT_MAIN, 1 },
 152 };
 153
 154 static const struct clk_parent_data gcc_parent_data_3[] = {
 155         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 156         { .hw = &gpll0.clkr.hw },
 157 };
 158
 159 static const struct parent_map gcc_parent_map_4[] = {
 160         { P_BI_TCXO, 0 },
 161 };
 162
 163 static const struct clk_parent_data gcc_parent_data_4[] = {
 164         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 165 };
 166
 167 static const struct parent_map gcc_parent_map_6[] = {
 168         { P_BI_TCXO, 0 },
 169         { P_GPLL0_OUT_MAIN, 1 },
 170         { P_AUD_REF_CLK, 2 },
 171         { P_GPLL0_OUT_EVEN, 6 },
 172 };
 173
 174 static const struct clk_parent_data gcc_parent_data_6[] = {
 175         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 176         { .hw = &gpll0.clkr.hw },
 177         { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
 178         { .hw = &gpll0_out_even.clkr.hw },
 179 };
 180
 181 static const struct clk_parent_data gcc_parent_data_7_ao[] = {
 182         { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
 183         { .hw = &gpll0.clkr.hw },
 184         { .hw = &gpll0_out_even.clkr.hw },
 185         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 186 };
 187
 188 static const struct clk_parent_data gcc_parent_data_8[] = {
 189         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 190         { .hw = &gpll0.clkr.hw },
 191         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 192 };
 193
 194 static const struct clk_parent_data gcc_parent_data_8_ao[] = {
 195         { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
 196         { .hw = &gpll0.clkr.hw },
 197         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 198 };
 199
 200 static const struct parent_map gcc_parent_map_10[] = {
 201         { P_BI_TCXO, 0 },
 202         { P_GPLL0_OUT_MAIN, 1 },
 203         { P_GPLL4_OUT_MAIN, 5 },
 204         { P_GPLL0_OUT_EVEN, 6 },
 205 };
 206
 207 static const struct clk_parent_data gcc_parent_data_10[] = {
 208         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 209         { .hw = &gpll0.clkr.hw },
 210         { .hw = &gpll4.clkr.hw },
 211         { .hw = &gpll0_out_even.clkr.hw },
 212 };
 213
 214 static const struct parent_map gcc_parent_map_11[] = {
 215         { P_BI_TCXO, 0 },
 216         { P_GPLL0_OUT_MAIN, 1 },
 217         { P_GPLL6_OUT_MAIN, 2 },
 218         { P_GPLL0_OUT_EVEN, 6 },
 219 };
 220
 221 static const struct clk_parent_data gcc_parent_data_11[] = {
 222         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 223         { .hw = &gpll0.clkr.hw },
 224         { .hw = &gpll6.clkr.hw },
 225         { .hw = &gpll0_out_even.clkr.hw },
 226 };
 227
 228 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 229         F(19200000, P_BI_TCXO, 1, 0, 0),
 230         { }
 231 };
 232
 233 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 234         .cmd_rcgr = 0x48014,
 235         .mnd_width = 0,
 236         .hid_width = 5,
 237         .parent_map = gcc_parent_map_0,
 238         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 239         .clkr.hw.init = &(struct clk_init_data){
 240                 .name = "gcc_cpuss_ahb_clk_src",
 241                 .parent_data = gcc_parent_data_7_ao,
 242                 .num_parents = ARRAY_SIZE(gcc_parent_data_7_ao),
 243                 .ops = &clk_rcg2_ops,
 244         },
 245 };
 246
 247 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
 248         F(19200000, P_BI_TCXO, 1, 0, 0),
 249         { }
 250 };
 251
 252 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
 253         .cmd_rcgr = 0x4815c,
 254         .mnd_width = 0,
 255         .hid_width = 5,
 256         .parent_map = gcc_parent_map_3,
 257         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 258         .clkr.hw.init = &(struct clk_init_data){
 259                 .name = "gcc_cpuss_rbcpr_clk_src",
 260                 .parent_data = gcc_parent_data_8_ao,
 261                 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
 262                 .ops = &clk_rcg2_ops,
 263         },
 264 };
 265
 266 static const struct freq_tbl ftbl_gcc_sdm670_cpuss_rbcpr_clk_src[] = {
 267         F(19200000, P_BI_TCXO, 1, 0, 0),
 268         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 269         { }
 270 };
 271
 272 static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = {
 273         .cmd_rcgr = 0x4815c,
 274         .mnd_width = 0,
 275         .hid_width = 5,
 276         .parent_map = gcc_parent_map_3,
 277         .freq_tbl = ftbl_gcc_sdm670_cpuss_rbcpr_clk_src,
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gcc_cpuss_rbcpr_clk_src",
 280                 .parent_data = gcc_parent_data_8_ao,
 281                 .num_parents = ARRAY_SIZE(gcc_parent_data_8_ao),
 282                 .ops = &clk_rcg2_ops,
 283         },
 284 };
 285
 286 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 287         { }
 288 };
 289
 290 static struct clk_rcg2 gcc_gp1_clk_src = {
 291         .cmd_rcgr = 0x64004,
 292         .mnd_width = 8,
 293         .hid_width = 5,
 294         .parent_map = gcc_parent_map_1,
 295         .freq_tbl = ftbl_gcc_gp1_clk_src,
 296         .clkr.hw.init = &(struct clk_init_data){
 297                 .name = "gcc_gp1_clk_src",
 298                 .parent_data = gcc_parent_data_1,
 299                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 300                 .ops = &clk_rcg2_gp_ops,
 301         },
 302 };
 303
 304 static struct clk_rcg2 gcc_gp2_clk_src = {
 305         .cmd_rcgr = 0x65004,
 306         .mnd_width = 8,
 307         .hid_width = 5,
 308         .parent_map = gcc_parent_map_1,
 309         .freq_tbl = ftbl_gcc_gp1_clk_src,
 310         .clkr.hw.init = &(struct clk_init_data){
 311                 .name = "gcc_gp2_clk_src",
 312                 .parent_data = gcc_parent_data_1,
 313                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 314                 .ops = &clk_rcg2_gp_ops,
 315         },
 316 };
 317
 318 static struct clk_rcg2 gcc_gp3_clk_src = {
 319         .cmd_rcgr = 0x66004,
 320         .mnd_width = 8,
 321         .hid_width = 5,
 322         .parent_map = gcc_parent_map_1,
 323         .freq_tbl = ftbl_gcc_gp1_clk_src,
 324         .clkr.hw.init = &(struct clk_init_data){
 325                 .name = "gcc_gp3_clk_src",
 326                 .parent_data = gcc_parent_data_1,
 327                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 328                 .ops = &clk_rcg2_gp_ops,
 329         },
 330 };
 331
 332 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 333         F(9600000, P_BI_TCXO, 2, 0, 0),
 334         F(19200000, P_BI_TCXO, 1, 0, 0),
 335         { }
 336 };
 337
 338 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 339         .cmd_rcgr = 0x6b028,
 340         .mnd_width = 16,
 341         .hid_width = 5,
 342         .parent_map = gcc_parent_map_2,
 343         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 344         .clkr.hw.init = &(struct clk_init_data){
 345                 .name = "gcc_pcie_0_aux_clk_src",
 346                 .parent_data = gcc_parent_data_2,
 347                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 348                 .ops = &clk_rcg2_ops,
 349         },
 350 };
 351
 352 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 353         .cmd_rcgr = 0x8d028,
 354         .mnd_width = 16,
 355         .hid_width = 5,
 356         .parent_map = gcc_parent_map_2,
 357         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 358         .clkr.hw.init = &(struct clk_init_data){
 359                 .name = "gcc_pcie_1_aux_clk_src",
 360                 .parent_data = gcc_parent_data_2,
 361                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 362                 .ops = &clk_rcg2_ops,
 363         },
 364 };
 365
 366 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
 367         F(19200000, P_BI_TCXO, 1, 0, 0),
 368         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 369         { }
 370 };
 371
 372 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
 373         .cmd_rcgr = 0x6f014,
 374         .mnd_width = 0,
 375         .hid_width = 5,
 376         .parent_map = gcc_parent_map_0,
 377         .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
 378         .clkr.hw.init = &(struct clk_init_data){
 379                 .name = "gcc_pcie_phy_refgen_clk_src",
 380                 .parent_data = gcc_parent_data_0,
 381                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 382                 .ops = &clk_rcg2_ops,
 383         },
 384 };
 385
 386 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 387         F(19200000, P_BI_TCXO, 1, 0, 0),
 388         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 389         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 390         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 391         { }
 392 };
 393
 394 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 395         .cmd_rcgr = 0x4b008,
 396         .mnd_width = 0,
 397         .hid_width = 5,
 398         .parent_map = gcc_parent_map_0,
 399         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "gcc_qspi_core_clk_src",
 402                 .parent_data = gcc_parent_data_0,
 403                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 404                 .ops = &clk_rcg2_floor_ops,
 405         },
 406 };
 407
 408 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 409         F(9600000, P_BI_TCXO, 2, 0, 0),
 410         F(19200000, P_BI_TCXO, 1, 0, 0),
 411         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 412         { }
 413 };
 414
 415 static struct clk_rcg2 gcc_pdm2_clk_src = {
 416         .cmd_rcgr = 0x33010,
 417         .mnd_width = 0,
 418         .hid_width = 5,
 419         .parent_map = gcc_parent_map_0,
 420         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 421         .clkr.hw.init = &(struct clk_init_data){
 422                 .name = "gcc_pdm2_clk_src",
 423                 .parent_data = gcc_parent_data_0,
 424                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 425                 .ops = &clk_rcg2_ops,
 426         },
 427 };
 428
 429 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 430         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 431         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 432         F(19200000, P_BI_TCXO, 1, 0, 0),
 433         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 434         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 435         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 436         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 437         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 438         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 439         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 440         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 441         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 442         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 443         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 444         F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
 445         { }
 446 };
 447
 448 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 449         .name = "gcc_qupv3_wrap0_s0_clk_src",
 450         .parent_data = gcc_parent_data_0,
 451         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 452         .ops = &clk_rcg2_ops,
 453 };
 454
 455 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 456         .cmd_rcgr = 0x17034,
 457         .mnd_width = 16,
 458         .hid_width = 5,
 459         .parent_map = gcc_parent_map_0,
 460         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 461         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 462 };
 463
 464 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 465         .name = "gcc_qupv3_wrap0_s1_clk_src",
 466         .parent_data = gcc_parent_data_0,
 467         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 468         .ops = &clk_rcg2_ops,
 469 };
 470
 471 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 472         .cmd_rcgr = 0x17164,
 473         .mnd_width = 16,
 474         .hid_width = 5,
 475         .parent_map = gcc_parent_map_0,
 476         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 477         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 478 };
 479
 480 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 481         .name = "gcc_qupv3_wrap0_s2_clk_src",
 482         .parent_data = gcc_parent_data_0,
 483         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 484         .ops = &clk_rcg2_ops,
 485 };
 486
 487 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 488         .cmd_rcgr = 0x17294,
 489         .mnd_width = 16,
 490         .hid_width = 5,
 491         .parent_map = gcc_parent_map_0,
 492         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 493         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 494 };
 495
 496 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 497         .name = "gcc_qupv3_wrap0_s3_clk_src",
 498         .parent_data = gcc_parent_data_0,
 499         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 500         .ops = &clk_rcg2_ops,
 501 };
 502
 503 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 504         .cmd_rcgr = 0x173c4,
 505         .mnd_width = 16,
 506         .hid_width = 5,
 507         .parent_map = gcc_parent_map_0,
 508         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 509         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 510 };
 511
 512 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 513         .name = "gcc_qupv3_wrap0_s4_clk_src",
 514         .parent_data = gcc_parent_data_0,
 515         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 516         .ops = &clk_rcg2_ops,
 517 };
 518
 519 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 520         .cmd_rcgr = 0x174f4,
 521         .mnd_width = 16,
 522         .hid_width = 5,
 523         .parent_map = gcc_parent_map_0,
 524         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 525         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 526 };
 527
 528 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 529         .name = "gcc_qupv3_wrap0_s5_clk_src",
 530         .parent_data = gcc_parent_data_0,
 531         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 532         .ops = &clk_rcg2_ops,
 533 };
 534
 535 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 536         .cmd_rcgr = 0x17624,
 537         .mnd_width = 16,
 538         .hid_width = 5,
 539         .parent_map = gcc_parent_map_0,
 540         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 541         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 542 };
 543
 544 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 545         .name = "gcc_qupv3_wrap0_s6_clk_src",
 546         .parent_data = gcc_parent_data_0,
 547         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 548         .ops = &clk_rcg2_ops,
 549 };
 550
 551 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 552         .cmd_rcgr = 0x17754,
 553         .mnd_width = 16,
 554         .hid_width = 5,
 555         .parent_map = gcc_parent_map_0,
 556         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 557         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 558 };
 559
 560 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 561         .name = "gcc_qupv3_wrap0_s7_clk_src",
 562         .parent_data = gcc_parent_data_0,
 563         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 564         .ops = &clk_rcg2_ops,
 565 };
 566
 567 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 568         .cmd_rcgr = 0x17884,
 569         .mnd_width = 16,
 570         .hid_width = 5,
 571         .parent_map = gcc_parent_map_0,
 572         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 573         .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 574 };
 575
 576 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 577         .name = "gcc_qupv3_wrap1_s0_clk_src",
 578         .parent_data = gcc_parent_data_0,
 579         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 580         .ops = &clk_rcg2_ops,
 581 };
 582
 583 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 584         .cmd_rcgr = 0x18018,
 585         .mnd_width = 16,
 586         .hid_width = 5,
 587         .parent_map = gcc_parent_map_0,
 588         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 589         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 590 };
 591
 592 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 593         .name = "gcc_qupv3_wrap1_s1_clk_src",
 594         .parent_data = gcc_parent_data_0,
 595         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 596         .ops = &clk_rcg2_ops,
 597 };
 598
 599 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 600         .cmd_rcgr = 0x18148,
 601         .mnd_width = 16,
 602         .hid_width = 5,
 603         .parent_map = gcc_parent_map_0,
 604         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 605         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 606 };
 607
 608 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 609         .name = "gcc_qupv3_wrap1_s2_clk_src",
 610         .parent_data = gcc_parent_data_0,
 611         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 612         .ops = &clk_rcg2_ops,
 613 };
 614
 615 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 616         .cmd_rcgr = 0x18278,
 617         .mnd_width = 16,
 618         .hid_width = 5,
 619         .parent_map = gcc_parent_map_0,
 620         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 621         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 622 };
 623
 624 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 625         .name = "gcc_qupv3_wrap1_s3_clk_src",
 626         .parent_data = gcc_parent_data_0,
 627         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 628         .ops = &clk_rcg2_ops,
 629 };
 630
 631 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 632         .cmd_rcgr = 0x183a8,
 633         .mnd_width = 16,
 634         .hid_width = 5,
 635         .parent_map = gcc_parent_map_0,
 636         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 637         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 638 };
 639
 640 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 641         .name = "gcc_qupv3_wrap1_s4_clk_src",
 642         .parent_data = gcc_parent_data_0,
 643         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 644         .ops = &clk_rcg2_ops,
 645 };
 646
 647 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 648         .cmd_rcgr = 0x184d8,
 649         .mnd_width = 16,
 650         .hid_width = 5,
 651         .parent_map = gcc_parent_map_0,
 652         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 653         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 654 };
 655
 656 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 657         .name = "gcc_qupv3_wrap1_s5_clk_src",
 658         .parent_data = gcc_parent_data_0,
 659         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 660         .ops = &clk_rcg2_ops,
 661 };
 662
 663 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 664         .cmd_rcgr = 0x18608,
 665         .mnd_width = 16,
 666         .hid_width = 5,
 667         .parent_map = gcc_parent_map_0,
 668         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 669         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 670 };
 671
 672 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 673         .name = "gcc_qupv3_wrap1_s6_clk_src",
 674         .parent_data = gcc_parent_data_0,
 675         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 676         .ops = &clk_rcg2_ops,
 677 };
 678
 679 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 680         .cmd_rcgr = 0x18738,
 681         .mnd_width = 16,
 682         .hid_width = 5,
 683         .parent_map = gcc_parent_map_0,
 684         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 685         .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 686 };
 687
 688 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 689         .name = "gcc_qupv3_wrap1_s7_clk_src",
 690         .parent_data = gcc_parent_data_0,
 691         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 692         .ops = &clk_rcg2_ops,
 693 };
 694
 695 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 696         .cmd_rcgr = 0x18868,
 697         .mnd_width = 16,
 698         .hid_width = 5,
 699         .parent_map = gcc_parent_map_0,
 700         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 701         .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 702 };
 703
 704 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 705         F(144000, P_BI_TCXO, 16, 3, 25),
 706         F(400000, P_BI_TCXO, 12, 1, 4),
 707         F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
 708         F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
 709         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 710         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 711         F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
 712         F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
 713         { }
 714 };
 715
 716 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 717         .cmd_rcgr = 0x26028,
 718         .mnd_width = 8,
 719         .hid_width = 5,
 720         .parent_map = gcc_parent_map_11,
 721         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 722         .clkr.hw.init = &(struct clk_init_data){
 723                 .name = "gcc_sdcc1_apps_clk_src",
 724                 .parent_data = gcc_parent_data_11,
 725                 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 726                 .ops = &clk_rcg2_floor_ops,
 727         },
 728 };
 729
 730 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 731         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 732         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 733         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 734         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 735         { }
 736 };
 737
 738 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 739         .cmd_rcgr = 0x26010,
 740         .mnd_width = 8,
 741         .hid_width = 5,
 742         .parent_map = gcc_parent_map_0,
 743         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 744         .clkr.hw.init = &(struct clk_init_data){
 745                 .name = "gcc_sdcc1_ice_core_clk_src",
 746                 .parent_data = gcc_parent_data_0,
 747                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 748                 .ops = &clk_rcg2_ops,
 749         },
 750 };
 751
 752 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 753         F(400000, P_BI_TCXO, 12, 1, 4),
 754         F(9600000, P_BI_TCXO, 2, 0, 0),
 755         F(19200000, P_BI_TCXO, 1, 0, 0),
 756         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 757         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 758         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 759         F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
 760         { }
 761 };
 762
 763 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 764         .cmd_rcgr = 0x1400c,
 765         .mnd_width = 8,
 766         .hid_width = 5,
 767         .parent_map = gcc_parent_map_10,
 768         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 769         .clkr.hw.init = &(struct clk_init_data){
 770                 .name = "gcc_sdcc2_apps_clk_src",
 771                 .parent_data = gcc_parent_data_10,
 772                 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
 773                 .ops = &clk_rcg2_floor_ops,
 774         },
 775 };
 776
 777 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 778         F(400000, P_BI_TCXO, 12, 1, 4),
 779         F(9600000, P_BI_TCXO, 2, 0, 0),
 780         F(19200000, P_BI_TCXO, 1, 0, 0),
 781         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 782         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 783         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 784         { }
 785 };
 786
 787 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 788         .cmd_rcgr = 0x1600c,
 789         .mnd_width = 8,
 790         .hid_width = 5,
 791         .parent_map = gcc_parent_map_0,
 792         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 793         .clkr.hw.init = &(struct clk_init_data){
 794                 .name = "gcc_sdcc4_apps_clk_src",
 795                 .parent_data = gcc_parent_data_0,
 796                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 797                 .ops = &clk_rcg2_floor_ops,
 798         },
 799 };
 800
 801 static const struct freq_tbl ftbl_gcc_sdm670_sdcc4_apps_clk_src[] = {
 802         F(400000, P_BI_TCXO, 12, 1, 4),
 803         F(9600000, P_BI_TCXO, 2, 0, 0),
 804         F(19200000, P_BI_TCXO, 1, 0, 0),
 805         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 806         F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
 807         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 808         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 809         { }
 810 };
 811
 812 static struct clk_rcg2 gcc_sdm670_sdcc4_apps_clk_src = {
 813         .cmd_rcgr = 0x1600c,
 814         .mnd_width = 8,
 815         .hid_width = 5,
 816         .parent_map = gcc_parent_map_0,
 817         .freq_tbl = ftbl_gcc_sdm670_sdcc4_apps_clk_src,
 818         .clkr.hw.init = &(struct clk_init_data){
 819                 .name = "gcc_sdcc4_apps_clk_src",
 820                 .parent_data = gcc_parent_data_0,
 821                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 822                 .ops = &clk_rcg2_floor_ops,
 823         },
 824 };
 825
 826 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
 827         F(105495, P_BI_TCXO, 2, 1, 91),
 828         { }
 829 };
 830
 831 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
 832         .cmd_rcgr = 0x36010,
 833         .mnd_width = 8,
 834         .hid_width = 5,
 835         .parent_map = gcc_parent_map_6,
 836         .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
 837         .clkr.hw.init = &(struct clk_init_data){
 838                 .name = "gcc_tsif_ref_clk_src",
 839                 .parent_data = gcc_parent_data_6,
 840                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 841                 .ops = &clk_rcg2_ops,
 842         },
 843 };
 844
 845 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
 846         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 847         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 848         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 849         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 850         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 851         { }
 852 };
 853
 854 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
 855         .cmd_rcgr = 0x7501c,
 856         .mnd_width = 8,
 857         .hid_width = 5,
 858         .parent_map = gcc_parent_map_0,
 859         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
 860         .clkr.hw.init = &(struct clk_init_data){
 861                 .name = "gcc_ufs_card_axi_clk_src",
 862                 .parent_data = gcc_parent_data_0,
 863                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 864                 .ops = &clk_rcg2_shared_ops,
 865         },
 866 };
 867
 868 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
 869         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 870         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 871         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 872         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 873         { }
 874 };
 875
 876 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
 877         .cmd_rcgr = 0x7505c,
 878         .mnd_width = 0,
 879         .hid_width = 5,
 880         .parent_map = gcc_parent_map_0,
 881         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 882         .clkr.hw.init = &(struct clk_init_data){
 883                 .name = "gcc_ufs_card_ice_core_clk_src",
 884                 .parent_data = gcc_parent_data_0,
 885                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 886                 .ops = &clk_rcg2_shared_ops,
 887         },
 888 };
 889
 890 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
 891         .cmd_rcgr = 0x75090,
 892         .mnd_width = 0,
 893         .hid_width = 5,
 894         .parent_map = gcc_parent_map_4,
 895         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
 896         .clkr.hw.init = &(struct clk_init_data){
 897                 .name = "gcc_ufs_card_phy_aux_clk_src",
 898                 .parent_data = gcc_parent_data_4,
 899                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 900                 .ops = &clk_rcg2_ops,
 901         },
 902 };
 903
 904 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
 905         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 906         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 907         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 908         { }
 909 };
 910
 911 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
 912         .cmd_rcgr = 0x75074,
 913         .mnd_width = 0,
 914         .hid_width = 5,
 915         .parent_map = gcc_parent_map_0,
 916         .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
 917         .clkr.hw.init = &(struct clk_init_data){
 918                 .name = "gcc_ufs_card_unipro_core_clk_src",
 919                 .parent_data = gcc_parent_data_0,
 920                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 921                 .ops = &clk_rcg2_shared_ops,
 922         },
 923 };
 924
 925 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 926         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 927         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 928         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 929         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 930         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 931         { }
 932 };
 933
 934 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 935         .cmd_rcgr = 0x7701c,
 936         .mnd_width = 8,
 937         .hid_width = 5,
 938         .parent_map = gcc_parent_map_0,
 939         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 940         .clkr.hw.init = &(struct clk_init_data){
 941                 .name = "gcc_ufs_phy_axi_clk_src",
 942                 .parent_data = gcc_parent_data_0,
 943                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 944                 .ops = &clk_rcg2_shared_ops,
 945         },
 946 };
 947
 948 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 949         .cmd_rcgr = 0x7705c,
 950         .mnd_width = 0,
 951         .hid_width = 5,
 952         .parent_map = gcc_parent_map_0,
 953         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
 954         .clkr.hw.init = &(struct clk_init_data){
 955                 .name = "gcc_ufs_phy_ice_core_clk_src",
 956                 .parent_data = gcc_parent_data_0,
 957                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 958                 .ops = &clk_rcg2_shared_ops,
 959         },
 960 };
 961
 962 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 963         .cmd_rcgr = 0x77090,
 964         .mnd_width = 0,
 965         .hid_width = 5,
 966         .parent_map = gcc_parent_map_4,
 967         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 968         .clkr.hw.init = &(struct clk_init_data){
 969                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 970                 .parent_data = gcc_parent_data_4,
 971                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 972                 .ops = &clk_rcg2_shared_ops,
 973         },
 974 };
 975
 976 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 977         .cmd_rcgr = 0x77074,
 978         .mnd_width = 0,
 979         .hid_width = 5,
 980         .parent_map = gcc_parent_map_0,
 981         .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
 982         .clkr.hw.init = &(struct clk_init_data){
 983                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 984                 .parent_data = gcc_parent_data_0,
 985                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 986                 .ops = &clk_rcg2_shared_ops,
 987         },
 988 };
 989
 990 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 991         F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
 992         F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
 993         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 994         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 995         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 996         { }
 997 };
 998
 999 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1000         .cmd_rcgr = 0xf018,
1001         .mnd_width = 8,
1002         .hid_width = 5,
1003         .parent_map = gcc_parent_map_0,
1004         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1005         .clkr.hw.init = &(struct clk_init_data){
1006                 .name = "gcc_usb30_prim_master_clk_src",
1007                 .parent_data = gcc_parent_data_0,
1008                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1009                 .ops = &clk_rcg2_shared_ops,
1010         },
1011 };
1012
1013 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1014         F(19200000, P_BI_TCXO, 1, 0, 0),
1015         F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1016         F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
1017         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1018         { }
1019 };
1020
1021 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1022         .cmd_rcgr = 0xf030,
1023         .mnd_width = 0,
1024         .hid_width = 5,
1025         .parent_map = gcc_parent_map_0,
1026         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1027         .clkr.hw.init = &(struct clk_init_data){
1028                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1029                 .parent_data = gcc_parent_data_0,
1030                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1031                 .ops = &clk_rcg2_shared_ops,
1032         },
1033 };
1034
1035 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1036         .cmd_rcgr = 0x10018,
1037         .mnd_width = 8,
1038         .hid_width = 5,
1039         .parent_map = gcc_parent_map_0,
1040         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1041         .clkr.hw.init = &(struct clk_init_data){
1042                 .name = "gcc_usb30_sec_master_clk_src",
1043                 .parent_data = gcc_parent_data_0,
1044                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1045                 .ops = &clk_rcg2_ops,
1046         },
1047 };
1048
1049 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1050         .cmd_rcgr = 0x10030,
1051         .mnd_width = 0,
1052         .hid_width = 5,
1053         .parent_map = gcc_parent_map_0,
1054         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1055         .clkr.hw.init = &(struct clk_init_data){
1056                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1057                 .parent_data = gcc_parent_data_0,
1058                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1059                 .ops = &clk_rcg2_ops,
1060         },
1061 };
1062
1063 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1064         .cmd_rcgr = 0xf05c,
1065         .mnd_width = 0,
1066         .hid_width = 5,
1067         .parent_map = gcc_parent_map_2,
1068         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1069         .clkr.hw.init = &(struct clk_init_data){
1070                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1071                 .parent_data = gcc_parent_data_2,
1072                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1073                 .ops = &clk_rcg2_ops,
1074         },
1075 };
1076
1077 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1078         .cmd_rcgr = 0x1005c,
1079         .mnd_width = 0,
1080         .hid_width = 5,
1081         .parent_map = gcc_parent_map_2,
1082         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1083         .clkr.hw.init = &(struct clk_init_data){
1084                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1085                 .parent_data = gcc_parent_data_2,
1086                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1087                 .ops = &clk_rcg2_shared_ops,
1088         },
1089 };
1090
1091 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
1092         .cmd_rcgr = 0x7a030,
1093         .mnd_width = 0,
1094         .hid_width = 5,
1095         .parent_map = gcc_parent_map_3,
1096         .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
1097         .clkr.hw.init = &(struct clk_init_data){
1098                 .name = "gcc_vs_ctrl_clk_src",
1099                 .parent_data = gcc_parent_data_3,
1100                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1101                 .ops = &clk_rcg2_ops,
1102         },
1103 };
1104
1105 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
1106         F(19200000, P_BI_TCXO, 1, 0, 0),
1107         F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1108         F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
1109         { }
1110 };
1111
1112 static struct clk_rcg2 gcc_vsensor_clk_src = {
1113         .cmd_rcgr = 0x7a018,
1114         .mnd_width = 0,
1115         .hid_width = 5,
1116         .parent_map = gcc_parent_map_3,
1117         .freq_tbl = ftbl_gcc_vsensor_clk_src,
1118         .clkr.hw.init = &(struct clk_init_data){
1119                 .name = "gcc_vsensor_clk_src",
1120                 .parent_data = gcc_parent_data_8,
1121                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
1122                 .ops = &clk_rcg2_ops,
1123         },
1124 };
1125
1126 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1127         .halt_reg = 0x90014,
1128         .halt_check = BRANCH_HALT,
1129         .clkr = {
1130                 .enable_reg = 0x90014,
1131                 .enable_mask = BIT(0),
1132                 .hw.init = &(struct clk_init_data){
1133                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1134                         .ops = &clk_branch2_ops,
1135                 },
1136         },
1137 };
1138
1139 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1140         .halt_reg = 0x82028,
1141         .halt_check = BRANCH_HALT,
1142         .hwcg_reg = 0x82028,
1143         .hwcg_bit = 1,
1144         .clkr = {
1145                 .enable_reg = 0x82028,
1146                 .enable_mask = BIT(0),
1147                 .hw.init = &(struct clk_init_data){
1148                         .name = "gcc_aggre_ufs_card_axi_clk",
1149                         .parent_hws = (const struct clk_hw*[]){
1150                                 &gcc_ufs_card_axi_clk_src.clkr.hw,
1151                         },
1152                         .num_parents = 1,
1153                         .flags = CLK_SET_RATE_PARENT,
1154                         .ops = &clk_branch2_ops,
1155                 },
1156         },
1157 };
1158
1159 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1160         .halt_reg = 0x82024,
1161         .halt_check = BRANCH_HALT,
1162         .hwcg_reg = 0x82024,
1163         .hwcg_bit = 1,
1164         .clkr = {
1165                 .enable_reg = 0x82024,
1166                 .enable_mask = BIT(0),
1167                 .hw.init = &(struct clk_init_data){
1168                         .name = "gcc_aggre_ufs_phy_axi_clk",
1169                         .parent_hws = (const struct clk_hw*[]){
1170                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1171                         },
1172                         .num_parents = 1,
1173                         .flags = CLK_SET_RATE_PARENT,
1174                         .ops = &clk_branch2_ops,
1175                 },
1176         },
1177 };
1178
1179 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1180         .halt_reg = 0x8201c,
1181         .halt_check = BRANCH_HALT,
1182         .clkr = {
1183                 .enable_reg = 0x8201c,
1184                 .enable_mask = BIT(0),
1185                 .hw.init = &(struct clk_init_data){
1186                         .name = "gcc_aggre_usb3_prim_axi_clk",
1187                         .parent_hws = (const struct clk_hw*[]){
1188                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1189                         },
1190                         .num_parents = 1,
1191                         .flags = CLK_SET_RATE_PARENT,
1192                         .ops = &clk_branch2_ops,
1193                 },
1194         },
1195 };
1196
1197 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1198         .halt_reg = 0x82020,
1199         .halt_check = BRANCH_HALT,
1200         .clkr = {
1201                 .enable_reg = 0x82020,
1202                 .enable_mask = BIT(0),
1203                 .hw.init = &(struct clk_init_data){
1204                         .name = "gcc_aggre_usb3_sec_axi_clk",
1205                         .parent_hws = (const struct clk_hw*[]){
1206                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1207                         },
1208                         .num_parents = 1,
1209                         .flags = CLK_SET_RATE_PARENT,
1210                         .ops = &clk_branch2_ops,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gcc_apc_vs_clk = {
1216         .halt_reg = 0x7a050,
1217         .halt_check = BRANCH_HALT,
1218         .clkr = {
1219                 .enable_reg = 0x7a050,
1220                 .enable_mask = BIT(0),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "gcc_apc_vs_clk",
1223                         .parent_hws = (const struct clk_hw*[]){
1224                                 &gcc_vsensor_clk_src.clkr.hw,
1225                         },
1226                         .num_parents = 1,
1227                         .flags = CLK_SET_RATE_PARENT,
1228                         .ops = &clk_branch2_ops,
1229                 },
1230         },
1231 };
1232
1233 static struct clk_branch gcc_boot_rom_ahb_clk = {
1234         .halt_reg = 0x38004,
1235         .halt_check = BRANCH_HALT_VOTED,
1236         .hwcg_reg = 0x38004,
1237         .hwcg_bit = 1,
1238         .clkr = {
1239                 .enable_reg = 0x52004,
1240                 .enable_mask = BIT(10),
1241                 .hw.init = &(struct clk_init_data){
1242                         .name = "gcc_boot_rom_ahb_clk",
1243                         .ops = &clk_branch2_ops,
1244                 },
1245         },
1246 };
1247
1248 static struct clk_branch gcc_camera_ahb_clk = {
1249         .halt_reg = 0xb008,
1250         .halt_check = BRANCH_HALT,
1251         .hwcg_reg = 0xb008,
1252         .hwcg_bit = 1,
1253         .clkr = {
1254                 .enable_reg = 0xb008,
1255                 .enable_mask = BIT(0),
1256                 .hw.init = &(struct clk_init_data){
1257                         .name = "gcc_camera_ahb_clk",
1258                         .flags = CLK_IS_CRITICAL,
1259                         .ops = &clk_branch2_ops,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gcc_camera_axi_clk = {
1265         .halt_reg = 0xb020,
1266         .halt_check = BRANCH_VOTED,
1267         .clkr = {
1268                 .enable_reg = 0xb020,
1269                 .enable_mask = BIT(0),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gcc_camera_axi_clk",
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_branch gcc_camera_xo_clk = {
1278         .halt_reg = 0xb02c,
1279         .halt_check = BRANCH_HALT,
1280         .clkr = {
1281                 .enable_reg = 0xb02c,
1282                 .enable_mask = BIT(0),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "gcc_camera_xo_clk",
1285                         .flags = CLK_IS_CRITICAL,
1286                         .ops = &clk_branch2_ops,
1287                 },
1288         },
1289 };
1290
1291 static struct clk_branch gcc_ce1_ahb_clk = {
1292         .halt_reg = 0x4100c,
1293         .halt_check = BRANCH_HALT_VOTED,
1294         .hwcg_reg = 0x4100c,
1295         .hwcg_bit = 1,
1296         .clkr = {
1297                 .enable_reg = 0x52004,
1298                 .enable_mask = BIT(3),
1299                 .hw.init = &(struct clk_init_data){
1300                         .name = "gcc_ce1_ahb_clk",
1301                         .ops = &clk_branch2_ops,
1302                 },
1303         },
1304 };
1305
1306 static struct clk_branch gcc_ce1_axi_clk = {
1307         .halt_reg = 0x41008,
1308         .halt_check = BRANCH_HALT_VOTED,
1309         .clkr = {
1310                 .enable_reg = 0x52004,
1311                 .enable_mask = BIT(4),
1312                 .hw.init = &(struct clk_init_data){
1313                         .name = "gcc_ce1_axi_clk",
1314                         .ops = &clk_branch2_ops,
1315                 },
1316         },
1317 };
1318
1319 static struct clk_branch gcc_ce1_clk = {
1320         .halt_reg = 0x41004,
1321         .halt_check = BRANCH_HALT_VOTED,
1322         .clkr = {
1323                 .enable_reg = 0x52004,
1324                 .enable_mask = BIT(5),
1325                 .hw.init = &(struct clk_init_data){
1326                         .name = "gcc_ce1_clk",
1327                         .ops = &clk_branch2_ops,
1328                 },
1329         },
1330 };
1331
1332 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1333         .halt_reg = 0x502c,
1334         .halt_check = BRANCH_HALT,
1335         .clkr = {
1336                 .enable_reg = 0x502c,
1337                 .enable_mask = BIT(0),
1338                 .hw.init = &(struct clk_init_data){
1339                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1340                         .parent_hws = (const struct clk_hw*[]){
1341                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1342                         },
1343                         .num_parents = 1,
1344                         .flags = CLK_SET_RATE_PARENT,
1345                         .ops = &clk_branch2_ops,
1346                 },
1347         },
1348 };
1349
1350 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1351         .halt_reg = 0x5030,
1352         .halt_check = BRANCH_HALT,
1353         .clkr = {
1354                 .enable_reg = 0x5030,
1355                 .enable_mask = BIT(0),
1356                 .hw.init = &(struct clk_init_data){
1357                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1358                         .parent_hws = (const struct clk_hw*[]){
1359                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1360                         },
1361                         .num_parents = 1,
1362                         .flags = CLK_SET_RATE_PARENT,
1363                         .ops = &clk_branch2_ops,
1364                 },
1365         },
1366 };
1367
1368 static struct clk_branch gcc_cpuss_ahb_clk = {
1369         .halt_reg = 0x48000,
1370         .halt_check = BRANCH_HALT_VOTED,
1371         .clkr = {
1372                 .enable_reg = 0x52004,
1373                 .enable_mask = BIT(21),
1374                 .hw.init = &(struct clk_init_data){
1375                         .name = "gcc_cpuss_ahb_clk",
1376                         .parent_hws = (const struct clk_hw*[]){
1377                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1378                         },
1379                         .num_parents = 1,
1380                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1381                         .ops = &clk_branch2_ops,
1382                 },
1383         },
1384 };
1385
1386 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1387         .halt_reg = 0x48008,
1388         .halt_check = BRANCH_HALT,
1389         .clkr = {
1390                 .enable_reg = 0x48008,
1391                 .enable_mask = BIT(0),
1392                 .hw.init = &(struct clk_init_data){
1393                         .name = "gcc_cpuss_rbcpr_clk",
1394                         .parent_hws = (const struct clk_hw*[]){
1395                                 &gcc_cpuss_rbcpr_clk_src.clkr.hw,
1396                         },
1397                         .num_parents = 1,
1398                         .flags = CLK_SET_RATE_PARENT,
1399                         .ops = &clk_branch2_ops,
1400                 },
1401         },
1402 };
1403
1404 /*
1405  * The source clock frequencies are different for SDM670; define a child clock
1406  * pointing to the source clock that uses SDM670 frequencies.
1407  */
1408 static struct clk_branch gcc_sdm670_cpuss_rbcpr_clk = {
1409         .halt_reg = 0x48008,
1410         .halt_check = BRANCH_HALT,
1411         .clkr = {
1412                 .enable_reg = 0x48008,
1413                 .enable_mask = BIT(0),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "gcc_cpuss_rbcpr_clk",
1416                         .parent_hws = (const struct clk_hw*[]){
1417                                 &gcc_sdm670_cpuss_rbcpr_clk_src.clkr.hw,
1418                         },
1419                         .num_parents = 1,
1420                         .flags = CLK_SET_RATE_PARENT,
1421                         .ops = &clk_branch2_ops,
1422                 },
1423         },
1424 };
1425
1426 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1427         .halt_reg = 0x44038,
1428         .halt_check = BRANCH_VOTED,
1429         .clkr = {
1430                 .enable_reg = 0x44038,
1431                 .enable_mask = BIT(0),
1432                 .hw.init = &(struct clk_init_data){
1433                         .name = "gcc_ddrss_gpu_axi_clk",
1434                         .ops = &clk_branch2_ops,
1435                 },
1436         },
1437 };
1438
1439 static struct clk_branch gcc_disp_ahb_clk = {
1440         .halt_reg = 0xb00c,
1441         .halt_check = BRANCH_HALT,
1442         .hwcg_reg = 0xb00c,
1443         .hwcg_bit = 1,
1444         .clkr = {
1445                 .enable_reg = 0xb00c,
1446                 .enable_mask = BIT(0),
1447                 .hw.init = &(struct clk_init_data){
1448                         .name = "gcc_disp_ahb_clk",
1449                         .flags = CLK_IS_CRITICAL,
1450                         .ops = &clk_branch2_ops,
1451                 },
1452         },
1453 };
1454
1455 static struct clk_branch gcc_disp_axi_clk = {
1456         .halt_reg = 0xb024,
1457         .halt_check = BRANCH_VOTED,
1458         .clkr = {
1459                 .enable_reg = 0xb024,
1460                 .enable_mask = BIT(0),
1461                 .hw.init = &(struct clk_init_data){
1462                         .name = "gcc_disp_axi_clk",
1463                         .ops = &clk_branch2_ops,
1464                 },
1465         },
1466 };
1467
1468 static struct clk_branch gcc_disp_gpll0_clk_src = {
1469         .halt_check = BRANCH_HALT_DELAY,
1470         .clkr = {
1471                 .enable_reg = 0x52004,
1472                 .enable_mask = BIT(18),
1473                 .hw.init = &(struct clk_init_data){
1474                         .name = "gcc_disp_gpll0_clk_src",
1475                         .parent_hws = (const struct clk_hw*[]){
1476                                 &gpll0.clkr.hw,
1477                         },
1478                         .num_parents = 1,
1479                         .ops = &clk_branch2_aon_ops,
1480                 },
1481         },
1482 };
1483
1484 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1485         .halt_check = BRANCH_HALT_DELAY,
1486         .clkr = {
1487                 .enable_reg = 0x52004,
1488                 .enable_mask = BIT(19),
1489                 .hw.init = &(struct clk_init_data){
1490                         .name = "gcc_disp_gpll0_div_clk_src",
1491                         .parent_hws = (const struct clk_hw*[]){
1492                                 &gpll0_out_even.clkr.hw,
1493                         },
1494                         .num_parents = 1,
1495                         .ops = &clk_branch2_ops,
1496                 },
1497         },
1498 };
1499
1500 static struct clk_branch gcc_disp_xo_clk = {
1501         .halt_reg = 0xb030,
1502         .halt_check = BRANCH_HALT,
1503         .clkr = {
1504                 .enable_reg = 0xb030,
1505                 .enable_mask = BIT(0),
1506                 .hw.init = &(struct clk_init_data){
1507                         .name = "gcc_disp_xo_clk",
1508                         .flags = CLK_IS_CRITICAL,
1509                         .ops = &clk_branch2_ops,
1510                 },
1511         },
1512 };
1513
1514 static struct clk_branch gcc_gp1_clk = {
1515         .halt_reg = 0x64000,
1516         .halt_check = BRANCH_HALT,
1517         .clkr = {
1518                 .enable_reg = 0x64000,
1519                 .enable_mask = BIT(0),
1520                 .hw.init = &(struct clk_init_data){
1521                         .name = "gcc_gp1_clk",
1522                         .parent_hws = (const struct clk_hw*[]){
1523                                 &gcc_gp1_clk_src.clkr.hw,
1524                         },
1525                         .num_parents = 1,
1526                         .flags = CLK_SET_RATE_PARENT,
1527                         .ops = &clk_branch2_ops,
1528                 },
1529         },
1530 };
1531
1532 static struct clk_branch gcc_gp2_clk = {
1533         .halt_reg = 0x65000,
1534         .halt_check = BRANCH_HALT,
1535         .clkr = {
1536                 .enable_reg = 0x65000,
1537                 .enable_mask = BIT(0),
1538                 .hw.init = &(struct clk_init_data){
1539                         .name = "gcc_gp2_clk",
1540                         .parent_hws = (const struct clk_hw*[]){
1541                                 &gcc_gp2_clk_src.clkr.hw,
1542                         },
1543                         .num_parents = 1,
1544                         .flags = CLK_SET_RATE_PARENT,
1545                         .ops = &clk_branch2_ops,
1546                 },
1547         },
1548 };
1549
1550 static struct clk_branch gcc_gp3_clk = {
1551         .halt_reg = 0x66000,
1552         .halt_check = BRANCH_HALT,
1553         .clkr = {
1554                 .enable_reg = 0x66000,
1555                 .enable_mask = BIT(0),
1556                 .hw.init = &(struct clk_init_data){
1557                         .name = "gcc_gp3_clk",
1558                         .parent_hws = (const struct clk_hw*[]){
1559                                 &gcc_gp3_clk_src.clkr.hw,
1560                         },
1561                         .num_parents = 1,
1562                         .flags = CLK_SET_RATE_PARENT,
1563                         .ops = &clk_branch2_ops,
1564                 },
1565         },
1566 };
1567
1568 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1569         .halt_reg = 0x71004,
1570         .halt_check = BRANCH_HALT,
1571         .hwcg_reg = 0x71004,
1572         .hwcg_bit = 1,
1573         .clkr = {
1574                 .enable_reg = 0x71004,
1575                 .enable_mask = BIT(0),
1576                 .hw.init = &(struct clk_init_data){
1577                         .name = "gcc_gpu_cfg_ahb_clk",
1578                         .flags = CLK_IS_CRITICAL,
1579                         .ops = &clk_branch2_ops,
1580                 },
1581         },
1582 };
1583
1584 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1585         .halt_check = BRANCH_HALT_DELAY,
1586         .clkr = {
1587                 .enable_reg = 0x52004,
1588                 .enable_mask = BIT(15),
1589                 .hw.init = &(struct clk_init_data){
1590                         .name = "gcc_gpu_gpll0_clk_src",
1591                         .parent_hws = (const struct clk_hw*[]){
1592                                 &gpll0.clkr.hw,
1593                         },
1594                         .num_parents = 1,
1595                         .ops = &clk_branch2_ops,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1601         .halt_check = BRANCH_HALT_DELAY,
1602         .clkr = {
1603                 .enable_reg = 0x52004,
1604                 .enable_mask = BIT(16),
1605                 .hw.init = &(struct clk_init_data){
1606                         .name = "gcc_gpu_gpll0_div_clk_src",
1607                         .parent_hws = (const struct clk_hw*[]){
1608                                 &gpll0_out_even.clkr.hw,
1609                         },
1610                         .num_parents = 1,
1611                         .ops = &clk_branch2_ops,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch gcc_gpu_iref_clk = {
1617         .halt_reg = 0x8c010,
1618         .halt_check = BRANCH_HALT,
1619         .clkr = {
1620                 .enable_reg = 0x8c010,
1621                 .enable_mask = BIT(0),
1622                 .hw.init = &(struct clk_init_data){
1623                         .name = "gcc_gpu_iref_clk",
1624                         .ops = &clk_branch2_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1630         .halt_reg = 0x7100c,
1631         .halt_check = BRANCH_VOTED,
1632         .clkr = {
1633                 .enable_reg = 0x7100c,
1634                 .enable_mask = BIT(0),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "gcc_gpu_memnoc_gfx_clk",
1637                         .ops = &clk_branch2_ops,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1643         .halt_reg = 0x71018,
1644         .halt_check = BRANCH_HALT,
1645         .clkr = {
1646                 .enable_reg = 0x71018,
1647                 .enable_mask = BIT(0),
1648                 .hw.init = &(struct clk_init_data){
1649                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1650                         .ops = &clk_branch2_ops,
1651                 },
1652         },
1653 };
1654
1655 static struct clk_branch gcc_gpu_vs_clk = {
1656         .halt_reg = 0x7a04c,
1657         .halt_check = BRANCH_HALT,
1658         .clkr = {
1659                 .enable_reg = 0x7a04c,
1660                 .enable_mask = BIT(0),
1661                 .hw.init = &(struct clk_init_data){
1662                         .name = "gcc_gpu_vs_clk",
1663                         .parent_hws = (const struct clk_hw*[]){
1664                                 &gcc_vsensor_clk_src.clkr.hw,
1665                         },
1666                         .num_parents = 1,
1667                         .flags = CLK_SET_RATE_PARENT,
1668                         .ops = &clk_branch2_ops,
1669                 },
1670         },
1671 };
1672
1673 static struct clk_branch gcc_mss_axis2_clk = {
1674         .halt_reg = 0x8a008,
1675         .halt_check = BRANCH_HALT,
1676         .clkr = {
1677                 .enable_reg = 0x8a008,
1678                 .enable_mask = BIT(0),
1679                 .hw.init = &(struct clk_init_data){
1680                         .name = "gcc_mss_axis2_clk",
1681                         .ops = &clk_branch2_ops,
1682                 },
1683         },
1684 };
1685
1686 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1687         .halt_reg = 0x8a000,
1688         .halt_check = BRANCH_HALT,
1689         .hwcg_reg = 0x8a000,
1690         .hwcg_bit = 1,
1691         .clkr = {
1692                 .enable_reg = 0x8a000,
1693                 .enable_mask = BIT(0),
1694                 .hw.init = &(struct clk_init_data){
1695                         .name = "gcc_mss_cfg_ahb_clk",
1696                         .ops = &clk_branch2_ops,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1702         .halt_check = BRANCH_HALT_DELAY,
1703         .clkr = {
1704                 .enable_reg = 0x52004,
1705                 .enable_mask = BIT(17),
1706                 .hw.init = &(struct clk_init_data){
1707                         .name = "gcc_mss_gpll0_div_clk_src",
1708                         .ops = &clk_branch2_ops,
1709                 },
1710         },
1711 };
1712
1713 static struct clk_branch gcc_mss_mfab_axis_clk = {
1714         .halt_reg = 0x8a004,
1715         .halt_check = BRANCH_VOTED,
1716         .hwcg_reg = 0x8a004,
1717         .hwcg_bit = 1,
1718         .clkr = {
1719                 .enable_reg = 0x8a004,
1720                 .enable_mask = BIT(0),
1721                 .hw.init = &(struct clk_init_data){
1722                         .name = "gcc_mss_mfab_axis_clk",
1723                         .ops = &clk_branch2_ops,
1724                 },
1725         },
1726 };
1727
1728 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1729         .halt_reg = 0x8a154,
1730         .halt_check = BRANCH_VOTED,
1731         .clkr = {
1732                 .enable_reg = 0x8a154,
1733                 .enable_mask = BIT(0),
1734                 .hw.init = &(struct clk_init_data){
1735                         .name = "gcc_mss_q6_memnoc_axi_clk",
1736                         .ops = &clk_branch2_ops,
1737                 },
1738         },
1739 };
1740
1741 static struct clk_branch gcc_mss_snoc_axi_clk = {
1742         .halt_reg = 0x8a150,
1743         .halt_check = BRANCH_HALT,
1744         .clkr = {
1745                 .enable_reg = 0x8a150,
1746                 .enable_mask = BIT(0),
1747                 .hw.init = &(struct clk_init_data){
1748                         .name = "gcc_mss_snoc_axi_clk",
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static struct clk_branch gcc_mss_vs_clk = {
1755         .halt_reg = 0x7a048,
1756         .halt_check = BRANCH_HALT,
1757         .clkr = {
1758                 .enable_reg = 0x7a048,
1759                 .enable_mask = BIT(0),
1760                 .hw.init = &(struct clk_init_data){
1761                         .name = "gcc_mss_vs_clk",
1762                         .parent_hws = (const struct clk_hw*[]){
1763                                 &gcc_vsensor_clk_src.clkr.hw,
1764                         },
1765                         .num_parents = 1,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                         .ops = &clk_branch2_ops,
1768                 },
1769         },
1770 };
1771
1772 static struct clk_branch gcc_pcie_0_aux_clk = {
1773         .halt_reg = 0x6b01c,
1774         .halt_check = BRANCH_HALT_VOTED,
1775         .clkr = {
1776                 .enable_reg = 0x5200c,
1777                 .enable_mask = BIT(3),
1778                 .hw.init = &(struct clk_init_data){
1779                         .name = "gcc_pcie_0_aux_clk",
1780                         .parent_hws = (const struct clk_hw*[]){
1781                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1782                         },
1783                         .num_parents = 1,
1784                         .flags = CLK_SET_RATE_PARENT,
1785                         .ops = &clk_branch2_ops,
1786                 },
1787         },
1788 };
1789
1790 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1791         .halt_reg = 0x6b018,
1792         .halt_check = BRANCH_HALT_VOTED,
1793         .hwcg_reg = 0x6b018,
1794         .hwcg_bit = 1,
1795         .clkr = {
1796                 .enable_reg = 0x5200c,
1797                 .enable_mask = BIT(2),
1798                 .hw.init = &(struct clk_init_data){
1799                         .name = "gcc_pcie_0_cfg_ahb_clk",
1800                         .ops = &clk_branch2_ops,
1801                 },
1802         },
1803 };
1804
1805 static struct clk_branch gcc_pcie_0_clkref_clk = {
1806         .halt_reg = 0x8c00c,
1807         .halt_check = BRANCH_HALT,
1808         .clkr = {
1809                 .enable_reg = 0x8c00c,
1810                 .enable_mask = BIT(0),
1811                 .hw.init = &(struct clk_init_data){
1812                         .name = "gcc_pcie_0_clkref_clk",
1813                         .ops = &clk_branch2_ops,
1814                 },
1815         },
1816 };
1817
1818 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1819         .halt_reg = 0x6b014,
1820         .halt_check = BRANCH_HALT_VOTED,
1821         .clkr = {
1822                 .enable_reg = 0x5200c,
1823                 .enable_mask = BIT(1),
1824                 .hw.init = &(struct clk_init_data){
1825                         .name = "gcc_pcie_0_mstr_axi_clk",
1826                         .ops = &clk_branch2_ops,
1827                 },
1828         },
1829 };
1830
1831 static struct clk_branch gcc_pcie_0_pipe_clk = {
1832         .halt_check = BRANCH_HALT_SKIP,
1833         .clkr = {
1834                 .enable_reg = 0x5200c,
1835                 .enable_mask = BIT(4),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "gcc_pcie_0_pipe_clk",
1838                         .parent_data = &(const struct clk_parent_data){
1839                                 .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk",
1840                         },
1841                         .num_parents = 1,
1842                         .flags = CLK_SET_RATE_PARENT,
1843                         .ops = &clk_branch2_ops,
1844                 },
1845         },
1846 };
1847
1848 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1849         .halt_reg = 0x6b010,
1850         .halt_check = BRANCH_HALT_VOTED,
1851         .hwcg_reg = 0x6b010,
1852         .hwcg_bit = 1,
1853         .clkr = {
1854                 .enable_reg = 0x5200c,
1855                 .enable_mask = BIT(0),
1856                 .hw.init = &(struct clk_init_data){
1857                         .name = "gcc_pcie_0_slv_axi_clk",
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1864         .halt_reg = 0x6b00c,
1865         .halt_check = BRANCH_HALT_VOTED,
1866         .clkr = {
1867                 .enable_reg = 0x5200c,
1868                 .enable_mask = BIT(5),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1871                         .ops = &clk_branch2_ops,
1872                 },
1873         },
1874 };
1875
1876 static struct clk_branch gcc_pcie_1_aux_clk = {
1877         .halt_reg = 0x8d01c,
1878         .halt_check = BRANCH_HALT_VOTED,
1879         .clkr = {
1880                 .enable_reg = 0x52004,
1881                 .enable_mask = BIT(29),
1882                 .hw.init = &(struct clk_init_data){
1883                         .name = "gcc_pcie_1_aux_clk",
1884                         .parent_hws = (const struct clk_hw*[]){
1885                                 &gcc_pcie_1_aux_clk_src.clkr.hw,
1886                         },
1887                         .num_parents = 1,
1888                         .flags = CLK_SET_RATE_PARENT,
1889                         .ops = &clk_branch2_ops,
1890                 },
1891         },
1892 };
1893
1894 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1895         .halt_reg = 0x8d018,
1896         .halt_check = BRANCH_HALT_VOTED,
1897         .hwcg_reg = 0x8d018,
1898         .hwcg_bit = 1,
1899         .clkr = {
1900                 .enable_reg = 0x52004,
1901                 .enable_mask = BIT(28),
1902                 .hw.init = &(struct clk_init_data){
1903                         .name = "gcc_pcie_1_cfg_ahb_clk",
1904                         .ops = &clk_branch2_ops,
1905                 },
1906         },
1907 };
1908
1909 static struct clk_branch gcc_pcie_1_clkref_clk = {
1910         .halt_reg = 0x8c02c,
1911         .halt_check = BRANCH_HALT,
1912         .clkr = {
1913                 .enable_reg = 0x8c02c,
1914                 .enable_mask = BIT(0),
1915                 .hw.init = &(struct clk_init_data){
1916                         .name = "gcc_pcie_1_clkref_clk",
1917                         .ops = &clk_branch2_ops,
1918                 },
1919         },
1920 };
1921
1922 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1923         .halt_reg = 0x8d014,
1924         .halt_check = BRANCH_HALT_VOTED,
1925         .clkr = {
1926                 .enable_reg = 0x52004,
1927                 .enable_mask = BIT(27),
1928                 .hw.init = &(struct clk_init_data){
1929                         .name = "gcc_pcie_1_mstr_axi_clk",
1930                         .ops = &clk_branch2_ops,
1931                 },
1932         },
1933 };
1934
1935 static struct clk_branch gcc_pcie_1_pipe_clk = {
1936         .halt_check = BRANCH_HALT_SKIP,
1937         .clkr = {
1938                 .enable_reg = 0x52004,
1939                 .enable_mask = BIT(30),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "gcc_pcie_1_pipe_clk",
1942                         .parent_data = &(const struct clk_parent_data){
1943                                 .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk",
1944                         },
1945                         .num_parents = 1,
1946                         .ops = &clk_branch2_ops,
1947                 },
1948         },
1949 };
1950
1951 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1952         .halt_reg = 0x8d010,
1953         .halt_check = BRANCH_HALT_VOTED,
1954         .hwcg_reg = 0x8d010,
1955         .hwcg_bit = 1,
1956         .clkr = {
1957                 .enable_reg = 0x52004,
1958                 .enable_mask = BIT(26),
1959                 .hw.init = &(struct clk_init_data){
1960                         .name = "gcc_pcie_1_slv_axi_clk",
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1967         .halt_reg = 0x8d00c,
1968         .halt_check = BRANCH_HALT_VOTED,
1969         .clkr = {
1970                 .enable_reg = 0x52004,
1971                 .enable_mask = BIT(25),
1972                 .hw.init = &(struct clk_init_data){
1973                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1974                         .ops = &clk_branch2_ops,
1975                 },
1976         },
1977 };
1978
1979 static struct clk_branch gcc_pcie_phy_aux_clk = {
1980         .halt_reg = 0x6f004,
1981         .halt_check = BRANCH_HALT,
1982         .clkr = {
1983                 .enable_reg = 0x6f004,
1984                 .enable_mask = BIT(0),
1985                 .hw.init = &(struct clk_init_data){
1986                         .name = "gcc_pcie_phy_aux_clk",
1987                         .parent_hws = (const struct clk_hw*[]){
1988                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1989                         },
1990                         .num_parents = 1,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                         .ops = &clk_branch2_ops,
1993                 },
1994         },
1995 };
1996
1997 static struct clk_branch gcc_pcie_phy_refgen_clk = {
1998         .halt_reg = 0x6f02c,
1999         .halt_check = BRANCH_HALT,
2000         .clkr = {
2001                 .enable_reg = 0x6f02c,
2002                 .enable_mask = BIT(0),
2003                 .hw.init = &(struct clk_init_data){
2004                         .name = "gcc_pcie_phy_refgen_clk",
2005                         .parent_hws = (const struct clk_hw*[]){
2006                                 &gcc_pcie_phy_refgen_clk_src.clkr.hw,
2007                         },
2008                         .num_parents = 1,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                         .ops = &clk_branch2_ops,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch gcc_pdm2_clk = {
2016         .halt_reg = 0x3300c,
2017         .halt_check = BRANCH_HALT,
2018         .clkr = {
2019                 .enable_reg = 0x3300c,
2020                 .enable_mask = BIT(0),
2021                 .hw.init = &(struct clk_init_data){
2022                         .name = "gcc_pdm2_clk",
2023                         .parent_hws = (const struct clk_hw*[]){
2024                                 &gcc_pdm2_clk_src.clkr.hw,
2025                         },
2026                         .num_parents = 1,
2027                         .flags = CLK_SET_RATE_PARENT,
2028                         .ops = &clk_branch2_ops,
2029                 },
2030         },
2031 };
2032
2033 static struct clk_branch gcc_pdm_ahb_clk = {
2034         .halt_reg = 0x33004,
2035         .halt_check = BRANCH_HALT,
2036         .hwcg_reg = 0x33004,
2037         .hwcg_bit = 1,
2038         .clkr = {
2039                 .enable_reg = 0x33004,
2040                 .enable_mask = BIT(0),
2041                 .hw.init = &(struct clk_init_data){
2042                         .name = "gcc_pdm_ahb_clk",
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_pdm_xo4_clk = {
2049         .halt_reg = 0x33008,
2050         .halt_check = BRANCH_HALT,
2051         .clkr = {
2052                 .enable_reg = 0x33008,
2053                 .enable_mask = BIT(0),
2054                 .hw.init = &(struct clk_init_data){
2055                         .name = "gcc_pdm_xo4_clk",
2056                         .ops = &clk_branch2_ops,
2057                 },
2058         },
2059 };
2060
2061 static struct clk_branch gcc_prng_ahb_clk = {
2062         .halt_reg = 0x34004,
2063         .halt_check = BRANCH_HALT_VOTED,
2064         .hwcg_reg = 0x34004,
2065         .hwcg_bit = 1,
2066         .clkr = {
2067                 .enable_reg = 0x52004,
2068                 .enable_mask = BIT(13),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "gcc_prng_ahb_clk",
2071                         .ops = &clk_branch2_ops,
2072                 },
2073         },
2074 };
2075
2076 static struct clk_branch gcc_qmip_camera_ahb_clk = {
2077         .halt_reg = 0xb014,
2078         .halt_check = BRANCH_HALT,
2079         .hwcg_reg = 0xb014,
2080         .hwcg_bit = 1,
2081         .clkr = {
2082                 .enable_reg = 0xb014,
2083                 .enable_mask = BIT(0),
2084                 .hw.init = &(struct clk_init_data){
2085                         .name = "gcc_qmip_camera_ahb_clk",
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2092         .halt_reg = 0xb018,
2093         .halt_check = BRANCH_HALT,
2094         .hwcg_reg = 0xb018,
2095         .hwcg_bit = 1,
2096         .clkr = {
2097                 .enable_reg = 0xb018,
2098                 .enable_mask = BIT(0),
2099                 .hw.init = &(struct clk_init_data){
2100                         .name = "gcc_qmip_disp_ahb_clk",
2101                         .ops = &clk_branch2_ops,
2102                 },
2103         },
2104 };
2105
2106 static struct clk_branch gcc_qmip_video_ahb_clk = {
2107         .halt_reg = 0xb010,
2108         .halt_check = BRANCH_HALT,
2109         .hwcg_reg = 0xb010,
2110         .hwcg_bit = 1,
2111         .clkr = {
2112                 .enable_reg = 0xb010,
2113                 .enable_mask = BIT(0),
2114                 .hw.init = &(struct clk_init_data){
2115                         .name = "gcc_qmip_video_ahb_clk",
2116                         .ops = &clk_branch2_ops,
2117                 },
2118         },
2119 };
2120
2121 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2122         .halt_reg = 0x4b000,
2123         .halt_check = BRANCH_HALT,
2124         .clkr = {
2125                 .enable_reg = 0x4b000,
2126                 .enable_mask = BIT(0),
2127                 .hw.init = &(struct clk_init_data){
2128                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
2129                         .ops = &clk_branch2_ops,
2130                 },
2131         },
2132 };
2133
2134 static struct clk_branch gcc_qspi_core_clk = {
2135         .halt_reg = 0x4b004,
2136         .halt_check = BRANCH_HALT,
2137         .clkr = {
2138                 .enable_reg = 0x4b004,
2139                 .enable_mask = BIT(0),
2140                 .hw.init = &(struct clk_init_data){
2141                         .name = "gcc_qspi_core_clk",
2142                         .parent_hws = (const struct clk_hw*[]){
2143                                 &gcc_qspi_core_clk_src.clkr.hw,
2144                         },
2145                         .num_parents = 1,
2146                         .flags = CLK_SET_RATE_PARENT,
2147                         .ops = &clk_branch2_ops,
2148                 },
2149         },
2150 };
2151
2152 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2153         .halt_reg = 0x17030,
2154         .halt_check = BRANCH_HALT_VOTED,
2155         .clkr = {
2156                 .enable_reg = 0x5200c,
2157                 .enable_mask = BIT(10),
2158                 .hw.init = &(struct clk_init_data){
2159                         .name = "gcc_qupv3_wrap0_s0_clk",
2160                         .parent_hws = (const struct clk_hw*[]){
2161                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2162                         },
2163                         .num_parents = 1,
2164                         .flags = CLK_SET_RATE_PARENT,
2165                         .ops = &clk_branch2_ops,
2166                 },
2167         },
2168 };
2169
2170 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2171         .halt_reg = 0x17160,
2172         .halt_check = BRANCH_HALT_VOTED,
2173         .clkr = {
2174                 .enable_reg = 0x5200c,
2175                 .enable_mask = BIT(11),
2176                 .hw.init = &(struct clk_init_data){
2177                         .name = "gcc_qupv3_wrap0_s1_clk",
2178                         .parent_hws = (const struct clk_hw*[]){
2179                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2180                         },
2181                         .num_parents = 1,
2182                         .flags = CLK_SET_RATE_PARENT,
2183                         .ops = &clk_branch2_ops,
2184                 },
2185         },
2186 };
2187
2188 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2189         .halt_reg = 0x17290,
2190         .halt_check = BRANCH_HALT_VOTED,
2191         .clkr = {
2192                 .enable_reg = 0x5200c,
2193                 .enable_mask = BIT(12),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gcc_qupv3_wrap0_s2_clk",
2196                         .parent_hws = (const struct clk_hw*[]){
2197                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2198                         },
2199                         .num_parents = 1,
2200                         .flags = CLK_SET_RATE_PARENT,
2201                         .ops = &clk_branch2_ops,
2202                 },
2203         },
2204 };
2205
2206 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2207         .halt_reg = 0x173c0,
2208         .halt_check = BRANCH_HALT_VOTED,
2209         .clkr = {
2210                 .enable_reg = 0x5200c,
2211                 .enable_mask = BIT(13),
2212                 .hw.init = &(struct clk_init_data){
2213                         .name = "gcc_qupv3_wrap0_s3_clk",
2214                         .parent_hws = (const struct clk_hw*[]){
2215                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2216                         },
2217                         .num_parents = 1,
2218                         .flags = CLK_SET_RATE_PARENT,
2219                         .ops = &clk_branch2_ops,
2220                 },
2221         },
2222 };
2223
2224 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2225         .halt_reg = 0x174f0,
2226         .halt_check = BRANCH_HALT_VOTED,
2227         .clkr = {
2228                 .enable_reg = 0x5200c,
2229                 .enable_mask = BIT(14),
2230                 .hw.init = &(struct clk_init_data){
2231                         .name = "gcc_qupv3_wrap0_s4_clk",
2232                         .parent_hws = (const struct clk_hw*[]){
2233                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2234                         },
2235                         .num_parents = 1,
2236                         .flags = CLK_SET_RATE_PARENT,
2237                         .ops = &clk_branch2_ops,
2238                 },
2239         },
2240 };
2241
2242 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2243         .halt_reg = 0x17620,
2244         .halt_check = BRANCH_HALT_VOTED,
2245         .clkr = {
2246                 .enable_reg = 0x5200c,
2247                 .enable_mask = BIT(15),
2248                 .hw.init = &(struct clk_init_data){
2249                         .name = "gcc_qupv3_wrap0_s5_clk",
2250                         .parent_hws = (const struct clk_hw*[]){
2251                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2252                         },
2253                         .num_parents = 1,
2254                         .flags = CLK_SET_RATE_PARENT,
2255                         .ops = &clk_branch2_ops,
2256                 },
2257         },
2258 };
2259
2260 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2261         .halt_reg = 0x17750,
2262         .halt_check = BRANCH_HALT_VOTED,
2263         .clkr = {
2264                 .enable_reg = 0x5200c,
2265                 .enable_mask = BIT(16),
2266                 .hw.init = &(struct clk_init_data){
2267                         .name = "gcc_qupv3_wrap0_s6_clk",
2268                         .parent_hws = (const struct clk_hw*[]){
2269                                 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2270                         },
2271                         .num_parents = 1,
2272                         .flags = CLK_SET_RATE_PARENT,
2273                         .ops = &clk_branch2_ops,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2279         .halt_reg = 0x17880,
2280         .halt_check = BRANCH_HALT_VOTED,
2281         .clkr = {
2282                 .enable_reg = 0x5200c,
2283                 .enable_mask = BIT(17),
2284                 .hw.init = &(struct clk_init_data){
2285                         .name = "gcc_qupv3_wrap0_s7_clk",
2286                         .parent_hws = (const struct clk_hw*[]){
2287                                 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2288                         },
2289                         .num_parents = 1,
2290                         .flags = CLK_SET_RATE_PARENT,
2291                         .ops = &clk_branch2_ops,
2292                 },
2293         },
2294 };
2295
2296 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2297         .halt_reg = 0x18014,
2298         .halt_check = BRANCH_HALT_VOTED,
2299         .clkr = {
2300                 .enable_reg = 0x5200c,
2301                 .enable_mask = BIT(22),
2302                 .hw.init = &(struct clk_init_data){
2303                         .name = "gcc_qupv3_wrap1_s0_clk",
2304                         .parent_hws = (const struct clk_hw*[]){
2305                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2306                         },
2307                         .num_parents = 1,
2308                         .flags = CLK_SET_RATE_PARENT,
2309                         .ops = &clk_branch2_ops,
2310                 },
2311         },
2312 };
2313
2314 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2315         .halt_reg = 0x18144,
2316         .halt_check = BRANCH_HALT_VOTED,
2317         .clkr = {
2318                 .enable_reg = 0x5200c,
2319                 .enable_mask = BIT(23),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_qupv3_wrap1_s1_clk",
2322                         .parent_hws = (const struct clk_hw*[]){
2323                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2324                         },
2325                         .num_parents = 1,
2326                         .flags = CLK_SET_RATE_PARENT,
2327                         .ops = &clk_branch2_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2333         .halt_reg = 0x18274,
2334         .halt_check = BRANCH_HALT_VOTED,
2335         .clkr = {
2336                 .enable_reg = 0x5200c,
2337                 .enable_mask = BIT(24),
2338                 .hw.init = &(struct clk_init_data){
2339                         .name = "gcc_qupv3_wrap1_s2_clk",
2340                         .parent_hws = (const struct clk_hw*[]){
2341                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2342                         },
2343                         .num_parents = 1,
2344                         .flags = CLK_SET_RATE_PARENT,
2345                         .ops = &clk_branch2_ops,
2346                 },
2347         },
2348 };
2349
2350 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2351         .halt_reg = 0x183a4,
2352         .halt_check = BRANCH_HALT_VOTED,
2353         .clkr = {
2354                 .enable_reg = 0x5200c,
2355                 .enable_mask = BIT(25),
2356                 .hw.init = &(struct clk_init_data){
2357                         .name = "gcc_qupv3_wrap1_s3_clk",
2358                         .parent_hws = (const struct clk_hw*[]){
2359                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2360                         },
2361                         .num_parents = 1,
2362                         .flags = CLK_SET_RATE_PARENT,
2363                         .ops = &clk_branch2_ops,
2364                 },
2365         },
2366 };
2367
2368 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2369         .halt_reg = 0x184d4,
2370         .halt_check = BRANCH_HALT_VOTED,
2371         .clkr = {
2372                 .enable_reg = 0x5200c,
2373                 .enable_mask = BIT(26),
2374                 .hw.init = &(struct clk_init_data){
2375                         .name = "gcc_qupv3_wrap1_s4_clk",
2376                         .parent_hws = (const struct clk_hw*[]){
2377                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2378                         },
2379                         .num_parents = 1,
2380                         .flags = CLK_SET_RATE_PARENT,
2381                         .ops = &clk_branch2_ops,
2382                 },
2383         },
2384 };
2385
2386 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2387         .halt_reg = 0x18604,
2388         .halt_check = BRANCH_HALT_VOTED,
2389         .clkr = {
2390                 .enable_reg = 0x5200c,
2391                 .enable_mask = BIT(27),
2392                 .hw.init = &(struct clk_init_data){
2393                         .name = "gcc_qupv3_wrap1_s5_clk",
2394                         .parent_hws = (const struct clk_hw*[]){
2395                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2396                         },
2397                         .num_parents = 1,
2398                         .flags = CLK_SET_RATE_PARENT,
2399                         .ops = &clk_branch2_ops,
2400                 },
2401         },
2402 };
2403
2404 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2405         .halt_reg = 0x18734,
2406         .halt_check = BRANCH_HALT_VOTED,
2407         .clkr = {
2408                 .enable_reg = 0x5200c,
2409                 .enable_mask = BIT(28),
2410                 .hw.init = &(struct clk_init_data){
2411                         .name = "gcc_qupv3_wrap1_s6_clk",
2412                         .parent_hws = (const struct clk_hw*[]){
2413                                 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2414                         },
2415                         .num_parents = 1,
2416                         .flags = CLK_SET_RATE_PARENT,
2417                         .ops = &clk_branch2_ops,
2418                 },
2419         },
2420 };
2421
2422 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2423         .halt_reg = 0x18864,
2424         .halt_check = BRANCH_HALT_VOTED,
2425         .clkr = {
2426                 .enable_reg = 0x5200c,
2427                 .enable_mask = BIT(29),
2428                 .hw.init = &(struct clk_init_data){
2429                         .name = "gcc_qupv3_wrap1_s7_clk",
2430                         .parent_hws = (const struct clk_hw*[]){
2431                                 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2432                         },
2433                         .num_parents = 1,
2434                         .flags = CLK_SET_RATE_PARENT,
2435                         .ops = &clk_branch2_ops,
2436                 },
2437         },
2438 };
2439
2440 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2441         .halt_reg = 0x17004,
2442         .halt_check = BRANCH_HALT_VOTED,
2443         .clkr = {
2444                 .enable_reg = 0x5200c,
2445                 .enable_mask = BIT(6),
2446                 .hw.init = &(struct clk_init_data){
2447                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2448                         .ops = &clk_branch2_ops,
2449                 },
2450         },
2451 };
2452
2453 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2454         .halt_reg = 0x17008,
2455         .halt_check = BRANCH_HALT_VOTED,
2456         .hwcg_reg = 0x17008,
2457         .hwcg_bit = 1,
2458         .clkr = {
2459                 .enable_reg = 0x5200c,
2460                 .enable_mask = BIT(7),
2461                 .hw.init = &(struct clk_init_data){
2462                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2463                         .ops = &clk_branch2_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2469         .halt_reg = 0x1800c,
2470         .halt_check = BRANCH_HALT_VOTED,
2471         .clkr = {
2472                 .enable_reg = 0x5200c,
2473                 .enable_mask = BIT(20),
2474                 .hw.init = &(struct clk_init_data){
2475                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2476                         .ops = &clk_branch2_ops,
2477                 },
2478         },
2479 };
2480
2481 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2482         .halt_reg = 0x18010,
2483         .halt_check = BRANCH_HALT_VOTED,
2484         .hwcg_reg = 0x18010,
2485         .hwcg_bit = 1,
2486         .clkr = {
2487                 .enable_reg = 0x5200c,
2488                 .enable_mask = BIT(21),
2489                 .hw.init = &(struct clk_init_data){
2490                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2491                         .ops = &clk_branch2_ops,
2492                 },
2493         },
2494 };
2495
2496 static struct clk_branch gcc_sdcc1_ahb_clk = {
2497         .halt_reg = 0x26008,
2498         .halt_check = BRANCH_HALT,
2499         .clkr = {
2500                 .enable_reg = 0x26008,
2501                 .enable_mask = BIT(0),
2502                 .hw.init = &(struct clk_init_data){
2503                         .name = "gcc_sdcc1_ahb_clk",
2504                         .ops = &clk_branch2_ops,
2505                 },
2506         },
2507 };
2508
2509 static struct clk_branch gcc_sdcc1_apps_clk = {
2510         .halt_reg = 0x26004,
2511         .halt_check = BRANCH_HALT,
2512         .clkr = {
2513                 .enable_reg = 0x26004,
2514                 .enable_mask = BIT(0),
2515                 .hw.init = &(struct clk_init_data){
2516                         .name = "gcc_sdcc1_apps_clk",
2517                         .parent_hws = (const struct clk_hw*[]){
2518                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
2519                         },
2520                         .num_parents = 1,
2521                         .flags = CLK_SET_RATE_PARENT,
2522                         .ops = &clk_branch2_ops,
2523                 },
2524         },
2525 };
2526
2527 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2528         .halt_reg = 0x2600c,
2529         .halt_check = BRANCH_HALT,
2530         .clkr = {
2531                 .enable_reg = 0x2600c,
2532                 .enable_mask = BIT(0),
2533                 .hw.init = &(struct clk_init_data){
2534                         .name = "gcc_sdcc1_ice_core_clk",
2535                         .parent_hws = (const struct clk_hw*[]){
2536                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2537                         },
2538                         .num_parents = 1,
2539                         .flags = CLK_SET_RATE_PARENT,
2540                         .ops = &clk_branch2_ops,
2541                 },
2542         },
2543 };
2544
2545 static struct clk_branch gcc_sdcc2_ahb_clk = {
2546         .halt_reg = 0x14008,
2547         .halt_check = BRANCH_HALT,
2548         .clkr = {
2549                 .enable_reg = 0x14008,
2550                 .enable_mask = BIT(0),
2551                 .hw.init = &(struct clk_init_data){
2552                         .name = "gcc_sdcc2_ahb_clk",
2553                         .ops = &clk_branch2_ops,
2554                 },
2555         },
2556 };
2557
2558 static struct clk_branch gcc_sdcc2_apps_clk = {
2559         .halt_reg = 0x14004,
2560         .halt_check = BRANCH_HALT,
2561         .clkr = {
2562                 .enable_reg = 0x14004,
2563                 .enable_mask = BIT(0),
2564                 .hw.init = &(struct clk_init_data){
2565                         .name = "gcc_sdcc2_apps_clk",
2566                         .parent_hws = (const struct clk_hw*[]){
2567                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
2568                         },
2569                         .num_parents = 1,
2570                         .flags = CLK_SET_RATE_PARENT,
2571                         .ops = &clk_branch2_ops,
2572                 },
2573         },
2574 };
2575
2576 static struct clk_branch gcc_sdcc4_ahb_clk = {
2577         .halt_reg = 0x16008,
2578         .halt_check = BRANCH_HALT,
2579         .clkr = {
2580                 .enable_reg = 0x16008,
2581                 .enable_mask = BIT(0),
2582                 .hw.init = &(struct clk_init_data){
2583                         .name = "gcc_sdcc4_ahb_clk",
2584                         .ops = &clk_branch2_ops,
2585                 },
2586         },
2587 };
2588
2589 static struct clk_branch gcc_sdcc4_apps_clk = {
2590         .halt_reg = 0x16004,
2591         .halt_check = BRANCH_HALT,
2592         .clkr = {
2593                 .enable_reg = 0x16004,
2594                 .enable_mask = BIT(0),
2595                 .hw.init = &(struct clk_init_data){
2596                         .name = "gcc_sdcc4_apps_clk",
2597                         .parent_hws = (const struct clk_hw*[]){
2598                                 &gcc_sdcc4_apps_clk_src.clkr.hw,
2599                         },
2600                         .num_parents = 1,
2601                         .flags = CLK_SET_RATE_PARENT,
2602                         .ops = &clk_branch2_ops,
2603                 },
2604         },
2605 };
2606
2607 /*
2608  * The source clock frequencies are different for SDM670; define a child clock
2609  * pointing to the source clock that uses SDM670 frequencies.
2610  */
2611 static struct clk_branch gcc_sdm670_sdcc4_apps_clk = {
2612         .halt_reg = 0x16004,
2613         .halt_check = BRANCH_HALT,
2614         .clkr = {
2615                 .enable_reg = 0x16004,
2616                 .enable_mask = BIT(0),
2617                 .hw.init = &(struct clk_init_data){
2618                         .name = "gcc_sdcc4_apps_clk",
2619                         .parent_hws = (const struct clk_hw*[]){
2620                                 &gcc_sdm670_sdcc4_apps_clk_src.clkr.hw,
2621                         },
2622                         .num_parents = 1,
2623                         .flags = CLK_SET_RATE_PARENT,
2624                         .ops = &clk_branch2_ops,
2625                 },
2626         },
2627 };
2628
2629 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2630         .halt_reg = 0x414c,
2631         .halt_check = BRANCH_HALT_VOTED,
2632         .clkr = {
2633                 .enable_reg = 0x52004,
2634                 .enable_mask = BIT(0),
2635                 .hw.init = &(struct clk_init_data){
2636                         .name = "gcc_sys_noc_cpuss_ahb_clk",
2637                         .parent_hws = (const struct clk_hw*[]){
2638                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
2639                         },
2640                         .num_parents = 1,
2641                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2642                         .ops = &clk_branch2_ops,
2643                 },
2644         },
2645 };
2646
2647 static struct clk_branch gcc_tsif_ahb_clk = {
2648         .halt_reg = 0x36004,
2649         .halt_check = BRANCH_HALT,
2650         .clkr = {
2651                 .enable_reg = 0x36004,
2652                 .enable_mask = BIT(0),
2653                 .hw.init = &(struct clk_init_data){
2654                         .name = "gcc_tsif_ahb_clk",
2655                         .ops = &clk_branch2_ops,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2661         .halt_reg = 0x3600c,
2662         .halt_check = BRANCH_HALT,
2663         .clkr = {
2664                 .enable_reg = 0x3600c,
2665                 .enable_mask = BIT(0),
2666                 .hw.init = &(struct clk_init_data){
2667                         .name = "gcc_tsif_inactivity_timers_clk",
2668                         .ops = &clk_branch2_ops,
2669                 },
2670         },
2671 };
2672
2673 static struct clk_branch gcc_tsif_ref_clk = {
2674         .halt_reg = 0x36008,
2675         .halt_check = BRANCH_HALT,
2676         .clkr = {
2677                 .enable_reg = 0x36008,
2678                 .enable_mask = BIT(0),
2679                 .hw.init = &(struct clk_init_data){
2680                         .name = "gcc_tsif_ref_clk",
2681                         .parent_hws = (const struct clk_hw*[]){
2682                                 &gcc_tsif_ref_clk_src.clkr.hw,
2683                         },
2684                         .num_parents = 1,
2685                         .flags = CLK_SET_RATE_PARENT,
2686                         .ops = &clk_branch2_ops,
2687                 },
2688         },
2689 };
2690
2691 static struct clk_branch gcc_ufs_card_ahb_clk = {
2692         .halt_reg = 0x75010,
2693         .halt_check = BRANCH_HALT,
2694         .hwcg_reg = 0x75010,
2695         .hwcg_bit = 1,
2696         .clkr = {
2697                 .enable_reg = 0x75010,
2698                 .enable_mask = BIT(0),
2699                 .hw.init = &(struct clk_init_data){
2700                         .name = "gcc_ufs_card_ahb_clk",
2701                         .ops = &clk_branch2_ops,
2702                 },
2703         },
2704 };
2705
2706 static struct clk_branch gcc_ufs_card_axi_clk = {
2707         .halt_reg = 0x7500c,
2708         .halt_check = BRANCH_HALT,
2709         .hwcg_reg = 0x7500c,
2710         .hwcg_bit = 1,
2711         .clkr = {
2712                 .enable_reg = 0x7500c,
2713                 .enable_mask = BIT(0),
2714                 .hw.init = &(struct clk_init_data){
2715                         .name = "gcc_ufs_card_axi_clk",
2716                         .parent_hws = (const struct clk_hw*[]){
2717                                 &gcc_ufs_card_axi_clk_src.clkr.hw,
2718                         },
2719                         .num_parents = 1,
2720                         .flags = CLK_SET_RATE_PARENT,
2721                         .ops = &clk_branch2_ops,
2722                 },
2723         },
2724 };
2725
2726 static struct clk_branch gcc_ufs_card_clkref_clk = {
2727         .halt_reg = 0x8c004,
2728         .halt_check = BRANCH_HALT,
2729         .clkr = {
2730                 .enable_reg = 0x8c004,
2731                 .enable_mask = BIT(0),
2732                 .hw.init = &(struct clk_init_data){
2733                         .name = "gcc_ufs_card_clkref_clk",
2734                         .ops = &clk_branch2_ops,
2735                 },
2736         },
2737 };
2738
2739 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2740         .halt_reg = 0x75058,
2741         .halt_check = BRANCH_HALT,
2742         .hwcg_reg = 0x75058,
2743         .hwcg_bit = 1,
2744         .clkr = {
2745                 .enable_reg = 0x75058,
2746                 .enable_mask = BIT(0),
2747                 .hw.init = &(struct clk_init_data){
2748                         .name = "gcc_ufs_card_ice_core_clk",
2749                         .parent_hws = (const struct clk_hw*[]){
2750                                 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2751                         },
2752                         .num_parents = 1,
2753                         .flags = CLK_SET_RATE_PARENT,
2754                         .ops = &clk_branch2_ops,
2755                 },
2756         },
2757 };
2758
2759 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2760         .halt_reg = 0x7508c,
2761         .halt_check = BRANCH_HALT,
2762         .hwcg_reg = 0x7508c,
2763         .hwcg_bit = 1,
2764         .clkr = {
2765                 .enable_reg = 0x7508c,
2766                 .enable_mask = BIT(0),
2767                 .hw.init = &(struct clk_init_data){
2768                         .name = "gcc_ufs_card_phy_aux_clk",
2769                         .parent_hws = (const struct clk_hw*[]){
2770                                 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2771                         },
2772                         .num_parents = 1,
2773                         .flags = CLK_SET_RATE_PARENT,
2774                         .ops = &clk_branch2_ops,
2775                 },
2776         },
2777 };
2778
2779 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2780         .halt_check = BRANCH_HALT_SKIP,
2781         .clkr = {
2782                 .enable_reg = 0x75018,
2783                 .enable_mask = BIT(0),
2784                 .hw.init = &(struct clk_init_data){
2785                         .name = "gcc_ufs_card_rx_symbol_0_clk",
2786                         .ops = &clk_branch2_ops,
2787                 },
2788         },
2789 };
2790
2791 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2792         .halt_check = BRANCH_HALT_SKIP,
2793         .clkr = {
2794                 .enable_reg = 0x750a8,
2795                 .enable_mask = BIT(0),
2796                 .hw.init = &(struct clk_init_data){
2797                         .name = "gcc_ufs_card_rx_symbol_1_clk",
2798                         .ops = &clk_branch2_ops,
2799                 },
2800         },
2801 };
2802
2803 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2804         .halt_check = BRANCH_HALT_SKIP,
2805         .clkr = {
2806                 .enable_reg = 0x75014,
2807                 .enable_mask = BIT(0),
2808                 .hw.init = &(struct clk_init_data){
2809                         .name = "gcc_ufs_card_tx_symbol_0_clk",
2810                         .ops = &clk_branch2_ops,
2811                 },
2812         },
2813 };
2814
2815 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2816         .halt_reg = 0x75054,
2817         .halt_check = BRANCH_HALT,
2818         .hwcg_reg = 0x75054,
2819         .hwcg_bit = 1,
2820         .clkr = {
2821                 .enable_reg = 0x75054,
2822                 .enable_mask = BIT(0),
2823                 .hw.init = &(struct clk_init_data){
2824                         .name = "gcc_ufs_card_unipro_core_clk",
2825                         .parent_hws = (const struct clk_hw*[]){
2826                                 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2827                         },
2828                         .num_parents = 1,
2829                         .flags = CLK_SET_RATE_PARENT,
2830                         .ops = &clk_branch2_ops,
2831                 },
2832         },
2833 };
2834
2835 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2836         .halt_reg = 0x8c000,
2837         .halt_check = BRANCH_HALT,
2838         .clkr = {
2839                 .enable_reg = 0x8c000,
2840                 .enable_mask = BIT(0),
2841                 .hw.init = &(struct clk_init_data){
2842                         .name = "gcc_ufs_mem_clkref_clk",
2843                         .ops = &clk_branch2_ops,
2844                 },
2845         },
2846 };
2847
2848 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2849         .halt_reg = 0x77010,
2850         .halt_check = BRANCH_HALT,
2851         .hwcg_reg = 0x77010,
2852         .hwcg_bit = 1,
2853         .clkr = {
2854                 .enable_reg = 0x77010,
2855                 .enable_mask = BIT(0),
2856                 .hw.init = &(struct clk_init_data){
2857                         .name = "gcc_ufs_phy_ahb_clk",
2858                         .ops = &clk_branch2_ops,
2859                 },
2860         },
2861 };
2862
2863 static struct clk_branch gcc_ufs_phy_axi_clk = {
2864         .halt_reg = 0x7700c,
2865         .halt_check = BRANCH_HALT,
2866         .hwcg_reg = 0x7700c,
2867         .hwcg_bit = 1,
2868         .clkr = {
2869                 .enable_reg = 0x7700c,
2870                 .enable_mask = BIT(0),
2871                 .hw.init = &(struct clk_init_data){
2872                         .name = "gcc_ufs_phy_axi_clk",
2873                         .parent_hws = (const struct clk_hw*[]){
2874                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2875                         },
2876                         .num_parents = 1,
2877                         .flags = CLK_SET_RATE_PARENT,
2878                         .ops = &clk_branch2_ops,
2879                 },
2880         },
2881 };
2882
2883 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2884         .halt_reg = 0x77058,
2885         .halt_check = BRANCH_HALT,
2886         .hwcg_reg = 0x77058,
2887         .hwcg_bit = 1,
2888         .clkr = {
2889                 .enable_reg = 0x77058,
2890                 .enable_mask = BIT(0),
2891                 .hw.init = &(struct clk_init_data){
2892                         .name = "gcc_ufs_phy_ice_core_clk",
2893                         .parent_hws = (const struct clk_hw*[]){
2894                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2895                         },
2896                         .num_parents = 1,
2897                         .flags = CLK_SET_RATE_PARENT,
2898                         .ops = &clk_branch2_ops,
2899                 },
2900         },
2901 };
2902
2903 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2904         .halt_reg = 0x7708c,
2905         .halt_check = BRANCH_HALT,
2906         .hwcg_reg = 0x7708c,
2907         .hwcg_bit = 1,
2908         .clkr = {
2909                 .enable_reg = 0x7708c,
2910                 .enable_mask = BIT(0),
2911                 .hw.init = &(struct clk_init_data){
2912                         .name = "gcc_ufs_phy_phy_aux_clk",
2913                         .parent_hws = (const struct clk_hw*[]){
2914                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2915                         },
2916                         .num_parents = 1,
2917                         .flags = CLK_SET_RATE_PARENT,
2918                         .ops = &clk_branch2_ops,
2919                 },
2920         },
2921 };
2922
2923 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2924         .halt_check = BRANCH_HALT_SKIP,
2925         .clkr = {
2926                 .enable_reg = 0x77018,
2927                 .enable_mask = BIT(0),
2928                 .hw.init = &(struct clk_init_data){
2929                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2930                         .ops = &clk_branch2_ops,
2931                 },
2932         },
2933 };
2934
2935 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2936         .halt_check = BRANCH_HALT_SKIP,
2937         .clkr = {
2938                 .enable_reg = 0x770a8,
2939                 .enable_mask = BIT(0),
2940                 .hw.init = &(struct clk_init_data){
2941                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
2942                         .ops = &clk_branch2_ops,
2943                 },
2944         },
2945 };
2946
2947 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2948         .halt_check = BRANCH_HALT_SKIP,
2949         .clkr = {
2950                 .enable_reg = 0x77014,
2951                 .enable_mask = BIT(0),
2952                 .hw.init = &(struct clk_init_data){
2953                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2954                         .ops = &clk_branch2_ops,
2955                 },
2956         },
2957 };
2958
2959 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2960         .halt_reg = 0x77054,
2961         .halt_check = BRANCH_HALT,
2962         .hwcg_reg = 0x77054,
2963         .hwcg_bit = 1,
2964         .clkr = {
2965                 .enable_reg = 0x77054,
2966                 .enable_mask = BIT(0),
2967                 .hw.init = &(struct clk_init_data){
2968                         .name = "gcc_ufs_phy_unipro_core_clk",
2969                         .parent_hws = (const struct clk_hw*[]){
2970                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2971                         },
2972                         .num_parents = 1,
2973                         .flags = CLK_SET_RATE_PARENT,
2974                         .ops = &clk_branch2_ops,
2975                 },
2976         },
2977 };
2978
2979 static struct clk_branch gcc_usb30_prim_master_clk = {
2980         .halt_reg = 0xf00c,
2981         .halt_check = BRANCH_HALT,
2982         .clkr = {
2983                 .enable_reg = 0xf00c,
2984                 .enable_mask = BIT(0),
2985                 .hw.init = &(struct clk_init_data){
2986                         .name = "gcc_usb30_prim_master_clk",
2987                         .parent_hws = (const struct clk_hw*[]){
2988                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2989                         },
2990                         .num_parents = 1,
2991                         .flags = CLK_SET_RATE_PARENT,
2992                         .ops = &clk_branch2_ops,
2993                 },
2994         },
2995 };
2996
2997 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2998         .halt_reg = 0xf014,
2999         .halt_check = BRANCH_HALT,
3000         .clkr = {
3001                 .enable_reg = 0xf014,
3002                 .enable_mask = BIT(0),
3003                 .hw.init = &(struct clk_init_data){
3004                         .name = "gcc_usb30_prim_mock_utmi_clk",
3005                         .parent_hws = (const struct clk_hw*[]){
3006                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3007                         },
3008                         .num_parents = 1,
3009                         .flags = CLK_SET_RATE_PARENT,
3010                         .ops = &clk_branch2_ops,
3011                 },
3012         },
3013 };
3014
3015 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3016         .halt_reg = 0xf010,
3017         .halt_check = BRANCH_HALT,
3018         .clkr = {
3019                 .enable_reg = 0xf010,
3020                 .enable_mask = BIT(0),
3021                 .hw.init = &(struct clk_init_data){
3022                         .name = "gcc_usb30_prim_sleep_clk",
3023                         .ops = &clk_branch2_ops,
3024                 },
3025         },
3026 };
3027
3028 static struct clk_branch gcc_usb30_sec_master_clk = {
3029         .halt_reg = 0x1000c,
3030         .halt_check = BRANCH_HALT,
3031         .clkr = {
3032                 .enable_reg = 0x1000c,
3033                 .enable_mask = BIT(0),
3034                 .hw.init = &(struct clk_init_data){
3035                         .name = "gcc_usb30_sec_master_clk",
3036                         .parent_hws = (const struct clk_hw*[]){
3037                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
3038                         },
3039                         .num_parents = 1,
3040                         .flags = CLK_SET_RATE_PARENT,
3041                         .ops = &clk_branch2_ops,
3042                 },
3043         },
3044 };
3045
3046 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3047         .halt_reg = 0x10014,
3048         .halt_check = BRANCH_HALT,
3049         .clkr = {
3050                 .enable_reg = 0x10014,
3051                 .enable_mask = BIT(0),
3052                 .hw.init = &(struct clk_init_data){
3053                         .name = "gcc_usb30_sec_mock_utmi_clk",
3054                         .parent_hws = (const struct clk_hw*[]){
3055                                 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
3056                         },
3057                         .num_parents = 1,
3058                         .flags = CLK_SET_RATE_PARENT,
3059                         .ops = &clk_branch2_ops,
3060                 },
3061         },
3062 };
3063
3064 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3065         .halt_reg = 0x10010,
3066         .halt_check = BRANCH_HALT,
3067         .clkr = {
3068                 .enable_reg = 0x10010,
3069                 .enable_mask = BIT(0),
3070                 .hw.init = &(struct clk_init_data){
3071                         .name = "gcc_usb30_sec_sleep_clk",
3072                         .ops = &clk_branch2_ops,
3073                 },
3074         },
3075 };
3076
3077 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3078         .halt_reg = 0x8c008,
3079         .halt_check = BRANCH_HALT,
3080         .clkr = {
3081                 .enable_reg = 0x8c008,
3082                 .enable_mask = BIT(0),
3083                 .hw.init = &(struct clk_init_data){
3084                         .name = "gcc_usb3_prim_clkref_clk",
3085                         .ops = &clk_branch2_ops,
3086                 },
3087         },
3088 };
3089
3090 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3091         .halt_reg = 0xf04c,
3092         .halt_check = BRANCH_HALT,
3093         .clkr = {
3094                 .enable_reg = 0xf04c,
3095                 .enable_mask = BIT(0),
3096                 .hw.init = &(struct clk_init_data){
3097                         .name = "gcc_usb3_prim_phy_aux_clk",
3098                         .parent_hws = (const struct clk_hw*[]){
3099                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3100                         },
3101                         .num_parents = 1,
3102                         .flags = CLK_SET_RATE_PARENT,
3103                         .ops = &clk_branch2_ops,
3104                 },
3105         },
3106 };
3107
3108 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3109         .halt_reg = 0xf050,
3110         .halt_check = BRANCH_HALT,
3111         .clkr = {
3112                 .enable_reg = 0xf050,
3113                 .enable_mask = BIT(0),
3114                 .hw.init = &(struct clk_init_data){
3115                         .name = "gcc_usb3_prim_phy_com_aux_clk",
3116                         .parent_hws = (const struct clk_hw*[]){
3117                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3118                         },
3119                         .num_parents = 1,
3120                         .flags = CLK_SET_RATE_PARENT,
3121                         .ops = &clk_branch2_ops,
3122                 },
3123         },
3124 };
3125
3126 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3127         .halt_check = BRANCH_HALT_SKIP,
3128         .clkr = {
3129                 .enable_reg = 0xf054,
3130                 .enable_mask = BIT(0),
3131                 .hw.init = &(struct clk_init_data){
3132                         .name = "gcc_usb3_prim_phy_pipe_clk",
3133                         .ops = &clk_branch2_ops,
3134                 },
3135         },
3136 };
3137
3138 static struct clk_branch gcc_usb3_sec_clkref_clk = {
3139         .halt_reg = 0x8c028,
3140         .halt_check = BRANCH_HALT,
3141         .clkr = {
3142                 .enable_reg = 0x8c028,
3143                 .enable_mask = BIT(0),
3144                 .hw.init = &(struct clk_init_data){
3145                         .name = "gcc_usb3_sec_clkref_clk",
3146                         .ops = &clk_branch2_ops,
3147                 },
3148         },
3149 };
3150
3151 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3152         .halt_reg = 0x1004c,
3153         .halt_check = BRANCH_HALT,
3154         .clkr = {
3155                 .enable_reg = 0x1004c,
3156                 .enable_mask = BIT(0),
3157                 .hw.init = &(struct clk_init_data){
3158                         .name = "gcc_usb3_sec_phy_aux_clk",
3159                         .parent_hws = (const struct clk_hw*[]){
3160                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3161                         },
3162                         .num_parents = 1,
3163                         .flags = CLK_SET_RATE_PARENT,
3164                         .ops = &clk_branch2_ops,
3165                 },
3166         },
3167 };
3168
3169 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3170         .halt_reg = 0x10050,
3171         .halt_check = BRANCH_HALT,
3172         .clkr = {
3173                 .enable_reg = 0x10050,
3174                 .enable_mask = BIT(0),
3175                 .hw.init = &(struct clk_init_data){
3176                         .name = "gcc_usb3_sec_phy_com_aux_clk",
3177                         .parent_hws = (const struct clk_hw*[]){
3178                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3179                         },
3180                         .num_parents = 1,
3181                         .flags = CLK_SET_RATE_PARENT,
3182                         .ops = &clk_branch2_ops,
3183                 },
3184         },
3185 };
3186
3187 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3188         .halt_check = BRANCH_HALT_SKIP,
3189         .clkr = {
3190                 .enable_reg = 0x10054,
3191                 .enable_mask = BIT(0),
3192                 .hw.init = &(struct clk_init_data){
3193                         .name = "gcc_usb3_sec_phy_pipe_clk",
3194                         .ops = &clk_branch2_ops,
3195                 },
3196         },
3197 };
3198
3199 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
3200         .halt_reg = 0x6a004,
3201         .halt_check = BRANCH_HALT,
3202         .hwcg_reg = 0x6a004,
3203         .hwcg_bit = 1,
3204         .clkr = {
3205                 .enable_reg = 0x6a004,
3206                 .enable_mask = BIT(0),
3207                 .hw.init = &(struct clk_init_data){
3208                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
3209                         .ops = &clk_branch2_ops,
3210                 },
3211         },
3212 };
3213
3214 static struct clk_branch gcc_vdda_vs_clk = {
3215         .halt_reg = 0x7a00c,
3216         .halt_check = BRANCH_HALT,
3217         .clkr = {
3218                 .enable_reg = 0x7a00c,
3219                 .enable_mask = BIT(0),
3220                 .hw.init = &(struct clk_init_data){
3221                         .name = "gcc_vdda_vs_clk",
3222                         .parent_hws = (const struct clk_hw*[]){
3223                                 &gcc_vsensor_clk_src.clkr.hw,
3224                         },
3225                         .num_parents = 1,
3226                         .flags = CLK_SET_RATE_PARENT,
3227                         .ops = &clk_branch2_ops,
3228                 },
3229         },
3230 };
3231
3232 static struct clk_branch gcc_vddcx_vs_clk = {
3233         .halt_reg = 0x7a004,
3234         .halt_check = BRANCH_HALT,
3235         .clkr = {
3236                 .enable_reg = 0x7a004,
3237                 .enable_mask = BIT(0),
3238                 .hw.init = &(struct clk_init_data){
3239                         .name = "gcc_vddcx_vs_clk",
3240                         .parent_hws = (const struct clk_hw*[]){
3241                                 &gcc_vsensor_clk_src.clkr.hw,
3242                         },
3243                         .num_parents = 1,
3244                         .flags = CLK_SET_RATE_PARENT,
3245                         .ops = &clk_branch2_ops,
3246                 },
3247         },
3248 };
3249
3250 static struct clk_branch gcc_vddmx_vs_clk = {
3251         .halt_reg = 0x7a008,
3252         .halt_check = BRANCH_HALT,
3253         .clkr = {
3254                 .enable_reg = 0x7a008,
3255                 .enable_mask = BIT(0),
3256                 .hw.init = &(struct clk_init_data){
3257                         .name = "gcc_vddmx_vs_clk",
3258                         .parent_hws = (const struct clk_hw*[]){
3259                                 &gcc_vsensor_clk_src.clkr.hw,
3260                         },
3261                         .num_parents = 1,
3262                         .flags = CLK_SET_RATE_PARENT,
3263                         .ops = &clk_branch2_ops,
3264                 },
3265         },
3266 };
3267
3268 static struct clk_branch gcc_video_ahb_clk = {
3269         .halt_reg = 0xb004,
3270         .halt_check = BRANCH_HALT,
3271         .hwcg_reg = 0xb004,
3272         .hwcg_bit = 1,
3273         .clkr = {
3274                 .enable_reg = 0xb004,
3275                 .enable_mask = BIT(0),
3276                 .hw.init = &(struct clk_init_data){
3277                         .name = "gcc_video_ahb_clk",
3278                         .flags = CLK_IS_CRITICAL,
3279                         .ops = &clk_branch2_ops,
3280                 },
3281         },
3282 };
3283
3284 static struct clk_branch gcc_video_axi_clk = {
3285         .halt_reg = 0xb01c,
3286         .halt_check = BRANCH_VOTED,
3287         .clkr = {
3288                 .enable_reg = 0xb01c,
3289                 .enable_mask = BIT(0),
3290                 .hw.init = &(struct clk_init_data){
3291                         .name = "gcc_video_axi_clk",
3292                         .ops = &clk_branch2_ops,
3293                 },
3294         },
3295 };
3296
3297 static struct clk_branch gcc_video_xo_clk = {
3298         .halt_reg = 0xb028,
3299         .halt_check = BRANCH_HALT,
3300         .clkr = {
3301                 .enable_reg = 0xb028,
3302                 .enable_mask = BIT(0),
3303                 .hw.init = &(struct clk_init_data){
3304                         .name = "gcc_video_xo_clk",
3305                         .flags = CLK_IS_CRITICAL,
3306                         .ops = &clk_branch2_ops,
3307                 },
3308         },
3309 };
3310
3311 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3312         .halt_reg = 0x7a014,
3313         .halt_check = BRANCH_HALT,
3314         .hwcg_reg = 0x7a014,
3315         .hwcg_bit = 1,
3316         .clkr = {
3317                 .enable_reg = 0x7a014,
3318                 .enable_mask = BIT(0),
3319                 .hw.init = &(struct clk_init_data){
3320                         .name = "gcc_vs_ctrl_ahb_clk",
3321                         .ops = &clk_branch2_ops,
3322                 },
3323         },
3324 };
3325
3326 static struct clk_branch gcc_vs_ctrl_clk = {
3327         .halt_reg = 0x7a010,
3328         .halt_check = BRANCH_HALT,
3329         .clkr = {
3330                 .enable_reg = 0x7a010,
3331                 .enable_mask = BIT(0),
3332                 .hw.init = &(struct clk_init_data){
3333                         .name = "gcc_vs_ctrl_clk",
3334                         .parent_hws = (const struct clk_hw*[]){
3335                                 &gcc_vs_ctrl_clk_src.clkr.hw,
3336                         },
3337                         .num_parents = 1,
3338                         .flags = CLK_SET_RATE_PARENT,
3339                         .ops = &clk_branch2_ops,
3340                 },
3341         },
3342 };
3343
3344 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3345         .halt_reg = 0x48190,
3346         .halt_check = BRANCH_HALT,
3347         .clkr = {
3348                 .enable_reg = 0x48190,
3349                 .enable_mask = BIT(0),
3350                 .hw.init = &(struct clk_init_data){
3351                         .name = "gcc_cpuss_dvm_bus_clk",
3352                         .flags = CLK_IS_CRITICAL,
3353                         .ops = &clk_branch2_ops,
3354                 },
3355         },
3356 };
3357
3358 static struct clk_branch gcc_cpuss_gnoc_clk = {
3359         .halt_reg = 0x48004,
3360         .halt_check = BRANCH_HALT_VOTED,
3361         .hwcg_reg = 0x48004,
3362         .hwcg_bit = 1,
3363         .clkr = {
3364                 .enable_reg = 0x52004,
3365                 .enable_mask = BIT(22),
3366                 .hw.init = &(struct clk_init_data){
3367                         .name = "gcc_cpuss_gnoc_clk",
3368                         .flags = CLK_IS_CRITICAL,
3369                         .ops = &clk_branch2_ops,
3370                 },
3371         },
3372 };
3373
3374 /* TODO: Remove after DTS updated to protect these */
3375 #ifdef CONFIG_SDM_LPASSCC_845
3376 static struct clk_branch gcc_lpass_q6_axi_clk = {
3377         .halt_reg = 0x47000,
3378         .halt_check = BRANCH_HALT,
3379         .clkr = {
3380                 .enable_reg = 0x47000,
3381                 .enable_mask = BIT(0),
3382                 .hw.init = &(struct clk_init_data){
3383                         .name = "gcc_lpass_q6_axi_clk",
3384                         .flags = CLK_IS_CRITICAL,
3385                         .ops = &clk_branch2_ops,
3386                 },
3387         },
3388 };
3389
3390 static struct clk_branch gcc_lpass_sway_clk = {
3391         .halt_reg = 0x47008,
3392         .halt_check = BRANCH_HALT,
3393         .clkr = {
3394                 .enable_reg = 0x47008,
3395                 .enable_mask = BIT(0),
3396                 .hw.init = &(struct clk_init_data){
3397                         .name = "gcc_lpass_sway_clk",
3398                         .flags = CLK_IS_CRITICAL,
3399                         .ops = &clk_branch2_ops,
3400                 },
3401         },
3402 };
3403 #endif
3404
3405 static struct gdsc pcie_0_gdsc = {
3406         .gdscr = 0x6b004,
3407         .pd = {
3408                 .name = "pcie_0_gdsc",
3409         },
3410         .pwrsts = PWRSTS_OFF_ON,
3411         .flags = POLL_CFG_GDSCR,
3412 };
3413
3414 static struct gdsc pcie_1_gdsc = {
3415         .gdscr = 0x8d004,
3416         .pd = {
3417                 .name = "pcie_1_gdsc",
3418         },
3419         .pwrsts = PWRSTS_OFF_ON,
3420         .flags = POLL_CFG_GDSCR,
3421 };
3422
3423 static struct gdsc ufs_card_gdsc = {
3424         .gdscr = 0x75004,
3425         .pd = {
3426                 .name = "ufs_card_gdsc",
3427         },
3428         .pwrsts = PWRSTS_OFF_ON,
3429         .flags = POLL_CFG_GDSCR,
3430 };
3431
3432 static struct gdsc ufs_phy_gdsc = {
3433         .gdscr = 0x77004,
3434         .pd = {
3435                 .name = "ufs_phy_gdsc",
3436         },
3437         .pwrsts = PWRSTS_OFF_ON,
3438         .flags = POLL_CFG_GDSCR,
3439 };
3440
3441 static struct gdsc usb30_prim_gdsc = {
3442         .gdscr = 0xf004,
3443         .pd = {
3444                 .name = "usb30_prim_gdsc",
3445         },
3446         .pwrsts = PWRSTS_OFF_ON,
3447         .flags = POLL_CFG_GDSCR,
3448 };
3449
3450 static struct gdsc usb30_sec_gdsc = {
3451         .gdscr = 0x10004,
3452         .pd = {
3453                 .name = "usb30_sec_gdsc",
3454         },
3455         .pwrsts = PWRSTS_OFF_ON,
3456         .flags = POLL_CFG_GDSCR,
3457 };
3458
3459 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3460         .gdscr = 0x7d030,
3461         .pd = {
3462                 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3463         },
3464         .pwrsts = PWRSTS_OFF_ON,
3465         .flags = VOTABLE,
3466 };
3467
3468 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3469         .gdscr = 0x7d03c,
3470         .pd = {
3471                 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3472         },
3473         .pwrsts = PWRSTS_OFF_ON,
3474         .flags = VOTABLE,
3475 };
3476
3477 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3478         .gdscr = 0x7d034,
3479         .pd = {
3480                 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3481         },
3482         .pwrsts = PWRSTS_OFF_ON,
3483         .flags = VOTABLE,
3484 };
3485
3486 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3487         .gdscr = 0x7d038,
3488         .pd = {
3489                 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3490         },
3491         .pwrsts = PWRSTS_OFF_ON,
3492         .flags = VOTABLE,
3493 };
3494
3495 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3496         .gdscr = 0x7d040,
3497         .pd = {
3498                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3499         },
3500         .pwrsts = PWRSTS_OFF_ON,
3501         .flags = VOTABLE,
3502 };
3503
3504 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3505         .gdscr = 0x7d048,
3506         .pd = {
3507                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3508         },
3509         .pwrsts = PWRSTS_OFF_ON,
3510         .flags = VOTABLE,
3511 };
3512
3513 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3514         .gdscr = 0x7d044,
3515         .pd = {
3516                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3517         },
3518         .pwrsts = PWRSTS_OFF_ON,
3519         .flags = VOTABLE,
3520 };
3521
3522 static struct clk_regmap *gcc_sdm670_clocks[] = {
3523         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3524         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3525         [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3526         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3527         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3528         [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3529         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3530         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3531         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3532         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3533         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3534         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3535         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3536         [GCC_CPUSS_RBCPR_CLK] = &gcc_sdm670_cpuss_rbcpr_clk.clkr,
3537         [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_sdm670_cpuss_rbcpr_clk_src.clkr,
3538         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3539         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3540         [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3541         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3542         [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3543         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3544         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3545         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3546         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3547         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3548         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3549         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3550         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3551         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3552         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3553         [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3554         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3555         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3556         [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3557         [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3558         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3559         [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3560         [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3561         [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3562         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3563         [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3564         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3565         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3566         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3567         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3568         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3569         [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3570         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3571         [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3572         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3573         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3574         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3575         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3576         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3577         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3578         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3579         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3580         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3581         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3582         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3583         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3584         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3585         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3586         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3587         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3588         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3589         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3590         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3591         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3592         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3593         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3594         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3595         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3596         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3597         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3598         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3599         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3600         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3601         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3602         [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3603         [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3604         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3605         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3606         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3607         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3608         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3609         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3610         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3611         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3612         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3613         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3614         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3615         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3616         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3617         [GCC_SDCC4_APPS_CLK] = &gcc_sdm670_sdcc4_apps_clk.clkr,
3618         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdm670_sdcc4_apps_clk_src.clkr,
3619         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3620         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3621         [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3622                                         &gcc_tsif_inactivity_timers_clk.clkr,
3623         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3624         [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3625         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3626         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3627         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3628         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3629         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3630         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3631         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3632         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3633         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3634         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3635         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3636         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3637                                         &gcc_ufs_phy_unipro_core_clk_src.clkr,
3638         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3639         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3640         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3641         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3642                                         &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3643         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3644         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3645         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3646         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3647         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3648         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3649         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3650         [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3651         [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3652         [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3653         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3654         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3655         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3656         [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3657         [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3658         [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3659         [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3660         [GPLL0] = &gpll0.clkr,
3661         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3662         [GPLL4] = &gpll4.clkr,
3663         [GPLL6] = &gpll6.clkr,
3664         [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3665         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3666         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3667         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3668         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3669 };
3670
3671 static struct clk_regmap *gcc_sdm845_clocks[] = {
3672         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3673         [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3674         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3675         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3676         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3677         [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3678         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3679         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3680         [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3681         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3682         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3683         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3684         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3685         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3686         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3687         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3688         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3689         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3690         [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3691         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3692         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3693         [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3694         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3695         [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3696         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3697         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3698         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3699         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3700         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3701         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3702         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3703         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3704         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3705         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3706         [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3707         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3708         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3709         [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3710         [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3711         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3712         [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3713         [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3714         [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3715         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3716         [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3717         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3718         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3719         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3720         [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3721         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3722         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3723         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3724         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3725         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3726         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3727         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3728         [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3729         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3730         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3731         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3732         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3733         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3734         [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3735         [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3736         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3737         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3738         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3739         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3740         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3741         [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3742         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3743         [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3744         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3745         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3746         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3747         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3748         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3749         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3750         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3751         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3752         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3753         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3754         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3755         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3756         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3757         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3758         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3759         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3760         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3761         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3762         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3763         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3764         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3765         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3766         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3767         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3768         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3769         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3770         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3771         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3772         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3773         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3774         [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3775         [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3776         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3777         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3778         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3779         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3780         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3781         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3782         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3783         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3784         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3785         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3786         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3787         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3788         [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3789                                         &gcc_tsif_inactivity_timers_clk.clkr,
3790         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3791         [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3792         [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3793         [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3794         [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3795         [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3796         [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3797         [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3798         [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3799         [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3800         [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3801         [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3802         [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3803         [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3804         [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3805                                         &gcc_ufs_card_unipro_core_clk_src.clkr,
3806         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3807         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3808         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3809         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3810         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3811         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3812         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3813         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3814         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3815         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3816         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3817         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3818         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3819                                         &gcc_ufs_phy_unipro_core_clk_src.clkr,
3820         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3821         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3822         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3823         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3824                                         &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3825         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3826         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3827         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3828         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3829         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3830                                         &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3831         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3832         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3833         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3834         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3835         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3836         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3837         [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3838         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3839         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3840         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3841         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3842         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3843         [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3844         [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3845         [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3846         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3847         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3848         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3849         [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3850         [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3851         [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3852         [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3853         [GPLL0] = &gpll0.clkr,
3854         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3855         [GPLL4] = &gpll4.clkr,
3856         [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3857         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3858         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3859         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3860         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3861 #ifdef CONFIG_SDM_LPASSCC_845
3862         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3863         [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3864 #endif
3865 };
3866
3867 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3868         [GCC_MMSS_BCR] = { 0xb000 },
3869         [GCC_PCIE_0_BCR] = { 0x6b000 },
3870         [GCC_PCIE_1_BCR] = { 0x8d000 },
3871         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3872         [GCC_PDM_BCR] = { 0x33000 },
3873         [GCC_PRNG_BCR] = { 0x34000 },
3874         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3875         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3876         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3877         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3878         [GCC_SDCC2_BCR] = { 0x14000 },
3879         [GCC_SDCC4_BCR] = { 0x16000 },
3880         [GCC_TSIF_BCR] = { 0x36000 },
3881         [GCC_UFS_CARD_BCR] = { 0x75000 },
3882         [GCC_UFS_PHY_BCR] = { 0x77000 },
3883         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3884         [GCC_USB30_SEC_BCR] = { 0x10000 },
3885         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3886         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3887         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3888         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3889         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3890         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3891         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3892         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3893         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3894 };
3895
3896 static struct gdsc *gcc_sdm670_gdscs[] = {
3897         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3898         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3899         [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3900                         &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3901         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3902                         &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3903         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3904                         &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3905         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3906                         &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3907         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3908                         &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3909         [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3910 };
3911
3912 static struct gdsc *gcc_sdm845_gdscs[] = {
3913         [PCIE_0_GDSC] = &pcie_0_gdsc,
3914         [PCIE_1_GDSC] = &pcie_1_gdsc,
3915         [UFS_CARD_GDSC] = &ufs_card_gdsc,
3916         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3917         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3918         [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3919         [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3920                         &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3921         [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3922                         &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3923         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3924                         &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3925         [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3926                         &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3927         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3928                         &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3929         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3930                         &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3931         [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3932 };
3933
3934 static const struct regmap_config gcc_sdm845_regmap_config = {
3935         .reg_bits       = 32,
3936         .reg_stride     = 4,
3937         .val_bits       = 32,
3938         .max_register   = 0x182090,
3939         .fast_io        = true,
3940 };
3941
3942 static const struct qcom_cc_desc gcc_sdm670_desc = {
3943         .config = &gcc_sdm845_regmap_config,
3944         .clks = gcc_sdm670_clocks,
3945         .num_clks = ARRAY_SIZE(gcc_sdm670_clocks),
3946         /* Snapdragon 670 can function without its own exclusive resets. */
3947         .resets = gcc_sdm845_resets,
3948         .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3949         .gdscs = gcc_sdm670_gdscs,
3950         .num_gdscs = ARRAY_SIZE(gcc_sdm670_gdscs),
3951 };
3952
3953 static const struct qcom_cc_desc gcc_sdm845_desc = {
3954         .config = &gcc_sdm845_regmap_config,
3955         .clks = gcc_sdm845_clocks,
3956         .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3957         .resets = gcc_sdm845_resets,
3958         .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3959         .gdscs = gcc_sdm845_gdscs,
3960         .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3961 };
3962
3963 static const struct of_device_id gcc_sdm845_match_table[] = {
3964         { .compatible = "qcom,gcc-sdm670", .data = &gcc_sdm670_desc },
3965         { .compatible = "qcom,gcc-sdm845", .data = &gcc_sdm845_desc },
3966         { }
3967 };
3968 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3969
3970 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3971         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3972         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3973         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3974         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3975         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3976         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3977         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3978         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3979         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3980         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3981         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3982         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3983         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3984         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3985         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3986         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3987 };
3988
3989 static int gcc_sdm845_probe(struct platform_device *pdev)
3990 {
3991         const struct qcom_cc_desc *gcc_desc;
3992         struct regmap *regmap;
3993         int ret;
3994
3995         regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3996         if (IS_ERR(regmap))
3997                 return PTR_ERR(regmap);
3998
3999         /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
4000         regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
4001         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
4002
4003         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4004                                         ARRAY_SIZE(gcc_dfs_clocks));
4005         if (ret)
4006                 return ret;
4007
4008         gcc_desc = of_device_get_match_data(&pdev->dev);
4009         return qcom_cc_really_probe(&pdev->dev, gcc_desc, regmap);
4010 }
4011
4012 static struct platform_driver gcc_sdm845_driver = {
4013         .probe          = gcc_sdm845_probe,
4014         .driver         = {
4015                 .name   = "gcc-sdm845",
4016                 .of_match_table = gcc_sdm845_match_table,
4017         },
4018 };
4019
4020 static int __init gcc_sdm845_init(void)
4021 {
4022         return platform_driver_register(&gcc_sdm845_driver);
4023 }
4024 core_initcall(gcc_sdm845_init);
4025
4026 static void __exit gcc_sdm845_exit(void)
4027 {
4028         platform_driver_unregister(&gcc_sdm845_driver);
4029 }
4030 module_exit(gcc_sdm845_exit);
4031
4032 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
4033 MODULE_LICENSE("GPL v2");
4034 MODULE_ALIAS("platform:gcc-sdm845");
4035 MODULE_SOFTDEP("pre: rpmhpd");