drivers/clk/qcom/gcc-sa8775p.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4  * Copyright (c) 2023, Linaro Limited
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/module.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
  15
  16 #include "clk-alpha-pll.h"
  17 #include "clk-branch.h"
  18 #include "clk-rcg.h"
  19 #include "clk-regmap.h"
  20 #include "clk-regmap-divider.h"
  21 #include "clk-regmap-mux.h"
  22 #include "clk-regmap-phy-mux.h"
  23 #include "common.h"
  24 #include "gdsc.h"
  25 #include "reset.h"
  26
  27 /* Need to match the order of clocks in DT binding */
  28 enum {
  29         DT_BI_TCXO,
  30         DT_SLEEP_CLK,
  31         DT_UFS_PHY_RX_SYMBOL_0_CLK,
  32         DT_UFS_PHY_RX_SYMBOL_1_CLK,
  33         DT_UFS_PHY_TX_SYMBOL_0_CLK,
  34         DT_UFS_CARD_RX_SYMBOL_0_CLK,
  35         DT_UFS_CARD_RX_SYMBOL_1_CLK,
  36         DT_UFS_CARD_TX_SYMBOL_0_CLK,
  37         DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
  38         DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK,
  39         DT_PCIE_0_PIPE_CLK,
  40         DT_PCIE_1_PIPE_CLK,
  41         DT_PCIE_PHY_AUX_CLK,
  42         DT_RXC0_REF_CLK,
  43         DT_RXC1_REF_CLK,
  44 };
  45
  46 enum {
  47         P_BI_TCXO,
  48         P_GCC_GPLL0_OUT_EVEN,
  49         P_GCC_GPLL0_OUT_MAIN,
  50         P_GCC_GPLL1_OUT_MAIN,
  51         P_GCC_GPLL4_OUT_MAIN,
  52         P_GCC_GPLL5_OUT_MAIN,
  53         P_GCC_GPLL7_OUT_MAIN,
  54         P_GCC_GPLL9_OUT_MAIN,
  55         P_PCIE_0_PIPE_CLK,
  56         P_PCIE_1_PIPE_CLK,
  57         P_PCIE_PHY_AUX_CLK,
  58         P_RXC0_REF_CLK,
  59         P_RXC1_REF_CLK,
  60         P_SLEEP_CLK,
  61         P_UFS_CARD_RX_SYMBOL_0_CLK,
  62         P_UFS_CARD_RX_SYMBOL_1_CLK,
  63         P_UFS_CARD_TX_SYMBOL_0_CLK,
  64         P_UFS_PHY_RX_SYMBOL_0_CLK,
  65         P_UFS_PHY_RX_SYMBOL_1_CLK,
  66         P_UFS_PHY_TX_SYMBOL_0_CLK,
  67         P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK,
  68         P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK,
  69 };
  70
  71 static const struct clk_parent_data gcc_parent_data_tcxo = { .index = DT_BI_TCXO };
  72
  73 static struct clk_alpha_pll gcc_gpll0 = {
  74         .offset = 0x0,
  75         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
  76         .clkr = {
  77                 .enable_reg = 0x4b028,
  78                 .enable_mask = BIT(0),
  79                 .hw.init = &(const struct clk_init_data){
  80                         .name = "gcc_gpll0",
  81                         .parent_data = &gcc_parent_data_tcxo,
  82                         .num_parents = 1,
  83                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
  84                 },
  85         },
  86 };
  87
  88 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  89         { 0x1, 2 },
  90         { }
  91 };
  92
  93 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  94         .offset = 0x0,
  95         .post_div_shift = 10,
  96         .post_div_table = post_div_table_gcc_gpll0_out_even,
  97         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  98         .width = 4,
  99         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 100         .clkr.hw.init = &(const struct clk_init_data){
 101                 .name = "gcc_gpll0_out_even",
 102                 .parent_hws = (const struct clk_hw*[]){
 103                         &gcc_gpll0.clkr.hw,
 104                 },
 105                 .num_parents = 1,
 106                 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
 107         },
 108 };
 109
 110 static struct clk_alpha_pll gcc_gpll1 = {
 111         .offset = 0x1000,
 112         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 113         .clkr = {
 114                 .enable_reg = 0x4b028,
 115                 .enable_mask = BIT(1),
 116                 .hw.init = &(const struct clk_init_data){
 117                         .name = "gcc_gpll1",
 118                         .parent_data = &gcc_parent_data_tcxo,
 119                         .num_parents = 1,
 120                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 121                 },
 122         },
 123 };
 124
 125 static struct clk_alpha_pll gcc_gpll4 = {
 126         .offset = 0x4000,
 127         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 128         .clkr = {
 129                 .enable_reg = 0x4b028,
 130                 .enable_mask = BIT(4),
 131                 .hw.init = &(const struct clk_init_data){
 132                         .name = "gcc_gpll4",
 133                         .parent_data = &gcc_parent_data_tcxo,
 134                         .num_parents = 1,
 135                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 136                 },
 137         },
 138 };
 139
 140 static struct clk_alpha_pll gcc_gpll5 = {
 141         .offset = 0x5000,
 142         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 143         .clkr = {
 144                 .enable_reg = 0x4b028,
 145                 .enable_mask = BIT(5),
 146                 .hw.init = &(const struct clk_init_data){
 147                         .name = "gcc_gpll5",
 148                         .parent_data = &gcc_parent_data_tcxo,
 149                         .num_parents = 1,
 150                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 151                 },
 152         },
 153 };
 154
 155 static struct clk_alpha_pll gcc_gpll7 = {
 156         .offset = 0x7000,
 157         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 158         .clkr = {
 159                 .enable_reg = 0x4b028,
 160                 .enable_mask = BIT(7),
 161                 .hw.init = &(const struct clk_init_data){
 162                         .name = "gcc_gpll7",
 163                         .parent_data = &gcc_parent_data_tcxo,
 164                         .num_parents = 1,
 165                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 166                 },
 167         },
 168 };
 169
 170 static struct clk_alpha_pll gcc_gpll9 = {
 171         .offset = 0x9000,
 172         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
 173         .clkr = {
 174                 .enable_reg = 0x4b028,
 175                 .enable_mask = BIT(9),
 176                 .hw.init = &(const struct clk_init_data){
 177                         .name = "gcc_gpll9",
 178                         .parent_data = &gcc_parent_data_tcxo,
 179                         .num_parents = 1,
 180                         .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
 181                 },
 182         },
 183 };
 184
 185 static const struct parent_map gcc_parent_map_0[] = {
 186         { P_BI_TCXO, 0 },
 187         { P_GCC_GPLL0_OUT_MAIN, 1 },
 188         { P_GCC_GPLL0_OUT_EVEN, 6 },
 189 };
 190
 191 static const struct clk_parent_data gcc_parent_data_0[] = {
 192         { .index = DT_BI_TCXO },
 193         { .hw = &gcc_gpll0.clkr.hw },
 194         { .hw = &gcc_gpll0_out_even.clkr.hw },
 195 };
 196
 197 static const struct parent_map gcc_parent_map_1[] = {
 198         { P_BI_TCXO, 0 },
 199         { P_GCC_GPLL0_OUT_MAIN, 1 },
 200         { P_GCC_GPLL4_OUT_MAIN, 5 },
 201         { P_GCC_GPLL0_OUT_EVEN, 6 },
 202 };
 203
 204 static const struct clk_parent_data gcc_parent_data_1[] = {
 205         { .index = DT_BI_TCXO },
 206         { .hw = &gcc_gpll0.clkr.hw },
 207         { .hw = &gcc_gpll4.clkr.hw },
 208         { .hw = &gcc_gpll0_out_even.clkr.hw },
 209 };
 210
 211 static const struct parent_map gcc_parent_map_2[] = {
 212         { P_BI_TCXO, 0 },
 213         { P_GCC_GPLL0_OUT_MAIN, 1 },
 214         { P_SLEEP_CLK, 5 },
 215         { P_GCC_GPLL0_OUT_EVEN, 6 },
 216 };
 217
 218 static const struct clk_parent_data gcc_parent_data_2[] = {
 219         { .index = DT_BI_TCXO },
 220         { .hw = &gcc_gpll0.clkr.hw },
 221         { .index = DT_SLEEP_CLK },
 222         { .hw = &gcc_gpll0_out_even.clkr.hw },
 223 };
 224
 225 static const struct parent_map gcc_parent_map_3[] = {
 226         { P_BI_TCXO, 0 },
 227         { P_SLEEP_CLK, 5 },
 228 };
 229
 230 static const struct clk_parent_data gcc_parent_data_3[] = {
 231         { .index = DT_BI_TCXO },
 232         { .index = DT_SLEEP_CLK },
 233 };
 234
 235 static const struct parent_map gcc_parent_map_4[] = {
 236         { P_BI_TCXO, 0 },
 237         { P_GCC_GPLL0_OUT_MAIN, 1 },
 238         { P_GCC_GPLL1_OUT_MAIN, 4 },
 239         { P_GCC_GPLL4_OUT_MAIN, 5 },
 240         { P_GCC_GPLL0_OUT_EVEN, 6 },
 241 };
 242
 243 static const struct clk_parent_data gcc_parent_data_4[] = {
 244         { .index = DT_BI_TCXO },
 245         { .hw = &gcc_gpll0.clkr.hw },
 246         { .hw = &gcc_gpll1.clkr.hw },
 247         { .hw = &gcc_gpll4.clkr.hw },
 248         { .hw = &gcc_gpll0_out_even.clkr.hw },
 249 };
 250
 251 static const struct parent_map gcc_parent_map_5[] = {
 252         { P_BI_TCXO, 0 },
 253 };
 254
 255 static const struct clk_parent_data gcc_parent_data_5[] = {
 256         { .index = DT_BI_TCXO },
 257 };
 258
 259 static const struct parent_map gcc_parent_map_6[] = {
 260         { P_BI_TCXO, 0 },
 261         { P_GCC_GPLL7_OUT_MAIN, 2 },
 262         { P_GCC_GPLL4_OUT_MAIN, 5 },
 263         { P_GCC_GPLL0_OUT_EVEN, 6 },
 264 };
 265
 266 static const struct clk_parent_data gcc_parent_data_6[] = {
 267         { .index = DT_BI_TCXO },
 268         { .hw = &gcc_gpll7.clkr.hw },
 269         { .hw = &gcc_gpll4.clkr.hw },
 270         { .hw = &gcc_gpll0_out_even.clkr.hw },
 271 };
 272
 273 static const struct parent_map gcc_parent_map_7[] = {
 274         { P_BI_TCXO, 0 },
 275         { P_GCC_GPLL7_OUT_MAIN, 2 },
 276         { P_RXC0_REF_CLK, 3 },
 277         { P_GCC_GPLL0_OUT_EVEN, 6 },
 278 };
 279
 280 static const struct clk_parent_data gcc_parent_data_7[] = {
 281         { .index = DT_BI_TCXO },
 282         { .hw = &gcc_gpll7.clkr.hw },
 283         { .index = DT_RXC0_REF_CLK },
 284         { .hw = &gcc_gpll0_out_even.clkr.hw },
 285 };
 286
 287 static const struct parent_map gcc_parent_map_8[] = {
 288         { P_BI_TCXO, 0 },
 289         { P_GCC_GPLL7_OUT_MAIN, 2 },
 290         { P_RXC1_REF_CLK, 3 },
 291         { P_GCC_GPLL0_OUT_EVEN, 6 },
 292 };
 293
 294 static const struct clk_parent_data gcc_parent_data_8[] = {
 295         { .index = DT_BI_TCXO },
 296         { .hw = &gcc_gpll7.clkr.hw },
 297         { .index = DT_RXC1_REF_CLK },
 298         { .hw = &gcc_gpll0_out_even.clkr.hw },
 299 };
 300
 301 static const struct parent_map gcc_parent_map_9[] = {
 302         { P_PCIE_PHY_AUX_CLK, 1 },
 303         { P_BI_TCXO, 2 },
 304 };
 305
 306 static const struct clk_parent_data gcc_parent_data_9[] = {
 307         { .index = DT_PCIE_PHY_AUX_CLK },
 308         { .index = DT_BI_TCXO },
 309 };
 310
 311 static const struct parent_map gcc_parent_map_11[] = {
 312         { P_PCIE_PHY_AUX_CLK, 1 },
 313         { P_BI_TCXO, 2 },
 314 };
 315
 316 static const struct clk_parent_data gcc_parent_data_11[] = {
 317         { .index = DT_PCIE_PHY_AUX_CLK },
 318         { .index = DT_BI_TCXO },
 319 };
 320
 321 static const struct parent_map gcc_parent_map_13[] = {
 322         { P_BI_TCXO, 0 },
 323         { P_GCC_GPLL0_OUT_MAIN, 1 },
 324         { P_GCC_GPLL9_OUT_MAIN, 2 },
 325         { P_GCC_GPLL4_OUT_MAIN, 5 },
 326         { P_GCC_GPLL0_OUT_EVEN, 6 },
 327 };
 328
 329 static const struct clk_parent_data gcc_parent_data_13[] = {
 330         { .index = DT_BI_TCXO },
 331         { .hw = &gcc_gpll0.clkr.hw },
 332         { .hw = &gcc_gpll9.clkr.hw },
 333         { .hw = &gcc_gpll4.clkr.hw },
 334         { .hw = &gcc_gpll0_out_even.clkr.hw },
 335 };
 336
 337 static const struct parent_map gcc_parent_map_14[] = {
 338         { P_BI_TCXO, 0 },
 339         { P_GCC_GPLL0_OUT_MAIN, 1 },
 340 };
 341
 342 static const struct clk_parent_data gcc_parent_data_14[] = {
 343         { .index = DT_BI_TCXO },
 344         { .hw = &gcc_gpll0.clkr.hw },
 345 };
 346
 347 static const struct parent_map gcc_parent_map_15[] = {
 348         { P_BI_TCXO, 0 },
 349         { P_GCC_GPLL7_OUT_MAIN, 2 },
 350         { P_GCC_GPLL5_OUT_MAIN, 3 },
 351         { P_GCC_GPLL4_OUT_MAIN, 5 },
 352         { P_GCC_GPLL0_OUT_EVEN, 6 },
 353 };
 354
 355 static const struct clk_parent_data gcc_parent_data_15[] = {
 356         { .index = DT_BI_TCXO },
 357         { .hw = &gcc_gpll7.clkr.hw },
 358         { .hw = &gcc_gpll5.clkr.hw },
 359         { .hw = &gcc_gpll4.clkr.hw },
 360         { .hw = &gcc_gpll0_out_even.clkr.hw },
 361 };
 362
 363 static const struct parent_map gcc_parent_map_16[] = {
 364         { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
 365         { P_BI_TCXO, 2 },
 366 };
 367
 368 static const struct clk_parent_data gcc_parent_data_16[] = {
 369         { .index = DT_UFS_CARD_RX_SYMBOL_0_CLK },
 370         { .index = DT_BI_TCXO },
 371 };
 372
 373 static const struct parent_map gcc_parent_map_17[] = {
 374         { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
 375         { P_BI_TCXO, 2 },
 376 };
 377
 378 static const struct clk_parent_data gcc_parent_data_17[] = {
 379         { .index = DT_UFS_CARD_RX_SYMBOL_1_CLK },
 380         { .index = DT_BI_TCXO },
 381 };
 382
 383 static const struct parent_map gcc_parent_map_18[] = {
 384         { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
 385         { P_BI_TCXO, 2 },
 386 };
 387
 388 static const struct clk_parent_data gcc_parent_data_18[] = {
 389         { .index = DT_UFS_CARD_TX_SYMBOL_0_CLK },
 390         { .index = DT_BI_TCXO },
 391 };
 392
 393 static const struct parent_map gcc_parent_map_19[] = {
 394         { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 395         { P_BI_TCXO, 2 },
 396 };
 397
 398 static const struct clk_parent_data gcc_parent_data_19[] = {
 399         { .index = DT_UFS_PHY_RX_SYMBOL_0_CLK },
 400         { .index = DT_BI_TCXO },
 401 };
 402
 403 static const struct parent_map gcc_parent_map_20[] = {
 404         { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 405         { P_BI_TCXO, 2 },
 406 };
 407
 408 static const struct clk_parent_data gcc_parent_data_20[] = {
 409         { .index = DT_UFS_PHY_RX_SYMBOL_1_CLK },
 410         { .index = DT_BI_TCXO },
 411 };
 412
 413 static const struct parent_map gcc_parent_map_21[] = {
 414         { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 415         { P_BI_TCXO, 2 },
 416 };
 417
 418 static const struct clk_parent_data gcc_parent_data_21[] = {
 419         { .index = DT_UFS_PHY_TX_SYMBOL_0_CLK },
 420         { .index = DT_BI_TCXO },
 421 };
 422
 423 static const struct parent_map gcc_parent_map_22[] = {
 424         { P_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK, 0 },
 425         { P_BI_TCXO, 2 },
 426 };
 427
 428 static const struct clk_parent_data gcc_parent_data_22[] = {
 429         { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PRIM_PIPE_CLK },
 430         { .index = DT_BI_TCXO },
 431 };
 432
 433 static const struct parent_map gcc_parent_map_23[] = {
 434         { P_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK, 0 },
 435         { P_BI_TCXO, 2 },
 436 };
 437
 438 static const struct clk_parent_data gcc_parent_data_23[] = {
 439         { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_SEC_PIPE_CLK },
 440         { .index = DT_BI_TCXO },
 441 };
 442
 443 static struct clk_regmap_mux gcc_pcie_0_phy_aux_clk_src = {
 444         .reg = 0xa9074,
 445         .shift = 0,
 446         .width = 2,
 447         .parent_map = gcc_parent_map_9,
 448         .clkr = {
 449                 .hw.init = &(const struct clk_init_data){
 450                         .name = "gcc_pcie_0_phy_aux_clk_src",
 451                         .parent_data = gcc_parent_data_9,
 452                         .num_parents = ARRAY_SIZE(gcc_parent_data_9),
 453                         .ops = &clk_regmap_mux_closest_ops,
 454                 },
 455         },
 456 };
 457
 458 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
 459         .reg = 0xa906c,
 460         .clkr = {
 461                 .hw.init = &(const struct clk_init_data){
 462                         .name = "gcc_pcie_0_pipe_clk_src",
 463                         .parent_data = &(const struct clk_parent_data){
 464                                 .index = DT_PCIE_0_PIPE_CLK,
 465                         },
 466                         .num_parents = 1,
 467                         .ops = &clk_regmap_phy_mux_ops,
 468                 },
 469         },
 470 };
 471
 472 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
 473         .reg = 0x77074,
 474         .shift = 0,
 475         .width = 2,
 476         .parent_map = gcc_parent_map_11,
 477         .clkr = {
 478                 .hw.init = &(const struct clk_init_data){
 479                         .name = "gcc_pcie_1_phy_aux_clk_src",
 480                         .parent_data = gcc_parent_data_11,
 481                         .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 482                         .ops = &clk_regmap_mux_closest_ops,
 483                 },
 484         },
 485 };
 486
 487 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
 488         .reg = 0x7706c,
 489         .clkr = {
 490                 .hw.init = &(const struct clk_init_data){
 491                         .name = "gcc_pcie_1_pipe_clk_src",
 492                         .parent_data = &(const struct clk_parent_data) {
 493                                 .index = DT_PCIE_1_PIPE_CLK,
 494                         },
 495                         .num_parents = 1,
 496                         .ops = &clk_regmap_phy_mux_ops,
 497                 },
 498         },
 499 };
 500
 501 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
 502         .reg = 0x81060,
 503         .shift = 0,
 504         .width = 2,
 505         .parent_map = gcc_parent_map_16,
 506         .clkr = {
 507                 .hw.init = &(const struct clk_init_data){
 508                         .name = "gcc_ufs_card_rx_symbol_0_clk_src",
 509                         .parent_data = gcc_parent_data_16,
 510                         .num_parents = ARRAY_SIZE(gcc_parent_data_16),
 511                         .ops = &clk_regmap_mux_closest_ops,
 512                 },
 513         },
 514 };
 515
 516 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
 517         .reg = 0x810d0,
 518         .shift = 0,
 519         .width = 2,
 520         .parent_map = gcc_parent_map_17,
 521         .clkr = {
 522                 .hw.init = &(const struct clk_init_data){
 523                         .name = "gcc_ufs_card_rx_symbol_1_clk_src",
 524                         .parent_data = gcc_parent_data_17,
 525                         .num_parents = ARRAY_SIZE(gcc_parent_data_17),
 526                         .ops = &clk_regmap_mux_closest_ops,
 527                 },
 528         },
 529 };
 530
 531 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
 532         .reg = 0x81050,
 533         .shift = 0,
 534         .width = 2,
 535         .parent_map = gcc_parent_map_18,
 536         .clkr = {
 537                 .hw.init = &(const struct clk_init_data){
 538                         .name = "gcc_ufs_card_tx_symbol_0_clk_src",
 539                         .parent_data = gcc_parent_data_18,
 540                         .num_parents = ARRAY_SIZE(gcc_parent_data_18),
 541                         .ops = &clk_regmap_mux_closest_ops,
 542                 },
 543         },
 544 };
 545
 546 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 547         .reg = 0x83060,
 548         .shift = 0,
 549         .width = 2,
 550         .parent_map = gcc_parent_map_19,
 551         .clkr = {
 552                 .hw.init = &(const struct clk_init_data){
 553                         .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 554                         .parent_data = gcc_parent_data_19,
 555                         .num_parents = ARRAY_SIZE(gcc_parent_data_19),
 556                         .ops = &clk_regmap_mux_closest_ops,
 557                 },
 558         },
 559 };
 560
 561 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 562         .reg = 0x830d0,
 563         .shift = 0,
 564         .width = 2,
 565         .parent_map = gcc_parent_map_20,
 566         .clkr = {
 567                 .hw.init = &(const struct clk_init_data){
 568                         .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 569                         .parent_data = gcc_parent_data_20,
 570                         .num_parents = ARRAY_SIZE(gcc_parent_data_20),
 571                         .ops = &clk_regmap_mux_closest_ops,
 572                 },
 573         },
 574 };
 575
 576 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 577         .reg = 0x83050,
 578         .shift = 0,
 579         .width = 2,
 580         .parent_map = gcc_parent_map_21,
 581         .clkr = {
 582                 .hw.init = &(const struct clk_init_data){
 583                         .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 584                         .parent_data = gcc_parent_data_21,
 585                         .num_parents = ARRAY_SIZE(gcc_parent_data_21),
 586                         .ops = &clk_regmap_mux_closest_ops,
 587                 },
 588         },
 589 };
 590
 591 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 592         .reg = 0x1b068,
 593         .shift = 0,
 594         .width = 2,
 595         .parent_map = gcc_parent_map_22,
 596         .clkr = {
 597                 .hw.init = &(const struct clk_init_data){
 598                         .name = "gcc_usb3_prim_phy_pipe_clk_src",
 599                         .parent_data = gcc_parent_data_22,
 600                         .num_parents = ARRAY_SIZE(gcc_parent_data_22),
 601                         .ops = &clk_regmap_mux_closest_ops,
 602                 },
 603         },
 604 };
 605
 606 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 607         .reg = 0x2f068,
 608         .shift = 0,
 609         .width = 2,
 610         .parent_map = gcc_parent_map_23,
 611         .clkr = {
 612                 .hw.init = &(const struct clk_init_data){
 613                         .name = "gcc_usb3_sec_phy_pipe_clk_src",
 614                         .parent_data = gcc_parent_data_23,
 615                         .num_parents = ARRAY_SIZE(gcc_parent_data_23),
 616                         .ops = &clk_regmap_mux_closest_ops,
 617                 },
 618         },
 619 };
 620
 621 static const struct freq_tbl ftbl_gcc_emac0_phy_aux_clk_src[] = {
 622         F(19200000, P_BI_TCXO, 1, 0, 0),
 623         { }
 624 };
 625
 626 static struct clk_rcg2 gcc_emac0_phy_aux_clk_src = {
 627         .cmd_rcgr = 0xb6028,
 628         .mnd_width = 0,
 629         .hid_width = 5,
 630         .parent_map = gcc_parent_map_3,
 631         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 632         .clkr.hw.init = &(const struct clk_init_data){
 633                 .name = "gcc_emac0_phy_aux_clk_src",
 634                 .parent_data = gcc_parent_data_3,
 635                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 636                 .ops = &clk_rcg2_shared_ops,
 637         },
 638 };
 639
 640 static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
 641         F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
 642         F(230400000, P_GCC_GPLL4_OUT_MAIN, 3.5, 0, 0),
 643         { }
 644 };
 645
 646 static struct clk_rcg2 gcc_emac0_ptp_clk_src = {
 647         .cmd_rcgr = 0xb6060,
 648         .mnd_width = 16,
 649         .hid_width = 5,
 650         .parent_map = gcc_parent_map_6,
 651         .freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
 652         .clkr.hw.init = &(const struct clk_init_data){
 653                 .name = "gcc_emac0_ptp_clk_src",
 654                 .parent_data = gcc_parent_data_6,
 655                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 656                 .ops = &clk_rcg2_shared_ops,
 657         },
 658 };
 659
 660 static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
 661         F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
 662         F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
 663         { }
 664 };
 665
 666 static struct clk_rcg2 gcc_emac0_rgmii_clk_src = {
 667         .cmd_rcgr = 0xb6048,
 668         .mnd_width = 16,
 669         .hid_width = 5,
 670         .parent_map = gcc_parent_map_7,
 671         .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
 672         .clkr.hw.init = &(const struct clk_init_data){
 673                 .name = "gcc_emac0_rgmii_clk_src",
 674                 .parent_data = gcc_parent_data_7,
 675                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 676                 .ops = &clk_rcg2_shared_ops,
 677         },
 678 };
 679
 680 static struct clk_rcg2 gcc_emac1_phy_aux_clk_src = {
 681         .cmd_rcgr = 0xb4028,
 682         .mnd_width = 0,
 683         .hid_width = 5,
 684         .parent_map = gcc_parent_map_3,
 685         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 686         .clkr.hw.init = &(const struct clk_init_data){
 687                 .name = "gcc_emac1_phy_aux_clk_src",
 688                 .parent_data = gcc_parent_data_3,
 689                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 690                 .ops = &clk_rcg2_shared_ops,
 691         },
 692 };
 693
 694 static struct clk_rcg2 gcc_emac1_ptp_clk_src = {
 695         .cmd_rcgr = 0xb4060,
 696         .mnd_width = 16,
 697         .hid_width = 5,
 698         .parent_map = gcc_parent_map_6,
 699         .freq_tbl = ftbl_gcc_emac0_ptp_clk_src,
 700         .clkr.hw.init = &(const struct clk_init_data){
 701                 .name = "gcc_emac1_ptp_clk_src",
 702                 .parent_data = gcc_parent_data_6,
 703                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 704                 .ops = &clk_rcg2_shared_ops,
 705         },
 706 };
 707
 708 static struct clk_rcg2 gcc_emac1_rgmii_clk_src = {
 709         .cmd_rcgr = 0xb4048,
 710         .mnd_width = 16,
 711         .hid_width = 5,
 712         .parent_map = gcc_parent_map_8,
 713         .freq_tbl = ftbl_gcc_emac0_rgmii_clk_src,
 714         .clkr.hw.init = &(const struct clk_init_data){
 715                 .name = "gcc_emac1_rgmii_clk_src",
 716                 .parent_data = gcc_parent_data_8,
 717                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 718                 .ops = &clk_rcg2_shared_ops,
 719         },
 720 };
 721
 722 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 723         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 724         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 725         { }
 726 };
 727
 728 static struct clk_rcg2 gcc_gp1_clk_src = {
 729         .cmd_rcgr = 0x70004,
 730         .mnd_width = 16,
 731         .hid_width = 5,
 732         .parent_map = gcc_parent_map_2,
 733         .freq_tbl = ftbl_gcc_gp1_clk_src,
 734         .clkr.hw.init = &(const struct clk_init_data){
 735                 .name = "gcc_gp1_clk_src",
 736                 .parent_data = gcc_parent_data_2,
 737                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 738                 .ops = &clk_rcg2_shared_ops,
 739         },
 740 };
 741
 742 static struct clk_rcg2 gcc_gp2_clk_src = {
 743         .cmd_rcgr = 0x71004,
 744         .mnd_width = 16,
 745         .hid_width = 5,
 746         .parent_map = gcc_parent_map_2,
 747         .freq_tbl = ftbl_gcc_gp1_clk_src,
 748         .clkr.hw.init = &(const struct clk_init_data){
 749                 .name = "gcc_gp2_clk_src",
 750                 .parent_data = gcc_parent_data_2,
 751                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 752                 .ops = &clk_rcg2_shared_ops,
 753         },
 754 };
 755
 756 static struct clk_rcg2 gcc_gp3_clk_src = {
 757         .cmd_rcgr = 0x62004,
 758         .mnd_width = 16,
 759         .hid_width = 5,
 760         .parent_map = gcc_parent_map_2,
 761         .freq_tbl = ftbl_gcc_gp1_clk_src,
 762         .clkr.hw.init = &(const struct clk_init_data){
 763                 .name = "gcc_gp3_clk_src",
 764                 .parent_data = gcc_parent_data_2,
 765                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 766                 .ops = &clk_rcg2_shared_ops,
 767         },
 768 };
 769
 770 static struct clk_rcg2 gcc_gp4_clk_src = {
 771         .cmd_rcgr = 0x1e004,
 772         .mnd_width = 16,
 773         .hid_width = 5,
 774         .parent_map = gcc_parent_map_2,
 775         .freq_tbl = ftbl_gcc_gp1_clk_src,
 776         .clkr.hw.init = &(const struct clk_init_data){
 777                 .name = "gcc_gp4_clk_src",
 778                 .parent_data = gcc_parent_data_2,
 779                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 780                 .ops = &clk_rcg2_shared_ops,
 781         },
 782 };
 783
 784 static struct clk_rcg2 gcc_gp5_clk_src = {
 785         .cmd_rcgr = 0x1f004,
 786         .mnd_width = 16,
 787         .hid_width = 5,
 788         .parent_map = gcc_parent_map_2,
 789         .freq_tbl = ftbl_gcc_gp1_clk_src,
 790         .clkr.hw.init = &(const struct clk_init_data){
 791                 .name = "gcc_gp5_clk_src",
 792                 .parent_data = gcc_parent_data_2,
 793                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 794                 .ops = &clk_rcg2_shared_ops,
 795         },
 796 };
 797
 798 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 799         .cmd_rcgr = 0xa9078,
 800         .mnd_width = 16,
 801         .hid_width = 5,
 802         .parent_map = gcc_parent_map_3,
 803         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 804         .clkr.hw.init = &(const struct clk_init_data){
 805                 .name = "gcc_pcie_0_aux_clk_src",
 806                 .parent_data = gcc_parent_data_3,
 807                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 808                 .ops = &clk_rcg2_shared_ops,
 809         },
 810 };
 811
 812 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 813         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 814         { }
 815 };
 816
 817 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 818         .cmd_rcgr = 0xa9054,
 819         .mnd_width = 0,
 820         .hid_width = 5,
 821         .parent_map = gcc_parent_map_0,
 822         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 823         .clkr.hw.init = &(const struct clk_init_data){
 824                 .name = "gcc_pcie_0_phy_rchng_clk_src",
 825                 .parent_data = gcc_parent_data_0,
 826                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 827                 .ops = &clk_rcg2_shared_ops,
 828         },
 829 };
 830
 831 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 832         .cmd_rcgr = 0x77078,
 833         .mnd_width = 16,
 834         .hid_width = 5,
 835         .parent_map = gcc_parent_map_3,
 836         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
 837         .clkr.hw.init = &(const struct clk_init_data){
 838                 .name = "gcc_pcie_1_aux_clk_src",
 839                 .parent_data = gcc_parent_data_3,
 840                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 841                 .ops = &clk_rcg2_shared_ops,
 842         },
 843 };
 844
 845 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 846         .cmd_rcgr = 0x77054,
 847         .mnd_width = 0,
 848         .hid_width = 5,
 849         .parent_map = gcc_parent_map_0,
 850         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 851         .clkr.hw.init = &(const struct clk_init_data){
 852                 .name = "gcc_pcie_1_phy_rchng_clk_src",
 853                 .parent_data = gcc_parent_data_0,
 854                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 855                 .ops = &clk_rcg2_shared_ops,
 856         },
 857 };
 858
 859 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 860         F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 861         { }
 862 };
 863
 864 static struct clk_rcg2 gcc_pdm2_clk_src = {
 865         .cmd_rcgr = 0x3f010,
 866         .mnd_width = 0,
 867         .hid_width = 5,
 868         .parent_map = gcc_parent_map_0,
 869         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 870         .clkr.hw.init = &(const struct clk_init_data){
 871                 .name = "gcc_pdm2_clk_src",
 872                 .parent_data = gcc_parent_data_0,
 873                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 874                 .ops = &clk_rcg2_shared_ops,
 875         },
 876 };
 877
 878 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 879         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 880         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 881         F(19200000, P_BI_TCXO, 1, 0, 0),
 882         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 883         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 884         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 885         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 886         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 887         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 888         F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 889         { }
 890 };
 891
 892 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 893         .name = "gcc_qupv3_wrap0_s0_clk_src",
 894         .parent_data = gcc_parent_data_0,
 895         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 896         .ops = &clk_rcg2_shared_ops,
 897 };
 898
 899 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 900         .cmd_rcgr = 0x23154,
 901         .mnd_width = 16,
 902         .hid_width = 5,
 903         .parent_map = gcc_parent_map_0,
 904         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 905         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 906 };
 907
 908 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 909         .name = "gcc_qupv3_wrap0_s1_clk_src",
 910         .parent_data = gcc_parent_data_0,
 911         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 912         .ops = &clk_rcg2_shared_ops,
 913 };
 914
 915 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 916         .cmd_rcgr = 0x23288,
 917         .mnd_width = 16,
 918         .hid_width = 5,
 919         .parent_map = gcc_parent_map_0,
 920         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 921         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 922 };
 923
 924 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
 925         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 926         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 927         F(19200000, P_BI_TCXO, 1, 0, 0),
 928         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 929         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 930         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 931         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 932         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 933         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 934         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 935         { }
 936 };
 937
 938 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 939         .name = "gcc_qupv3_wrap0_s2_clk_src",
 940         .parent_data = gcc_parent_data_0,
 941         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 942         .ops = &clk_rcg2_shared_ops,
 943 };
 944
 945 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 946         .cmd_rcgr = 0x233bc,
 947         .mnd_width = 16,
 948         .hid_width = 5,
 949         .parent_map = gcc_parent_map_0,
 950         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 951         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 952 };
 953
 954 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 955         .name = "gcc_qupv3_wrap0_s3_clk_src",
 956         .parent_data = gcc_parent_data_0,
 957         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 958         .ops = &clk_rcg2_shared_ops,
 959 };
 960
 961 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 962         .cmd_rcgr = 0x234f0,
 963         .mnd_width = 16,
 964         .hid_width = 5,
 965         .parent_map = gcc_parent_map_0,
 966         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 967         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 968 };
 969
 970 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 971         .name = "gcc_qupv3_wrap0_s4_clk_src",
 972         .parent_data = gcc_parent_data_1,
 973         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 974         .ops = &clk_rcg2_shared_ops,
 975 };
 976
 977 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 978         .cmd_rcgr = 0x23624,
 979         .mnd_width = 16,
 980         .hid_width = 5,
 981         .parent_map = gcc_parent_map_1,
 982         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 983         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 984 };
 985
 986 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 987         .name = "gcc_qupv3_wrap0_s5_clk_src",
 988         .parent_data = gcc_parent_data_0,
 989         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 990         .ops = &clk_rcg2_shared_ops,
 991 };
 992
 993 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 994         .cmd_rcgr = 0x23758,
 995         .mnd_width = 16,
 996         .hid_width = 5,
 997         .parent_map = gcc_parent_map_0,
 998         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 999         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1000 };
1001
1002 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
1003         .name = "gcc_qupv3_wrap0_s6_clk_src",
1004         .parent_data = gcc_parent_data_0,
1005         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1006         .ops = &clk_rcg2_shared_ops,
1007 };
1008
1009 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
1010         .cmd_rcgr = 0x2388c,
1011         .mnd_width = 16,
1012         .hid_width = 5,
1013         .parent_map = gcc_parent_map_0,
1014         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1015         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
1016 };
1017
1018 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1019         .name = "gcc_qupv3_wrap1_s0_clk_src",
1020         .parent_data = gcc_parent_data_0,
1021         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1022         .ops = &clk_rcg2_shared_ops,
1023 };
1024
1025 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1026         .cmd_rcgr = 0x24154,
1027         .mnd_width = 16,
1028         .hid_width = 5,
1029         .parent_map = gcc_parent_map_0,
1030         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1031         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1032 };
1033
1034 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1035         .name = "gcc_qupv3_wrap1_s1_clk_src",
1036         .parent_data = gcc_parent_data_0,
1037         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1038         .ops = &clk_rcg2_shared_ops,
1039 };
1040
1041 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1042         .cmd_rcgr = 0x24288,
1043         .mnd_width = 16,
1044         .hid_width = 5,
1045         .parent_map = gcc_parent_map_0,
1046         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1047         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1048 };
1049
1050 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1051         .name = "gcc_qupv3_wrap1_s2_clk_src",
1052         .parent_data = gcc_parent_data_0,
1053         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1054         .ops = &clk_rcg2_shared_ops,
1055 };
1056
1057 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1058         .cmd_rcgr = 0x243bc,
1059         .mnd_width = 16,
1060         .hid_width = 5,
1061         .parent_map = gcc_parent_map_0,
1062         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1063         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1064 };
1065
1066 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1067         .name = "gcc_qupv3_wrap1_s3_clk_src",
1068         .parent_data = gcc_parent_data_0,
1069         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1070         .ops = &clk_rcg2_shared_ops,
1071 };
1072
1073 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1074         .cmd_rcgr = 0x244f0,
1075         .mnd_width = 16,
1076         .hid_width = 5,
1077         .parent_map = gcc_parent_map_0,
1078         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1079         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1080 };
1081
1082 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1083         .name = "gcc_qupv3_wrap1_s4_clk_src",
1084         .parent_data = gcc_parent_data_1,
1085         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1086         .ops = &clk_rcg2_shared_ops,
1087 };
1088
1089 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1090         .cmd_rcgr = 0x24624,
1091         .mnd_width = 16,
1092         .hid_width = 5,
1093         .parent_map = gcc_parent_map_1,
1094         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1095         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1096 };
1097
1098 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1099         .name = "gcc_qupv3_wrap1_s5_clk_src",
1100         .parent_data = gcc_parent_data_0,
1101         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1102         .ops = &clk_rcg2_shared_ops,
1103 };
1104
1105 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1106         .cmd_rcgr = 0x24758,
1107         .mnd_width = 16,
1108         .hid_width = 5,
1109         .parent_map = gcc_parent_map_0,
1110         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1111         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1112 };
1113
1114 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
1115         .name = "gcc_qupv3_wrap1_s6_clk_src",
1116         .parent_data = gcc_parent_data_0,
1117         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1118         .ops = &clk_rcg2_shared_ops,
1119 };
1120
1121 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
1122         .cmd_rcgr = 0x2488c,
1123         .mnd_width = 16,
1124         .hid_width = 5,
1125         .parent_map = gcc_parent_map_0,
1126         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1127         .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
1128 };
1129
1130 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
1131         .name = "gcc_qupv3_wrap2_s0_clk_src",
1132         .parent_data = gcc_parent_data_1,
1133         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1134         .ops = &clk_rcg2_shared_ops,
1135 };
1136
1137 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
1138         .cmd_rcgr = 0x2a154,
1139         .mnd_width = 16,
1140         .hid_width = 5,
1141         .parent_map = gcc_parent_map_1,
1142         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1143         .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
1144 };
1145
1146 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
1147         .name = "gcc_qupv3_wrap2_s1_clk_src",
1148         .parent_data = gcc_parent_data_1,
1149         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1150         .ops = &clk_rcg2_shared_ops,
1151 };
1152
1153 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
1154         .cmd_rcgr = 0x2a288,
1155         .mnd_width = 16,
1156         .hid_width = 5,
1157         .parent_map = gcc_parent_map_1,
1158         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1159         .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1160 };
1161
1162 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1163         .name = "gcc_qupv3_wrap2_s2_clk_src",
1164         .parent_data = gcc_parent_data_1,
1165         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1166         .ops = &clk_rcg2_shared_ops,
1167 };
1168
1169 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1170         .cmd_rcgr = 0x2a3bc,
1171         .mnd_width = 16,
1172         .hid_width = 5,
1173         .parent_map = gcc_parent_map_1,
1174         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1175         .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1176 };
1177
1178 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1179         .name = "gcc_qupv3_wrap2_s3_clk_src",
1180         .parent_data = gcc_parent_data_1,
1181         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1182         .ops = &clk_rcg2_shared_ops,
1183 };
1184
1185 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1186         .cmd_rcgr = 0x2a4f0,
1187         .mnd_width = 16,
1188         .hid_width = 5,
1189         .parent_map = gcc_parent_map_1,
1190         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1191         .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1192 };
1193
1194 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1195         .name = "gcc_qupv3_wrap2_s4_clk_src",
1196         .parent_data = gcc_parent_data_1,
1197         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1198         .ops = &clk_rcg2_shared_ops,
1199 };
1200
1201 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1202         .cmd_rcgr = 0x2a624,
1203         .mnd_width = 16,
1204         .hid_width = 5,
1205         .parent_map = gcc_parent_map_1,
1206         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1207         .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1208 };
1209
1210 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1211         .name = "gcc_qupv3_wrap2_s5_clk_src",
1212         .parent_data = gcc_parent_data_1,
1213         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1214         .ops = &clk_rcg2_shared_ops,
1215 };
1216
1217 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1218         .cmd_rcgr = 0x2a758,
1219         .mnd_width = 16,
1220         .hid_width = 5,
1221         .parent_map = gcc_parent_map_1,
1222         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1223         .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1224 };
1225
1226 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1227         .name = "gcc_qupv3_wrap2_s6_clk_src",
1228         .parent_data = gcc_parent_data_1,
1229         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1230         .ops = &clk_rcg2_shared_ops,
1231 };
1232
1233 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1234         .cmd_rcgr = 0x2a88c,
1235         .mnd_width = 16,
1236         .hid_width = 5,
1237         .parent_map = gcc_parent_map_1,
1238         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1239         .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1240 };
1241
1242 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
1243         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
1244         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
1245         F(19200000, P_BI_TCXO, 1, 0, 0),
1246         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
1247         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
1248         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
1249         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
1250         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1251         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
1252         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
1253         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
1254         F(403200000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1255         { }
1256 };
1257
1258 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = {
1259         .name = "gcc_qupv3_wrap3_s0_clk_src",
1260         .parent_data = gcc_parent_data_4,
1261         .num_parents = ARRAY_SIZE(gcc_parent_data_4),
1262         .ops = &clk_rcg2_shared_ops,
1263 };
1264
1265 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = {
1266         .cmd_rcgr = 0xc4154,
1267         .mnd_width = 16,
1268         .hid_width = 5,
1269         .parent_map = gcc_parent_map_4,
1270         .freq_tbl = ftbl_gcc_qupv3_wrap3_s0_clk_src,
1271         .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init,
1272 };
1273
1274 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1275         F(144000, P_BI_TCXO, 16, 3, 25),
1276         F(400000, P_BI_TCXO, 12, 1, 4),
1277         F(19200000, P_BI_TCXO, 1, 0, 0),
1278         F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
1279         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1280         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1281         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1282         F(192000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1283         F(384000000, P_GCC_GPLL9_OUT_MAIN, 2, 0, 0),
1284         { }
1285 };
1286
1287 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1288         .cmd_rcgr = 0x20014,
1289         .mnd_width = 8,
1290         .hid_width = 5,
1291         .parent_map = gcc_parent_map_13,
1292         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1293         .clkr.hw.init = &(const struct clk_init_data){
1294                 .name = "gcc_sdcc1_apps_clk_src",
1295                 .parent_data = gcc_parent_data_13,
1296                 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
1297                 .ops = &clk_rcg2_floor_ops,
1298         },
1299 };
1300
1301 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1302         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1303         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1304         { }
1305 };
1306
1307 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1308         .cmd_rcgr = 0x2002c,
1309         .mnd_width = 0,
1310         .hid_width = 5,
1311         .parent_map = gcc_parent_map_14,
1312         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1313         .clkr.hw.init = &(const struct clk_init_data){
1314                 .name = "gcc_sdcc1_ice_core_clk_src",
1315                 .parent_data = gcc_parent_data_14,
1316                 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
1317                 .ops = &clk_rcg2_floor_ops,
1318         },
1319 };
1320
1321 static const struct freq_tbl ftbl_gcc_tscss_cntr_clk_src[] = {
1322         F(15625000, P_GCC_GPLL7_OUT_MAIN, 16, 1, 4),
1323         { }
1324 };
1325
1326 static struct clk_rcg2 gcc_tscss_cntr_clk_src = {
1327         .cmd_rcgr = 0x21008,
1328         .mnd_width = 16,
1329         .hid_width = 5,
1330         .parent_map = gcc_parent_map_15,
1331         .freq_tbl = ftbl_gcc_tscss_cntr_clk_src,
1332         .clkr.hw.init = &(const struct clk_init_data){
1333                 .name = "gcc_tscss_cntr_clk_src",
1334                 .parent_data = gcc_parent_data_15,
1335                 .num_parents = ARRAY_SIZE(gcc_parent_data_15),
1336                 .ops = &clk_rcg2_shared_ops,
1337         },
1338 };
1339
1340 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1341         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1342         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1343         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1344         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1345         F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1346         { }
1347 };
1348
1349 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1350         .cmd_rcgr = 0x8102c,
1351         .mnd_width = 8,
1352         .hid_width = 5,
1353         .parent_map = gcc_parent_map_0,
1354         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1355         .clkr.hw.init = &(const struct clk_init_data){
1356                 .name = "gcc_ufs_card_axi_clk_src",
1357                 .parent_data = gcc_parent_data_0,
1358                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1359                 .ops = &clk_rcg2_shared_ops,
1360         },
1361 };
1362
1363 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1364         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1365         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1366         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1367         F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
1368         { }
1369 };
1370
1371 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1372         .cmd_rcgr = 0x81074,
1373         .mnd_width = 0,
1374         .hid_width = 5,
1375         .parent_map = gcc_parent_map_0,
1376         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1377         .clkr.hw.init = &(const struct clk_init_data){
1378                 .name = "gcc_ufs_card_ice_core_clk_src",
1379                 .parent_data = gcc_parent_data_0,
1380                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1381                 .ops = &clk_rcg2_shared_ops,
1382         },
1383 };
1384
1385 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1386         .cmd_rcgr = 0x810a8,
1387         .mnd_width = 0,
1388         .hid_width = 5,
1389         .parent_map = gcc_parent_map_5,
1390         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1391         .clkr.hw.init = &(const struct clk_init_data){
1392                 .name = "gcc_ufs_card_phy_aux_clk_src",
1393                 .parent_data = gcc_parent_data_5,
1394                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1395                 .ops = &clk_rcg2_shared_ops,
1396         },
1397 };
1398
1399 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1400         .cmd_rcgr = 0x8108c,
1401         .mnd_width = 0,
1402         .hid_width = 5,
1403         .parent_map = gcc_parent_map_0,
1404         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1405         .clkr.hw.init = &(const struct clk_init_data){
1406                 .name = "gcc_ufs_card_unipro_core_clk_src",
1407                 .parent_data = gcc_parent_data_0,
1408                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1409                 .ops = &clk_rcg2_shared_ops,
1410         },
1411 };
1412
1413 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1414         .cmd_rcgr = 0x8302c,
1415         .mnd_width = 8,
1416         .hid_width = 5,
1417         .parent_map = gcc_parent_map_0,
1418         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1419         .clkr.hw.init = &(const struct clk_init_data){
1420                 .name = "gcc_ufs_phy_axi_clk_src",
1421                 .parent_data = gcc_parent_data_0,
1422                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1423                 .ops = &clk_rcg2_shared_ops,
1424         },
1425 };
1426
1427 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1428         .cmd_rcgr = 0x83074,
1429         .mnd_width = 0,
1430         .hid_width = 5,
1431         .parent_map = gcc_parent_map_0,
1432         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1433         .clkr.hw.init = &(const struct clk_init_data){
1434                 .name = "gcc_ufs_phy_ice_core_clk_src",
1435                 .parent_data = gcc_parent_data_0,
1436                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1437                 .ops = &clk_rcg2_shared_ops,
1438         },
1439 };
1440
1441 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1442         .cmd_rcgr = 0x830a8,
1443         .mnd_width = 0,
1444         .hid_width = 5,
1445         .parent_map = gcc_parent_map_5,
1446         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1447         .clkr.hw.init = &(const struct clk_init_data){
1448                 .name = "gcc_ufs_phy_phy_aux_clk_src",
1449                 .parent_data = gcc_parent_data_5,
1450                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1451                 .ops = &clk_rcg2_shared_ops,
1452         },
1453 };
1454
1455 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1456         .cmd_rcgr = 0x8308c,
1457         .mnd_width = 0,
1458         .hid_width = 5,
1459         .parent_map = gcc_parent_map_0,
1460         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1461         .clkr.hw.init = &(const struct clk_init_data){
1462                 .name = "gcc_ufs_phy_unipro_core_clk_src",
1463                 .parent_data = gcc_parent_data_0,
1464                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1465                 .ops = &clk_rcg2_shared_ops,
1466         },
1467 };
1468
1469 static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
1470         F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1471         { }
1472 };
1473
1474 static struct clk_rcg2 gcc_usb20_master_clk_src = {
1475         .cmd_rcgr = 0x1c028,
1476         .mnd_width = 8,
1477         .hid_width = 5,
1478         .parent_map = gcc_parent_map_0,
1479         .freq_tbl = ftbl_gcc_usb20_master_clk_src,
1480         .clkr.hw.init = &(const struct clk_init_data){
1481                 .name = "gcc_usb20_master_clk_src",
1482                 .parent_data = gcc_parent_data_0,
1483                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1484                 .ops = &clk_rcg2_shared_ops,
1485         },
1486 };
1487
1488 static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
1489         .cmd_rcgr = 0x1c040,
1490         .mnd_width = 0,
1491         .hid_width = 5,
1492         .parent_map = gcc_parent_map_0,
1493         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1494         .clkr.hw.init = &(const struct clk_init_data){
1495                 .name = "gcc_usb20_mock_utmi_clk_src",
1496                 .parent_data = gcc_parent_data_0,
1497                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1498                 .ops = &clk_rcg2_shared_ops,
1499         },
1500 };
1501
1502 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1503         F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1504         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1505         F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1506         { }
1507 };
1508
1509 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1510         .cmd_rcgr = 0x1b028,
1511         .mnd_width = 8,
1512         .hid_width = 5,
1513         .parent_map = gcc_parent_map_0,
1514         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1515         .clkr.hw.init = &(const struct clk_init_data){
1516                 .name = "gcc_usb30_prim_master_clk_src",
1517                 .parent_data = gcc_parent_data_0,
1518                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1519                 .ops = &clk_rcg2_shared_ops,
1520         },
1521 };
1522
1523 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1524         .cmd_rcgr = 0x1b040,
1525         .mnd_width = 0,
1526         .hid_width = 5,
1527         .parent_map = gcc_parent_map_0,
1528         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1529         .clkr.hw.init = &(const struct clk_init_data){
1530                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1531                 .parent_data = gcc_parent_data_0,
1532                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1533                 .ops = &clk_rcg2_shared_ops,
1534         },
1535 };
1536
1537 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1538         .cmd_rcgr = 0x2f028,
1539         .mnd_width = 8,
1540         .hid_width = 5,
1541         .parent_map = gcc_parent_map_0,
1542         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1543         .clkr.hw.init = &(const struct clk_init_data){
1544                 .name = "gcc_usb30_sec_master_clk_src",
1545                 .parent_data = gcc_parent_data_0,
1546                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1547                 .ops = &clk_rcg2_shared_ops,
1548         },
1549 };
1550
1551 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1552         .cmd_rcgr = 0x2f040,
1553         .mnd_width = 0,
1554         .hid_width = 5,
1555         .parent_map = gcc_parent_map_0,
1556         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1557         .clkr.hw.init = &(const struct clk_init_data){
1558                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1559                 .parent_data = gcc_parent_data_0,
1560                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1561                 .ops = &clk_rcg2_shared_ops,
1562         },
1563 };
1564
1565 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1566         .cmd_rcgr = 0x1b06c,
1567         .mnd_width = 0,
1568         .hid_width = 5,
1569         .parent_map = gcc_parent_map_3,
1570         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1571         .clkr.hw.init = &(const struct clk_init_data){
1572                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1573                 .parent_data = gcc_parent_data_3,
1574                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1575                 .ops = &clk_rcg2_shared_ops,
1576         },
1577 };
1578
1579 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1580         .cmd_rcgr = 0x2f06c,
1581         .mnd_width = 0,
1582         .hid_width = 5,
1583         .parent_map = gcc_parent_map_3,
1584         .freq_tbl = ftbl_gcc_emac0_phy_aux_clk_src,
1585         .clkr.hw.init = &(const struct clk_init_data){
1586                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1587                 .parent_data = gcc_parent_data_3,
1588                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1589                 .ops = &clk_rcg2_shared_ops,
1590         },
1591 };
1592
1593 static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = {
1594         .reg = 0xa9070,
1595         .shift = 0,
1596         .width = 4,
1597         .clkr.hw.init = &(const struct clk_init_data) {
1598                 .name = "gcc_pcie_0_pipe_div_clk_src",
1599                 .parent_hws = (const struct clk_hw*[]){
1600                         &gcc_pcie_0_pipe_clk_src.clkr.hw,
1601                 },
1602                 .num_parents = 1,
1603                 .flags = CLK_SET_RATE_PARENT,
1604                 .ops = &clk_regmap_div_ro_ops,
1605         },
1606 };
1607
1608 static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = {
1609         .reg = 0x77070,
1610         .shift = 0,
1611         .width = 4,
1612         .clkr.hw.init = &(const struct clk_init_data) {
1613                 .name = "gcc_pcie_1_pipe_div_clk_src",
1614                 .parent_hws = (const struct clk_hw*[]){
1615                         &gcc_pcie_1_pipe_clk_src.clkr.hw,
1616                 },
1617                 .num_parents = 1,
1618                 .flags = CLK_SET_RATE_PARENT,
1619                 .ops = &clk_regmap_div_ro_ops,
1620         },
1621 };
1622
1623 static struct clk_regmap_div gcc_qupv3_wrap3_s0_div_clk_src = {
1624         .reg = 0xc4284,
1625         .shift = 0,
1626         .width = 4,
1627         .clkr.hw.init = &(const struct clk_init_data) {
1628                 .name = "gcc_qupv3_wrap3_s0_div_clk_src",
1629                 .parent_hws = (const struct clk_hw*[]){
1630                         &gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
1631                 },
1632                 .num_parents = 1,
1633                 .flags = CLK_SET_RATE_PARENT,
1634                 .ops = &clk_regmap_div_ro_ops,
1635         },
1636 };
1637
1638 static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
1639         .reg = 0x1c058,
1640         .shift = 0,
1641         .width = 4,
1642         .clkr.hw.init = &(const struct clk_init_data) {
1643                 .name = "gcc_usb20_mock_utmi_postdiv_clk_src",
1644                 .parent_hws = (const struct clk_hw*[]){
1645                         &gcc_usb20_mock_utmi_clk_src.clkr.hw,
1646                 },
1647                 .num_parents = 1,
1648                 .flags = CLK_SET_RATE_PARENT,
1649                 .ops = &clk_regmap_div_ro_ops,
1650         },
1651 };
1652
1653 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1654         .reg = 0x1b058,
1655         .shift = 0,
1656         .width = 4,
1657         .clkr.hw.init = &(const struct clk_init_data) {
1658                 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1659                 .parent_hws = (const struct clk_hw*[]){
1660                         &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1661                 },
1662                 .num_parents = 1,
1663                 .flags = CLK_SET_RATE_PARENT,
1664                 .ops = &clk_regmap_div_ro_ops,
1665         },
1666 };
1667
1668 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1669         .reg = 0x2f058,
1670         .shift = 0,
1671         .width = 4,
1672         .clkr.hw.init = &(const struct clk_init_data) {
1673                 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1674                 .parent_hws = (const struct clk_hw*[]){
1675                         &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1676                 },
1677                 .num_parents = 1,
1678                 .flags = CLK_SET_RATE_PARENT,
1679                 .ops = &clk_regmap_div_ro_ops,
1680         },
1681 };
1682
1683 static struct clk_branch gcc_aggre_noc_qupv3_axi_clk = {
1684         .halt_reg = 0x8e200,
1685         .halt_check = BRANCH_HALT_VOTED,
1686         .hwcg_reg = 0x8e200,
1687         .hwcg_bit = 1,
1688         .clkr = {
1689                 .enable_reg = 0x4b000,
1690                 .enable_mask = BIT(28),
1691                 .hw.init = &(const struct clk_init_data){
1692                         .name = "gcc_aggre_noc_qupv3_axi_clk",
1693                         .ops = &clk_branch2_ops,
1694                 },
1695         },
1696 };
1697
1698 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1699         .halt_reg = 0x810d4,
1700         .halt_check = BRANCH_HALT_VOTED,
1701         .hwcg_reg = 0x810d4,
1702         .hwcg_bit = 1,
1703         .clkr = {
1704                 .enable_reg = 0x810d4,
1705                 .enable_mask = BIT(0),
1706                 .hw.init = &(const struct clk_init_data){
1707                         .name = "gcc_aggre_ufs_card_axi_clk",
1708                         .parent_hws = (const struct clk_hw*[]){
1709                                 &gcc_ufs_card_axi_clk_src.clkr.hw,
1710                         },
1711                         .num_parents = 1,
1712                         .flags = CLK_SET_RATE_PARENT,
1713                         .ops = &clk_branch2_ops,
1714                 },
1715         },
1716 };
1717
1718 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1719         .halt_reg = 0x830d4,
1720         .halt_check = BRANCH_HALT_VOTED,
1721         .hwcg_reg = 0x830d4,
1722         .hwcg_bit = 1,
1723         .clkr = {
1724                 .enable_reg = 0x830d4,
1725                 .enable_mask = BIT(0),
1726                 .hw.init = &(const struct clk_init_data){
1727                         .name = "gcc_aggre_ufs_phy_axi_clk",
1728                         .parent_hws = (const struct clk_hw*[]){
1729                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1730                         },
1731                         .num_parents = 1,
1732                         .flags = CLK_SET_RATE_PARENT,
1733                         .ops = &clk_branch2_ops,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
1739         .halt_reg = 0x1c05c,
1740         .halt_check = BRANCH_HALT_VOTED,
1741         .hwcg_reg = 0x1c05c,
1742         .hwcg_bit = 1,
1743         .clkr = {
1744                 .enable_reg = 0x1c05c,
1745                 .enable_mask = BIT(0),
1746                 .hw.init = &(const struct clk_init_data){
1747                         .name = "gcc_aggre_usb2_prim_axi_clk",
1748                         .parent_hws = (const struct clk_hw*[]){
1749                                 &gcc_usb20_master_clk_src.clkr.hw,
1750                         },
1751                         .num_parents = 1,
1752                         .flags = CLK_SET_RATE_PARENT,
1753                         .ops = &clk_branch2_ops,
1754                 },
1755         },
1756 };
1757
1758 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1759         .halt_reg = 0x1b084,
1760         .halt_check = BRANCH_HALT_VOTED,
1761         .hwcg_reg = 0x1b084,
1762         .hwcg_bit = 1,
1763         .clkr = {
1764                 .enable_reg = 0x1b084,
1765                 .enable_mask = BIT(0),
1766                 .hw.init = &(const struct clk_init_data){
1767                         .name = "gcc_aggre_usb3_prim_axi_clk",
1768                         .parent_hws = (const struct clk_hw*[]){
1769                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1770                         },
1771                         .num_parents = 1,
1772                         .flags = CLK_SET_RATE_PARENT,
1773                         .ops = &clk_branch2_ops,
1774                 },
1775         },
1776 };
1777
1778 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1779         .halt_reg = 0x2f088,
1780         .halt_check = BRANCH_HALT_VOTED,
1781         .hwcg_reg = 0x2f088,
1782         .hwcg_bit = 1,
1783         .clkr = {
1784                 .enable_reg = 0x2f088,
1785                 .enable_mask = BIT(0),
1786                 .hw.init = &(const struct clk_init_data){
1787                         .name = "gcc_aggre_usb3_sec_axi_clk",
1788                         .parent_hws = (const struct clk_hw*[]){
1789                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1790                         },
1791                         .num_parents = 1,
1792                         .flags = CLK_SET_RATE_PARENT,
1793                         .ops = &clk_branch2_ops,
1794                 },
1795         },
1796 };
1797
1798 static struct clk_branch gcc_ahb2phy0_clk = {
1799         .halt_reg = 0x76004,
1800         .halt_check = BRANCH_HALT_VOTED,
1801         .hwcg_reg = 0x76004,
1802         .hwcg_bit = 1,
1803         .clkr = {
1804                 .enable_reg = 0x76004,
1805                 .enable_mask = BIT(0),
1806                 .hw.init = &(const struct clk_init_data){
1807                         .name = "gcc_ahb2phy0_clk",
1808                         .ops = &clk_branch2_ops,
1809                 },
1810         },
1811 };
1812
1813 static struct clk_branch gcc_ahb2phy2_clk = {
1814         .halt_reg = 0x76008,
1815         .halt_check = BRANCH_HALT_VOTED,
1816         .hwcg_reg = 0x76008,
1817         .hwcg_bit = 1,
1818         .clkr = {
1819                 .enable_reg = 0x76008,
1820                 .enable_mask = BIT(0),
1821                 .hw.init = &(const struct clk_init_data){
1822                         .name = "gcc_ahb2phy2_clk",
1823                         .ops = &clk_branch2_ops,
1824                 },
1825         },
1826 };
1827
1828 static struct clk_branch gcc_ahb2phy3_clk = {
1829         .halt_reg = 0x7600c,
1830         .halt_check = BRANCH_HALT_VOTED,
1831         .hwcg_reg = 0x7600c,
1832         .hwcg_bit = 1,
1833         .clkr = {
1834                 .enable_reg = 0x7600c,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(const struct clk_init_data){
1837                         .name = "gcc_ahb2phy3_clk",
1838                         .ops = &clk_branch2_ops,
1839                 },
1840         },
1841 };
1842
1843 static struct clk_branch gcc_boot_rom_ahb_clk = {
1844         .halt_reg = 0x44004,
1845         .halt_check = BRANCH_HALT_VOTED,
1846         .hwcg_reg = 0x44004,
1847         .hwcg_bit = 1,
1848         .clkr = {
1849                 .enable_reg = 0x4b000,
1850                 .enable_mask = BIT(10),
1851                 .hw.init = &(const struct clk_init_data){
1852                         .name = "gcc_boot_rom_ahb_clk",
1853                         .ops = &clk_branch2_ops,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_branch gcc_camera_hf_axi_clk = {
1859         .halt_reg = 0x32010,
1860         .halt_check = BRANCH_HALT_SKIP,
1861         .hwcg_reg = 0x32010,
1862         .hwcg_bit = 1,
1863         .clkr = {
1864                 .enable_reg = 0x32010,
1865                 .enable_mask = BIT(0),
1866                 .hw.init = &(const struct clk_init_data){
1867                         .name = "gcc_camera_hf_axi_clk",
1868                         .ops = &clk_branch2_ops,
1869                 },
1870         },
1871 };
1872
1873 static struct clk_branch gcc_camera_sf_axi_clk = {
1874         .halt_reg = 0x32018,
1875         .halt_check = BRANCH_HALT_SKIP,
1876         .hwcg_reg = 0x32018,
1877         .hwcg_bit = 1,
1878         .clkr = {
1879                 .enable_reg = 0x32018,
1880                 .enable_mask = BIT(0),
1881                 .hw.init = &(const struct clk_init_data){
1882                         .name = "gcc_camera_sf_axi_clk",
1883                         .ops = &clk_branch2_ops,
1884                 },
1885         },
1886 };
1887
1888 static struct clk_branch gcc_camera_throttle_xo_clk = {
1889         .halt_reg = 0x32024,
1890         .halt_check = BRANCH_HALT,
1891         .clkr = {
1892                 .enable_reg = 0x32024,
1893                 .enable_mask = BIT(0),
1894                 .hw.init = &(const struct clk_init_data){
1895                         .name = "gcc_camera_throttle_xo_clk",
1896                         .ops = &clk_branch2_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
1902         .halt_reg = 0x1c060,
1903         .halt_check = BRANCH_HALT_VOTED,
1904         .hwcg_reg = 0x1c060,
1905         .hwcg_bit = 1,
1906         .clkr = {
1907                 .enable_reg = 0x1c060,
1908                 .enable_mask = BIT(0),
1909                 .hw.init = &(const struct clk_init_data){
1910                         .name = "gcc_cfg_noc_usb2_prim_axi_clk",
1911                         .parent_hws = (const struct clk_hw*[]){
1912                                 &gcc_usb20_master_clk_src.clkr.hw,
1913                         },
1914                         .num_parents = 1,
1915                         .flags = CLK_SET_RATE_PARENT,
1916                         .ops = &clk_branch2_ops,
1917                 },
1918         },
1919 };
1920
1921 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1922         .halt_reg = 0x1b088,
1923         .halt_check = BRANCH_HALT_VOTED,
1924         .hwcg_reg = 0x1b088,
1925         .hwcg_bit = 1,
1926         .clkr = {
1927                 .enable_reg = 0x1b088,
1928                 .enable_mask = BIT(0),
1929                 .hw.init = &(const struct clk_init_data){
1930                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1931                         .parent_hws = (const struct clk_hw*[]){
1932                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1933                         },
1934                         .num_parents = 1,
1935                         .flags = CLK_SET_RATE_PARENT,
1936                         .ops = &clk_branch2_ops,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1942         .halt_reg = 0x2f084,
1943         .halt_check = BRANCH_HALT_VOTED,
1944         .hwcg_reg = 0x2f084,
1945         .hwcg_bit = 1,
1946         .clkr = {
1947                 .enable_reg = 0x2f084,
1948                 .enable_mask = BIT(0),
1949                 .hw.init = &(const struct clk_init_data){
1950                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1951                         .parent_hws = (const struct clk_hw*[]){
1952                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1953                         },
1954                         .num_parents = 1,
1955                         .flags = CLK_SET_RATE_PARENT,
1956                         .ops = &clk_branch2_ops,
1957                 },
1958         },
1959 };
1960
1961 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1962         .halt_reg = 0x7d164,
1963         .halt_check = BRANCH_HALT_VOTED,
1964         .hwcg_reg = 0x7d164,
1965         .hwcg_bit = 1,
1966         .clkr = {
1967                 .enable_reg = 0x7d164,
1968                 .enable_mask = BIT(0),
1969                 .hw.init = &(const struct clk_init_data){
1970                         .name = "gcc_ddrss_gpu_axi_clk",
1971                         .ops = &clk_branch2_aon_ops,
1972                 },
1973         },
1974 };
1975
1976 static struct clk_branch gcc_disp1_hf_axi_clk = {
1977         .halt_reg = 0xc7010,
1978         .halt_check = BRANCH_HALT_VOTED,
1979         .hwcg_reg = 0xc7010,
1980         .hwcg_bit = 1,
1981         .clkr = {
1982                 .enable_reg = 0xc7010,
1983                 .enable_mask = BIT(0),
1984                 .hw.init = &(const struct clk_init_data){
1985                         .name = "gcc_disp1_hf_axi_clk",
1986                         .ops = &clk_branch2_ops,
1987                 },
1988         },
1989 };
1990
1991 static struct clk_branch gcc_disp_hf_axi_clk = {
1992         .halt_reg = 0x33010,
1993         .halt_check = BRANCH_HALT_VOTED,
1994         .hwcg_reg = 0x33010,
1995         .hwcg_bit = 1,
1996         .clkr = {
1997                 .enable_reg = 0x33010,
1998                 .enable_mask = BIT(0),
1999                 .hw.init = &(const struct clk_init_data){
2000                         .name = "gcc_disp_hf_axi_clk",
2001                         .ops = &clk_branch2_ops,
2002                 },
2003         },
2004 };
2005
2006 static struct clk_branch gcc_edp_ref_clkref_en = {
2007         .halt_reg = 0x97448,
2008         .halt_check = BRANCH_HALT_DELAY,
2009         .clkr = {
2010                 .enable_reg = 0x97448,
2011                 .enable_mask = BIT(0),
2012                 .hw.init = &(const struct clk_init_data){
2013                         .name = "gcc_edp_ref_clkref_en",
2014                         .ops = &clk_branch2_ops,
2015                 },
2016         },
2017 };
2018
2019 static struct clk_branch gcc_emac0_axi_clk = {
2020         .halt_reg = 0xb6018,
2021         .halt_check = BRANCH_HALT_VOTED,
2022         .hwcg_reg = 0xb6018,
2023         .hwcg_bit = 1,
2024         .clkr = {
2025                 .enable_reg = 0xb6018,
2026                 .enable_mask = BIT(0),
2027                 .hw.init = &(const struct clk_init_data){
2028                         .name = "gcc_emac0_axi_clk",
2029                         .ops = &clk_branch2_ops,
2030                 },
2031         },
2032 };
2033
2034 static struct clk_branch gcc_emac0_phy_aux_clk = {
2035         .halt_reg = 0xb6024,
2036         .halt_check = BRANCH_HALT,
2037         .clkr = {
2038                 .enable_reg = 0xb6024,
2039                 .enable_mask = BIT(0),
2040                 .hw.init = &(const struct clk_init_data){
2041                         .name = "gcc_emac0_phy_aux_clk",
2042                         .parent_hws = (const struct clk_hw*[]){
2043                                 &gcc_emac0_phy_aux_clk_src.clkr.hw,
2044                         },
2045                         .num_parents = 1,
2046                         .flags = CLK_SET_RATE_PARENT,
2047                         .ops = &clk_branch2_ops,
2048                 },
2049         },
2050 };
2051
2052 static struct clk_branch gcc_emac0_ptp_clk = {
2053         .halt_reg = 0xb6040,
2054         .halt_check = BRANCH_HALT,
2055         .clkr = {
2056                 .enable_reg = 0xb6040,
2057                 .enable_mask = BIT(0),
2058                 .hw.init = &(const struct clk_init_data){
2059                         .name = "gcc_emac0_ptp_clk",
2060                         .parent_hws = (const struct clk_hw*[]){
2061                                 &gcc_emac0_ptp_clk_src.clkr.hw,
2062                         },
2063                         .num_parents = 1,
2064                         .flags = CLK_SET_RATE_PARENT,
2065                         .ops = &clk_branch2_ops,
2066                 },
2067         },
2068 };
2069
2070 static struct clk_branch gcc_emac0_rgmii_clk = {
2071         .halt_reg = 0xb6044,
2072         .halt_check = BRANCH_HALT,
2073         .clkr = {
2074                 .enable_reg = 0xb6044,
2075                 .enable_mask = BIT(0),
2076                 .hw.init = &(const struct clk_init_data){
2077                         .name = "gcc_emac0_rgmii_clk",
2078                         .parent_hws = (const struct clk_hw*[]){
2079                                 &gcc_emac0_rgmii_clk_src.clkr.hw,
2080                         },
2081                         .num_parents = 1,
2082                         .flags = CLK_SET_RATE_PARENT,
2083                         .ops = &clk_branch2_ops,
2084                 },
2085         },
2086 };
2087
2088 static struct clk_branch gcc_emac0_slv_ahb_clk = {
2089         .halt_reg = 0xb6020,
2090         .halt_check = BRANCH_HALT_VOTED,
2091         .hwcg_reg = 0xb6020,
2092         .hwcg_bit = 1,
2093         .clkr = {
2094                 .enable_reg = 0xb6020,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(const struct clk_init_data){
2097                         .name = "gcc_emac0_slv_ahb_clk",
2098                         .ops = &clk_branch2_ops,
2099                 },
2100         },
2101 };
2102
2103 static struct clk_branch gcc_emac1_axi_clk = {
2104         .halt_reg = 0xb4018,
2105         .halt_check = BRANCH_HALT_VOTED,
2106         .hwcg_reg = 0xb4018,
2107         .hwcg_bit = 1,
2108         .clkr = {
2109                 .enable_reg = 0xb4018,
2110                 .enable_mask = BIT(0),
2111                 .hw.init = &(const struct clk_init_data){
2112                         .name = "gcc_emac1_axi_clk",
2113                         .ops = &clk_branch2_ops,
2114                 },
2115         },
2116 };
2117
2118 static struct clk_branch gcc_emac1_phy_aux_clk = {
2119         .halt_reg = 0xb4024,
2120         .halt_check = BRANCH_HALT,
2121         .clkr = {
2122                 .enable_reg = 0xb4024,
2123                 .enable_mask = BIT(0),
2124                 .hw.init = &(const struct clk_init_data){
2125                         .name = "gcc_emac1_phy_aux_clk",
2126                         .parent_hws = (const struct clk_hw*[]){
2127                                 &gcc_emac1_phy_aux_clk_src.clkr.hw,
2128                         },
2129                         .num_parents = 1,
2130                         .flags = CLK_SET_RATE_PARENT,
2131                         .ops = &clk_branch2_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch gcc_emac1_ptp_clk = {
2137         .halt_reg = 0xb4040,
2138         .halt_check = BRANCH_HALT,
2139         .clkr = {
2140                 .enable_reg = 0xb4040,
2141                 .enable_mask = BIT(0),
2142                 .hw.init = &(const struct clk_init_data){
2143                         .name = "gcc_emac1_ptp_clk",
2144                         .parent_hws = (const struct clk_hw*[]){
2145                                 &gcc_emac1_ptp_clk_src.clkr.hw,
2146                         },
2147                         .num_parents = 1,
2148                         .flags = CLK_SET_RATE_PARENT,
2149                         .ops = &clk_branch2_ops,
2150                 },
2151         },
2152 };
2153
2154 static struct clk_branch gcc_emac1_rgmii_clk = {
2155         .halt_reg = 0xb4044,
2156         .halt_check = BRANCH_HALT,
2157         .clkr = {
2158                 .enable_reg = 0xb4044,
2159                 .enable_mask = BIT(0),
2160                 .hw.init = &(const struct clk_init_data){
2161                         .name = "gcc_emac1_rgmii_clk",
2162                         .parent_hws = (const struct clk_hw*[]){
2163                                 &gcc_emac1_rgmii_clk_src.clkr.hw,
2164                         },
2165                         .num_parents = 1,
2166                         .flags = CLK_SET_RATE_PARENT,
2167                         .ops = &clk_branch2_ops,
2168                 },
2169         },
2170 };
2171
2172 static struct clk_branch gcc_emac1_slv_ahb_clk = {
2173         .halt_reg = 0xb4020,
2174         .halt_check = BRANCH_HALT_VOTED,
2175         .hwcg_reg = 0xb4020,
2176         .hwcg_bit = 1,
2177         .clkr = {
2178                 .enable_reg = 0xb4020,
2179                 .enable_mask = BIT(0),
2180                 .hw.init = &(const struct clk_init_data){
2181                         .name = "gcc_emac1_slv_ahb_clk",
2182                         .ops = &clk_branch2_ops,
2183                 },
2184         },
2185 };
2186
2187 static struct clk_branch gcc_gp1_clk = {
2188         .halt_reg = 0x70000,
2189         .halt_check = BRANCH_HALT,
2190         .clkr = {
2191                 .enable_reg = 0x70000,
2192                 .enable_mask = BIT(0),
2193                 .hw.init = &(const struct clk_init_data){
2194                         .name = "gcc_gp1_clk",
2195                         .parent_hws = (const struct clk_hw*[]){
2196                                 &gcc_gp1_clk_src.clkr.hw,
2197                         },
2198                         .num_parents = 1,
2199                         .flags = CLK_SET_RATE_PARENT,
2200                         .ops = &clk_branch2_ops,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_branch gcc_gp2_clk = {
2206         .halt_reg = 0x71000,
2207         .halt_check = BRANCH_HALT,
2208         .clkr = {
2209                 .enable_reg = 0x71000,
2210                 .enable_mask = BIT(0),
2211                 .hw.init = &(const struct clk_init_data){
2212                         .name = "gcc_gp2_clk",
2213                         .parent_hws = (const struct clk_hw*[]){
2214                                 &gcc_gp2_clk_src.clkr.hw,
2215                         },
2216                         .num_parents = 1,
2217                         .flags = CLK_SET_RATE_PARENT,
2218                         .ops = &clk_branch2_ops,
2219                 },
2220         },
2221 };
2222
2223 static struct clk_branch gcc_gp3_clk = {
2224         .halt_reg = 0x62000,
2225         .halt_check = BRANCH_HALT,
2226         .clkr = {
2227                 .enable_reg = 0x62000,
2228                 .enable_mask = BIT(0),
2229                 .hw.init = &(const struct clk_init_data){
2230                         .name = "gcc_gp3_clk",
2231                         .parent_hws = (const struct clk_hw*[]){
2232                                 &gcc_gp3_clk_src.clkr.hw,
2233                         },
2234                         .num_parents = 1,
2235                         .flags = CLK_SET_RATE_PARENT,
2236                         .ops = &clk_branch2_ops,
2237                 },
2238         },
2239 };
2240
2241 static struct clk_branch gcc_gp4_clk = {
2242         .halt_reg = 0x1e000,
2243         .halt_check = BRANCH_HALT,
2244         .clkr = {
2245                 .enable_reg = 0x1e000,
2246                 .enable_mask = BIT(0),
2247                 .hw.init = &(const struct clk_init_data){
2248                         .name = "gcc_gp4_clk",
2249                         .parent_hws = (const struct clk_hw*[]){
2250                                 &gcc_gp4_clk_src.clkr.hw,
2251                         },
2252                         .num_parents = 1,
2253                         .flags = CLK_SET_RATE_PARENT,
2254                         .ops = &clk_branch2_ops,
2255                 },
2256         },
2257 };
2258
2259 static struct clk_branch gcc_gp5_clk = {
2260         .halt_reg = 0x1f000,
2261         .halt_check = BRANCH_HALT,
2262         .clkr = {
2263                 .enable_reg = 0x1f000,
2264                 .enable_mask = BIT(0),
2265                 .hw.init = &(const struct clk_init_data){
2266                         .name = "gcc_gp5_clk",
2267                         .parent_hws = (const struct clk_hw*[]){
2268                                 &gcc_gp5_clk_src.clkr.hw,
2269                         },
2270                         .num_parents = 1,
2271                         .flags = CLK_SET_RATE_PARENT,
2272                         .ops = &clk_branch2_ops,
2273                 },
2274         },
2275 };
2276
2277 static struct clk_branch gcc_gpu_gpll0_clk_src = {
2278         .halt_check = BRANCH_HALT_DELAY,
2279         .clkr = {
2280                 .enable_reg = 0x4b000,
2281                 .enable_mask = BIT(15),
2282                 .hw.init = &(const struct clk_init_data){
2283                         .name = "gcc_gpu_gpll0_clk_src",
2284                         .parent_hws = (const struct clk_hw*[]){
2285                                 &gcc_gpll0.clkr.hw,
2286                         },
2287                         .num_parents = 1,
2288                         .flags = CLK_SET_RATE_PARENT,
2289                         .ops = &clk_branch2_ops,
2290                 },
2291         },
2292 };
2293
2294 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2295         .halt_check = BRANCH_HALT_DELAY,
2296         .clkr = {
2297                 .enable_reg = 0x4b000,
2298                 .enable_mask = BIT(16),
2299                 .hw.init = &(const struct clk_init_data){
2300                         .name = "gcc_gpu_gpll0_div_clk_src",
2301                         .parent_hws = (const struct clk_hw*[]){
2302                                 &gcc_gpll0_out_even.clkr.hw,
2303                         },
2304                         .num_parents = 1,
2305                         .flags = CLK_SET_RATE_PARENT,
2306                         .ops = &clk_branch2_ops,
2307                 },
2308         },
2309 };
2310
2311 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2312         .halt_reg = 0x7d010,
2313         .halt_check = BRANCH_HALT_VOTED,
2314         .hwcg_reg = 0x7d010,
2315         .hwcg_bit = 1,
2316         .clkr = {
2317                 .enable_reg = 0x7d010,
2318                 .enable_mask = BIT(0),
2319                 .hw.init = &(const struct clk_init_data){
2320                         .name = "gcc_gpu_memnoc_gfx_clk",
2321                         .ops = &clk_branch2_aon_ops,
2322                 },
2323         },
2324 };
2325
2326 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2327         .halt_reg = 0x7d01c,
2328         .halt_check = BRANCH_HALT_DELAY,
2329         .clkr = {
2330                 .enable_reg = 0x7d01c,
2331                 .enable_mask = BIT(0),
2332                 .hw.init = &(const struct clk_init_data){
2333                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
2334                         .ops = &clk_branch2_aon_ops,
2335                 },
2336         },
2337 };
2338
2339 static struct clk_branch gcc_gpu_tcu_throttle_ahb_clk = {
2340         .halt_reg = 0x7d008,
2341         .halt_check = BRANCH_HALT_VOTED,
2342         .hwcg_reg = 0x7d008,
2343         .hwcg_bit = 1,
2344         .clkr = {
2345                 .enable_reg = 0x7d008,
2346                 .enable_mask = BIT(0),
2347                 .hw.init = &(const struct clk_init_data){
2348                         .name = "gcc_gpu_tcu_throttle_ahb_clk",
2349                         .ops = &clk_branch2_ops,
2350                 },
2351         },
2352 };
2353
2354 static struct clk_branch gcc_gpu_tcu_throttle_clk = {
2355         .halt_reg = 0x7d014,
2356         .halt_check = BRANCH_HALT_VOTED,
2357         .hwcg_reg = 0x7d014,
2358         .hwcg_bit = 1,
2359         .clkr = {
2360                 .enable_reg = 0x7d014,
2361                 .enable_mask = BIT(0),
2362                 .hw.init = &(const struct clk_init_data){
2363                         .name = "gcc_gpu_tcu_throttle_clk",
2364                         .ops = &clk_branch2_ops,
2365                 },
2366         },
2367 };
2368
2369 static struct clk_branch gcc_pcie_0_aux_clk = {
2370         .halt_reg = 0xa9038,
2371         .halt_check = BRANCH_HALT_VOTED,
2372         .clkr = {
2373                 .enable_reg = 0x4b010,
2374                 .enable_mask = BIT(16),
2375                 .hw.init = &(const struct clk_init_data){
2376                         .name = "gcc_pcie_0_aux_clk",
2377                         .parent_hws = (const struct clk_hw*[]){
2378                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
2379                         },
2380                         .num_parents = 1,
2381                         .flags = CLK_SET_RATE_PARENT,
2382                         .ops = &clk_branch2_ops,
2383                 },
2384         },
2385 };
2386
2387 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2388         .halt_reg = 0xa902c,
2389         .halt_check = BRANCH_HALT_VOTED,
2390         .hwcg_reg = 0xa902c,
2391         .hwcg_bit = 1,
2392         .clkr = {
2393                 .enable_reg = 0x4b010,
2394                 .enable_mask = BIT(12),
2395                 .hw.init = &(const struct clk_init_data){
2396                         .name = "gcc_pcie_0_cfg_ahb_clk",
2397                         .ops = &clk_branch2_ops,
2398                 },
2399         },
2400 };
2401
2402 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2403         .halt_reg = 0xa9024,
2404         .halt_check = BRANCH_HALT_VOTED,
2405         .clkr = {
2406                 .enable_reg = 0x4b010,
2407                 .enable_mask = BIT(11),
2408                 .hw.init = &(const struct clk_init_data){
2409                         .name = "gcc_pcie_0_mstr_axi_clk",
2410                         .ops = &clk_branch2_ops,
2411                 },
2412         },
2413 };
2414
2415 static struct clk_branch gcc_pcie_0_phy_aux_clk = {
2416         .halt_reg = 0xa9030,
2417         .halt_check = BRANCH_HALT_VOTED,
2418         .clkr = {
2419                 .enable_reg = 0x4b010,
2420                 .enable_mask = BIT(13),
2421                 .hw.init = &(const struct clk_init_data){
2422                         .name = "gcc_pcie_0_phy_aux_clk",
2423                         .parent_hws = (const struct clk_hw*[]){
2424                                 &gcc_pcie_0_phy_aux_clk_src.clkr.hw,
2425                         },
2426                         .num_parents = 1,
2427                         .flags = CLK_SET_RATE_PARENT,
2428                         .ops = &clk_branch2_ops,
2429                 },
2430         },
2431 };
2432
2433 static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
2434         .halt_reg = 0xa9050,
2435         .halt_check = BRANCH_HALT_VOTED,
2436         .clkr = {
2437                 .enable_reg = 0x4b010,
2438                 .enable_mask = BIT(15),
2439                 .hw.init = &(const struct clk_init_data){
2440                         .name = "gcc_pcie_0_phy_rchng_clk",
2441                         .parent_hws = (const struct clk_hw*[]){
2442                                 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
2443                         },
2444                         .num_parents = 1,
2445                         .flags = CLK_SET_RATE_PARENT,
2446                         .ops = &clk_branch2_ops,
2447                 },
2448         },
2449 };
2450
2451 static struct clk_branch gcc_pcie_0_pipe_clk = {
2452         .halt_reg = 0xa9040,
2453         .halt_check = BRANCH_HALT_SKIP,
2454         .clkr = {
2455                 .enable_reg = 0x4b010,
2456                 .enable_mask = BIT(14),
2457                 .hw.init = &(const struct clk_init_data){
2458                         .name = "gcc_pcie_0_pipe_clk",
2459                         .parent_hws = (const struct clk_hw*[]){
2460                                 &gcc_pcie_0_pipe_clk_src.clkr.hw,
2461                         },
2462                         .num_parents = 1,
2463                         .flags = CLK_SET_RATE_PARENT,
2464                         .ops = &clk_branch2_ops,
2465                 },
2466         },
2467 };
2468
2469 static struct clk_branch gcc_pcie_0_pipediv2_clk = {
2470         .halt_reg = 0xa9048,
2471         .halt_check = BRANCH_HALT_SKIP,
2472         .clkr = {
2473                 .enable_reg = 0x4b018,
2474                 .enable_mask = BIT(22),
2475                 .hw.init = &(const struct clk_init_data){
2476                         .name = "gcc_pcie_0_pipediv2_clk",
2477                         .parent_hws = (const struct clk_hw*[]){
2478                                 &gcc_pcie_0_pipe_div_clk_src.clkr.hw,
2479                         },
2480                         .num_parents = 1,
2481                         .flags = CLK_SET_RATE_PARENT,
2482                         .ops = &clk_branch2_ops,
2483                 },
2484         },
2485 };
2486
2487 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2488         .halt_reg = 0xa901c,
2489         .halt_check = BRANCH_HALT_VOTED,
2490         .clkr = {
2491                 .enable_reg = 0x4b010,
2492                 .enable_mask = BIT(10),
2493                 .hw.init = &(const struct clk_init_data){
2494                         .name = "gcc_pcie_0_slv_axi_clk",
2495                         .ops = &clk_branch2_ops,
2496                 },
2497         },
2498 };
2499
2500 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2501         .halt_reg = 0xa9018,
2502         .halt_check = BRANCH_HALT_VOTED,
2503         .clkr = {
2504                 .enable_reg = 0x4b018,
2505                 .enable_mask = BIT(12),
2506                 .hw.init = &(const struct clk_init_data){
2507                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
2508                         .ops = &clk_branch2_ops,
2509                 },
2510         },
2511 };
2512
2513 static struct clk_branch gcc_pcie_1_aux_clk = {
2514         .halt_reg = 0x77038,
2515         .halt_check = BRANCH_HALT_VOTED,
2516         .clkr = {
2517                 .enable_reg = 0x4b000,
2518                 .enable_mask = BIT(31),
2519                 .hw.init = &(const struct clk_init_data){
2520                         .name = "gcc_pcie_1_aux_clk",
2521                         .parent_hws = (const struct clk_hw*[]){
2522                                 &gcc_pcie_1_aux_clk_src.clkr.hw,
2523                         },
2524                         .num_parents = 1,
2525                         .flags = CLK_SET_RATE_PARENT,
2526                         .ops = &clk_branch2_ops,
2527                 },
2528         },
2529 };
2530
2531 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2532         .halt_reg = 0x7702c,
2533         .halt_check = BRANCH_HALT_VOTED,
2534         .hwcg_reg = 0x7702c,
2535         .hwcg_bit = 1,
2536         .clkr = {
2537                 .enable_reg = 0x4b008,
2538                 .enable_mask = BIT(2),
2539                 .hw.init = &(const struct clk_init_data){
2540                         .name = "gcc_pcie_1_cfg_ahb_clk",
2541                         .ops = &clk_branch2_ops,
2542                 },
2543         },
2544 };
2545
2546 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2547         .halt_reg = 0x77024,
2548         .halt_check = BRANCH_HALT_VOTED,
2549         .clkr = {
2550                 .enable_reg = 0x4b008,
2551                 .enable_mask = BIT(1),
2552                 .hw.init = &(const struct clk_init_data){
2553                         .name = "gcc_pcie_1_mstr_axi_clk",
2554                         .ops = &clk_branch2_ops,
2555                 },
2556         },
2557 };
2558
2559 static struct clk_branch gcc_pcie_1_phy_aux_clk = {
2560         .halt_reg = 0x77030,
2561         .halt_check = BRANCH_HALT_VOTED,
2562         .clkr = {
2563                 .enable_reg = 0x4b008,
2564                 .enable_mask = BIT(3),
2565                 .hw.init = &(const struct clk_init_data){
2566                         .name = "gcc_pcie_1_phy_aux_clk",
2567                         .parent_hws = (const struct clk_hw*[]){
2568                                 &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
2569                         },
2570                         .num_parents = 1,
2571                         .flags = CLK_SET_RATE_PARENT,
2572                         .ops = &clk_branch2_ops,
2573                 },
2574         },
2575 };
2576
2577 static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
2578         .halt_reg = 0x77050,
2579         .halt_check = BRANCH_HALT_VOTED,
2580         .clkr = {
2581                 .enable_reg = 0x4b000,
2582                 .enable_mask = BIT(22),
2583                 .hw.init = &(const struct clk_init_data){
2584                         .name = "gcc_pcie_1_phy_rchng_clk",
2585                         .parent_hws = (const struct clk_hw*[]){
2586                                 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
2587                         },
2588                         .num_parents = 1,
2589                         .flags = CLK_SET_RATE_PARENT,
2590                         .ops = &clk_branch2_ops,
2591                 },
2592         },
2593 };
2594
2595 static struct clk_branch gcc_pcie_1_pipe_clk = {
2596         .halt_reg = 0x77040,
2597         .halt_check = BRANCH_HALT_SKIP,
2598         .clkr = {
2599                 .enable_reg = 0x4b008,
2600                 .enable_mask = BIT(4),
2601                 .hw.init = &(const struct clk_init_data){
2602                         .name = "gcc_pcie_1_pipe_clk",
2603                         .parent_hws = (const struct clk_hw*[]){
2604                                 &gcc_pcie_1_pipe_clk_src.clkr.hw,
2605                         },
2606                         .num_parents = 1,
2607                         .flags = CLK_SET_RATE_PARENT,
2608                         .ops = &clk_branch2_ops,
2609                 },
2610         },
2611 };
2612
2613 static struct clk_branch gcc_pcie_1_pipediv2_clk = {
2614         .halt_reg = 0x77048,
2615         .halt_check = BRANCH_HALT_SKIP,
2616         .clkr = {
2617                 .enable_reg = 0x4b018,
2618                 .enable_mask = BIT(16),
2619                 .hw.init = &(const struct clk_init_data){
2620                         .name = "gcc_pcie_1_pipediv2_clk",
2621                         .parent_hws = (const struct clk_hw*[]){
2622                                 &gcc_pcie_1_pipe_div_clk_src.clkr.hw,
2623                         },
2624                         .num_parents = 1,
2625                         .flags = CLK_SET_RATE_PARENT,
2626                         .ops = &clk_branch2_ops,
2627                 },
2628         },
2629 };
2630
2631 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2632         .halt_reg = 0x7701c,
2633         .halt_check = BRANCH_HALT_VOTED,
2634         .clkr = {
2635                 .enable_reg = 0x4b008,
2636                 .enable_mask = BIT(0),
2637                 .hw.init = &(const struct clk_init_data){
2638                         .name = "gcc_pcie_1_slv_axi_clk",
2639                         .ops = &clk_branch2_ops,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2645         .halt_reg = 0x77018,
2646         .halt_check = BRANCH_HALT_VOTED,
2647         .clkr = {
2648                 .enable_reg = 0x4b008,
2649                 .enable_mask = BIT(5),
2650                 .hw.init = &(const struct clk_init_data){
2651                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
2652                         .ops = &clk_branch2_ops,
2653                 },
2654         },
2655 };
2656
2657 static struct clk_branch gcc_pcie_clkref_en = {
2658         .halt_reg = 0x9746c,
2659         .halt_check = BRANCH_HALT_DELAY,
2660         .clkr = {
2661                 .enable_reg = 0x9746c,
2662                 .enable_mask = BIT(0),
2663                 .hw.init = &(const struct clk_init_data){
2664                         .name = "gcc_pcie_clkref_en",
2665                         .ops = &clk_branch2_ops,
2666                 },
2667         },
2668 };
2669
2670 static struct clk_branch gcc_pcie_throttle_cfg_clk = {
2671         .halt_reg = 0xb2034,
2672         .halt_check = BRANCH_HALT_VOTED,
2673         .clkr = {
2674                 .enable_reg = 0x4b020,
2675                 .enable_mask = BIT(15),
2676                 .hw.init = &(const struct clk_init_data){
2677                         .name = "gcc_pcie_throttle_cfg_clk",
2678                         .ops = &clk_branch2_ops,
2679                 },
2680         },
2681 };
2682
2683 static struct clk_branch gcc_pdm2_clk = {
2684         .halt_reg = 0x3f00c,
2685         .halt_check = BRANCH_HALT,
2686         .clkr = {
2687                 .enable_reg = 0x3f00c,
2688                 .enable_mask = BIT(0),
2689                 .hw.init = &(const struct clk_init_data){
2690                         .name = "gcc_pdm2_clk",
2691                         .parent_hws = (const struct clk_hw*[]){
2692                                 &gcc_pdm2_clk_src.clkr.hw,
2693                         },
2694                         .num_parents = 1,
2695                         .flags = CLK_SET_RATE_PARENT,
2696                         .ops = &clk_branch2_ops,
2697                 },
2698         },
2699 };
2700
2701 static struct clk_branch gcc_pdm_ahb_clk = {
2702         .halt_reg = 0x3f004,
2703         .halt_check = BRANCH_HALT_VOTED,
2704         .hwcg_reg = 0x3f004,
2705         .hwcg_bit = 1,
2706         .clkr = {
2707                 .enable_reg = 0x3f004,
2708                 .enable_mask = BIT(0),
2709                 .hw.init = &(const struct clk_init_data){
2710                         .name = "gcc_pdm_ahb_clk",
2711                         .ops = &clk_branch2_ops,
2712                 },
2713         },
2714 };
2715
2716 static struct clk_branch gcc_pdm_xo4_clk = {
2717         .halt_reg = 0x3f008,
2718         .halt_check = BRANCH_HALT,
2719         .clkr = {
2720                 .enable_reg = 0x3f008,
2721                 .enable_mask = BIT(0),
2722                 .hw.init = &(const struct clk_init_data){
2723                         .name = "gcc_pdm_xo4_clk",
2724                         .ops = &clk_branch2_ops,
2725                 },
2726         },
2727 };
2728
2729 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2730         .halt_reg = 0x32008,
2731         .halt_check = BRANCH_HALT_VOTED,
2732         .hwcg_reg = 0x32008,
2733         .hwcg_bit = 1,
2734         .clkr = {
2735                 .enable_reg = 0x32008,
2736                 .enable_mask = BIT(0),
2737                 .hw.init = &(const struct clk_init_data){
2738                         .name = "gcc_qmip_camera_nrt_ahb_clk",
2739                         .ops = &clk_branch2_ops,
2740                 },
2741         },
2742 };
2743
2744 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2745         .halt_reg = 0x3200c,
2746         .halt_check = BRANCH_HALT_VOTED,
2747         .hwcg_reg = 0x3200c,
2748         .hwcg_bit = 1,
2749         .clkr = {
2750                 .enable_reg = 0x3200c,
2751                 .enable_mask = BIT(0),
2752                 .hw.init = &(const struct clk_init_data){
2753                         .name = "gcc_qmip_camera_rt_ahb_clk",
2754                         .ops = &clk_branch2_ops,
2755                 },
2756         },
2757 };
2758
2759 static struct clk_branch gcc_qmip_disp1_ahb_clk = {
2760         .halt_reg = 0xc7008,
2761         .halt_check = BRANCH_HALT_VOTED,
2762         .hwcg_reg = 0xc7008,
2763         .hwcg_bit = 1,
2764         .clkr = {
2765                 .enable_reg = 0xc7008,
2766                 .enable_mask = BIT(0),
2767                 .hw.init = &(const struct clk_init_data){
2768                         .name = "gcc_qmip_disp1_ahb_clk",
2769                         .ops = &clk_branch2_ops,
2770                 },
2771         },
2772 };
2773
2774 static struct clk_branch gcc_qmip_disp1_rot_ahb_clk = {
2775         .halt_reg = 0xc700c,
2776         .halt_check = BRANCH_HALT_VOTED,
2777         .clkr = {
2778                 .enable_reg = 0xc700c,
2779                 .enable_mask = BIT(0),
2780                 .hw.init = &(const struct clk_init_data){
2781                         .name = "gcc_qmip_disp1_rot_ahb_clk",
2782                         .ops = &clk_branch2_ops,
2783                 },
2784         },
2785 };
2786
2787 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2788         .halt_reg = 0x33008,
2789         .halt_check = BRANCH_HALT_VOTED,
2790         .hwcg_reg = 0x33008,
2791         .hwcg_bit = 1,
2792         .clkr = {
2793                 .enable_reg = 0x33008,
2794                 .enable_mask = BIT(0),
2795                 .hw.init = &(const struct clk_init_data){
2796                         .name = "gcc_qmip_disp_ahb_clk",
2797                         .ops = &clk_branch2_ops,
2798                 },
2799         },
2800 };
2801
2802 static struct clk_branch gcc_qmip_disp_rot_ahb_clk = {
2803         .halt_reg = 0x3300c,
2804         .halt_check = BRANCH_HALT_VOTED,
2805         .clkr = {
2806                 .enable_reg = 0x3300c,
2807                 .enable_mask = BIT(0),
2808                 .hw.init = &(const struct clk_init_data){
2809                         .name = "gcc_qmip_disp_rot_ahb_clk",
2810                         .ops = &clk_branch2_ops,
2811                 },
2812         },
2813 };
2814
2815 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2816         .halt_reg = 0x34008,
2817         .halt_check = BRANCH_HALT_VOTED,
2818         .hwcg_reg = 0x34008,
2819         .hwcg_bit = 1,
2820         .clkr = {
2821                 .enable_reg = 0x34008,
2822                 .enable_mask = BIT(0),
2823                 .hw.init = &(const struct clk_init_data){
2824                         .name = "gcc_qmip_video_cvp_ahb_clk",
2825                         .ops = &clk_branch2_ops,
2826                 },
2827         },
2828 };
2829
2830 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2831         .halt_reg = 0x3400c,
2832         .halt_check = BRANCH_HALT_VOTED,
2833         .hwcg_reg = 0x3400c,
2834         .hwcg_bit = 1,
2835         .clkr = {
2836                 .enable_reg = 0x3400c,
2837                 .enable_mask = BIT(0),
2838                 .hw.init = &(const struct clk_init_data){
2839                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2840                         .ops = &clk_branch2_ops,
2841                 },
2842         },
2843 };
2844
2845 static struct clk_branch gcc_qmip_video_vcpu_ahb_clk = {
2846         .halt_reg = 0x34010,
2847         .halt_check = BRANCH_HALT_VOTED,
2848         .hwcg_reg = 0x34010,
2849         .hwcg_bit = 1,
2850         .clkr = {
2851                 .enable_reg = 0x34010,
2852                 .enable_mask = BIT(0),
2853                 .hw.init = &(const struct clk_init_data){
2854                         .name = "gcc_qmip_video_vcpu_ahb_clk",
2855                         .ops = &clk_branch2_ops,
2856                 },
2857         },
2858 };
2859
2860 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2861         .halt_reg = 0x23018,
2862         .halt_check = BRANCH_HALT_VOTED,
2863         .clkr = {
2864                 .enable_reg = 0x4b008,
2865                 .enable_mask = BIT(9),
2866                 .hw.init = &(const struct clk_init_data){
2867                         .name = "gcc_qupv3_wrap0_core_2x_clk",
2868                         .ops = &clk_branch2_ops,
2869                 },
2870         },
2871 };
2872
2873 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2874         .halt_reg = 0x2300c,
2875         .halt_check = BRANCH_HALT_VOTED,
2876         .clkr = {
2877                 .enable_reg = 0x4b008,
2878                 .enable_mask = BIT(8),
2879                 .hw.init = &(const struct clk_init_data){
2880                         .name = "gcc_qupv3_wrap0_core_clk",
2881                         .ops = &clk_branch2_ops,
2882                 },
2883         },
2884 };
2885
2886 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2887         .halt_reg = 0x2314c,
2888         .halt_check = BRANCH_HALT_VOTED,
2889         .clkr = {
2890                 .enable_reg = 0x4b008,
2891                 .enable_mask = BIT(10),
2892                 .hw.init = &(const struct clk_init_data){
2893                         .name = "gcc_qupv3_wrap0_s0_clk",
2894                         .parent_hws = (const struct clk_hw*[]){
2895                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2896                         },
2897                         .num_parents = 1,
2898                         .flags = CLK_SET_RATE_PARENT,
2899                         .ops = &clk_branch2_ops,
2900                 },
2901         },
2902 };
2903
2904 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2905         .halt_reg = 0x23280,
2906         .halt_check = BRANCH_HALT_VOTED,
2907         .clkr = {
2908                 .enable_reg = 0x4b008,
2909                 .enable_mask = BIT(11),
2910                 .hw.init = &(const struct clk_init_data){
2911                         .name = "gcc_qupv3_wrap0_s1_clk",
2912                         .parent_hws = (const struct clk_hw*[]){
2913                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2914                         },
2915                         .num_parents = 1,
2916                         .flags = CLK_SET_RATE_PARENT,
2917                         .ops = &clk_branch2_ops,
2918                 },
2919         },
2920 };
2921
2922 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2923         .halt_reg = 0x233b4,
2924         .halt_check = BRANCH_HALT_VOTED,
2925         .clkr = {
2926                 .enable_reg = 0x4b008,
2927                 .enable_mask = BIT(12),
2928                 .hw.init = &(const struct clk_init_data){
2929                         .name = "gcc_qupv3_wrap0_s2_clk",
2930                         .parent_hws = (const struct clk_hw*[]){
2931                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2932                         },
2933                         .num_parents = 1,
2934                         .flags = CLK_SET_RATE_PARENT,
2935                         .ops = &clk_branch2_ops,
2936                 },
2937         },
2938 };
2939
2940 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2941         .halt_reg = 0x234e8,
2942         .halt_check = BRANCH_HALT_VOTED,
2943         .clkr = {
2944                 .enable_reg = 0x4b008,
2945                 .enable_mask = BIT(13),
2946                 .hw.init = &(const struct clk_init_data){
2947                         .name = "gcc_qupv3_wrap0_s3_clk",
2948                         .parent_hws = (const struct clk_hw*[]){
2949                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2950                         },
2951                         .num_parents = 1,
2952                         .flags = CLK_SET_RATE_PARENT,
2953                         .ops = &clk_branch2_ops,
2954                 },
2955         },
2956 };
2957
2958 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2959         .halt_reg = 0x2361c,
2960         .halt_check = BRANCH_HALT_VOTED,
2961         .clkr = {
2962                 .enable_reg = 0x4b008,
2963                 .enable_mask = BIT(14),
2964                 .hw.init = &(const struct clk_init_data){
2965                         .name = "gcc_qupv3_wrap0_s4_clk",
2966                         .parent_hws = (const struct clk_hw*[]){
2967                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2968                         },
2969                         .num_parents = 1,
2970                         .flags = CLK_SET_RATE_PARENT,
2971                         .ops = &clk_branch2_ops,
2972                 },
2973         },
2974 };
2975
2976 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2977         .halt_reg = 0x23750,
2978         .halt_check = BRANCH_HALT_VOTED,
2979         .clkr = {
2980                 .enable_reg = 0x4b008,
2981                 .enable_mask = BIT(15),
2982                 .hw.init = &(const struct clk_init_data){
2983                         .name = "gcc_qupv3_wrap0_s5_clk",
2984                         .parent_hws = (const struct clk_hw*[]){
2985                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2986                         },
2987                         .num_parents = 1,
2988                         .flags = CLK_SET_RATE_PARENT,
2989                         .ops = &clk_branch2_ops,
2990                 },
2991         },
2992 };
2993
2994 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2995         .halt_reg = 0x23884,
2996         .halt_check = BRANCH_HALT_VOTED,
2997         .clkr = {
2998                 .enable_reg = 0x4b008,
2999                 .enable_mask = BIT(16),
3000                 .hw.init = &(const struct clk_init_data){
3001                         .name = "gcc_qupv3_wrap0_s6_clk",
3002                         .parent_hws = (const struct clk_hw*[]){
3003                                 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
3004                         },
3005                         .num_parents = 1,
3006                         .flags = CLK_SET_RATE_PARENT,
3007                         .ops = &clk_branch2_ops,
3008                 },
3009         },
3010 };
3011
3012 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
3013         .halt_reg = 0x24018,
3014         .halt_check = BRANCH_HALT_VOTED,
3015         .clkr = {
3016                 .enable_reg = 0x4b008,
3017                 .enable_mask = BIT(18),
3018                 .hw.init = &(const struct clk_init_data){
3019                         .name = "gcc_qupv3_wrap1_core_2x_clk",
3020                         .ops = &clk_branch2_ops,
3021                 },
3022         },
3023 };
3024
3025 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
3026         .halt_reg = 0x2400c,
3027         .halt_check = BRANCH_HALT_VOTED,
3028         .clkr = {
3029                 .enable_reg = 0x4b008,
3030                 .enable_mask = BIT(19),
3031                 .hw.init = &(const struct clk_init_data){
3032                         .name = "gcc_qupv3_wrap1_core_clk",
3033                         .ops = &clk_branch2_ops,
3034                 },
3035         },
3036 };
3037
3038 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
3039         .halt_reg = 0x2414c,
3040         .halt_check = BRANCH_HALT_VOTED,
3041         .clkr = {
3042                 .enable_reg = 0x4b008,
3043                 .enable_mask = BIT(22),
3044                 .hw.init = &(const struct clk_init_data){
3045                         .name = "gcc_qupv3_wrap1_s0_clk",
3046                         .parent_hws = (const struct clk_hw*[]){
3047                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
3048                         },
3049                         .num_parents = 1,
3050                         .flags = CLK_SET_RATE_PARENT,
3051                         .ops = &clk_branch2_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
3057         .halt_reg = 0x24280,
3058         .halt_check = BRANCH_HALT_VOTED,
3059         .clkr = {
3060                 .enable_reg = 0x4b008,
3061                 .enable_mask = BIT(23),
3062                 .hw.init = &(const struct clk_init_data){
3063                         .name = "gcc_qupv3_wrap1_s1_clk",
3064                         .parent_hws = (const struct clk_hw*[]){
3065                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
3066                         },
3067                         .num_parents = 1,
3068                         .flags = CLK_SET_RATE_PARENT,
3069                         .ops = &clk_branch2_ops,
3070                 },
3071         },
3072 };
3073
3074 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
3075         .halt_reg = 0x243b4,
3076         .halt_check = BRANCH_HALT_VOTED,
3077         .clkr = {
3078                 .enable_reg = 0x4b008,
3079                 .enable_mask = BIT(24),
3080                 .hw.init = &(const struct clk_init_data){
3081                         .name = "gcc_qupv3_wrap1_s2_clk",
3082                         .parent_hws = (const struct clk_hw*[]){
3083                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
3084                         },
3085                         .num_parents = 1,
3086                         .flags = CLK_SET_RATE_PARENT,
3087                         .ops = &clk_branch2_ops,
3088                 },
3089         },
3090 };
3091
3092 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
3093         .halt_reg = 0x244e8,
3094         .halt_check = BRANCH_HALT_VOTED,
3095         .clkr = {
3096                 .enable_reg = 0x4b008,
3097                 .enable_mask = BIT(25),
3098                 .hw.init = &(const struct clk_init_data){
3099                         .name = "gcc_qupv3_wrap1_s3_clk",
3100                         .parent_hws = (const struct clk_hw*[]){
3101                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
3102                         },
3103                         .num_parents = 1,
3104                         .flags = CLK_SET_RATE_PARENT,
3105                         .ops = &clk_branch2_ops,
3106                 },
3107         },
3108 };
3109
3110 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
3111         .halt_reg = 0x2461c,
3112         .halt_check = BRANCH_HALT_VOTED,
3113         .clkr = {
3114                 .enable_reg = 0x4b008,
3115                 .enable_mask = BIT(26),
3116                 .hw.init = &(const struct clk_init_data){
3117                         .name = "gcc_qupv3_wrap1_s4_clk",
3118                         .parent_hws = (const struct clk_hw*[]){
3119                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
3120                         },
3121                         .num_parents = 1,
3122                         .flags = CLK_SET_RATE_PARENT,
3123                         .ops = &clk_branch2_ops,
3124                 },
3125         },
3126 };
3127
3128 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
3129         .halt_reg = 0x24750,
3130         .halt_check = BRANCH_HALT_VOTED,
3131         .clkr = {
3132                 .enable_reg = 0x4b008,
3133                 .enable_mask = BIT(27),
3134                 .hw.init = &(const struct clk_init_data){
3135                         .name = "gcc_qupv3_wrap1_s5_clk",
3136                         .parent_hws = (const struct clk_hw*[]){
3137                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
3138                         },
3139                         .num_parents = 1,
3140                         .flags = CLK_SET_RATE_PARENT,
3141                         .ops = &clk_branch2_ops,
3142                 },
3143         },
3144 };
3145
3146 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
3147         .halt_reg = 0x24884,
3148         .halt_check = BRANCH_HALT_VOTED,
3149         .clkr = {
3150                 .enable_reg = 0x4b018,
3151                 .enable_mask = BIT(27),
3152                 .hw.init = &(const struct clk_init_data){
3153                         .name = "gcc_qupv3_wrap1_s6_clk",
3154                         .parent_hws = (const struct clk_hw*[]){
3155                                 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
3156                         },
3157                         .num_parents = 1,
3158                         .flags = CLK_SET_RATE_PARENT,
3159                         .ops = &clk_branch2_ops,
3160                 },
3161         },
3162 };
3163
3164 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
3165         .halt_reg = 0x2a018,
3166         .halt_check = BRANCH_HALT_VOTED,
3167         .clkr = {
3168                 .enable_reg = 0x4b010,
3169                 .enable_mask = BIT(3),
3170                 .hw.init = &(const struct clk_init_data){
3171                         .name = "gcc_qupv3_wrap2_core_2x_clk",
3172                         .ops = &clk_branch2_ops,
3173                 },
3174         },
3175 };
3176
3177 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
3178         .halt_reg = 0x2a00c,
3179         .halt_check = BRANCH_HALT_VOTED,
3180         .clkr = {
3181                 .enable_reg = 0x4b010,
3182                 .enable_mask = BIT(0),
3183                 .hw.init = &(const struct clk_init_data){
3184                         .name = "gcc_qupv3_wrap2_core_clk",
3185                         .ops = &clk_branch2_ops,
3186                 },
3187         },
3188 };
3189
3190 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
3191         .halt_reg = 0x2a14c,
3192         .halt_check = BRANCH_HALT_VOTED,
3193         .clkr = {
3194                 .enable_reg = 0x4b010,
3195                 .enable_mask = BIT(4),
3196                 .hw.init = &(const struct clk_init_data){
3197                         .name = "gcc_qupv3_wrap2_s0_clk",
3198                         .parent_hws = (const struct clk_hw*[]){
3199                                 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
3200                         },
3201                         .num_parents = 1,
3202                         .flags = CLK_SET_RATE_PARENT,
3203                         .ops = &clk_branch2_ops,
3204                 },
3205         },
3206 };
3207
3208 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
3209         .halt_reg = 0x2a280,
3210         .halt_check = BRANCH_HALT_VOTED,
3211         .clkr = {
3212                 .enable_reg = 0x4b010,
3213                 .enable_mask = BIT(5),
3214                 .hw.init = &(const struct clk_init_data){
3215                         .name = "gcc_qupv3_wrap2_s1_clk",
3216                         .parent_hws = (const struct clk_hw*[]){
3217                                 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
3218                         },
3219                         .num_parents = 1,
3220                         .flags = CLK_SET_RATE_PARENT,
3221                         .ops = &clk_branch2_ops,
3222                 },
3223         },
3224 };
3225
3226 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
3227         .halt_reg = 0x2a3b4,
3228         .halt_check = BRANCH_HALT_VOTED,
3229         .clkr = {
3230                 .enable_reg = 0x4b010,
3231                 .enable_mask = BIT(6),
3232                 .hw.init = &(const struct clk_init_data){
3233                         .name = "gcc_qupv3_wrap2_s2_clk",
3234                         .parent_hws = (const struct clk_hw*[]){
3235                                 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
3236                         },
3237                         .num_parents = 1,
3238                         .flags = CLK_SET_RATE_PARENT,
3239                         .ops = &clk_branch2_ops,
3240                 },
3241         },
3242 };
3243
3244 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
3245         .halt_reg = 0x2a4e8,
3246         .halt_check = BRANCH_HALT_VOTED,
3247         .clkr = {
3248                 .enable_reg = 0x4b010,
3249                 .enable_mask = BIT(7),
3250                 .hw.init = &(const struct clk_init_data){
3251                         .name = "gcc_qupv3_wrap2_s3_clk",
3252                         .parent_hws = (const struct clk_hw*[]){
3253                                 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
3254                         },
3255                         .num_parents = 1,
3256                         .flags = CLK_SET_RATE_PARENT,
3257                         .ops = &clk_branch2_ops,
3258                 },
3259         },
3260 };
3261
3262 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
3263         .halt_reg = 0x2a61c,
3264         .halt_check = BRANCH_HALT_VOTED,
3265         .clkr = {
3266                 .enable_reg = 0x4b010,
3267                 .enable_mask = BIT(8),
3268                 .hw.init = &(const struct clk_init_data){
3269                         .name = "gcc_qupv3_wrap2_s4_clk",
3270                         .parent_hws = (const struct clk_hw*[]){
3271                                 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
3272                         },
3273                         .num_parents = 1,
3274                         .flags = CLK_SET_RATE_PARENT,
3275                         .ops = &clk_branch2_ops,
3276                 },
3277         },
3278 };
3279
3280 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
3281         .halt_reg = 0x2a750,
3282         .halt_check = BRANCH_HALT_VOTED,
3283         .clkr = {
3284                 .enable_reg = 0x4b010,
3285                 .enable_mask = BIT(9),
3286                 .hw.init = &(const struct clk_init_data){
3287                         .name = "gcc_qupv3_wrap2_s5_clk",
3288                         .parent_hws = (const struct clk_hw*[]){
3289                                 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
3290                         },
3291                         .num_parents = 1,
3292                         .flags = CLK_SET_RATE_PARENT,
3293                         .ops = &clk_branch2_ops,
3294                 },
3295         },
3296 };
3297
3298 static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
3299         .halt_reg = 0x2a884,
3300         .halt_check = BRANCH_HALT_VOTED,
3301         .clkr = {
3302                 .enable_reg = 0x4b018,
3303                 .enable_mask = BIT(29),
3304                 .hw.init = &(const struct clk_init_data){
3305                         .name = "gcc_qupv3_wrap2_s6_clk",
3306                         .parent_hws = (const struct clk_hw*[]){
3307                                 &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
3308                         },
3309                         .num_parents = 1,
3310                         .flags = CLK_SET_RATE_PARENT,
3311                         .ops = &clk_branch2_ops,
3312                 },
3313         },
3314 };
3315
3316 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = {
3317         .halt_reg = 0xc4018,
3318         .halt_check = BRANCH_HALT_VOTED,
3319         .clkr = {
3320                 .enable_reg = 0x4b000,
3321                 .enable_mask = BIT(24),
3322                 .hw.init = &(const struct clk_init_data){
3323                         .name = "gcc_qupv3_wrap3_core_2x_clk",
3324                         .ops = &clk_branch2_ops,
3325                 },
3326         },
3327 };
3328
3329 static struct clk_branch gcc_qupv3_wrap3_core_clk = {
3330         .halt_reg = 0xc400c,
3331         .halt_check = BRANCH_HALT_VOTED,
3332         .clkr = {
3333                 .enable_reg = 0x4b000,
3334                 .enable_mask = BIT(23),
3335                 .hw.init = &(const struct clk_init_data){
3336                         .name = "gcc_qupv3_wrap3_core_clk",
3337                         .ops = &clk_branch2_ops,
3338                 },
3339         },
3340 };
3341
3342 static struct clk_branch gcc_qupv3_wrap3_qspi_clk = {
3343         .halt_reg = 0xc4280,
3344         .halt_check = BRANCH_HALT_VOTED,
3345         .clkr = {
3346                 .enable_reg = 0x4b000,
3347                 .enable_mask = BIT(26),
3348                 .hw.init = &(const struct clk_init_data){
3349                         .name = "gcc_qupv3_wrap3_qspi_clk",
3350                         .parent_hws = (const struct clk_hw*[]){
3351                                 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw,
3352                         },
3353                         .num_parents = 1,
3354                         .flags = CLK_SET_RATE_PARENT,
3355                         .ops = &clk_branch2_ops,
3356                 },
3357         },
3358 };
3359
3360 static struct clk_branch gcc_qupv3_wrap3_s0_clk = {
3361         .halt_reg = 0xc414c,
3362         .halt_check = BRANCH_HALT_VOTED,
3363         .clkr = {
3364                 .enable_reg = 0x4b000,
3365                 .enable_mask = BIT(25),
3366                 .hw.init = &(const struct clk_init_data){
3367                         .name = "gcc_qupv3_wrap3_s0_clk",
3368                         .parent_hws = (const struct clk_hw*[]){
3369                                 &gcc_qupv3_wrap3_s0_div_clk_src.clkr.hw,
3370                         },
3371                         .num_parents = 1,
3372                         .flags = CLK_SET_RATE_PARENT,
3373                         .ops = &clk_branch2_ops,
3374                 },
3375         },
3376 };
3377
3378 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3379         .halt_reg = 0x23004,
3380         .halt_check = BRANCH_HALT_VOTED,
3381         .hwcg_reg = 0x23004,
3382         .hwcg_bit = 1,
3383         .clkr = {
3384                 .enable_reg = 0x4b008,
3385                 .enable_mask = BIT(6),
3386                 .hw.init = &(const struct clk_init_data){
3387                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
3388                         .ops = &clk_branch2_ops,
3389                 },
3390         },
3391 };
3392
3393 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3394         .halt_reg = 0x23008,
3395         .halt_check = BRANCH_HALT_VOTED,
3396         .hwcg_reg = 0x23008,
3397         .hwcg_bit = 1,
3398         .clkr = {
3399                 .enable_reg = 0x4b008,
3400                 .enable_mask = BIT(7),
3401                 .hw.init = &(const struct clk_init_data){
3402                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
3403                         .ops = &clk_branch2_ops,
3404                 },
3405         },
3406 };
3407
3408 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3409         .halt_reg = 0x24004,
3410         .halt_check = BRANCH_HALT_VOTED,
3411         .hwcg_reg = 0x24004,
3412         .hwcg_bit = 1,
3413         .clkr = {
3414                 .enable_reg = 0x4b008,
3415                 .enable_mask = BIT(20),
3416                 .hw.init = &(const struct clk_init_data){
3417                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
3418                         .ops = &clk_branch2_ops,
3419                 },
3420         },
3421 };
3422
3423 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3424         .halt_reg = 0x24008,
3425         .halt_check = BRANCH_HALT_VOTED,
3426         .hwcg_reg = 0x24008,
3427         .hwcg_bit = 1,
3428         .clkr = {
3429                 .enable_reg = 0x4b008,
3430                 .enable_mask = BIT(21),
3431                 .hw.init = &(const struct clk_init_data){
3432                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
3433                         .ops = &clk_branch2_ops,
3434                 },
3435         },
3436 };
3437
3438 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
3439         .halt_reg = 0x2a004,
3440         .halt_check = BRANCH_HALT_VOTED,
3441         .hwcg_reg = 0x2a004,
3442         .hwcg_bit = 1,
3443         .clkr = {
3444                 .enable_reg = 0x4b010,
3445                 .enable_mask = BIT(2),
3446                 .hw.init = &(const struct clk_init_data){
3447                         .name = "gcc_qupv3_wrap_2_m_ahb_clk",
3448                         .ops = &clk_branch2_ops,
3449                 },
3450         },
3451 };
3452
3453 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
3454         .halt_reg = 0x2a008,
3455         .halt_check = BRANCH_HALT_VOTED,
3456         .hwcg_reg = 0x2a008,
3457         .hwcg_bit = 1,
3458         .clkr = {
3459                 .enable_reg = 0x4b010,
3460                 .enable_mask = BIT(1),
3461                 .hw.init = &(const struct clk_init_data){
3462                         .name = "gcc_qupv3_wrap_2_s_ahb_clk",
3463                         .ops = &clk_branch2_ops,
3464                 },
3465         },
3466 };
3467
3468 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = {
3469         .halt_reg = 0xc4004,
3470         .halt_check = BRANCH_HALT_VOTED,
3471         .hwcg_reg = 0xc4004,
3472         .hwcg_bit = 1,
3473         .clkr = {
3474                 .enable_reg = 0x4b000,
3475                 .enable_mask = BIT(27),
3476                 .hw.init = &(const struct clk_init_data){
3477                         .name = "gcc_qupv3_wrap_3_m_ahb_clk",
3478                         .ops = &clk_branch2_ops,
3479                 },
3480         },
3481 };
3482
3483 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = {
3484         .halt_reg = 0xc4008,
3485         .halt_check = BRANCH_HALT_VOTED,
3486         .hwcg_reg = 0xc4008,
3487         .hwcg_bit = 1,
3488         .clkr = {
3489                 .enable_reg = 0x4b000,
3490                 .enable_mask = BIT(20),
3491                 .hw.init = &(const struct clk_init_data){
3492                         .name = "gcc_qupv3_wrap_3_s_ahb_clk",
3493                         .ops = &clk_branch2_ops,
3494                 },
3495         },
3496 };
3497
3498 static struct clk_branch gcc_sdcc1_ahb_clk = {
3499         .halt_reg = 0x2000c,
3500         .halt_check = BRANCH_HALT,
3501         .clkr = {
3502                 .enable_reg = 0x2000c,
3503                 .enable_mask = BIT(0),
3504                 .hw.init = &(const struct clk_init_data){
3505                         .name = "gcc_sdcc1_ahb_clk",
3506                         .ops = &clk_branch2_ops,
3507                 },
3508         },
3509 };
3510
3511 static struct clk_branch gcc_sdcc1_apps_clk = {
3512         .halt_reg = 0x20004,
3513         .halt_check = BRANCH_HALT,
3514         .clkr = {
3515                 .enable_reg = 0x20004,
3516                 .enable_mask = BIT(0),
3517                 .hw.init = &(const struct clk_init_data){
3518                         .name = "gcc_sdcc1_apps_clk",
3519                         .parent_hws = (const struct clk_hw*[]){
3520                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
3521                         },
3522                         .num_parents = 1,
3523                         .flags = CLK_SET_RATE_PARENT,
3524                         .ops = &clk_branch2_ops,
3525                 },
3526         },
3527 };
3528
3529 static struct clk_branch gcc_sdcc1_ice_core_clk = {
3530         .halt_reg = 0x20044,
3531         .halt_check = BRANCH_HALT_VOTED,
3532         .hwcg_reg = 0x20044,
3533         .hwcg_bit = 1,
3534         .clkr = {
3535                 .enable_reg = 0x20044,
3536                 .enable_mask = BIT(0),
3537                 .hw.init = &(const struct clk_init_data){
3538                         .name = "gcc_sdcc1_ice_core_clk",
3539                         .parent_hws = (const struct clk_hw*[]){
3540                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
3541                         },
3542                         .num_parents = 1,
3543                         .flags = CLK_SET_RATE_PARENT,
3544                         .ops = &clk_branch2_ops,
3545                 },
3546         },
3547 };
3548
3549 static struct clk_branch gcc_sgmi_clkref_en = {
3550         .halt_reg = 0x9c034,
3551         .halt_check = BRANCH_HALT_DELAY,
3552         .clkr = {
3553                 .enable_reg = 0x9c034,
3554                 .enable_mask = BIT(0),
3555                 .hw.init = &(const struct clk_init_data){
3556                         .name = "gcc_sgmi_clkref_en",
3557                         .ops = &clk_branch2_ops,
3558                 },
3559         },
3560 };
3561
3562 static struct clk_branch gcc_tscss_ahb_clk = {
3563         .halt_reg = 0x21024,
3564         .halt_check = BRANCH_HALT,
3565         .clkr = {
3566                 .enable_reg = 0x21024,
3567                 .enable_mask = BIT(0),
3568                 .hw.init = &(const struct clk_init_data){
3569                         .name = "gcc_tscss_ahb_clk",
3570                         .ops = &clk_branch2_ops,
3571                 },
3572         },
3573 };
3574
3575 static struct clk_branch gcc_tscss_etu_clk = {
3576         .halt_reg = 0x21020,
3577         .halt_check = BRANCH_HALT,
3578         .clkr = {
3579                 .enable_reg = 0x21020,
3580                 .enable_mask = BIT(0),
3581                 .hw.init = &(const struct clk_init_data){
3582                         .name = "gcc_tscss_etu_clk",
3583                         .ops = &clk_branch2_ops,
3584                 },
3585         },
3586 };
3587
3588 static struct clk_branch gcc_tscss_global_cntr_clk = {
3589         .halt_reg = 0x21004,
3590         .halt_check = BRANCH_HALT_VOTED,
3591         .clkr = {
3592                 .enable_reg = 0x21004,
3593                 .enable_mask = BIT(0),
3594                 .hw.init = &(const struct clk_init_data){
3595                         .name = "gcc_tscss_global_cntr_clk",
3596                         .parent_hws = (const struct clk_hw*[]){
3597                                 &gcc_tscss_cntr_clk_src.clkr.hw,
3598                         },
3599                         .num_parents = 1,
3600                         .flags = CLK_SET_RATE_PARENT,
3601                         .ops = &clk_branch2_ops,
3602                 },
3603         },
3604 };
3605
3606 static struct clk_branch gcc_ufs_card_ahb_clk = {
3607         .halt_reg = 0x81020,
3608         .halt_check = BRANCH_HALT_VOTED,
3609         .hwcg_reg = 0x81020,
3610         .hwcg_bit = 1,
3611         .clkr = {
3612                 .enable_reg = 0x81020,
3613                 .enable_mask = BIT(0),
3614                 .hw.init = &(const struct clk_init_data){
3615                         .name = "gcc_ufs_card_ahb_clk",
3616                         .ops = &clk_branch2_ops,
3617                 },
3618         },
3619 };
3620
3621 static struct clk_branch gcc_ufs_card_axi_clk = {
3622         .halt_reg = 0x81018,
3623         .halt_check = BRANCH_HALT_VOTED,
3624         .hwcg_reg = 0x81018,
3625         .hwcg_bit = 1,
3626         .clkr = {
3627                 .enable_reg = 0x81018,
3628                 .enable_mask = BIT(0),
3629                 .hw.init = &(const struct clk_init_data){
3630                         .name = "gcc_ufs_card_axi_clk",
3631                         .parent_hws = (const struct clk_hw*[]){
3632                                 &gcc_ufs_card_axi_clk_src.clkr.hw,
3633                         },
3634                         .num_parents = 1,
3635                         .flags = CLK_SET_RATE_PARENT,
3636                         .ops = &clk_branch2_ops,
3637                 },
3638         },
3639 };
3640
3641 static struct clk_branch gcc_ufs_card_ice_core_clk = {
3642         .halt_reg = 0x8106c,
3643         .halt_check = BRANCH_HALT_VOTED,
3644         .hwcg_reg = 0x8106c,
3645         .hwcg_bit = 1,
3646         .clkr = {
3647                 .enable_reg = 0x8106c,
3648                 .enable_mask = BIT(0),
3649                 .hw.init = &(const struct clk_init_data){
3650                         .name = "gcc_ufs_card_ice_core_clk",
3651                         .parent_hws = (const struct clk_hw*[]){
3652                                 &gcc_ufs_card_ice_core_clk_src.clkr.hw,
3653                         },
3654                         .num_parents = 1,
3655                         .flags = CLK_SET_RATE_PARENT,
3656                         .ops = &clk_branch2_ops,
3657                 },
3658         },
3659 };
3660
3661 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
3662         .halt_reg = 0x810a4,
3663         .halt_check = BRANCH_HALT_VOTED,
3664         .hwcg_reg = 0x810a4,
3665         .hwcg_bit = 1,
3666         .clkr = {
3667                 .enable_reg = 0x810a4,
3668                 .enable_mask = BIT(0),
3669                 .hw.init = &(const struct clk_init_data){
3670                         .name = "gcc_ufs_card_phy_aux_clk",
3671                         .parent_hws = (const struct clk_hw*[]){
3672                                 &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
3673                         },
3674                         .num_parents = 1,
3675                         .flags = CLK_SET_RATE_PARENT,
3676                         .ops = &clk_branch2_ops,
3677                 },
3678         },
3679 };
3680
3681 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
3682         .halt_reg = 0x81028,
3683         .halt_check = BRANCH_HALT_DELAY,
3684         .clkr = {
3685                 .enable_reg = 0x81028,
3686                 .enable_mask = BIT(0),
3687                 .hw.init = &(const struct clk_init_data){
3688                         .name = "gcc_ufs_card_rx_symbol_0_clk",
3689                         .parent_hws = (const struct clk_hw*[]){
3690                                 &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
3691                         },
3692                         .num_parents = 1,
3693                         .flags = CLK_SET_RATE_PARENT,
3694                         .ops = &clk_branch2_ops,
3695                 },
3696         },
3697 };
3698
3699 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
3700         .halt_reg = 0x810c0,
3701         .halt_check = BRANCH_HALT_DELAY,
3702         .clkr = {
3703                 .enable_reg = 0x810c0,
3704                 .enable_mask = BIT(0),
3705                 .hw.init = &(const struct clk_init_data){
3706                         .name = "gcc_ufs_card_rx_symbol_1_clk",
3707                         .parent_hws = (const struct clk_hw*[]){
3708                                 &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
3709                         },
3710                         .num_parents = 1,
3711                         .flags = CLK_SET_RATE_PARENT,
3712                         .ops = &clk_branch2_ops,
3713                 },
3714         },
3715 };
3716
3717 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
3718         .halt_reg = 0x81024,
3719         .halt_check = BRANCH_HALT_DELAY,
3720         .clkr = {
3721                 .enable_reg = 0x81024,
3722                 .enable_mask = BIT(0),
3723                 .hw.init = &(const struct clk_init_data){
3724                         .name = "gcc_ufs_card_tx_symbol_0_clk",
3725                         .parent_hws = (const struct clk_hw*[]){
3726                                 &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
3727                         },
3728                         .num_parents = 1,
3729                         .flags = CLK_SET_RATE_PARENT,
3730                         .ops = &clk_branch2_ops,
3731                 },
3732         },
3733 };
3734
3735 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
3736         .halt_reg = 0x81064,
3737         .halt_check = BRANCH_HALT_VOTED,
3738         .hwcg_reg = 0x81064,
3739         .hwcg_bit = 1,
3740         .clkr = {
3741                 .enable_reg = 0x81064,
3742                 .enable_mask = BIT(0),
3743                 .hw.init = &(const struct clk_init_data){
3744                         .name = "gcc_ufs_card_unipro_core_clk",
3745                         .parent_hws = (const struct clk_hw*[]){
3746                                 &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
3747                         },
3748                         .num_parents = 1,
3749                         .flags = CLK_SET_RATE_PARENT,
3750                         .ops = &clk_branch2_ops,
3751                 },
3752         },
3753 };
3754
3755 static struct clk_branch gcc_ufs_phy_ahb_clk = {
3756         .halt_reg = 0x83020,
3757         .halt_check = BRANCH_HALT_VOTED,
3758         .hwcg_reg = 0x83020,
3759         .hwcg_bit = 1,
3760         .clkr = {
3761                 .enable_reg = 0x83020,
3762                 .enable_mask = BIT(0),
3763                 .hw.init = &(const struct clk_init_data){
3764                         .name = "gcc_ufs_phy_ahb_clk",
3765                         .ops = &clk_branch2_ops,
3766                 },
3767         },
3768 };
3769
3770 static struct clk_branch gcc_ufs_phy_axi_clk = {
3771         .halt_reg = 0x83018,
3772         .halt_check = BRANCH_HALT_VOTED,
3773         .hwcg_reg = 0x83018,
3774         .hwcg_bit = 1,
3775         .clkr = {
3776                 .enable_reg = 0x83018,
3777                 .enable_mask = BIT(0),
3778                 .hw.init = &(const struct clk_init_data){
3779                         .name = "gcc_ufs_phy_axi_clk",
3780                         .parent_hws = (const struct clk_hw*[]){
3781                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
3782                         },
3783                         .num_parents = 1,
3784                         .flags = CLK_SET_RATE_PARENT,
3785                         .ops = &clk_branch2_ops,
3786                 },
3787         },
3788 };
3789
3790 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3791         .halt_reg = 0x8306c,
3792         .halt_check = BRANCH_HALT_VOTED,
3793         .hwcg_reg = 0x8306c,
3794         .hwcg_bit = 1,
3795         .clkr = {
3796                 .enable_reg = 0x8306c,
3797                 .enable_mask = BIT(0),
3798                 .hw.init = &(const struct clk_init_data){
3799                         .name = "gcc_ufs_phy_ice_core_clk",
3800                         .parent_hws = (const struct clk_hw*[]){
3801                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3802                         },
3803                         .num_parents = 1,
3804                         .flags = CLK_SET_RATE_PARENT,
3805                         .ops = &clk_branch2_ops,
3806                 },
3807         },
3808 };
3809
3810 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3811         .halt_reg = 0x830a4,
3812         .halt_check = BRANCH_HALT_VOTED,
3813         .hwcg_reg = 0x830a4,
3814         .hwcg_bit = 1,
3815         .clkr = {
3816                 .enable_reg = 0x830a4,
3817                 .enable_mask = BIT(0),
3818                 .hw.init = &(const struct clk_init_data){
3819                         .name = "gcc_ufs_phy_phy_aux_clk",
3820                         .parent_hws = (const struct clk_hw*[]){
3821                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3822                         },
3823                         .num_parents = 1,
3824                         .flags = CLK_SET_RATE_PARENT,
3825                         .ops = &clk_branch2_ops,
3826                 },
3827         },
3828 };
3829
3830 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3831         .halt_reg = 0x83028,
3832         .halt_check = BRANCH_HALT_DELAY,
3833         .clkr = {
3834                 .enable_reg = 0x83028,
3835                 .enable_mask = BIT(0),
3836                 .hw.init = &(const struct clk_init_data){
3837                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
3838                         .parent_hws = (const struct clk_hw*[]){
3839                                 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3840                         },
3841                         .num_parents = 1,
3842                         .flags = CLK_SET_RATE_PARENT,
3843                         .ops = &clk_branch2_ops,
3844                 },
3845         },
3846 };
3847
3848 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3849         .halt_reg = 0x830c0,
3850         .halt_check = BRANCH_HALT_DELAY,
3851         .clkr = {
3852                 .enable_reg = 0x830c0,
3853                 .enable_mask = BIT(0),
3854                 .hw.init = &(const struct clk_init_data){
3855                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
3856                         .parent_hws = (const struct clk_hw*[]){
3857                                 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3858                         },
3859                         .num_parents = 1,
3860                         .flags = CLK_SET_RATE_PARENT,
3861                         .ops = &clk_branch2_ops,
3862                 },
3863         },
3864 };
3865
3866 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3867         .halt_reg = 0x83024,
3868         .halt_check = BRANCH_HALT_DELAY,
3869         .clkr = {
3870                 .enable_reg = 0x83024,
3871                 .enable_mask = BIT(0),
3872                 .hw.init = &(const struct clk_init_data){
3873                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
3874                         .parent_hws = (const struct clk_hw*[]){
3875                                 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3876                         },
3877                         .num_parents = 1,
3878                         .flags = CLK_SET_RATE_PARENT,
3879                         .ops = &clk_branch2_ops,
3880                 },
3881         },
3882 };
3883
3884 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3885         .halt_reg = 0x83064,
3886         .halt_check = BRANCH_HALT_VOTED,
3887         .hwcg_reg = 0x83064,
3888         .hwcg_bit = 1,
3889         .clkr = {
3890                 .enable_reg = 0x83064,
3891                 .enable_mask = BIT(0),
3892                 .hw.init = &(const struct clk_init_data){
3893                         .name = "gcc_ufs_phy_unipro_core_clk",
3894                         .parent_hws = (const struct clk_hw*[]){
3895                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3896                         },
3897                         .num_parents = 1,
3898                         .flags = CLK_SET_RATE_PARENT,
3899                         .ops = &clk_branch2_ops,
3900                 },
3901         },
3902 };
3903
3904 static struct clk_branch gcc_usb20_master_clk = {
3905         .halt_reg = 0x1c018,
3906         .halt_check = BRANCH_HALT,
3907         .clkr = {
3908                 .enable_reg = 0x1c018,
3909                 .enable_mask = BIT(0),
3910                 .hw.init = &(const struct clk_init_data){
3911                         .name = "gcc_usb20_master_clk",
3912                         .parent_hws = (const struct clk_hw*[]){
3913                                 &gcc_usb20_master_clk_src.clkr.hw,
3914                         },
3915                         .num_parents = 1,
3916                         .flags = CLK_SET_RATE_PARENT,
3917                         .ops = &clk_branch2_ops,
3918                 },
3919         },
3920 };
3921
3922 static struct clk_branch gcc_usb20_mock_utmi_clk = {
3923         .halt_reg = 0x1c024,
3924         .halt_check = BRANCH_HALT,
3925         .clkr = {
3926                 .enable_reg = 0x1c024,
3927                 .enable_mask = BIT(0),
3928                 .hw.init = &(const struct clk_init_data){
3929                         .name = "gcc_usb20_mock_utmi_clk",
3930                         .parent_hws = (const struct clk_hw*[]){
3931                                 &gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
3932                         },
3933                         .num_parents = 1,
3934                         .flags = CLK_SET_RATE_PARENT,
3935                         .ops = &clk_branch2_ops,
3936                 },
3937         },
3938 };
3939
3940 static struct clk_branch gcc_usb20_sleep_clk = {
3941         .halt_reg = 0x1c020,
3942         .halt_check = BRANCH_HALT,
3943         .clkr = {
3944                 .enable_reg = 0x1c020,
3945                 .enable_mask = BIT(0),
3946                 .hw.init = &(const struct clk_init_data){
3947                         .name = "gcc_usb20_sleep_clk",
3948                         .ops = &clk_branch2_ops,
3949                 },
3950         },
3951 };
3952
3953 static struct clk_branch gcc_usb30_prim_master_clk = {
3954         .halt_reg = 0x1b018,
3955         .halt_check = BRANCH_HALT,
3956         .clkr = {
3957                 .enable_reg = 0x1b018,
3958                 .enable_mask = BIT(0),
3959                 .hw.init = &(const struct clk_init_data){
3960                         .name = "gcc_usb30_prim_master_clk",
3961                         .parent_hws = (const struct clk_hw*[]){
3962                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
3963                         },
3964                         .num_parents = 1,
3965                         .flags = CLK_SET_RATE_PARENT,
3966                         .ops = &clk_branch2_ops,
3967                 },
3968         },
3969 };
3970
3971 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3972         .halt_reg = 0x1b024,
3973         .halt_check = BRANCH_HALT,
3974         .clkr = {
3975                 .enable_reg = 0x1b024,
3976                 .enable_mask = BIT(0),
3977                 .hw.init = &(const struct clk_init_data){
3978                         .name = "gcc_usb30_prim_mock_utmi_clk",
3979                         .parent_hws = (const struct clk_hw*[]){
3980                                 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3981                         },
3982                         .num_parents = 1,
3983                         .flags = CLK_SET_RATE_PARENT,
3984                         .ops = &clk_branch2_ops,
3985                 },
3986         },
3987 };
3988
3989 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3990         .halt_reg = 0x1b020,
3991         .halt_check = BRANCH_HALT,
3992         .clkr = {
3993                 .enable_reg = 0x1b020,
3994                 .enable_mask = BIT(0),
3995                 .hw.init = &(const struct clk_init_data){
3996                         .name = "gcc_usb30_prim_sleep_clk",
3997                         .ops = &clk_branch2_ops,
3998                 },
3999         },
4000 };
4001
4002 static struct clk_branch gcc_usb30_sec_master_clk = {
4003         .halt_reg = 0x2f018,
4004         .halt_check = BRANCH_HALT,
4005         .clkr = {
4006                 .enable_reg = 0x2f018,
4007                 .enable_mask = BIT(0),
4008                 .hw.init = &(const struct clk_init_data){
4009                         .name = "gcc_usb30_sec_master_clk",
4010                         .parent_hws = (const struct clk_hw*[]){
4011                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
4012                         },
4013                         .num_parents = 1,
4014                         .flags = CLK_SET_RATE_PARENT,
4015                         .ops = &clk_branch2_ops,
4016                 },
4017         },
4018 };
4019
4020 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
4021         .halt_reg = 0x2f024,
4022         .halt_check = BRANCH_HALT,
4023         .clkr = {
4024                 .enable_reg = 0x2f024,
4025                 .enable_mask = BIT(0),
4026                 .hw.init = &(const struct clk_init_data){
4027                         .name = "gcc_usb30_sec_mock_utmi_clk",
4028                         .parent_hws = (const struct clk_hw*[]){
4029                                 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
4030                         },
4031                         .num_parents = 1,
4032                         .flags = CLK_SET_RATE_PARENT,
4033                         .ops = &clk_branch2_ops,
4034                 },
4035         },
4036 };
4037
4038 static struct clk_branch gcc_usb30_sec_sleep_clk = {
4039         .halt_reg = 0x2f020,
4040         .halt_check = BRANCH_HALT,
4041         .clkr = {
4042                 .enable_reg = 0x2f020,
4043                 .enable_mask = BIT(0),
4044                 .hw.init = &(const struct clk_init_data){
4045                         .name = "gcc_usb30_sec_sleep_clk",
4046                         .ops = &clk_branch2_ops,
4047                 },
4048         },
4049 };
4050
4051 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
4052         .halt_reg = 0x1b05c,
4053         .halt_check = BRANCH_HALT,
4054         .clkr = {
4055                 .enable_reg = 0x1b05c,
4056                 .enable_mask = BIT(0),
4057                 .hw.init = &(const struct clk_init_data){
4058                         .name = "gcc_usb3_prim_phy_aux_clk",
4059                         .parent_hws = (const struct clk_hw*[]){
4060                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
4061                         },
4062                         .num_parents = 1,
4063                         .flags = CLK_SET_RATE_PARENT,
4064                         .ops = &clk_branch2_ops,
4065                 },
4066         },
4067 };
4068
4069 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
4070         .halt_reg = 0x1b060,
4071         .halt_check = BRANCH_HALT,
4072         .clkr = {
4073                 .enable_reg = 0x1b060,
4074                 .enable_mask = BIT(0),
4075                 .hw.init = &(const struct clk_init_data){
4076                         .name = "gcc_usb3_prim_phy_com_aux_clk",
4077                         .parent_hws = (const struct clk_hw*[]){
4078                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
4079                         },
4080                         .num_parents = 1,
4081                         .flags = CLK_SET_RATE_PARENT,
4082                         .ops = &clk_branch2_ops,
4083                 },
4084         },
4085 };
4086
4087 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
4088         .halt_reg = 0x1b064,
4089         .halt_check = BRANCH_HALT_DELAY,
4090         .hwcg_reg = 0x1b064,
4091         .hwcg_bit = 1,
4092         .clkr = {
4093                 .enable_reg = 0x1b064,
4094                 .enable_mask = BIT(0),
4095                 .hw.init = &(const struct clk_init_data){
4096                         .name = "gcc_usb3_prim_phy_pipe_clk",
4097                         .parent_hws = (const struct clk_hw*[]){
4098                                 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
4099                         },
4100                         .num_parents = 1,
4101                         .flags = CLK_SET_RATE_PARENT,
4102                         .ops = &clk_branch2_ops,
4103                 },
4104         },
4105 };
4106
4107 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
4108         .halt_reg = 0x2f05c,
4109         .halt_check = BRANCH_HALT,
4110         .clkr = {
4111                 .enable_reg = 0x2f05c,
4112                 .enable_mask = BIT(0),
4113                 .hw.init = &(const struct clk_init_data){
4114                         .name = "gcc_usb3_sec_phy_aux_clk",
4115                         .parent_hws = (const struct clk_hw*[]){
4116                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
4117                         },
4118                         .num_parents = 1,
4119                         .flags = CLK_SET_RATE_PARENT,
4120                         .ops = &clk_branch2_ops,
4121                 },
4122         },
4123 };
4124
4125 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
4126         .halt_reg = 0x2f060,
4127         .halt_check = BRANCH_HALT,
4128         .clkr = {
4129                 .enable_reg = 0x2f060,
4130                 .enable_mask = BIT(0),
4131                 .hw.init = &(const struct clk_init_data){
4132                         .name = "gcc_usb3_sec_phy_com_aux_clk",
4133                         .parent_hws = (const struct clk_hw*[]){
4134                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
4135                         },
4136                         .num_parents = 1,
4137                         .flags = CLK_SET_RATE_PARENT,
4138                         .ops = &clk_branch2_ops,
4139                 },
4140         },
4141 };
4142
4143 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
4144         .halt_reg = 0x2f064,
4145         .halt_check = BRANCH_HALT_DELAY,
4146         .clkr = {
4147                 .enable_reg = 0x2f064,
4148                 .enable_mask = BIT(0),
4149                 .hw.init = &(const struct clk_init_data){
4150                         .name = "gcc_usb3_sec_phy_pipe_clk",
4151                         .parent_hws = (const struct clk_hw*[]){
4152                                 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
4153                         },
4154                         .num_parents = 1,
4155                         .flags = CLK_SET_RATE_PARENT,
4156                         .ops = &clk_branch2_ops,
4157                 },
4158         },
4159 };
4160
4161 static struct clk_branch gcc_usb_clkref_en = {
4162         .halt_reg = 0x97468,
4163         .halt_check = BRANCH_HALT_DELAY,
4164         .clkr = {
4165                 .enable_reg = 0x97468,
4166                 .enable_mask = BIT(0),
4167                 .hw.init = &(const struct clk_init_data){
4168                         .name = "gcc_usb_clkref_en",
4169                         .ops = &clk_branch2_ops,
4170                 },
4171         },
4172 };
4173
4174 static struct clk_branch gcc_video_axi0_clk = {
4175         .halt_reg = 0x34014,
4176         .halt_check = BRANCH_HALT_VOTED,
4177         .hwcg_reg = 0x34014,
4178         .hwcg_bit = 1,
4179         .clkr = {
4180                 .enable_reg = 0x34014,
4181                 .enable_mask = BIT(0),
4182                 .hw.init = &(const struct clk_init_data){
4183                         .name = "gcc_video_axi0_clk",
4184                         .ops = &clk_branch2_ops,
4185                 },
4186         },
4187 };
4188
4189 static struct clk_branch gcc_video_axi1_clk = {
4190         .halt_reg = 0x3401c,
4191         .halt_check = BRANCH_HALT_VOTED,
4192         .hwcg_reg = 0x3401c,
4193         .hwcg_bit = 1,
4194         .clkr = {
4195                 .enable_reg = 0x3401c,
4196                 .enable_mask = BIT(0),
4197                 .hw.init = &(const struct clk_init_data){
4198                         .name = "gcc_video_axi1_clk",
4199                         .ops = &clk_branch2_ops,
4200                 },
4201         },
4202 };
4203
4204 static struct gdsc pcie_0_gdsc = {
4205         .gdscr = 0xa9004,
4206         .collapse_ctrl = 0x4b104,
4207         .collapse_mask = BIT(0),
4208         .en_rest_wait_val = 0x2,
4209         .en_few_wait_val = 0x2,
4210         .clk_dis_wait_val = 0xf,
4211         .pd = {
4212                 .name = "pcie_0_gdsc",
4213         },
4214         .pwrsts = PWRSTS_OFF_ON,
4215         .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4216 };
4217
4218 static struct gdsc pcie_1_gdsc = {
4219         .gdscr = 0x77004,
4220         .collapse_ctrl = 0x4b104,
4221         .collapse_mask = BIT(1),
4222         .en_rest_wait_val = 0x2,
4223         .en_few_wait_val = 0x2,
4224         .clk_dis_wait_val = 0xf,
4225         .pd = {
4226                 .name = "pcie_1_gdsc",
4227         },
4228         .pwrsts = PWRSTS_OFF_ON,
4229         .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4230 };
4231
4232 static struct gdsc ufs_card_gdsc = {
4233         .gdscr = 0x81004,
4234         .en_rest_wait_val = 0x2,
4235         .en_few_wait_val = 0x2,
4236         .clk_dis_wait_val = 0xf,
4237         .pd = {
4238                 .name = "ufs_card_gdsc",
4239         },
4240         .pwrsts = PWRSTS_OFF_ON,
4241         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4242 };
4243
4244 static struct gdsc ufs_phy_gdsc = {
4245         .gdscr = 0x83004,
4246         .en_rest_wait_val = 0x2,
4247         .en_few_wait_val = 0x2,
4248         .clk_dis_wait_val = 0xf,
4249         .pd = {
4250                 .name = "ufs_phy_gdsc",
4251         },
4252         .pwrsts = PWRSTS_OFF_ON,
4253         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4254 };
4255
4256 static struct gdsc usb20_prim_gdsc = {
4257         .gdscr = 0x1c004,
4258         .en_rest_wait_val = 0x2,
4259         .en_few_wait_val = 0x2,
4260         .clk_dis_wait_val = 0xf,
4261         .pd = {
4262                 .name = "usb20_prim_gdsc",
4263         },
4264         .pwrsts = PWRSTS_OFF_ON,
4265         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4266 };
4267
4268 static struct gdsc usb30_prim_gdsc = {
4269         .gdscr = 0x1b004,
4270         .en_rest_wait_val = 0x2,
4271         .en_few_wait_val = 0x2,
4272         .clk_dis_wait_val = 0xf,
4273         .pd = {
4274                 .name = "usb30_prim_gdsc",
4275         },
4276         .pwrsts = PWRSTS_OFF_ON,
4277         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4278 };
4279
4280 static struct gdsc usb30_sec_gdsc = {
4281         .gdscr = 0x2f004,
4282         .en_rest_wait_val = 0x2,
4283         .en_few_wait_val = 0x2,
4284         .clk_dis_wait_val = 0xf,
4285         .pd = {
4286                 .name = "usb30_sec_gdsc",
4287         },
4288         .pwrsts = PWRSTS_OFF_ON,
4289         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4290 };
4291
4292 static struct gdsc emac0_gdsc = {
4293         .gdscr = 0xb6004,
4294         .en_rest_wait_val = 0x2,
4295         .en_few_wait_val = 0x2,
4296         .clk_dis_wait_val = 0xf,
4297         .pd = {
4298                 .name = "emac0_gdsc",
4299         },
4300         .pwrsts = PWRSTS_OFF_ON,
4301         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4302 };
4303
4304 static struct gdsc emac1_gdsc = {
4305         .gdscr = 0xb4004,
4306         .en_rest_wait_val = 0x2,
4307         .en_few_wait_val = 0x2,
4308         .clk_dis_wait_val = 0xf,
4309         .pd = {
4310                 .name = "emac1_gdsc",
4311         },
4312         .pwrsts = PWRSTS_OFF_ON,
4313         .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
4314 };
4315
4316 static struct clk_regmap *gcc_sa8775p_clocks[] = {
4317         [GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
4318         [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
4319         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4320         [GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
4321         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
4322         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
4323         [GCC_AHB2PHY0_CLK] = &gcc_ahb2phy0_clk.clkr,
4324         [GCC_AHB2PHY2_CLK] = &gcc_ahb2phy2_clk.clkr,
4325         [GCC_AHB2PHY3_CLK] = &gcc_ahb2phy3_clk.clkr,
4326         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
4327         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
4328         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
4329         [GCC_CAMERA_THROTTLE_XO_CLK] = &gcc_camera_throttle_xo_clk.clkr,
4330         [GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
4331         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
4332         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
4333         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
4334         [GCC_DISP1_HF_AXI_CLK] = &gcc_disp1_hf_axi_clk.clkr,
4335         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
4336         [GCC_EDP_REF_CLKREF_EN] = &gcc_edp_ref_clkref_en.clkr,
4337         [GCC_EMAC0_AXI_CLK] = &gcc_emac0_axi_clk.clkr,
4338         [GCC_EMAC0_PHY_AUX_CLK] = &gcc_emac0_phy_aux_clk.clkr,
4339         [GCC_EMAC0_PHY_AUX_CLK_SRC] = &gcc_emac0_phy_aux_clk_src.clkr,
4340         [GCC_EMAC0_PTP_CLK] = &gcc_emac0_ptp_clk.clkr,
4341         [GCC_EMAC0_PTP_CLK_SRC] = &gcc_emac0_ptp_clk_src.clkr,
4342         [GCC_EMAC0_RGMII_CLK] = &gcc_emac0_rgmii_clk.clkr,
4343         [GCC_EMAC0_RGMII_CLK_SRC] = &gcc_emac0_rgmii_clk_src.clkr,
4344         [GCC_EMAC0_SLV_AHB_CLK] = &gcc_emac0_slv_ahb_clk.clkr,
4345         [GCC_EMAC1_AXI_CLK] = &gcc_emac1_axi_clk.clkr,
4346         [GCC_EMAC1_PHY_AUX_CLK] = &gcc_emac1_phy_aux_clk.clkr,
4347         [GCC_EMAC1_PHY_AUX_CLK_SRC] = &gcc_emac1_phy_aux_clk_src.clkr,
4348         [GCC_EMAC1_PTP_CLK] = &gcc_emac1_ptp_clk.clkr,
4349         [GCC_EMAC1_PTP_CLK_SRC] = &gcc_emac1_ptp_clk_src.clkr,
4350         [GCC_EMAC1_RGMII_CLK] = &gcc_emac1_rgmii_clk.clkr,
4351         [GCC_EMAC1_RGMII_CLK_SRC] = &gcc_emac1_rgmii_clk_src.clkr,
4352         [GCC_EMAC1_SLV_AHB_CLK] = &gcc_emac1_slv_ahb_clk.clkr,
4353         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4354         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
4355         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4356         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
4357         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4358         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
4359         [GCC_GP4_CLK] = &gcc_gp4_clk.clkr,
4360         [GCC_GP4_CLK_SRC] = &gcc_gp4_clk_src.clkr,
4361         [GCC_GP5_CLK] = &gcc_gp5_clk.clkr,
4362         [GCC_GP5_CLK_SRC] = &gcc_gp5_clk_src.clkr,
4363         [GCC_GPLL0] = &gcc_gpll0.clkr,
4364         [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
4365         [GCC_GPLL1] = &gcc_gpll1.clkr,
4366         [GCC_GPLL4] = &gcc_gpll4.clkr,
4367         [GCC_GPLL5] = &gcc_gpll5.clkr,
4368         [GCC_GPLL7] = &gcc_gpll7.clkr,
4369         [GCC_GPLL9] = &gcc_gpll9.clkr,
4370         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
4371         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
4372         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
4373         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
4374         [GCC_GPU_TCU_THROTTLE_AHB_CLK] = &gcc_gpu_tcu_throttle_ahb_clk.clkr,
4375         [GCC_GPU_TCU_THROTTLE_CLK] = &gcc_gpu_tcu_throttle_clk.clkr,
4376         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
4377         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
4378         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
4379         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
4380         [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr,
4381         [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr,
4382         [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
4383         [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
4384         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
4385         [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
4386         [GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr,
4387         [GCC_PCIE_0_PIPEDIV2_CLK] = &gcc_pcie_0_pipediv2_clk.clkr,
4388         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
4389         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
4390         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
4391         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
4392         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
4393         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
4394         [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
4395         [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
4396         [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
4397         [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
4398         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
4399         [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
4400         [GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr,
4401         [GCC_PCIE_1_PIPEDIV2_CLK] = &gcc_pcie_1_pipediv2_clk.clkr,
4402         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
4403         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
4404         [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
4405         [GCC_PCIE_THROTTLE_CFG_CLK] = &gcc_pcie_throttle_cfg_clk.clkr,
4406         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
4407         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
4408         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
4409         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
4410         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
4411         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
4412         [GCC_QMIP_DISP1_AHB_CLK] = &gcc_qmip_disp1_ahb_clk.clkr,
4413         [GCC_QMIP_DISP1_ROT_AHB_CLK] = &gcc_qmip_disp1_rot_ahb_clk.clkr,
4414         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
4415         [GCC_QMIP_DISP_ROT_AHB_CLK] = &gcc_qmip_disp_rot_ahb_clk.clkr,
4416         [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
4417         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
4418         [GCC_QMIP_VIDEO_VCPU_AHB_CLK] = &gcc_qmip_video_vcpu_ahb_clk.clkr,
4419         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
4420         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
4421         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
4422         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
4423         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
4424         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4425         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4426         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4427         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4428         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4429         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4430         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4431         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4432         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4433         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
4434         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
4435         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
4436         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
4437         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4438         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4439         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4440         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4441         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4442         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4443         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4444         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4445         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4446         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4447         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4448         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4449         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
4450         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
4451         [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
4452         [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
4453         [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
4454         [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
4455         [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
4456         [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
4457         [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
4458         [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
4459         [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
4460         [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
4461         [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
4462         [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
4463         [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
4464         [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
4465         [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
4466         [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
4467         [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr,
4468         [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr,
4469         [GCC_QUPV3_WRAP3_QSPI_CLK] = &gcc_qupv3_wrap3_qspi_clk.clkr,
4470         [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr,
4471         [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr,
4472         [GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC] = &gcc_qupv3_wrap3_s0_div_clk_src.clkr,
4473         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4474         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4475         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4476         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4477         [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
4478         [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
4479         [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr,
4480         [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr,
4481         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4482         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4483         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
4484         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4485         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
4486         [GCC_SGMI_CLKREF_EN] = &gcc_sgmi_clkref_en.clkr,
4487         [GCC_TSCSS_AHB_CLK] = &gcc_tscss_ahb_clk.clkr,
4488         [GCC_TSCSS_CNTR_CLK_SRC] = &gcc_tscss_cntr_clk_src.clkr,
4489         [GCC_TSCSS_ETU_CLK] = &gcc_tscss_etu_clk.clkr,
4490         [GCC_TSCSS_GLOBAL_CNTR_CLK] = &gcc_tscss_global_cntr_clk.clkr,
4491         [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
4492         [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
4493         [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
4494         [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
4495         [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
4496         [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
4497         [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
4498         [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
4499         [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
4500         [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
4501         [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
4502         [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
4503         [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
4504         [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
4505         [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
4506         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4507         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4508         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4509         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4510         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4511         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4512         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4513         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4514         [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
4515         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
4516         [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
4517         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4518         [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
4519         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4520         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4521         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
4522         [GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
4523         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
4524         [GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
4525         [GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
4526         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
4527         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4528         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4529         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4530         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
4531         [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
4532         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4533         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
4534         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
4535         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
4536         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
4537         [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
4538         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
4539         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
4540         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4541         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4542         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4543         [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
4544         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
4545         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
4546         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
4547         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
4548         [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
4549         [GCC_USB_CLKREF_EN] = &gcc_usb_clkref_en.clkr,
4550         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4551         [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
4552 };
4553
4554 static const struct qcom_reset_map gcc_sa8775p_resets[] = {
4555         [GCC_CAMERA_BCR] = { 0x32000 },
4556         [GCC_DISPLAY1_BCR] = { 0xc7000 },
4557         [GCC_DISPLAY_BCR] = { 0x33000 },
4558         [GCC_EMAC0_BCR] = { 0xb6000 },
4559         [GCC_EMAC1_BCR] = { 0xb4000 },
4560         [GCC_GPU_BCR] = { 0x7d000 },
4561         [GCC_MMSS_BCR] = { 0x17000 },
4562         [GCC_PCIE_0_BCR] = { 0xa9000 },
4563         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xbf000 },
4564         [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xbf008 },
4565         [GCC_PCIE_0_PHY_BCR] = { 0xad144 },
4566         [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xbf00c },
4567         [GCC_PCIE_1_BCR] = { 0x77000 },
4568         [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xae084 },
4569         [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xae090 },
4570         [GCC_PCIE_1_PHY_BCR] = { 0xae08c },
4571         [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xae094 },
4572         [GCC_PDM_BCR] = { 0x3f000 },
4573         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
4574         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
4575         [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2a000 },
4576         [GCC_QUPV3_WRAPPER_3_BCR] = { 0xc4000 },
4577         [GCC_SDCC1_BCR] = { 0x20000 },
4578         [GCC_TSCSS_BCR] = { 0x21000 },
4579         [GCC_UFS_CARD_BCR] = { 0x81000 },
4580         [GCC_UFS_PHY_BCR] = { 0x83000 },
4581         [GCC_USB20_PRIM_BCR] = { 0x1c000 },
4582         [GCC_USB2_PHY_PRIM_BCR] = { 0x5c028 },
4583         [GCC_USB2_PHY_SEC_BCR] = { 0x5c02c },
4584         [GCC_USB30_PRIM_BCR] = { 0x1b000 },
4585         [GCC_USB30_SEC_BCR] = { 0x2f000 },
4586         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x5c008 },
4587         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x5c014 },
4588         [GCC_USB3_PHY_PRIM_BCR] = { 0x5c000 },
4589         [GCC_USB3_PHY_SEC_BCR] = { 0x5c00c },
4590         [GCC_USB3_PHY_TERT_BCR] = { 0x5c030 },
4591         [GCC_USB3_UNIPHY_MP0_BCR] = { 0x5c018 },
4592         [GCC_USB3_UNIPHY_MP1_BCR] = { 0x5c01c },
4593         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x5c004 },
4594         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x5c010 },
4595         [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
4596         [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
4597         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
4598         [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
4599         [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
4600         [GCC_VIDEO_BCR] = { 0x34000 },
4601 };
4602
4603 static struct gdsc *gcc_sa8775p_gdscs[] = {
4604         [PCIE_0_GDSC] = &pcie_0_gdsc,
4605         [PCIE_1_GDSC] = &pcie_1_gdsc,
4606         [UFS_CARD_GDSC] = &ufs_card_gdsc,
4607         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
4608         [USB20_PRIM_GDSC] = &usb20_prim_gdsc,
4609         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
4610         [USB30_SEC_GDSC] = &usb30_sec_gdsc,
4611         [EMAC0_GDSC] = &emac0_gdsc,
4612         [EMAC1_GDSC] = &emac1_gdsc,
4613 };
4614
4615 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
4616         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
4617         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
4618         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
4619         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
4620         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
4621         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
4622         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
4623         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
4624         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
4625         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
4626         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
4627         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
4628         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
4629         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
4630         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
4631         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
4632         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
4633         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
4634         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
4635         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
4636         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
4637         DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src),
4638 };
4639
4640 static const struct regmap_config gcc_sa8775p_regmap_config = {
4641         .reg_bits = 32,
4642         .reg_stride = 4,
4643         .val_bits = 32,
4644         .max_register = 0xc7018,
4645         .fast_io = true,
4646 };
4647
4648 static const struct qcom_cc_desc gcc_sa8775p_desc = {
4649         .config = &gcc_sa8775p_regmap_config,
4650         .clks = gcc_sa8775p_clocks,
4651         .num_clks = ARRAY_SIZE(gcc_sa8775p_clocks),
4652         .resets = gcc_sa8775p_resets,
4653         .num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
4654         .gdscs = gcc_sa8775p_gdscs,
4655         .num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
4656 };
4657
4658 static const struct of_device_id gcc_sa8775p_match_table[] = {
4659         { .compatible = "qcom,sa8775p-gcc" },
4660         { }
4661 };
4662 MODULE_DEVICE_TABLE(of, gcc_sa8775p_match_table);
4663
4664 static int gcc_sa8775p_probe(struct platform_device *pdev)
4665 {
4666         struct regmap *regmap;
4667         int ret;
4668
4669         regmap = qcom_cc_map(pdev, &gcc_sa8775p_desc);
4670         if (IS_ERR(regmap))
4671                 return PTR_ERR(regmap);
4672
4673         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4674                                        ARRAY_SIZE(gcc_dfs_clocks));
4675         if (ret)
4676                 return ret;
4677
4678         /* Keep some clocks always-on */
4679         qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */
4680         qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */
4681         qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */
4682         qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */
4683         qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */
4684         qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */
4685         qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */
4686         qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
4687         qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
4688
4689         /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
4690         qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
4691
4692         return qcom_cc_really_probe(&pdev->dev, &gcc_sa8775p_desc, regmap);
4693 }
4694
4695 static struct platform_driver gcc_sa8775p_driver = {
4696         .probe = gcc_sa8775p_probe,
4697         .driver = {
4698                 .name = "sa8775p-gcc",
4699                 .of_match_table = gcc_sa8775p_match_table,
4700         },
4701 };
4702
4703 static int __init gcc_sa8775p_init(void)
4704 {
4705         return platform_driver_register(&gcc_sa8775p_driver);
4706 }
4707 core_initcall(gcc_sa8775p_init);
4708
4709 static void __exit gcc_sa8775p_exit(void)
4710 {
4711         platform_driver_unregister(&gcc_sa8775p_driver);
4712 }
4713 module_exit(gcc_sa8775p_exit);
4714
4715 MODULE_DESCRIPTION("Qualcomm SA8775P GCC driver");
4716 MODULE_LICENSE("GPL");