1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Support for Vector Instructions
5 * Assembler macros to generate .byte/.word code for particular
6 * vector instructions that are supported by recent binutils (>= 2.26) only.
8 * Copyright IBM Corp. 2015
12 #ifndef __ASM_S390_FPU_INSN_ASM_H
13 #define __ASM_S390_FPU_INSN_ASM_H
15 #ifndef __ASM_S390_FPU_INSN_H
16 #error only <asm/fpu-insn.h> can be included directly
21 /* Macros to generate vector instruction byte code */
23 /* GR_NUM - Retrieve general-purpose register number
25 * @opd: Operand to store register number
26 * @r64: String designation register in the format "%rN"
83 /* VX_NUM - Retrieve vector register number
85 * @opd: Operand to store register number
86 * @vxr: String designation register in the format "%vN"
88 * The vector register number is used for as input number to the
89 * instruction and, as well as, to compute the RXB field of the
195 /* RXB - Compute most significant bit used vector registers
197 * @rxb: Operand to store computed RXB value
198 * @v1: Vector register designated operand whose MSB is stored in
199 * RXB bit 0 (instruction bit 36) and whose remaining bits
200 * are stored in instruction bits 8-11.
201 * @v2: Vector register designated operand whose MSB is stored in
202 * RXB bit 1 (instruction bit 37) and whose remaining bits
203 * are stored in instruction bits 12-15.
204 * @v3: Vector register designated operand whose MSB is stored in
205 * RXB bit 2 (instruction bit 38) and whose remaining bits
206 * are stored in instruction bits 16-19.
207 * @v4: Vector register designated operand whose MSB is stored in
208 * RXB bit 3 (instruction bit 39) and whose remaining bits
209 * are stored in instruction bits 32-35.
211 * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
212 * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
213 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
216 * [1] IBM z/Architecture Principles of Operation, chapter "Program
217 * Execution, section "Instructions", subsection "Instruction Formats".
219 .macro RXB rxb v1 v2=0 v3=0 v4=0
235 /* MRXB - Generate Element Size Control and RXB value
237 * @m: Element size control
238 * @v1: First vector register designated operand (for RXB)
239 * @v2: Second vector register designated operand (for RXB)
240 * @v3: Third vector register designated operand (for RXB)
241 * @v4: Fourth vector register designated operand (for RXB)
243 * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
244 * description for further details.
246 .macro MRXB m v1 v2=0 v3=0 v4=0
248 RXB rxb, \v1, \v2, \v3, \v4
249 .byte (\m << 4) | rxb
252 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
254 * @m: Element size control
256 * @v1: First vector register designated operand (for RXB)
257 * @v2: Second vector register designated operand (for RXB)
258 * @v3: Third vector register designated operand (for RXB)
259 * @v4: Fourth vector register designated operand (for RXB)
261 * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
262 * description for further details.
264 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
265 MRXB \m, \v1, \v2, \v3, \v4
269 /* Vector support instructions */
271 /* VECTOR GENERATE BYTE MASK */
274 .word (0xE700 | ((v1&15) << 4))
285 /* VECTOR LOAD VR ELEMENT FROM GR */
286 .macro VLVG v, gr, disp, m
290 .word 0xE700 | ((v1&15) << 4) | r3
291 .word (b2 << 12) | (\disp)
294 .macro VLVGB v, gr, index, base
295 VLVG \v, \gr, \index, \base, 0
297 .macro VLVGH v, gr, index
298 VLVG \v, \gr, \index, 1
300 .macro VLVGF v, gr, index
301 VLVG \v, \gr, \index, 2
303 .macro VLVGG v, gr, index
304 VLVG \v, \gr, \index, 3
307 /* VECTOR LOAD REGISTER */
311 .word 0xE700 | ((v1&15) << 4) | (v2&15)
313 MRXBOPC 0, 0x56, v1, v2
317 .macro VL v, disp, index="%r0", base
321 .word 0xE700 | ((v1&15) << 4) | x2
322 .word (b2 << 12) | (\disp)
326 /* VECTOR LOAD ELEMENT */
327 .macro VLEx vr1, disp, index="%r0", base, m3, opc
331 .word 0xE700 | ((v1&15) << 4) | x2
332 .word (b2 << 12) | (\disp)
333 MRXBOPC \m3, \opc, v1
335 .macro VLEB vr1, disp, index="%r0", base, m3
336 VLEx \vr1, \disp, \index, \base, \m3, 0x00
338 .macro VLEH vr1, disp, index="%r0", base, m3
339 VLEx \vr1, \disp, \index, \base, \m3, 0x01
341 .macro VLEF vr1, disp, index="%r0", base, m3
342 VLEx \vr1, \disp, \index, \base, \m3, 0x03
344 .macro VLEG vr1, disp, index="%r0", base, m3
345 VLEx \vr1, \disp, \index, \base, \m3, 0x02
348 /* VECTOR LOAD ELEMENT IMMEDIATE */
349 .macro VLEIx vr1, imm2, m3, opc
351 .word 0xE700 | ((v1&15) << 4)
353 MRXBOPC \m3, \opc, v1
355 .macro VLEIB vr1, imm2, index
356 VLEIx \vr1, \imm2, \index, 0x40
358 .macro VLEIH vr1, imm2, index
359 VLEIx \vr1, \imm2, \index, 0x41
361 .macro VLEIF vr1, imm2, index
362 VLEIx \vr1, \imm2, \index, 0x43
364 .macro VLEIG vr1, imm2, index
365 VLEIx \vr1, \imm2, \index, 0x42
368 /* VECTOR LOAD GR FROM VR ELEMENT */
369 .macro VLGV gr, vr, disp, base="%r0", m
373 .word 0xE700 | (r1 << 4) | (v3&15)
374 .word (b2 << 12) | (\disp)
375 MRXBOPC \m, 0x21, 0, v3
377 .macro VLGVB gr, vr, disp, base="%r0"
378 VLGV \gr, \vr, \disp, \base, 0
380 .macro VLGVH gr, vr, disp, base="%r0"
381 VLGV \gr, \vr, \disp, \base, 1
383 .macro VLGVF gr, vr, disp, base="%r0"
384 VLGV \gr, \vr, \disp, \base, 2
386 .macro VLGVG gr, vr, disp, base="%r0"
387 VLGV \gr, \vr, \disp, \base, 3
390 /* VECTOR LOAD MULTIPLE */
391 .macro VLM vfrom, vto, disp, base, hint=3
395 .word 0xE700 | ((v1&15) << 4) | (v3&15)
396 .word (b2 << 12) | (\disp)
397 MRXBOPC \hint, 0x36, v1, v3
401 .macro VST vr1, disp, index="%r0", base
405 .word 0xE700 | ((v1&15) << 4) | (x2&15)
406 .word (b2 << 12) | (\disp)
410 /* VECTOR STORE BYTE REVERSED ELEMENTS */
411 .macro VSTBR vr1, disp, index="%r0", base, m
415 .word 0xE600 | ((v1&15) << 4) | (x2&15)
416 .word (b2 << 12) | (\disp)
419 .macro VSTBRH vr1, disp, index="%r0", base
420 VSTBR \vr1, \disp, \index, \base, 1
422 .macro VSTBRF vr1, disp, index="%r0", base
423 VSTBR \vr1, \disp, \index, \base, 2
425 .macro VSTBRG vr1, disp, index="%r0", base
426 VSTBR \vr1, \disp, \index, \base, 3
428 .macro VSTBRQ vr1, disp, index="%r0", base
429 VSTBR \vr1, \disp, \index, \base, 4
432 /* VECTOR STORE MULTIPLE */
433 .macro VSTM vfrom, vto, disp, base, hint=3
437 .word 0xE700 | ((v1&15) << 4) | (v3&15)
438 .word (b2 << 12) | (\disp)
439 MRXBOPC \hint, 0x3E, v1, v3
443 .macro VPERM vr1, vr2, vr3, vr4
448 .word 0xE700 | ((v1&15) << 4) | (v2&15)
449 .word ((v3&15) << 12)
450 MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4
453 /* VECTOR UNPACK LOGICAL LOW */
454 .macro VUPLL vr1, vr2, m3
457 .word 0xE700 | ((v1&15) << 4) | (v2&15)
459 MRXBOPC \m3, 0xD4, v1, v2
461 .macro VUPLLB vr1, vr2
464 .macro VUPLLH vr1, vr2
467 .macro VUPLLF vr1, vr2
471 /* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */
472 .macro VPDI vr1, vr2, vr3, m4
476 .word 0xE700 | ((v1&15) << 4) | (v2&15)
477 .word ((v3&15) << 12)
478 MRXBOPC \m4, 0x84, v1, v2, v3
481 /* VECTOR REPLICATE */
482 .macro VREP vr1, vr3, imm2, m4
485 .word 0xE700 | ((v1&15) << 4) | (v3&15)
487 MRXBOPC \m4, 0x4D, v1, v3
489 .macro VREPB vr1, vr3, imm2
490 VREP \vr1, \vr3, \imm2, 0
492 .macro VREPH vr1, vr3, imm2
493 VREP \vr1, \vr3, \imm2, 1
495 .macro VREPF vr1, vr3, imm2
496 VREP \vr1, \vr3, \imm2, 2
498 .macro VREPG vr1, vr3, imm2
499 VREP \vr1, \vr3, \imm2, 3
502 /* VECTOR MERGE HIGH */
503 .macro VMRH vr1, vr2, vr3, m4
507 .word 0xE700 | ((v1&15) << 4) | (v2&15)
508 .word ((v3&15) << 12)
509 MRXBOPC \m4, 0x61, v1, v2, v3
511 .macro VMRHB vr1, vr2, vr3
512 VMRH \vr1, \vr2, \vr3, 0
514 .macro VMRHH vr1, vr2, vr3
515 VMRH \vr1, \vr2, \vr3, 1
517 .macro VMRHF vr1, vr2, vr3
518 VMRH \vr1, \vr2, \vr3, 2
520 .macro VMRHG vr1, vr2, vr3
521 VMRH \vr1, \vr2, \vr3, 3
524 /* VECTOR MERGE LOW */
525 .macro VMRL vr1, vr2, vr3, m4
529 .word 0xE700 | ((v1&15) << 4) | (v2&15)
530 .word ((v3&15) << 12)
531 MRXBOPC \m4, 0x60, v1, v2, v3
533 .macro VMRLB vr1, vr2, vr3
534 VMRL \vr1, \vr2, \vr3, 0
536 .macro VMRLH vr1, vr2, vr3
537 VMRL \vr1, \vr2, \vr3, 1
539 .macro VMRLF vr1, vr2, vr3
540 VMRL \vr1, \vr2, \vr3, 2
542 .macro VMRLG vr1, vr2, vr3
543 VMRL \vr1, \vr2, \vr3, 3
546 /* VECTOR LOAD WITH LENGTH */
547 .macro VLL v, gr, disp, base
551 .word 0xE700 | ((v1&15) << 4) | r3
552 .word (b2 << 12) | (\disp)
556 /* VECTOR STORE WITH LENGTH */
557 .macro VSTL v, gr, disp, base
561 .word 0xE700 | ((v1&15) << 4) | r3
562 .word (b2 << 12) | (\disp)
566 /* Vector integer instructions */
569 .macro VN vr1, vr2, vr3
573 .word 0xE700 | ((v1&15) << 4) | (v2&15)
574 .word ((v3&15) << 12)
575 MRXBOPC 0, 0x68, v1, v2, v3
578 /* VECTOR CHECKSUM */
579 .macro VCKSM vr1, vr2, vr3
583 .word 0xE700 | ((v1&15) << 4) | (v2&15)
584 .word ((v3&15) << 12)
585 MRXBOPC 0, 0x66, v1, v2, v3
588 /* VECTOR EXCLUSIVE OR */
589 .macro VX vr1, vr2, vr3
593 .word 0xE700 | ((v1&15) << 4) | (v2&15)
594 .word ((v3&15) << 12)
595 MRXBOPC 0, 0x6D, v1, v2, v3
598 /* VECTOR GALOIS FIELD MULTIPLY SUM */
599 .macro VGFM vr1, vr2, vr3, m4
603 .word 0xE700 | ((v1&15) << 4) | (v2&15)
604 .word ((v3&15) << 12)
605 MRXBOPC \m4, 0xB4, v1, v2, v3
607 .macro VGFMB vr1, vr2, vr3
608 VGFM \vr1, \vr2, \vr3, 0
610 .macro VGFMH vr1, vr2, vr3
611 VGFM \vr1, \vr2, \vr3, 1
613 .macro VGFMF vr1, vr2, vr3
614 VGFM \vr1, \vr2, \vr3, 2
616 .macro VGFMG vr1, vr2, vr3
617 VGFM \vr1, \vr2, \vr3, 3
620 /* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */
621 .macro VGFMA vr1, vr2, vr3, vr4, m5
626 .word 0xE700 | ((v1&15) << 4) | (v2&15)
627 .word ((v3&15) << 12) | (\m5 << 8)
628 MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4
630 .macro VGFMAB vr1, vr2, vr3, vr4
631 VGFMA \vr1, \vr2, \vr3, \vr4, 0
633 .macro VGFMAH vr1, vr2, vr3, vr4
634 VGFMA \vr1, \vr2, \vr3, \vr4, 1
636 .macro VGFMAF vr1, vr2, vr3, vr4
637 VGFMA \vr1, \vr2, \vr3, \vr4, 2
639 .macro VGFMAG vr1, vr2, vr3, vr4
640 VGFMA \vr1, \vr2, \vr3, \vr4, 3
643 /* VECTOR SHIFT RIGHT LOGICAL BY BYTE */
644 .macro VSRLB vr1, vr2, vr3
648 .word 0xE700 | ((v1&15) << 4) | (v2&15)
649 .word ((v3&15) << 12)
650 MRXBOPC 0, 0x7D, v1, v2, v3
653 /* VECTOR REPLICATE IMMEDIATE */
654 .macro VREPI vr1, imm2, m3
656 .word 0xE700 | ((v1&15) << 4)
658 MRXBOPC \m3, 0x45, v1
660 .macro VREPIB vr1, imm2
663 .macro VREPIH vr1, imm2
666 .macro VREPIF vr1, imm2
669 .macro VREPIG vr1, imm2
674 .macro VA vr1, vr2, vr3, m4
678 .word 0xE700 | ((v1&15) << 4) | (v2&15)
679 .word ((v3&15) << 12)
680 MRXBOPC \m4, 0xF3, v1, v2, v3
682 .macro VAB vr1, vr2, vr3
683 VA \vr1, \vr2, \vr3, 0
685 .macro VAH vr1, vr2, vr3
686 VA \vr1, \vr2, \vr3, 1
688 .macro VAF vr1, vr2, vr3
689 VA \vr1, \vr2, \vr3, 2
691 .macro VAG vr1, vr2, vr3
692 VA \vr1, \vr2, \vr3, 3
694 .macro VAQ vr1, vr2, vr3
695 VA \vr1, \vr2, \vr3, 4
698 /* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
699 .macro VESRAV vr1, vr2, vr3, m4
703 .word 0xE700 | ((v1&15) << 4) | (v2&15)
704 .word ((v3&15) << 12)
705 MRXBOPC \m4, 0x7A, v1, v2, v3
708 .macro VESRAVB vr1, vr2, vr3
709 VESRAV \vr1, \vr2, \vr3, 0
711 .macro VESRAVH vr1, vr2, vr3
712 VESRAV \vr1, \vr2, \vr3, 1
714 .macro VESRAVF vr1, vr2, vr3
715 VESRAV \vr1, \vr2, \vr3, 2
717 .macro VESRAVG vr1, vr2, vr3
718 VESRAV \vr1, \vr2, \vr3, 3
721 /* VECTOR ELEMENT ROTATE LEFT LOGICAL */
722 .macro VERLL vr1, vr3, disp, base="%r0", m4
726 .word 0xE700 | ((v1&15) << 4) | (v3&15)
727 .word (b2 << 12) | (\disp)
728 MRXBOPC \m4, 0x33, v1, v3
730 .macro VERLLB vr1, vr3, disp, base="%r0"
731 VERLL \vr1, \vr3, \disp, \base, 0
733 .macro VERLLH vr1, vr3, disp, base="%r0"
734 VERLL \vr1, \vr3, \disp, \base, 1
736 .macro VERLLF vr1, vr3, disp, base="%r0"
737 VERLL \vr1, \vr3, \disp, \base, 2
739 .macro VERLLG vr1, vr3, disp, base="%r0"
740 VERLL \vr1, \vr3, \disp, \base, 3
743 /* VECTOR SHIFT LEFT DOUBLE BY BYTE */
744 .macro VSLDB vr1, vr2, vr3, imm4
748 .word 0xE700 | ((v1&15) << 4) | (v2&15)
749 .word ((v3&15) << 12) | (\imm4)
750 MRXBOPC 0, 0x77, v1, v2, v3
753 #endif /* __ASSEMBLY__ */
754 #endif /* __ASM_S390_FPU_INSN_ASM_H */