1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,osm-l3.h>
13 #include <dt-bindings/interconnect/qcom,sc8180x.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 interrupt-parent = <&intc>;
27 xo_board_clk: xo-board {
28 compatible = "fixed-clock";
30 clock-frequency = <38400000>;
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
47 compatible = "qcom,kryo485";
49 enable-method = "psci";
50 capacity-dmips-mhz = <602>;
51 next-level-cache = <&l2_0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
53 operating-points-v2 = <&cpu0_opp_table>;
54 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
55 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
56 power-domains = <&cpu_pd0>;
57 power-domain-names = "psci";
59 clocks = <&cpufreq_hw 0>;
65 next-level-cache = <&l3_0>;
76 compatible = "qcom,kryo485";
78 enable-method = "psci";
79 capacity-dmips-mhz = <602>;
80 next-level-cache = <&l2_100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
82 operating-points-v2 = <&cpu0_opp_table>;
83 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
84 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
85 power-domains = <&cpu_pd1>;
86 power-domain-names = "psci";
88 clocks = <&cpufreq_hw 0>;
94 next-level-cache = <&l3_0>;
101 compatible = "qcom,kryo485";
103 enable-method = "psci";
104 capacity-dmips-mhz = <602>;
105 next-level-cache = <&l2_200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
107 operating-points-v2 = <&cpu0_opp_table>;
108 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
109 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
110 power-domains = <&cpu_pd2>;
111 power-domain-names = "psci";
112 #cooling-cells = <2>;
113 clocks = <&cpufreq_hw 0>;
116 compatible = "cache";
119 next-level-cache = <&l3_0>;
125 compatible = "qcom,kryo485";
127 enable-method = "psci";
128 capacity-dmips-mhz = <602>;
129 next-level-cache = <&l2_300>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
132 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
134 power-domains = <&cpu_pd3>;
135 power-domain-names = "psci";
136 #cooling-cells = <2>;
137 clocks = <&cpufreq_hw 0>;
140 compatible = "cache";
143 next-level-cache = <&l3_0>;
149 compatible = "qcom,kryo485";
151 enable-method = "psci";
152 capacity-dmips-mhz = <1024>;
153 next-level-cache = <&l2_400>;
154 qcom,freq-domain = <&cpufreq_hw 1>;
155 operating-points-v2 = <&cpu4_opp_table>;
156 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
157 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
158 power-domains = <&cpu_pd4>;
159 power-domain-names = "psci";
160 #cooling-cells = <2>;
161 clocks = <&cpufreq_hw 1>;
164 compatible = "cache";
167 next-level-cache = <&l3_0>;
173 compatible = "qcom,kryo485";
175 enable-method = "psci";
176 capacity-dmips-mhz = <1024>;
177 next-level-cache = <&l2_500>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 operating-points-v2 = <&cpu4_opp_table>;
180 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
181 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
182 power-domains = <&cpu_pd5>;
183 power-domain-names = "psci";
184 #cooling-cells = <2>;
185 clocks = <&cpufreq_hw 1>;
188 compatible = "cache";
191 next-level-cache = <&l3_0>;
197 compatible = "qcom,kryo485";
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 next-level-cache = <&l2_600>;
202 qcom,freq-domain = <&cpufreq_hw 1>;
203 operating-points-v2 = <&cpu4_opp_table>;
204 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
205 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
206 power-domains = <&cpu_pd6>;
207 power-domain-names = "psci";
208 #cooling-cells = <2>;
209 clocks = <&cpufreq_hw 1>;
212 compatible = "cache";
215 next-level-cache = <&l3_0>;
221 compatible = "qcom,kryo485";
223 enable-method = "psci";
224 capacity-dmips-mhz = <1024>;
225 next-level-cache = <&l2_700>;
226 qcom,freq-domain = <&cpufreq_hw 1>;
227 operating-points-v2 = <&cpu4_opp_table>;
228 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
229 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
230 power-domains = <&cpu_pd7>;
231 power-domain-names = "psci";
232 #cooling-cells = <2>;
233 clocks = <&cpufreq_hw 1>;
236 compatible = "cache";
239 next-level-cache = <&l3_0>;
280 entry-method = "psci";
282 little_cpu_sleep_0: cpu-sleep-0-0 {
283 compatible = "arm,idle-state";
284 arm,psci-suspend-param = <0x40000004>;
285 entry-latency-us = <355>;
286 exit-latency-us = <909>;
287 min-residency-us = <3934>;
291 big_cpu_sleep_0: cpu-sleep-1-0 {
292 compatible = "arm,idle-state";
293 arm,psci-suspend-param = <0x40000004>;
294 entry-latency-us = <2411>;
295 exit-latency-us = <1461>;
296 min-residency-us = <4488>;
302 cluster_sleep_apss_off: cluster-sleep-0 {
303 compatible = "domain-idle-state";
304 arm,psci-suspend-param = <0x41000044>;
305 entry-latency-us = <3300>;
306 exit-latency-us = <3300>;
307 min-residency-us = <6000>;
310 cluster_sleep_aoss_sleep: cluster-sleep-1 {
311 compatible = "domain-idle-state";
312 arm,psci-suspend-param = <0x4100a344>;
313 entry-latency-us = <3263>;
314 exit-latency-us = <6562>;
315 min-residency-us = <9987>;
320 cpu0_opp_table: opp-table-cpu0 {
321 compatible = "operating-points-v2";
325 opp-hz = /bits/ 64 <300000000>;
326 opp-peak-kBps = <800000 9600000>;
330 opp-hz = /bits/ 64 <422400000>;
331 opp-peak-kBps = <800000 9600000>;
335 opp-hz = /bits/ 64 <537600000>;
336 opp-peak-kBps = <800000 12902400>;
340 opp-hz = /bits/ 64 <652800000>;
341 opp-peak-kBps = <800000 12902400>;
345 opp-hz = /bits/ 64 <768000000>;
346 opp-peak-kBps = <800000 15974400>;
350 opp-hz = /bits/ 64 <883200000>;
351 opp-peak-kBps = <1804000 19660800>;
355 opp-hz = /bits/ 64 <998400000>;
356 opp-peak-kBps = <1804000 19660800>;
360 opp-hz = /bits/ 64 <1113600000>;
361 opp-peak-kBps = <1804000 22732800>;
365 opp-hz = /bits/ 64 <1228800000>;
366 opp-peak-kBps = <1804000 22732800>;
370 opp-hz = /bits/ 64 <1363200000>;
371 opp-peak-kBps = <2188000 25804800>;
375 opp-hz = /bits/ 64 <1478400000>;
376 opp-peak-kBps = <2188000 31948800>;
380 opp-hz = /bits/ 64 <1574400000>;
381 opp-peak-kBps = <3072000 31948800>;
385 opp-hz = /bits/ 64 <1670400000>;
386 opp-peak-kBps = <3072000 31948800>;
390 opp-hz = /bits/ 64 <1766400000>;
391 opp-peak-kBps = <3072000 31948800>;
395 cpu4_opp_table: opp-table-cpu4 {
396 compatible = "operating-points-v2";
400 opp-hz = /bits/ 64 <825600000>;
401 opp-peak-kBps = <1804000 15974400>;
405 opp-hz = /bits/ 64 <940800000>;
406 opp-peak-kBps = <2188000 19660800>;
410 opp-hz = /bits/ 64 <1056000000>;
411 opp-peak-kBps = <2188000 22732800>;
415 opp-hz = /bits/ 64 <1171200000>;
416 opp-peak-kBps = <3072000 25804800>;
420 opp-hz = /bits/ 64 <1286400000>;
421 opp-peak-kBps = <3072000 31948800>;
425 opp-hz = /bits/ 64 <1420800000>;
426 opp-peak-kBps = <4068000 31948800>;
430 opp-hz = /bits/ 64 <1536000000>;
431 opp-peak-kBps = <4068000 31948800>;
435 opp-hz = /bits/ 64 <1651200000>;
436 opp-peak-kBps = <4068000 40550400>;
440 opp-hz = /bits/ 64 <1766400000>;
441 opp-peak-kBps = <4068000 40550400>;
445 opp-hz = /bits/ 64 <1881600000>;
446 opp-peak-kBps = <4068000 43008000>;
450 opp-hz = /bits/ 64 <1996800000>;
451 opp-peak-kBps = <6220000 43008000>;
455 opp-hz = /bits/ 64 <2131200000>;
456 opp-peak-kBps = <6220000 49152000>;
460 opp-hz = /bits/ 64 <2246400000>;
461 opp-peak-kBps = <7216000 49152000>;
465 opp-hz = /bits/ 64 <2361600000>;
466 opp-peak-kBps = <8368000 49152000>;
470 opp-hz = /bits/ 64 <2457600000>;
471 opp-peak-kBps = <8368000 51609600>;
475 opp-hz = /bits/ 64 <2553600000>;
476 opp-peak-kBps = <8368000 51609600>;
480 opp-hz = /bits/ 64 <2649600000>;
481 opp-peak-kBps = <8368000 51609600>;
485 opp-hz = /bits/ 64 <2745600000>;
486 opp-peak-kBps = <8368000 51609600>;
490 opp-hz = /bits/ 64 <2841600000>;
491 opp-peak-kBps = <8368000 51609600>;
495 opp-hz = /bits/ 64 <2918400000>;
496 opp-peak-kBps = <8368000 51609600>;
500 opp-hz = /bits/ 64 <2995200000>;
501 opp-peak-kBps = <8368000 51609600>;
507 compatible = "qcom,scm-sc8180x", "qcom,scm";
511 camnoc_virt: interconnect-camnoc-virt {
512 compatible = "qcom,sc8180x-camnoc-virt";
513 #interconnect-cells = <2>;
514 qcom,bcm-voters = <&apps_bcm_voter>;
517 mc_virt: interconnect-mc-virt {
518 compatible = "qcom,sc8180x-mc-virt";
519 #interconnect-cells = <2>;
520 qcom,bcm-voters = <&apps_bcm_voter>;
523 qup_virt: interconnect-qup-virt {
524 compatible = "qcom,sc8180x-qup-virt";
525 #interconnect-cells = <2>;
526 qcom,bcm-voters = <&apps_bcm_voter>;
530 device_type = "memory";
531 /* We expect the bootloader to fill in the size */
532 reg = <0x0 0x80000000 0x0 0x0>;
536 compatible = "arm,armv8-pmuv3";
537 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
541 compatible = "arm,psci-1.0";
544 cpu_pd0: power-domain-cpu0 {
545 #power-domain-cells = <0>;
546 power-domains = <&cluster_pd>;
547 domain-idle-states = <&little_cpu_sleep_0>;
550 cpu_pd1: power-domain-cpu1 {
551 #power-domain-cells = <0>;
552 power-domains = <&cluster_pd>;
553 domain-idle-states = <&little_cpu_sleep_0>;
556 cpu_pd2: power-domain-cpu2 {
557 #power-domain-cells = <0>;
558 power-domains = <&cluster_pd>;
559 domain-idle-states = <&little_cpu_sleep_0>;
562 cpu_pd3: power-domain-cpu3 {
563 #power-domain-cells = <0>;
564 power-domains = <&cluster_pd>;
565 domain-idle-states = <&little_cpu_sleep_0>;
568 cpu_pd4: power-domain-cpu4 {
569 #power-domain-cells = <0>;
570 power-domains = <&cluster_pd>;
571 domain-idle-states = <&big_cpu_sleep_0>;
574 cpu_pd5: power-domain-cpu5 {
575 #power-domain-cells = <0>;
576 power-domains = <&cluster_pd>;
577 domain-idle-states = <&big_cpu_sleep_0>;
580 cpu_pd6: power-domain-cpu6 {
581 #power-domain-cells = <0>;
582 power-domains = <&cluster_pd>;
583 domain-idle-states = <&big_cpu_sleep_0>;
586 cpu_pd7: power-domain-cpu7 {
587 #power-domain-cells = <0>;
588 power-domains = <&cluster_pd>;
589 domain-idle-states = <&big_cpu_sleep_0>;
592 cluster_pd: power-domain-cpu-cluster0 {
593 #power-domain-cells = <0>;
594 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
599 #address-cells = <2>;
603 hyp_mem: hyp@85700000 {
604 reg = <0x0 0x85700000 0x0 0x600000>;
608 xbl_mem: xbl@85d00000 {
609 reg = <0x0 0x85d00000 0x0 0x140000>;
613 aop_mem: aop@85f00000 {
614 reg = <0x0 0x85f00000 0x0 0x20000>;
618 aop_cmd_db: cmd-db@85f20000 {
619 compatible = "qcom,cmd-db";
620 reg = <0x0 0x85f20000 0x0 0x20000>;
625 reg = <0x0 0x85f40000 0x0 0x10000>;
629 smem_mem: smem@86000000 {
630 compatible = "qcom,smem";
631 reg = <0x0 0x86000000 0x0 0x200000>;
633 hwlocks = <&tcsr_mutex 3>;
637 reg = <0x0 0x86200000 0x0 0x3900000>;
642 reg = <0x0 0x89b00000 0x0 0x1c00000>;
647 reg = <0x0 0x9d400000 0x0 0x1000000>;
652 reg = <0x0 0x9e400000 0x0 0x1400000>;
657 reg = <0x0 0x9f800000 0x0 0x800000>;
663 compatible = "qcom,smp2p";
664 qcom,smem = <94>, <432>;
666 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
668 mboxes = <&apss_shared 6>;
670 qcom,local-pid = <0>;
671 qcom,remote-pid = <5>;
673 cdsp_smp2p_out: master-kernel {
674 qcom,entry-name = "master-kernel";
675 #qcom,smem-state-cells = <1>;
678 cdsp_smp2p_in: slave-kernel {
679 qcom,entry-name = "slave-kernel";
681 interrupt-controller;
682 #interrupt-cells = <2>;
687 compatible = "qcom,smp2p";
688 qcom,smem = <443>, <429>;
690 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
692 mboxes = <&apss_shared 10>;
694 qcom,local-pid = <0>;
695 qcom,remote-pid = <2>;
697 adsp_smp2p_out: master-kernel {
698 qcom,entry-name = "master-kernel";
699 #qcom,smem-state-cells = <1>;
702 adsp_smp2p_in: slave-kernel {
703 qcom,entry-name = "slave-kernel";
705 interrupt-controller;
706 #interrupt-cells = <2>;
711 compatible = "qcom,smp2p";
712 qcom,smem = <435>, <428>;
714 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
716 mboxes = <&apss_shared 14>;
718 qcom,local-pid = <0>;
719 qcom,remote-pid = <1>;
721 modem_smp2p_out: master-kernel {
722 qcom,entry-name = "master-kernel";
723 #qcom,smem-state-cells = <1>;
726 modem_smp2p_in: slave-kernel {
727 qcom,entry-name = "slave-kernel";
729 interrupt-controller;
730 #interrupt-cells = <2>;
733 modem_smp2p_ipa_out: ipa-ap-to-modem {
734 qcom,entry-name = "ipa";
735 #qcom,smem-state-cells = <1>;
738 modem_smp2p_ipa_in: ipa-modem-to-ap {
739 qcom,entry-name = "ipa";
740 interrupt-controller;
741 #interrupt-cells = <2>;
744 modem_smp2p_wlan_in: wlan-wpss-to-ap {
745 qcom,entry-name = "wlan";
746 interrupt-controller;
747 #interrupt-cells = <2>;
752 compatible = "qcom,smp2p";
753 qcom,smem = <481>, <430>;
755 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
757 mboxes = <&apss_shared 26>;
759 qcom,local-pid = <0>;
760 qcom,remote-pid = <3>;
762 slpi_smp2p_out: master-kernel {
763 qcom,entry-name = "master-kernel";
764 #qcom,smem-state-cells = <1>;
767 slpi_smp2p_in: slave-kernel {
768 qcom,entry-name = "slave-kernel";
770 interrupt-controller;
771 #interrupt-cells = <2>;
776 compatible = "simple-bus";
777 #address-cells = <2>;
779 ranges = <0 0 0 0 0x10 0>;
780 dma-ranges = <0 0 0 0 0x10 0>;
782 gcc: clock-controller@100000 {
783 compatible = "qcom,gcc-sc8180x";
784 reg = <0x0 0x00100000 0x0 0x1f0000>;
787 #power-domain-cells = <1>;
788 clocks = <&rpmhcc RPMH_CXO_CLK>,
789 <&rpmhcc RPMH_CXO_CLK_A>,
791 clock-names = "bi_tcxo",
794 power-domains = <&rpmhpd SC8180X_CX>;
797 qupv3_id_0: geniqup@8c0000 {
798 compatible = "qcom,geni-se-qup";
799 reg = <0 0x008c0000 0 0x6000>;
800 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
801 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
802 clock-names = "m-ahb", "s-ahb";
803 #address-cells = <2>;
806 iommus = <&apps_smmu 0x4c3 0>;
810 compatible = "qcom,geni-i2c";
811 reg = <0 0x00880000 0 0x4000>;
812 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
814 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
815 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
816 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
817 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
819 #address-cells = <1>;
825 compatible = "qcom,geni-spi";
826 reg = <0 0x00880000 0 0x4000>;
827 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
829 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
830 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
831 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
832 interconnect-names = "qup-core", "qup-config";
833 #address-cells = <1>;
838 uart0: serial@880000 {
839 compatible = "qcom,geni-uart";
840 reg = <0 0x00880000 0 0x4000>;
841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
843 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
844 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
845 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
846 interconnect-names = "qup-core", "qup-config";
851 compatible = "qcom,geni-i2c";
852 reg = <0 0x00884000 0 0x4000>;
853 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
855 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
856 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
857 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
858 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
859 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 #address-cells = <1>;
866 compatible = "qcom,geni-spi";
867 reg = <0 0x00884000 0 0x4000>;
868 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
870 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
871 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
872 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
873 interconnect-names = "qup-core", "qup-config";
874 #address-cells = <1>;
879 uart1: serial@884000 {
880 compatible = "qcom,geni-uart";
881 reg = <0 0x00884000 0 0x4000>;
882 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
884 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
885 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
886 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
887 interconnect-names = "qup-core", "qup-config";
892 compatible = "qcom,geni-i2c";
893 reg = <0 0x00888000 0 0x4000>;
894 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
896 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
898 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
899 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
900 interconnect-names = "qup-core", "qup-config", "qup-memory";
901 #address-cells = <1>;
907 compatible = "qcom,geni-spi";
908 reg = <0 0x00888000 0 0x4000>;
909 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
911 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
912 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
913 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
914 interconnect-names = "qup-core", "qup-config";
915 #address-cells = <1>;
920 uart2: serial@888000 {
921 compatible = "qcom,geni-uart";
922 reg = <0 0x00888000 0 0x4000>;
923 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
925 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
926 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
927 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
928 interconnect-names = "qup-core", "qup-config";
933 compatible = "qcom,geni-i2c";
934 reg = <0 0x0088c000 0 0x4000>;
935 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
937 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
938 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
939 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
940 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
941 interconnect-names = "qup-core", "qup-config", "qup-memory";
942 #address-cells = <1>;
948 compatible = "qcom,geni-spi";
949 reg = <0 0x0088c000 0 0x4000>;
950 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
952 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
953 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
954 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
955 interconnect-names = "qup-core", "qup-config";
956 #address-cells = <1>;
961 uart3: serial@88c000 {
962 compatible = "qcom,geni-uart";
963 reg = <0 0x0088c000 0 0x4000>;
964 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
966 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
967 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
968 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
969 interconnect-names = "qup-core", "qup-config";
974 compatible = "qcom,geni-i2c";
975 reg = <0 0x00890000 0 0x4000>;
976 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
978 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
979 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
980 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
981 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
982 interconnect-names = "qup-core", "qup-config", "qup-memory";
983 #address-cells = <1>;
989 compatible = "qcom,geni-spi";
990 reg = <0 0x00890000 0 0x4000>;
991 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
993 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
994 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
995 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
996 interconnect-names = "qup-core", "qup-config";
997 #address-cells = <1>;
1002 uart4: serial@890000 {
1003 compatible = "qcom,geni-uart";
1004 reg = <0 0x00890000 0 0x4000>;
1005 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1007 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1008 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1009 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1010 interconnect-names = "qup-core", "qup-config";
1011 status = "disabled";
1015 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00894000 0 0x4000>;
1017 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1020 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1021 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1022 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1023 interconnect-names = "qup-core", "qup-config", "qup-memory";
1024 #address-cells = <1>;
1026 status = "disabled";
1030 compatible = "qcom,geni-spi";
1031 reg = <0 0x00894000 0 0x4000>;
1032 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1034 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1035 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1037 interconnect-names = "qup-core", "qup-config";
1038 #address-cells = <1>;
1040 status = "disabled";
1043 uart5: serial@894000 {
1044 compatible = "qcom,geni-uart";
1045 reg = <0 0x00894000 0 0x4000>;
1046 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1048 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1049 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1050 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1051 interconnect-names = "qup-core", "qup-config";
1052 status = "disabled";
1056 compatible = "qcom,geni-i2c";
1057 reg = <0 0x00898000 0 0x4000>;
1058 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1060 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1062 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1063 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1064 interconnect-names = "qup-core", "qup-config", "qup-memory";
1065 #address-cells = <1>;
1067 status = "disabled";
1071 compatible = "qcom,geni-spi";
1072 reg = <0 0x00898000 0 0x4000>;
1073 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1075 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1076 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1077 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1078 interconnect-names = "qup-core", "qup-config";
1079 #address-cells = <1>;
1081 status = "disabled";
1084 uart6: serial@898000 {
1085 compatible = "qcom,geni-uart";
1086 reg = <0 0x00898000 0 0x4000>;
1087 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1089 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1090 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1091 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1092 interconnect-names = "qup-core", "qup-config";
1093 status = "disabled";
1097 compatible = "qcom,geni-i2c";
1098 reg = <0 0x0089c000 0 0x4000>;
1099 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1101 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1102 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1104 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1105 interconnect-names = "qup-core", "qup-config", "qup-memory";
1106 #address-cells = <1>;
1108 status = "disabled";
1112 compatible = "qcom,geni-spi";
1113 reg = <0 0x0089c000 0 0x4000>;
1114 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1116 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1117 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1118 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1119 interconnect-names = "qup-core", "qup-config";
1120 #address-cells = <1>;
1122 status = "disabled";
1125 uart7: serial@89c000 {
1126 compatible = "qcom,geni-uart";
1127 reg = <0 0x0089c000 0 0x4000>;
1128 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1130 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1132 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1133 interconnect-names = "qup-core", "qup-config";
1134 status = "disabled";
1138 qupv3_id_1: geniqup@ac0000 {
1139 compatible = "qcom,geni-se-qup";
1140 reg = <0x0 0x00ac0000 0x0 0x6000>;
1141 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1142 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1143 clock-names = "m-ahb", "s-ahb";
1144 #address-cells = <2>;
1147 iommus = <&apps_smmu 0x603 0>;
1148 status = "disabled";
1151 compatible = "qcom,geni-i2c";
1152 reg = <0 0x00a80000 0 0x4000>;
1153 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1155 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1156 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1157 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1158 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1160 #address-cells = <1>;
1162 status = "disabled";
1166 compatible = "qcom,geni-spi";
1167 reg = <0 0x00a80000 0 0x4000>;
1168 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1170 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1171 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1172 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1173 interconnect-names = "qup-core", "qup-config";
1174 #address-cells = <1>;
1176 status = "disabled";
1179 uart8: serial@a80000 {
1180 compatible = "qcom,geni-uart";
1181 reg = <0 0x00a80000 0 0x4000>;
1182 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1184 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1185 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1186 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1187 interconnect-names = "qup-core", "qup-config";
1188 status = "disabled";
1192 compatible = "qcom,geni-i2c";
1193 reg = <0 0x00a84000 0 0x4000>;
1194 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1196 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1198 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1200 interconnect-names = "qup-core", "qup-config", "qup-memory";
1201 #address-cells = <1>;
1203 status = "disabled";
1207 compatible = "qcom,geni-spi";
1208 reg = <0 0x00a84000 0 0x4000>;
1209 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1211 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1212 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1214 interconnect-names = "qup-core", "qup-config";
1215 #address-cells = <1>;
1217 status = "disabled";
1220 uart9: serial@a84000 {
1221 compatible = "qcom,geni-debug-uart";
1222 reg = <0 0x00a84000 0 0x4000>;
1223 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1225 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1226 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1227 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1228 interconnect-names = "qup-core", "qup-config";
1229 status = "disabled";
1233 compatible = "qcom,geni-i2c";
1234 reg = <0 0x00a88000 0 0x4000>;
1235 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1237 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1238 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1239 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1240 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1241 interconnect-names = "qup-core", "qup-config", "qup-memory";
1242 #address-cells = <1>;
1244 status = "disabled";
1248 compatible = "qcom,geni-spi";
1249 reg = <0 0x00a88000 0 0x4000>;
1250 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1252 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1253 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1255 interconnect-names = "qup-core", "qup-config";
1256 #address-cells = <1>;
1258 status = "disabled";
1261 uart10: serial@a88000 {
1262 compatible = "qcom,geni-uart";
1263 reg = <0 0x00a88000 0 0x4000>;
1264 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1266 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1267 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1268 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1269 interconnect-names = "qup-core", "qup-config";
1270 status = "disabled";
1274 compatible = "qcom,geni-i2c";
1275 reg = <0 0x00a8c000 0 0x4000>;
1276 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1278 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1279 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1280 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1281 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1282 interconnect-names = "qup-core", "qup-config", "qup-memory";
1283 #address-cells = <1>;
1285 status = "disabled";
1289 compatible = "qcom,geni-spi";
1290 reg = <0 0x00a8c000 0 0x4000>;
1291 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1293 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1294 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1296 interconnect-names = "qup-core", "qup-config";
1297 #address-cells = <1>;
1299 status = "disabled";
1302 uart11: serial@a8c000 {
1303 compatible = "qcom,geni-uart";
1304 reg = <0 0x00a8c000 0 0x4000>;
1305 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1307 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1310 interconnect-names = "qup-core", "qup-config";
1311 status = "disabled";
1315 compatible = "qcom,geni-i2c";
1316 reg = <0 0x00a90000 0 0x4000>;
1317 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1320 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1321 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1322 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1323 interconnect-names = "qup-core", "qup-config", "qup-memory";
1324 #address-cells = <1>;
1326 status = "disabled";
1330 compatible = "qcom,geni-spi";
1331 reg = <0 0x00a90000 0 0x4000>;
1332 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1334 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1335 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1336 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1337 interconnect-names = "qup-core", "qup-config";
1338 #address-cells = <1>;
1340 status = "disabled";
1343 uart12: serial@a90000 {
1344 compatible = "qcom,geni-uart";
1345 reg = <0 0x00a90000 0 0x4000>;
1346 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1348 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1349 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1350 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1351 interconnect-names = "qup-core", "qup-config";
1352 status = "disabled";
1356 compatible = "qcom,geni-i2c";
1357 reg = <0 0x00a94000 0 0x4000>;
1358 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1362 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1363 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1364 interconnect-names = "qup-core", "qup-config", "qup-memory";
1365 #address-cells = <1>;
1367 status = "disabled";
1371 compatible = "qcom,geni-spi";
1372 reg = <0 0x00a94000 0 0x4000>;
1373 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1375 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1376 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1377 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1378 interconnect-names = "qup-core", "qup-config";
1379 #address-cells = <1>;
1381 status = "disabled";
1384 uart16: serial@a94000 {
1385 compatible = "qcom,geni-uart";
1386 reg = <0 0x00a94000 0 0x4000>;
1387 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1389 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1390 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1391 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1392 interconnect-names = "qup-core", "qup-config";
1393 status = "disabled";
1397 qupv3_id_2: geniqup@cc0000 {
1398 compatible = "qcom,geni-se-qup";
1399 reg = <0x0 0x00cc0000 0x0 0x6000>;
1400 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1401 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1402 clock-names = "m-ahb", "s-ahb";
1403 #address-cells = <2>;
1406 iommus = <&apps_smmu 0x7a3 0>;
1407 status = "disabled";
1410 compatible = "qcom,geni-i2c";
1411 reg = <0 0x00c80000 0 0x4000>;
1412 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1414 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1415 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1416 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1417 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1418 interconnect-names = "qup-core", "qup-config", "qup-memory";
1419 #address-cells = <1>;
1421 status = "disabled";
1425 compatible = "qcom,geni-spi";
1426 reg = <0 0x00c80000 0 0x4000>;
1427 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1429 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1430 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1431 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1432 interconnect-names = "qup-core", "qup-config";
1433 #address-cells = <1>;
1435 status = "disabled";
1438 uart17: serial@c80000 {
1439 compatible = "qcom,geni-uart";
1440 reg = <0 0x00c80000 0 0x4000>;
1441 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1443 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1444 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1445 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1446 interconnect-names = "qup-core", "qup-config";
1447 status = "disabled";
1451 compatible = "qcom,geni-i2c";
1452 reg = <0 0x00c84000 0 0x4000>;
1453 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1455 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1456 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1457 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1458 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1459 interconnect-names = "qup-core", "qup-config", "qup-memory";
1460 #address-cells = <1>;
1462 status = "disabled";
1466 compatible = "qcom,geni-spi";
1467 reg = <0 0x00c84000 0 0x4000>;
1468 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1470 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1471 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1472 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1473 interconnect-names = "qup-core", "qup-config";
1474 #address-cells = <1>;
1476 status = "disabled";
1479 uart18: serial@c84000 {
1480 compatible = "qcom,geni-uart";
1481 reg = <0 0x00c84000 0 0x4000>;
1482 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1484 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1485 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1486 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1487 interconnect-names = "qup-core", "qup-config";
1488 status = "disabled";
1492 compatible = "qcom,geni-i2c";
1493 reg = <0 0x00c88000 0 0x4000>;
1494 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1496 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1497 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1498 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1499 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1500 interconnect-names = "qup-core", "qup-config", "qup-memory";
1501 #address-cells = <1>;
1503 status = "disabled";
1507 compatible = "qcom,geni-spi";
1508 reg = <0 0x00c88000 0 0x4000>;
1509 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1511 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1512 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1513 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1514 interconnect-names = "qup-core", "qup-config";
1515 #address-cells = <1>;
1517 status = "disabled";
1520 uart19: serial@c88000 {
1521 compatible = "qcom,geni-uart";
1522 reg = <0 0x00c88000 0 0x4000>;
1523 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1525 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1526 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1528 interconnect-names = "qup-core", "qup-config";
1529 status = "disabled";
1533 compatible = "qcom,geni-i2c";
1534 reg = <0 0x00c8c000 0 0x4000>;
1535 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1537 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1538 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1539 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1540 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1541 interconnect-names = "qup-core", "qup-config", "qup-memory";
1542 #address-cells = <1>;
1544 status = "disabled";
1548 compatible = "qcom,geni-spi";
1549 reg = <0 0x00c8c000 0 0x4000>;
1550 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1552 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1553 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1554 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1555 interconnect-names = "qup-core", "qup-config";
1556 #address-cells = <1>;
1558 status = "disabled";
1561 uart13: serial@c8c000 {
1562 compatible = "qcom,geni-uart";
1563 reg = <0 0x00c8c000 0 0x4000>;
1564 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1566 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1567 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1568 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1569 interconnect-names = "qup-core", "qup-config";
1570 status = "disabled";
1574 compatible = "qcom,geni-i2c";
1575 reg = <0 0x00c90000 0 0x4000>;
1576 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1578 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1579 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1580 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1581 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1582 interconnect-names = "qup-core", "qup-config", "qup-memory";
1583 #address-cells = <1>;
1585 status = "disabled";
1589 compatible = "qcom,geni-spi";
1590 reg = <0 0x00c90000 0 0x4000>;
1591 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1593 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1594 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1596 interconnect-names = "qup-core", "qup-config";
1597 #address-cells = <1>;
1599 status = "disabled";
1602 uart14: serial@c90000 {
1603 compatible = "qcom,geni-uart";
1604 reg = <0 0x00c90000 0 0x4000>;
1605 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1607 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1608 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1609 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1610 interconnect-names = "qup-core", "qup-config";
1611 status = "disabled";
1615 compatible = "qcom,geni-i2c";
1616 reg = <0 0x00c94000 0 0x4000>;
1617 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1619 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1620 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1621 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1622 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1623 interconnect-names = "qup-core", "qup-config", "qup-memory";
1624 #address-cells = <1>;
1626 status = "disabled";
1630 compatible = "qcom,geni-spi";
1631 reg = <0 0x00c94000 0 0x4000>;
1632 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1634 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1635 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1636 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1637 interconnect-names = "qup-core", "qup-config";
1638 #address-cells = <1>;
1640 status = "disabled";
1643 uart15: serial@c94000 {
1644 compatible = "qcom,geni-uart";
1645 reg = <0 0x00c94000 0 0x4000>;
1646 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1648 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1649 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1650 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1651 interconnect-names = "qup-core", "qup-config";
1652 status = "disabled";
1656 config_noc: interconnect@1500000 {
1657 compatible = "qcom,sc8180x-config-noc";
1658 reg = <0 0x01500000 0 0x7400>;
1659 #interconnect-cells = <2>;
1660 qcom,bcm-voters = <&apps_bcm_voter>;
1663 system_noc: interconnect@1620000 {
1664 compatible = "qcom,sc8180x-system-noc";
1665 reg = <0 0x01620000 0 0x19400>;
1666 #interconnect-cells = <2>;
1667 qcom,bcm-voters = <&apps_bcm_voter>;
1670 aggre1_noc: interconnect@16e0000 {
1671 compatible = "qcom,sc8180x-aggre1-noc";
1672 reg = <0 0x016e0000 0 0xd080>;
1673 #interconnect-cells = <2>;
1674 qcom,bcm-voters = <&apps_bcm_voter>;
1677 aggre2_noc: interconnect@1700000 {
1678 compatible = "qcom,sc8180x-aggre2-noc";
1679 reg = <0 0x01700000 0 0x20000>;
1680 #interconnect-cells = <2>;
1681 qcom,bcm-voters = <&apps_bcm_voter>;
1684 compute_noc: interconnect@1720000 {
1685 compatible = "qcom,sc8180x-compute-noc";
1686 reg = <0 0x01720000 0 0x7000>;
1687 #interconnect-cells = <2>;
1688 qcom,bcm-voters = <&apps_bcm_voter>;
1691 mmss_noc: interconnect@1740000 {
1692 compatible = "qcom,sc8180x-mmss-noc";
1693 reg = <0 0x01740000 0 0x1c100>;
1694 #interconnect-cells = <2>;
1695 qcom,bcm-voters = <&apps_bcm_voter>;
1698 pcie0: pcie@1c00000 {
1699 compatible = "qcom,pcie-sc8180x";
1700 reg = <0 0x01c00000 0 0x3000>,
1701 <0 0x60000000 0 0xf1d>,
1702 <0 0x60000f20 0 0xa8>,
1703 <0 0x60001000 0 0x1000>,
1704 <0 0x60100000 0 0x100000>;
1710 device_type = "pci";
1711 linux,pci-domain = <0>;
1712 bus-range = <0x00 0xff>;
1715 #address-cells = <3>;
1718 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1719 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1721 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1722 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1725 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1729 interrupt-names = "msi0",
1737 #interrupt-cells = <1>;
1738 interrupt-map-mask = <0 0 0 0x7>;
1739 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1740 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1741 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1742 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1744 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1745 <&gcc GCC_PCIE_0_AUX_CLK>,
1746 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1747 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1748 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1749 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1750 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1751 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1752 clock-names = "pipe",
1761 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1762 assigned-clock-rates = <19200000>;
1764 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1765 <0x100 &apps_smmu 0x1d81 0x1>;
1767 resets = <&gcc GCC_PCIE_0_BCR>;
1768 reset-names = "pci";
1770 power-domains = <&gcc PCIE_0_GDSC>;
1772 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1773 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1774 interconnect-names = "pcie-mem", "cpu-pcie";
1776 phys = <&pcie0_phy>;
1777 phy-names = "pciephy";
1780 status = "disabled";
1783 device_type = "pci";
1784 reg = <0x0 0x0 0x0 0x0 0x0>;
1785 bus-range = <0x01 0xff>;
1787 #address-cells = <3>;
1793 pcie0_phy: phy@1c06000 {
1794 compatible = "qcom,sc8180x-qmp-pcie-phy";
1795 reg = <0 0x01c06000 0 0x1000>;
1796 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1797 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1798 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1799 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>,
1800 <&gcc GCC_PCIE_0_PIPE_CLK>;
1801 clock-names = "aux",
1807 clock-output-names = "pcie_0_pipe_clk";
1810 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1811 reset-names = "phy";
1813 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1814 assigned-clock-rates = <100000000>;
1816 status = "disabled";
1819 pcie3: pcie@1c08000 {
1820 compatible = "qcom,pcie-sc8180x";
1821 reg = <0 0x01c08000 0 0x3000>,
1822 <0 0x40000000 0 0xf1d>,
1823 <0 0x40000f20 0 0xa8>,
1824 <0 0x40001000 0 0x1000>,
1825 <0 0x40100000 0 0x100000>;
1831 device_type = "pci";
1832 linux,pci-domain = <3>;
1833 bus-range = <0x00 0xff>;
1836 #address-cells = <3>;
1839 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1840 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1842 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1850 interrupt-names = "msi0",
1858 #interrupt-cells = <1>;
1859 interrupt-map-mask = <0 0 0 0x7>;
1860 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1861 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1862 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1863 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1865 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1866 <&gcc GCC_PCIE_3_AUX_CLK>,
1867 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1868 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1869 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1870 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1871 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1872 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1873 clock-names = "pipe",
1882 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1883 assigned-clock-rates = <19200000>;
1885 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1886 <0x100 &apps_smmu 0x1e01 0x1>;
1888 resets = <&gcc GCC_PCIE_3_BCR>;
1889 reset-names = "pci";
1891 power-domains = <&gcc PCIE_3_GDSC>;
1893 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1894 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>;
1895 interconnect-names = "pcie-mem", "cpu-pcie";
1897 phys = <&pcie3_phy>;
1898 phy-names = "pciephy";
1901 status = "disabled";
1904 device_type = "pci";
1905 reg = <0x0 0x0 0x0 0x0 0x0>;
1906 bus-range = <0x01 0xff>;
1908 #address-cells = <3>;
1914 pcie3_phy: phy@1c0c000 {
1915 compatible = "qcom,sc8180x-qmp-pcie-phy";
1916 reg = <0 0x01c0c000 0 0x1000>;
1917 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1918 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1919 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1920 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>,
1921 <&gcc GCC_PCIE_3_PIPE_CLK>;
1922 clock-names = "aux",
1928 clock-output-names = "pcie_3_pipe_clk";
1932 resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1933 reset-names = "phy";
1935 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1936 assigned-clock-rates = <100000000>;
1938 status = "disabled";
1941 pcie1: pcie@1c10000 {
1942 compatible = "qcom,pcie-sc8180x";
1943 reg = <0 0x01c10000 0 0x3000>,
1944 <0 0x68000000 0 0xf1d>,
1945 <0 0x68000f20 0 0xa8>,
1946 <0 0x68001000 0 0x1000>,
1947 <0 0x68100000 0 0x100000>;
1953 device_type = "pci";
1954 linux,pci-domain = <1>;
1955 bus-range = <0x00 0xff>;
1958 #address-cells = <3>;
1961 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1962 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1964 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>;
1972 interrupt-names = "msi0",
1980 #interrupt-cells = <1>;
1981 interrupt-map-mask = <0 0 0 0x7>;
1982 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1983 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1984 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1985 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1987 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1988 <&gcc GCC_PCIE_1_AUX_CLK>,
1989 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1990 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1991 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1992 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1993 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1994 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1995 clock-names = "pipe",
2004 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2005 assigned-clock-rates = <19200000>;
2007 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2008 <0x100 &apps_smmu 0x1c81 0x1>;
2010 resets = <&gcc GCC_PCIE_1_BCR>;
2011 reset-names = "pci";
2013 power-domains = <&gcc PCIE_1_GDSC>;
2015 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2016 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>;
2017 interconnect-names = "pcie-mem", "cpu-pcie";
2019 phys = <&pcie1_phy>;
2020 phy-names = "pciephy";
2023 status = "disabled";
2026 device_type = "pci";
2027 reg = <0x0 0x0 0x0 0x0 0x0>;
2028 bus-range = <0x01 0xff>;
2030 #address-cells = <3>;
2036 pcie1_phy: phy@1c16000 {
2037 compatible = "qcom,sc8180x-qmp-pcie-phy";
2038 reg = <0 0x01c16000 0 0x1000>;
2039 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2040 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2041 <&gcc GCC_PCIE_1_CLKREF_CLK>,
2042 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>,
2043 <&gcc GCC_PCIE_1_PIPE_CLK>;
2044 clock-names = "aux",
2050 clock-output-names = "pcie_1_pipe_clk";
2054 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2055 reset-names = "phy";
2057 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2058 assigned-clock-rates = <100000000>;
2060 status = "disabled";
2063 pcie2: pcie@1c18000 {
2064 compatible = "qcom,pcie-sc8180x";
2065 reg = <0 0x01c18000 0 0x3000>,
2066 <0 0x70000000 0 0xf1d>,
2067 <0 0x70000f20 0 0xa8>,
2068 <0 0x70001000 0 0x1000>,
2069 <0 0x70100000 0 0x100000>;
2075 device_type = "pci";
2076 linux,pci-domain = <2>;
2077 bus-range = <0x00 0xff>;
2080 #address-cells = <3>;
2083 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2084 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2086 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>;
2094 interrupt-names = "msi0",
2102 #interrupt-cells = <1>;
2103 interrupt-map-mask = <0 0 0 0x7>;
2104 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2105 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2106 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2107 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2109 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2110 <&gcc GCC_PCIE_2_AUX_CLK>,
2111 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2112 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2113 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2114 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2115 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2116 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2117 clock-names = "pipe",
2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2127 assigned-clock-rates = <19200000>;
2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2130 <0x100 &apps_smmu 0x1d01 0x1>;
2132 resets = <&gcc GCC_PCIE_2_BCR>;
2133 reset-names = "pci";
2135 power-domains = <&gcc PCIE_2_GDSC>;
2137 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2138 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>;
2139 interconnect-names = "pcie-mem", "cpu-pcie";
2141 phys = <&pcie2_phy>;
2142 phy-names = "pciephy";
2145 status = "disabled";
2148 device_type = "pci";
2149 reg = <0x0 0x0 0x0 0x0 0x0>;
2150 bus-range = <0x01 0xff>;
2152 #address-cells = <3>;
2158 pcie2_phy: phy@1c1c000 {
2159 compatible = "qcom,sc8180x-qmp-pcie-phy";
2160 reg = <0 0x01c1c000 0 0x1000>;
2161 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2162 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2163 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2164 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>,
2165 <&gcc GCC_PCIE_2_PIPE_CLK>;
2166 clock-names = "aux",
2172 clock-output-names = "pcie_2_pipe_clk";
2176 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2177 reset-names = "phy";
2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2180 assigned-clock-rates = <100000000>;
2182 status = "disabled";
2185 ufs_mem_hc: ufshc@1d84000 {
2186 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2188 reg = <0 0x01d84000 0 0x2500>;
2189 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2190 phys = <&ufs_mem_phy>;
2191 phy-names = "ufsphy";
2192 lanes-per-direction = <2>;
2194 resets = <&gcc GCC_UFS_PHY_BCR>;
2195 reset-names = "rst";
2197 iommus = <&apps_smmu 0x300 0>;
2199 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2200 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2201 <&gcc GCC_UFS_PHY_AHB_CLK>,
2202 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2203 <&rpmhcc RPMH_CXO_CLK>,
2204 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2205 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2206 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2207 clock-names = "core_clk",
2212 "tx_lane0_sync_clk",
2213 "rx_lane0_sync_clk",
2214 "rx_lane1_sync_clk";
2215 freq-table-hz = <37500000 300000000>,
2218 <37500000 300000000>,
2224 power-domains = <&gcc UFS_PHY_GDSC>;
2226 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
2227 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2228 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
2229 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>;
2230 interconnect-names = "ufs-ddr", "cpu-ufs";
2232 status = "disabled";
2235 ufs_mem_phy: phy-wrapper@1d87000 {
2236 compatible = "qcom,sc8180x-qmp-ufs-phy";
2237 reg = <0 0x01d87000 0 0x1000>;
2239 clocks = <&rpmhcc RPMH_CXO_CLK>,
2240 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2241 <&gcc GCC_UFS_MEM_CLKREF_EN>;
2242 clock-names = "ref",
2246 resets = <&ufs_mem_hc 0>;
2247 reset-names = "ufsphy";
2249 power-domains = <&gcc UFS_PHY_GDSC>;
2253 status = "disabled";
2256 tcsr_mutex: hwlock@1f40000 {
2257 compatible = "qcom,tcsr-mutex";
2258 reg = <0x0 0x01f40000 0x0 0x40000>;
2259 #hwlock-cells = <1>;
2263 compatible = "qcom,adreno-680.1", "qcom,adreno";
2265 reg = <0 0x02c00000 0 0x40000>;
2266 reg-names = "kgsl_3d0_reg_memory";
2268 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2270 iommus = <&adreno_smmu 0 0xc01>;
2272 operating-points-v2 = <&gpu_opp_table>;
2274 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2275 interconnect-names = "gfx-mem";
2278 #cooling-cells = <2>;
2280 status = "disabled";
2282 gpu_opp_table: opp-table {
2283 compatible = "operating-points-v2";
2286 opp-hz = /bits/ 64 <514000000>;
2287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2291 opp-hz = /bits/ 64 <500000000>;
2292 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2296 opp-hz = /bits/ 64 <461000000>;
2297 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2301 opp-hz = /bits/ 64 <405000000>;
2302 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2306 opp-hz = /bits/ 64 <315000000>;
2307 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2311 opp-hz = /bits/ 64 <256000000>;
2312 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2316 opp-hz = /bits/ 64 <177000000>;
2317 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2323 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2325 reg = <0 0x02c6a000 0 0x30000>,
2326 <0 0x0b290000 0 0x10000>,
2327 <0 0x0b490000 0 0x10000>;
2332 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2333 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2334 interrupt-names = "hfi", "gmu";
2336 clocks = <&gpucc GPU_CC_AHB_CLK>,
2337 <&gpucc GPU_CC_CX_GMU_CLK>,
2338 <&gpucc GPU_CC_CXO_CLK>,
2339 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2340 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2341 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2343 power-domains = <&gpucc GPU_CX_GDSC>,
2344 <&gpucc GPU_GX_GDSC>;
2345 power-domain-names = "cx", "gx";
2347 iommus = <&adreno_smmu 5 0xc00>;
2349 operating-points-v2 = <&gmu_opp_table>;
2351 gmu_opp_table: opp-table {
2352 compatible = "operating-points-v2";
2355 opp-hz = /bits/ 64 <200000000>;
2356 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2360 opp-hz = /bits/ 64 <500000000>;
2361 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2366 gpucc: clock-controller@2c90000 {
2367 compatible = "qcom,sc8180x-gpucc";
2368 reg = <0 0x02c90000 0 0x9000>;
2369 clocks = <&rpmhcc RPMH_CXO_CLK>,
2370 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2371 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2372 clock-names = "bi_tcxo",
2373 "gcc_gpu_gpll0_clk_src",
2374 "gcc_gpu_gpll0_div_clk_src";
2377 #power-domain-cells = <1>;
2380 adreno_smmu: iommu@2ca0000 {
2381 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2382 "qcom,smmu-500", "arm,mmu-500";
2383 reg = <0 0x02ca0000 0 0x10000>;
2385 #global-interrupts = <1>;
2386 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2387 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2388 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2389 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2390 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2391 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2392 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2395 clocks = <&gpucc GPU_CC_AHB_CLK>,
2396 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2397 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2398 clock-names = "ahb", "bus", "iface";
2400 power-domains = <&gpucc GPU_CX_GDSC>;
2403 tlmm: pinctrl@3100000 {
2404 compatible = "qcom,sc8180x-tlmm";
2405 reg = <0 0x03100000 0 0x300000>,
2406 <0 0x03500000 0 0x700000>,
2407 <0 0x03d00000 0 0x300000>;
2408 reg-names = "west", "east", "south";
2409 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2412 interrupt-controller;
2413 #interrupt-cells = <2>;
2414 gpio-ranges = <&tlmm 0 0 191>;
2415 wakeup-parent = <&pdc>;
2418 remoteproc_mpss: remoteproc@4080000 {
2419 compatible = "qcom,sc8180x-mpss-pas";
2420 reg = <0x0 0x04080000 0x0 0x4040>;
2422 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2423 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2424 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2425 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2426 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2427 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2428 interrupt-names = "wdog", "fatal", "ready", "handover",
2429 "stop-ack", "shutdown-ack";
2431 clocks = <&rpmhcc RPMH_CXO_CLK>;
2434 power-domains = <&rpmhpd SC8180X_CX>,
2435 <&rpmhpd SC8180X_MSS>;
2436 power-domain-names = "cx", "mss";
2438 qcom,qmp = <&aoss_qmp>;
2440 qcom,smem-states = <&modem_smp2p_out 0>;
2441 qcom,smem-state-names = "stop";
2444 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2446 qcom,remote-pid = <1>;
2447 mboxes = <&apss_shared 12>;
2451 remoteproc_cdsp: remoteproc@8300000 {
2452 compatible = "qcom,sc8180x-cdsp-pas";
2453 reg = <0x0 0x08300000 0x0 0x4040>;
2455 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2456 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2457 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2458 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2459 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2460 interrupt-names = "wdog", "fatal", "ready",
2461 "handover", "stop-ack";
2463 clocks = <&rpmhcc RPMH_CXO_CLK>;
2466 power-domains = <&rpmhpd SC8180X_CX>;
2467 power-domain-names = "cx";
2469 qcom,qmp = <&aoss_qmp>;
2471 qcom,smem-states = <&cdsp_smp2p_out 0>;
2472 qcom,smem-state-names = "stop";
2474 status = "disabled";
2477 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2479 qcom,remote-pid = <5>;
2480 mboxes = <&apss_shared 4>;
2484 usb_prim_hsphy: phy@88e2000 {
2485 compatible = "qcom,sc8180x-usb-hs-phy",
2486 "qcom,usb-snps-hs-7nm-phy";
2487 reg = <0 0x088e2000 0 0x400>;
2488 clocks = <&rpmhcc RPMH_CXO_CLK>;
2489 clock-names = "ref";
2490 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2494 status = "disabled";
2497 usb_sec_hsphy: phy@88e3000 {
2498 compatible = "qcom,sc8180x-usb-hs-phy",
2499 "qcom,usb-snps-hs-7nm-phy";
2500 reg = <0 0x088e3000 0 0x400>;
2501 clocks = <&rpmhcc RPMH_CXO_CLK>;
2502 clock-names = "ref";
2503 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2507 status = "disabled";
2510 usb_mp_hsphy0: phy@88e4000 {
2511 compatible = "qcom,sc8180x-usb-hs-phy",
2512 "qcom,usb-snps-hs-7nm-phy";
2513 reg = <0 0x088e4000 0 0x400>;
2516 clocks = <&rpmhcc RPMH_CXO_CLK>;
2517 clock-names = "ref";
2519 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
2521 status = "disabled";
2524 usb_mp_hsphy1: phy@88e5000 {
2525 compatible = "qcom,sc8180x-usb-hs-phy",
2526 "qcom,usb-snps-hs-7nm-phy";
2527 reg = <0 0x088e5000 0 0x400>;
2530 clocks = <&rpmhcc RPMH_CXO_CLK>;
2531 clock-names = "ref";
2533 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
2535 status = "disabled";
2538 usb_prim_qmpphy: phy@88e8000 {
2539 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2540 reg = <0 0x088e8000 0 0x3000>;
2542 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2543 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2544 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2545 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2546 clock-names = "aux",
2551 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2552 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2553 reset-names = "phy", "common";
2558 status = "disabled";
2561 #address-cells = <1>;
2567 usb_prim_qmpphy_out: endpoint {};
2573 usb_prim_qmpphy_usb_ss_in: endpoint {
2574 remote-endpoint = <&usb_prim_dwc3_ss>;
2581 usb_prim_qmpphy_dp_in: endpoint {};
2586 usb_mp_qmpphy0: phy@88eb000 {
2587 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2588 reg = <0 0x088eb000 0 0x1000>;
2590 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2591 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2592 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2593 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2594 clock-names = "aux",
2599 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2600 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2601 reset-names = "phy", "phy_phy";
2603 power-domains = <&gcc USB30_MP_GDSC>;
2606 clock-output-names = "usb2_phy0_pipe_clk";
2610 status = "disabled";
2613 usb_mp_qmpphy1: phy@88ec000 {
2614 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2615 reg = <0 0x088ec000 0 0x1000>;
2617 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2618 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2619 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2620 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2621 clock-names = "aux",
2626 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2627 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2628 reset-names = "phy", "phy_phy";
2630 power-domains = <&gcc USB30_MP_GDSC>;
2633 clock-output-names = "usb2_phy1_pipe_clk";
2637 status = "disabled";
2640 usb_sec_qmpphy: phy@88ee000 {
2641 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2642 reg = <0 0x088ed000 0 0x3000>;
2644 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2645 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2646 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2647 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2648 clock-names = "aux",
2652 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2653 <&gcc GCC_USB3_PHY_SEC_BCR>;
2654 reset-names = "phy", "common";
2659 status = "disabled";
2662 #address-cells = <1>;
2668 usb_sec_qmpphy_out: endpoint {};
2674 usb_sec_qmpphy_usb_ss_in: endpoint {
2675 remote-endpoint = <&usb_sec_dwc3_ss>;
2682 usb_sec_qmpphy_dp_in: endpoint {};
2687 system-cache-controller@9200000 {
2688 compatible = "qcom,sc8180x-llcc";
2689 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
2690 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
2691 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
2692 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
2693 <0 0x09600000 0 0x58000>;
2694 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2695 "llcc3_base", "llcc4_base", "llcc5_base",
2696 "llcc6_base", "llcc7_base", "llcc_broadcast_base";
2697 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2700 gem_noc: interconnect@9680000 {
2701 compatible = "qcom,sc8180x-gem-noc";
2702 reg = <0 0x09680000 0 0x58200>;
2703 #interconnect-cells = <2>;
2704 qcom,bcm-voters = <&apps_bcm_voter>;
2707 usb_mp: usb@a4f8800 {
2708 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2709 reg = <0 0x0a4f8800 0 0x400>;
2710 #address-cells = <2>;
2715 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
2716 <&gcc GCC_USB30_MP_MASTER_CLK>,
2717 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
2718 <&gcc GCC_USB30_MP_SLEEP_CLK>,
2719 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2720 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2721 clock-names = "cfg_noc",
2728 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2729 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
2730 interconnect-names = "usb-ddr", "apps-usb";
2732 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2733 <&gcc GCC_USB30_MP_MASTER_CLK>;
2734 assigned-clock-rates = <19200000>, <200000000>;
2736 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2737 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
2738 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
2739 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
2740 <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
2741 <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
2742 <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
2743 <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
2744 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
2745 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
2746 interrupt-names = "pwr_event_1", "pwr_event_2",
2747 "hs_phy_1", "hs_phy_2",
2748 "dp_hs_phy_1", "dm_hs_phy_1",
2749 "dp_hs_phy_2", "dm_hs_phy_2",
2750 "ss_phy_1", "ss_phy_2";
2752 power-domains = <&gcc USB30_MP_GDSC>;
2754 resets = <&gcc GCC_USB30_MP_BCR>;
2756 status = "disabled";
2758 usb_mp_dwc3: usb@a400000 {
2759 compatible = "snps,dwc3";
2760 reg = <0 0x0a400000 0 0xcd00>;
2761 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
2762 iommus = <&apps_smmu 0x60 0>;
2763 snps,dis_u2_susphy_quirk;
2764 snps,dis_enblslpm_quirk;
2765 snps,dis-u1-entry-quirk;
2766 snps,dis-u2-entry-quirk;
2767 phys = <&usb_mp_hsphy0>,
2771 phy-names = "usb2-0",
2779 usb_prim: usb@a6f8800 {
2780 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2781 reg = <0 0x0a6f8800 0 0x400>;
2782 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2783 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2784 <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
2785 <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
2786 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
2787 interrupt-names = "pwr_event",
2793 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2794 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2795 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2796 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2797 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2798 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2799 clock-names = "cfg_noc",
2805 resets = <&gcc GCC_USB30_PRIM_BCR>;
2806 power-domains = <&gcc USB30_PRIM_GDSC>;
2808 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2809 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2810 interconnect-names = "usb-ddr", "apps-usb";
2812 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2813 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2814 assigned-clock-rates = <19200000>, <200000000>;
2816 #address-cells = <2>;
2821 status = "disabled";
2823 usb_prim_dwc3: usb@a600000 {
2824 compatible = "snps,dwc3";
2825 reg = <0 0x0a600000 0 0xcd00>;
2826 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2827 iommus = <&apps_smmu 0x140 0>;
2828 snps,dis_u2_susphy_quirk;
2829 snps,dis_enblslpm_quirk;
2830 snps,dis-u1-entry-quirk;
2831 snps,dis-u2-entry-quirk;
2832 phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>;
2833 phy-names = "usb2-phy", "usb3-phy";
2836 #address-cells = <1>;
2842 usb_prim_dwc3_hs: endpoint {
2849 usb_prim_dwc3_ss: endpoint {
2850 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2857 usb_sec: usb@a8f8800 {
2858 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2859 reg = <0 0x0a8f8800 0 0x400>;
2861 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2862 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2863 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2864 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2865 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2866 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2867 clock-names = "cfg_noc",
2873 resets = <&gcc GCC_USB30_SEC_BCR>;
2874 power-domains = <&gcc USB30_SEC_GDSC>;
2876 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2877 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2878 <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
2879 <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
2880 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
2881 interrupt-names = "pwr_event",
2887 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2888 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2889 assigned-clock-rates = <19200000>, <200000000>;
2891 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2893 interconnect-names = "usb-ddr", "apps-usb";
2895 #address-cells = <2>;
2900 status = "disabled";
2902 usb_sec_dwc3: usb@a800000 {
2903 compatible = "snps,dwc3";
2904 reg = <0 0x0a800000 0 0xcd00>;
2905 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2906 iommus = <&apps_smmu 0x160 0>;
2907 snps,dis_u2_susphy_quirk;
2908 snps,dis_enblslpm_quirk;
2909 snps,dis-u1-entry-quirk;
2910 snps,dis-u2-entry-quirk;
2911 phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>;
2912 phy-names = "usb2-phy", "usb3-phy";
2915 #address-cells = <1>;
2921 usb_sec_dwc3_hs: endpoint {
2928 usb_sec_dwc3_ss: endpoint {
2929 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2936 mdss: mdss@ae00000 {
2937 compatible = "qcom,sc8180x-mdss";
2938 reg = <0 0x0ae00000 0 0x1000>;
2941 power-domains = <&dispcc MDSS_GDSC>;
2943 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2944 <&gcc GCC_DISP_HF_AXI_CLK>,
2945 <&gcc GCC_DISP_SF_AXI_CLK>,
2946 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2947 clock-names = "iface",
2952 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2954 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2955 interrupt-controller;
2956 #interrupt-cells = <1>;
2958 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS
2959 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2960 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS
2961 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
2962 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS
2963 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>;
2964 interconnect-names = "mdp0-mem",
2968 iommus = <&apps_smmu 0x800 0x420>;
2970 #address-cells = <2>;
2974 status = "disabled";
2976 mdss_mdp: mdp@ae01000 {
2977 compatible = "qcom,sc8180x-dpu";
2978 reg = <0 0x0ae01000 0 0x8f000>,
2979 <0 0x0aeb0000 0 0x2008>;
2980 reg-names = "mdp", "vbif";
2982 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2983 <&gcc GCC_DISP_HF_AXI_CLK>,
2984 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2985 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2986 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2987 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
2988 clock-names = "iface",
2995 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2996 assigned-clock-rates = <19200000>;
2998 operating-points-v2 = <&mdp_opp_table>;
2999 power-domains = <&rpmhpd SC8180X_MMCX>;
3001 interrupt-parent = <&mdss>;
3005 #address-cells = <1>;
3010 dpu_intf0_out: endpoint {
3011 remote-endpoint = <&dp0_in>;
3017 dpu_intf1_out: endpoint {
3018 remote-endpoint = <&mdss_dsi0_in>;
3024 dpu_intf2_out: endpoint {
3025 remote-endpoint = <&mdss_dsi1_in>;
3031 dpu_intf4_out: endpoint {
3032 remote-endpoint = <&dp1_in>;
3038 dpu_intf5_out: endpoint {
3039 remote-endpoint = <&edp_in>;
3044 mdp_opp_table: opp-table {
3045 compatible = "operating-points-v2";
3048 opp-hz = /bits/ 64 <200000000>;
3049 required-opps = <&rpmhpd_opp_low_svs>;
3053 opp-hz = /bits/ 64 <300000000>;
3054 required-opps = <&rpmhpd_opp_svs>;
3058 opp-hz = /bits/ 64 <345000000>;
3059 required-opps = <&rpmhpd_opp_svs_l1>;
3063 opp-hz = /bits/ 64 <460000000>;
3064 required-opps = <&rpmhpd_opp_nom>;
3069 mdss_dsi0: dsi@ae94000 {
3070 compatible = "qcom,mdss-dsi-ctrl";
3071 reg = <0 0x0ae94000 0 0x400>;
3072 reg-names = "dsi_ctrl";
3074 interrupt-parent = <&mdss>;
3077 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3078 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3079 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3080 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3081 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3082 <&gcc GCC_DISP_HF_AXI_CLK>;
3083 clock-names = "byte",
3090 operating-points-v2 = <&dsi_opp_table>;
3091 power-domains = <&rpmhpd SC8180X_MMCX>;
3093 phys = <&mdss_dsi0_phy>;
3096 status = "disabled";
3099 #address-cells = <1>;
3104 mdss_dsi0_in: endpoint {
3105 remote-endpoint = <&dpu_intf1_out>;
3111 mdss_dsi0_out: endpoint {
3116 dsi_opp_table: opp-table {
3117 compatible = "operating-points-v2";
3120 opp-hz = /bits/ 64 <187500000>;
3121 required-opps = <&rpmhpd_opp_low_svs>;
3125 opp-hz = /bits/ 64 <300000000>;
3126 required-opps = <&rpmhpd_opp_svs>;
3130 opp-hz = /bits/ 64 <358000000>;
3131 required-opps = <&rpmhpd_opp_svs_l1>;
3136 mdss_dsi0_phy: dsi-phy@ae94400 {
3137 compatible = "qcom,dsi-phy-7nm";
3138 reg = <0 0x0ae94400 0 0x200>,
3139 <0 0x0ae94600 0 0x280>,
3140 <0 0x0ae94900 0 0x260>;
3141 reg-names = "dsi_phy",
3148 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3149 <&rpmhcc RPMH_CXO_CLK>;
3150 clock-names = "iface", "ref";
3152 status = "disabled";
3155 mdss_dsi1: dsi@ae96000 {
3156 compatible = "qcom,mdss-dsi-ctrl";
3157 reg = <0 0x0ae96000 0 0x400>;
3158 reg-names = "dsi_ctrl";
3160 interrupt-parent = <&mdss>;
3163 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
3164 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
3165 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
3166 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
3167 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3168 <&gcc GCC_DISP_HF_AXI_CLK>;
3169 clock-names = "byte",
3176 operating-points-v2 = <&dsi_opp_table>;
3177 power-domains = <&rpmhpd SC8180X_MMCX>;
3179 phys = <&mdss_dsi1_phy>;
3182 status = "disabled";
3185 #address-cells = <1>;
3190 mdss_dsi1_in: endpoint {
3191 remote-endpoint = <&dpu_intf2_out>;
3197 mdss_dsi1_out: endpoint {
3203 mdss_dsi1_phy: dsi-phy@ae96400 {
3204 compatible = "qcom,dsi-phy-7nm";
3205 reg = <0 0x0ae96400 0 0x200>,
3206 <0 0x0ae96600 0 0x280>,
3207 <0 0x0ae96900 0 0x260>;
3208 reg-names = "dsi_phy",
3215 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3216 <&rpmhcc RPMH_CXO_CLK>;
3217 clock-names = "iface", "ref";
3219 status = "disabled";
3222 mdss_dp0: displayport-controller@ae90000 {
3223 compatible = "qcom,sc8180x-dp";
3224 reg = <0 0xae90000 0 0x200>,
3225 <0 0xae90200 0 0x200>,
3226 <0 0xae90400 0 0x600>,
3227 <0 0xae90a00 0 0x400>,
3228 <0 0xae91000 0 0x400>;
3229 interrupt-parent = <&mdss>;
3231 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3232 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3233 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3234 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3235 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3236 clock-names = "core_iface",
3242 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3243 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3244 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3245 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3247 phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
3250 #sound-dai-cells = <0>;
3252 operating-points-v2 = <&dp0_opp_table>;
3253 power-domains = <&rpmhpd SC8180X_MMCX>;
3255 status = "disabled";
3258 #address-cells = <1>;
3264 remote-endpoint = <&dpu_intf0_out>;
3270 mdss_dp0_out: endpoint {
3275 dp0_opp_table: opp-table {
3276 compatible = "operating-points-v2";
3279 opp-hz = /bits/ 64 <160000000>;
3280 required-opps = <&rpmhpd_opp_low_svs>;
3284 opp-hz = /bits/ 64 <270000000>;
3285 required-opps = <&rpmhpd_opp_svs>;
3289 opp-hz = /bits/ 64 <540000000>;
3290 required-opps = <&rpmhpd_opp_svs_l1>;
3294 opp-hz = /bits/ 64 <810000000>;
3295 required-opps = <&rpmhpd_opp_nom>;
3300 mdss_dp1: displayport-controller@ae98000 {
3301 compatible = "qcom,sc8180x-dp";
3302 reg = <0 0xae98000 0 0x200>,
3303 <0 0xae98200 0 0x200>,
3304 <0 0xae98400 0 0x600>,
3305 <0 0xae98a00 0 0x400>,
3306 <0 0xae99000 0 0x400>;
3307 interrupt-parent = <&mdss>;
3309 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3310 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
3311 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
3312 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
3313 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
3314 clock-names = "core_iface",
3320 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3321 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
3322 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3323 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3325 phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
3328 #sound-dai-cells = <0>;
3330 operating-points-v2 = <&dp0_opp_table>;
3331 power-domains = <&rpmhpd SC8180X_MMCX>;
3333 status = "disabled";
3336 #address-cells = <1>;
3342 remote-endpoint = <&dpu_intf4_out>;
3348 mdss_dp1_out: endpoint {
3353 dp1_opp_table: opp-table {
3354 compatible = "operating-points-v2";
3357 opp-hz = /bits/ 64 <160000000>;
3358 required-opps = <&rpmhpd_opp_low_svs>;
3362 opp-hz = /bits/ 64 <270000000>;
3363 required-opps = <&rpmhpd_opp_svs>;
3367 opp-hz = /bits/ 64 <540000000>;
3368 required-opps = <&rpmhpd_opp_svs_l1>;
3372 opp-hz = /bits/ 64 <810000000>;
3373 required-opps = <&rpmhpd_opp_nom>;
3378 mdss_edp: displayport-controller@ae9a000 {
3379 compatible = "qcom,sc8180x-edp";
3380 reg = <0 0xae9a000 0 0x200>,
3381 <0 0xae9a200 0 0x200>,
3382 <0 0xae9a400 0 0x600>,
3383 <0 0xae9aa00 0 0x400>;
3384 interrupt-parent = <&mdss>;
3386 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3387 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3388 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
3389 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
3390 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
3391 clock-names = "core_iface",
3397 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3398 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
3399 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3404 operating-points-v2 = <&edp_opp_table>;
3405 power-domains = <&rpmhpd SC8180X_MMCX>;
3407 status = "disabled";
3410 #address-cells = <1>;
3416 remote-endpoint = <&dpu_intf5_out>;
3421 edp_opp_table: opp-table {
3422 compatible = "operating-points-v2";
3425 opp-hz = /bits/ 64 <160000000>;
3426 required-opps = <&rpmhpd_opp_low_svs>;
3430 opp-hz = /bits/ 64 <270000000>;
3431 required-opps = <&rpmhpd_opp_svs>;
3435 opp-hz = /bits/ 64 <540000000>;
3436 required-opps = <&rpmhpd_opp_svs_l1>;
3440 opp-hz = /bits/ 64 <810000000>;
3441 required-opps = <&rpmhpd_opp_nom>;
3447 edp_phy: phy@aec2a00 {
3448 compatible = "qcom,sc8180x-edp-phy";
3449 reg = <0 0x0aec2a00 0 0x1c0>,
3450 <0 0x0aec2200 0 0xa0>,
3451 <0 0x0aec2600 0 0xa0>,
3452 <0 0x0aec2000 0 0x19c>;
3454 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3455 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3456 clock-names = "aux", "cfg_ahb";
3458 power-domains = <&rpmhpd SC8180X_MX>;
3464 dispcc: clock-controller@af00000 {
3465 compatible = "qcom,sc8180x-dispcc";
3466 reg = <0 0x0af00000 0 0x20000>;
3467 clocks = <&rpmhcc RPMH_CXO_CLK>,
3472 <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3473 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3476 <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3477 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3478 clock-names = "bi_tcxo",
3479 "dsi0_phy_pll_out_byteclk",
3480 "dsi0_phy_pll_out_dsiclk",
3481 "dsi1_phy_pll_out_byteclk",
3482 "dsi1_phy_pll_out_dsiclk",
3483 "dp_phy_pll_link_clk",
3484 "dp_phy_pll_vco_div_clk",
3485 "edp_phy_pll_link_clk",
3486 "edp_phy_pll_vco_div_clk",
3487 "dptx1_phy_pll_link_clk",
3488 "dptx1_phy_pll_vco_div_clk";
3489 power-domains = <&rpmhpd SC8180X_MMCX>;
3490 required-opps = <&rpmhpd_opp_low_svs>;
3493 #power-domain-cells = <1>;
3496 pdc: interrupt-controller@b220000 {
3497 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3498 reg = <0 0x0b220000 0 0x30000>;
3499 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3500 #interrupt-cells = <2>;
3501 interrupt-parent = <&intc>;
3502 interrupt-controller;
3505 tsens0: thermal-sensor@c263000 {
3506 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3507 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3508 <0 0x0c222000 0 0x1ff>; /* SROT */
3509 #qcom,sensors = <16>;
3510 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3511 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3512 interrupt-names = "uplow", "critical";
3513 #thermal-sensor-cells = <1>;
3516 tsens1: thermal-sensor@c265000 {
3517 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3518 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3519 <0 0x0c223000 0 0x1ff>; /* SROT */
3520 #qcom,sensors = <9>;
3521 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3522 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3523 interrupt-names = "uplow", "critical";
3524 #thermal-sensor-cells = <1>;
3527 aoss_qmp: power-controller@c300000 {
3528 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3529 reg = <0x0 0x0c300000 0x0 0x400>;
3530 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3531 mboxes = <&apss_shared 0>;
3537 compatible = "qcom,rpmh-stats";
3538 reg = <0x0 0x0c3f0000 0x0 0x400>;
3541 spmi_bus: spmi@c440000 {
3542 compatible = "qcom,spmi-pmic-arb";
3543 reg = <0x0 0x0c440000 0x0 0x0001100>,
3544 <0x0 0x0c600000 0x0 0x2000000>,
3545 <0x0 0x0e600000 0x0 0x0100000>,
3546 <0x0 0x0e700000 0x0 0x00a0000>,
3547 <0x0 0x0c40a000 0x0 0x0026000>;
3548 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3549 interrupt-names = "periph_irq";
3550 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3553 #address-cells = <2>;
3555 interrupt-controller;
3556 #interrupt-cells = <4>;
3559 apps_smmu: iommu@15000000 {
3560 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3561 reg = <0 0x15000000 0 0x100000>;
3563 #global-interrupts = <1>;
3564 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3565 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3566 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3567 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3568 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3569 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3570 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3571 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3572 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3573 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3574 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3575 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3576 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3577 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3578 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3579 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3580 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3586 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3587 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3588 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3589 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3590 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3591 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3592 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3593 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3594 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3595 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3596 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3597 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3599 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3600 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3601 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3602 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3603 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3604 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3605 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3606 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3607 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3608 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3609 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3610 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3611 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3616 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3617 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3618 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3619 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3620 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3621 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3622 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3623 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3624 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3625 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3626 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3627 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3628 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3629 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3630 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3631 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3632 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3633 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3634 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3635 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3636 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3637 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3638 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3639 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3640 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3641 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3642 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3643 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3644 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3645 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3646 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3647 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3648 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3649 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3650 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3651 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3652 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3653 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3654 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3655 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3656 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3657 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3658 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3659 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
3660 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
3661 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3662 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3663 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
3664 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
3665 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
3666 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
3667 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
3668 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
3669 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
3670 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
3674 remoteproc_adsp: remoteproc@17300000 {
3675 compatible = "qcom,sc8180x-adsp-pas";
3676 reg = <0x0 0x17300000 0x0 0x4040>;
3678 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3679 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3680 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3681 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3682 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3683 interrupt-names = "wdog", "fatal", "ready",
3684 "handover", "stop-ack";
3686 clocks = <&rpmhcc RPMH_CXO_CLK>;
3689 power-domains = <&rpmhpd SC8180X_CX>;
3690 power-domain-names = "cx";
3692 qcom,qmp = <&aoss_qmp>;
3694 qcom,smem-states = <&adsp_smp2p_out 0>;
3695 qcom,smem-state-names = "stop";
3697 status = "disabled";
3699 remoteproc_adsp_glink: glink-edge {
3700 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3702 qcom,remote-pid = <2>;
3703 mboxes = <&apss_shared 8>;
3707 intc: interrupt-controller@17a00000 {
3708 compatible = "arm,gic-v3";
3709 interrupt-controller;
3710 #interrupt-cells = <3>;
3711 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3712 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3714 #redistributor-regions = <1>;
3715 redistributor-stride = <0 0x20000>;
3718 apss_shared: mailbox@17c00000 {
3719 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3720 reg = <0x0 0x17c00000 0x0 0x1000>;
3725 compatible = "arm,armv7-timer-mem";
3726 reg = <0x0 0x17c20000 0x0 0x1000>;
3728 #address-cells = <1>;
3730 ranges = <0 0 0 0x20000000>;
3733 reg = <0x17c21000 0x1000>,
3734 <0x17c22000 0x1000>;
3736 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3737 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3741 reg = <0x17c23000 0x1000>;
3743 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3744 status = "disabled";
3748 reg = <0x17c25000 0x1000>;
3750 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3751 status = "disabled";
3755 reg = <0x17c26000 0x1000>;
3757 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3758 status = "disabled";
3762 reg = <0x17c29000 0x1000>;
3764 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3765 status = "disabled";
3769 reg = <0x17c2b000 0x1000>;
3771 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3772 status = "disabled";
3776 reg = <0x17c2d000 0x1000>;
3778 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3779 status = "disabled";
3783 apps_rsc: rsc@18200000 {
3784 compatible = "qcom,rpmh-rsc";
3785 reg = <0x0 0x18200000 0x0 0x10000>,
3786 <0x0 0x18210000 0x0 0x10000>,
3787 <0x0 0x18220000 0x0 0x10000>;
3788 reg-names = "drv-0", "drv-1", "drv-2";
3789 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3790 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3791 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3792 qcom,tcs-offset = <0xd00>;
3794 qcom,tcs-config = <ACTIVE_TCS 2>,
3799 power-domains = <&cluster_pd>;
3801 apps_bcm_voter: bcm-voter {
3802 compatible = "qcom,bcm-voter";
3805 rpmhcc: clock-controller {
3806 compatible = "qcom,sc8180x-rpmh-clk";
3809 clocks = <&xo_board_clk>;
3812 rpmhpd: power-controller {
3813 compatible = "qcom,sc8180x-rpmhpd";
3814 #power-domain-cells = <1>;
3815 operating-points-v2 = <&rpmhpd_opp_table>;
3817 rpmhpd_opp_table: opp-table {
3818 compatible = "operating-points-v2";
3820 rpmhpd_opp_ret: opp1 {
3821 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3824 rpmhpd_opp_min_svs: opp2 {
3825 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3828 rpmhpd_opp_low_svs: opp3 {
3829 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3832 rpmhpd_opp_svs: opp4 {
3833 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3836 rpmhpd_opp_svs_l1: opp5 {
3837 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3840 rpmhpd_opp_nom: opp6 {
3841 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3844 rpmhpd_opp_nom_l1: opp7 {
3845 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3848 rpmhpd_opp_nom_l2: opp8 {
3849 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3852 rpmhpd_opp_turbo: opp9 {
3853 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3856 rpmhpd_opp_turbo_l1: opp10 {
3857 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3863 osm_l3: interconnect@18321000 {
3864 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3865 reg = <0 0x18321000 0 0x1400>;
3867 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3868 clock-names = "xo", "alternate";
3870 #interconnect-cells = <1>;
3874 compatible = "qcom,sc8180x-lmh";
3875 reg = <0 0x18350800 0 0x400>;
3876 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3878 qcom,lmh-temp-arm-millicelsius = <65000>;
3879 qcom,lmh-temp-low-millicelsius = <94500>;
3880 qcom,lmh-temp-high-millicelsius = <95000>;
3881 interrupt-controller;
3882 #interrupt-cells = <1>;
3886 compatible = "qcom,sc8180x-lmh";
3887 reg = <0 0x18358800 0 0x400>;
3888 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3890 qcom,lmh-temp-arm-millicelsius = <65000>;
3891 qcom,lmh-temp-low-millicelsius = <94500>;
3892 qcom,lmh-temp-high-millicelsius = <95000>;
3893 interrupt-controller;
3894 #interrupt-cells = <1>;
3897 cpufreq_hw: cpufreq@18323000 {
3898 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
3899 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3900 reg-names = "freq-domain0", "freq-domain1";
3902 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3903 clock-names = "xo", "alternate";
3905 #freq-domain-cells = <1>;
3909 wifi: wifi@18800000 {
3910 compatible = "qcom,wcn3990-wifi";
3911 reg = <0 0x18800000 0 0x800000>;
3912 reg-names = "membase";
3913 clock-names = "cxo_ref_clk_pin";
3914 clocks = <&rpmhcc RPMH_RF_CLK2>;
3915 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3916 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3917 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3918 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3919 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3920 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3921 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3922 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3923 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3924 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3925 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3926 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3927 iommus = <&apps_smmu 0x0640 0x1>;
3928 qcom,msa-fixed-perm;
3929 status = "disabled";
3935 polling-delay-passive = <250>;
3937 thermal-sensors = <&tsens0 1>;
3941 temperature = <110000>;
3942 hysteresis = <1000>;
3949 polling-delay-passive = <250>;
3951 thermal-sensors = <&tsens0 2>;
3955 temperature = <110000>;
3956 hysteresis = <1000>;
3963 polling-delay-passive = <250>;
3965 thermal-sensors = <&tsens0 3>;
3969 temperature = <110000>;
3970 hysteresis = <1000>;
3977 polling-delay-passive = <250>;
3979 thermal-sensors = <&tsens0 4>;
3983 temperature = <110000>;
3984 hysteresis = <1000>;
3991 polling-delay-passive = <250>;
3993 thermal-sensors = <&tsens0 7>;
3997 temperature = <110000>;
3998 hysteresis = <1000>;
4005 polling-delay-passive = <250>;
4007 thermal-sensors = <&tsens0 8>;
4011 temperature = <110000>;
4012 hysteresis = <1000>;
4019 polling-delay-passive = <250>;
4021 thermal-sensors = <&tsens0 9>;
4025 temperature = <110000>;
4026 hysteresis = <1000>;
4033 polling-delay-passive = <250>;
4035 thermal-sensors = <&tsens0 10>;
4039 temperature = <110000>;
4040 hysteresis = <1000>;
4046 cpu4-bottom-thermal {
4047 polling-delay-passive = <250>;
4049 thermal-sensors = <&tsens0 11>;
4053 temperature = <110000>;
4054 hysteresis = <1000>;
4060 cpu5-bottom-thermal {
4061 polling-delay-passive = <250>;
4063 thermal-sensors = <&tsens0 12>;
4067 temperature = <110000>;
4068 hysteresis = <1000>;
4074 cpu6-bottom-thermal {
4075 polling-delay-passive = <250>;
4077 thermal-sensors = <&tsens0 13>;
4081 temperature = <110000>;
4082 hysteresis = <1000>;
4088 cpu7-bottom-thermal {
4089 polling-delay-passive = <250>;
4091 thermal-sensors = <&tsens0 14>;
4095 temperature = <110000>;
4096 hysteresis = <1000>;
4103 polling-delay-passive = <250>;
4105 thermal-sensors = <&tsens0 0>;
4109 temperature = <90000>;
4110 hysteresis = <2000>;
4117 polling-delay-passive = <250>;
4119 thermal-sensors = <&tsens0 5>;
4123 temperature = <110000>;
4124 hysteresis = <2000>;
4131 polling-delay-passive = <250>;
4133 thermal-sensors = <&tsens0 6>;
4137 temperature = <110000>;
4138 hysteresis = <2000>;
4145 polling-delay-passive = <250>;
4147 thermal-sensors = <&tsens0 15>;
4151 trip = <&gpu_top_alert0>;
4152 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4157 gpu_top_alert0: trip-point0 {
4158 temperature = <85000>;
4159 hysteresis = <1000>;
4164 temperature = <90000>;
4165 hysteresis = <1000>;
4170 temperature = <110000>;
4171 hysteresis = <1000>;
4178 polling-delay-passive = <250>;
4180 thermal-sensors = <&tsens1 0>;
4184 temperature = <90000>;
4185 hysteresis = <2000>;
4192 polling-delay-passive = <250>;
4194 thermal-sensors = <&tsens1 1>;
4198 temperature = <90000>;
4199 hysteresis = <2000>;
4206 polling-delay-passive = <250>;
4208 thermal-sensors = <&tsens1 2>;
4212 temperature = <90000>;
4213 hysteresis = <2000>;
4220 polling-delay-passive = <250>;
4222 thermal-sensors = <&tsens1 3>;
4226 temperature = <90000>;
4227 hysteresis = <2000>;
4234 polling-delay-passive = <250>;
4236 thermal-sensors = <&tsens1 4>;
4240 temperature = <90000>;
4241 hysteresis = <2000>;
4248 polling-delay-passive = <250>;
4250 thermal-sensors = <&tsens1 5>;
4254 temperature = <90000>;
4255 hysteresis = <2000>;
4262 polling-delay-passive = <250>;
4264 thermal-sensors = <&tsens1 6>;
4268 temperature = <90000>;
4269 hysteresis = <2000>;
4276 polling-delay-passive = <250>;
4278 thermal-sensors = <&tsens1 7>;
4282 temperature = <90000>;
4283 hysteresis = <2000>;
4290 polling-delay-passive = <250>;
4292 thermal-sensors = <&tsens1 8>;
4296 temperature = <90000>;
4297 hysteresis = <2000>;
4303 gpu-bottom-thermal {
4304 polling-delay-passive = <250>;
4306 thermal-sensors = <&tsens1 11>;
4310 trip = <&gpu_bottom_alert0>;
4311 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4316 gpu_bottom_alert0: trip-point0 {
4317 temperature = <85000>;
4318 hysteresis = <1000>;
4323 temperature = <90000>;
4324 hysteresis = <1000>;
4329 temperature = <110000>;
4330 hysteresis = <1000>;
4338 compatible = "arm,armv8-timer";
4339 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4340 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4341 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4342 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;