1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019, Intel Corporation
5 #include "socfpga_agilex.dtsi"
8 model = "SoCFPGA Agilex SoCDK";
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
26 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
31 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
36 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
41 device_type = "memory";
42 /* We expect the bootloader to fill in the reg */
43 reg = <0 0x80000000 0 0>;
56 max-frame-size = <9000>;
61 compatible = "snps,dwmac-mdio";
62 phy0: ethernet-phy@0 {
65 txd0-skew-ps = <0>; /* -420ps */
66 txd1-skew-ps = <0>; /* -420ps */
67 txd2-skew-ps = <0>; /* -420ps */
68 txd3-skew-ps = <0>; /* -420ps */
69 rxd0-skew-ps = <420>; /* 0ps */
70 rxd1-skew-ps = <420>; /* 0ps */
71 rxd2-skew-ps = <420>; /* 0ps */
72 rxd3-skew-ps = <420>; /* 0ps */
73 txen-skew-ps = <0>; /* -420ps */
74 txc-skew-ps = <900>; /* 0ps */
75 rxdv-skew-ps = <420>; /* 0ps */
76 rxc-skew-ps = <1680>; /* 780ps */
86 clk-phase-sd-hs = <0>, <135>;
90 clock-frequency = <25000000>;
109 compatible = "micron,mt25qu02g", "jedec,spi-nor";
111 spi-max-frequency = <100000000>;
114 cdns,read-delay = <2>;
115 cdns,tshsl-ns = <50>;
116 cdns,tsd2d-ns = <50>;
121 compatible = "fixed-partitions";
122 #address-cells = <1>;
125 qspi_boot: partition@0 {
126 label = "Boot and fpga data";
127 reg = <0x0 0x04200000>;
130 root: partition@4200000 {
131 label = "Root Filesystem - UBIFS";
132 reg = <0x04200000 0x0BE00000>;