1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2019 Solarflare Communications Inc.
5 * Copyright 2020-2022 Xilinx Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
14 #include <net/flow_offload.h>
15 #include <linux/rhashtable.h>
16 #include "net_driver.h"
17 #include "tc_counters.h"
19 #define IS_ALL_ONES(v) (!(typeof (v))~(v))
22 static inline bool efx_ipv6_addr_all_ones(struct in6_addr *addr)
24 return !memchr_inv(addr, 0xff, sizeof(*addr));
28 struct efx_tc_action_set {
33 __be16 vlan_tci[2]; /* TCIs for vlan_push */
34 __be16 vlan_proto[2]; /* Ethertypes for vlan_push */
35 struct efx_tc_counter_index *count;
37 u32 fw_id; /* index of this entry in firmware actions table */
38 struct list_head list;
41 struct efx_tc_match_fields {
45 /* L2 (inner when encap) */
47 __be16 vlan_tci[2], vlan_proto[2];
48 u8 eth_saddr[ETH_ALEN], eth_daddr[ETH_ALEN];
50 u8 ip_proto, ip_tos, ip_ttl;
51 __be32 src_ip, dst_ip;
53 struct in6_addr src_ip6, dst_ip6;
55 bool ip_frag, ip_firstfrag;
57 __be16 l4_sport, l4_dport; /* Ports (UDP, TCP) */
59 /* Encap. The following are *outer* fields. Note that there are no
60 * outer eth (L2) fields; this is because TC doesn't have them.
62 __be32 enc_src_ip, enc_dst_ip;
63 struct in6_addr enc_src_ip6, enc_dst_ip6;
64 u8 enc_ip_tos, enc_ip_ttl;
65 __be16 enc_sport, enc_dport;
66 __be32 enc_keyid; /* e.g. VNI, VSID */
69 static inline bool efx_tc_match_is_encap(const struct efx_tc_match_fields *mask)
71 return mask->enc_src_ip || mask->enc_dst_ip ||
72 !ipv6_addr_any(&mask->enc_src_ip6) ||
73 !ipv6_addr_any(&mask->enc_dst_ip6) || mask->enc_ip_tos ||
74 mask->enc_ip_ttl || mask->enc_sport || mask->enc_dport;
77 struct efx_tc_encap_match {
78 __be32 src_ip, dst_ip;
79 struct in6_addr src_ip6, dst_ip6;
81 struct rhash_head linkage;
82 enum efx_encap_type tun_type;
84 u32 fw_id; /* index of this entry in firmware encap match table */
88 struct efx_tc_match_fields value;
89 struct efx_tc_match_fields mask;
90 struct efx_tc_encap_match *encap;
93 struct efx_tc_action_set_list {
94 struct list_head list;
98 struct efx_tc_flow_rule {
100 struct rhash_head linkage;
101 struct efx_tc_match match;
102 struct efx_tc_action_set_list acts;
106 enum efx_tc_rule_prios {
107 EFX_TC_PRIO_TC, /* Rule inserted by TC */
108 EFX_TC_PRIO_DFLT, /* Default switch rule; one of efx_tc_default_rules */
113 * struct efx_tc_state - control plane data for TC offload
115 * @caps: MAE capabilities reported by MCDI
116 * @block_list: List of &struct efx_tc_block_binding
117 * @mutex: Used to serialise operations on TC hashtables
118 * @counter_ht: Hashtable of TC counters (FW IDs and counter values)
119 * @counter_id_ht: Hashtable mapping TC counter cookies to counters
120 * @encap_match_ht: Hashtable of TC encap matches
121 * @match_action_ht: Hashtable of TC match-action rules
122 * @reps_mport_id: MAE port allocated for representor RX
123 * @reps_filter_uc: VNIC filter for representor unicast RX (promisc)
124 * @reps_filter_mc: VNIC filter for representor multicast RX (allmulti)
125 * @reps_mport_vport_id: vport_id for representor RX filters
126 * @flush_counters: counters have been stopped, waiting for drain
127 * @flush_gen: final generation count per type array as reported by
128 * MC_CMD_MAE_COUNTERS_STREAM_STOP
129 * @seen_gen: most recent generation count per type as seen by efx_tc_rx()
130 * @flush_wq: wait queue used by efx_mae_stop_counters() to wait for
131 * MAE counters RXQ to finish draining
132 * @dflt: Match-action rules for default switching; at priority
133 * %EFX_TC_PRIO_DFLT. Named by *ingress* port
134 * @dflt.pf: rule for traffic ingressing from PF (egresses to wire)
135 * @dflt.wire: rule for traffic ingressing from wire (egresses to PF)
136 * @up: have TC datastructures been set up?
138 struct efx_tc_state {
139 struct mae_caps *caps;
140 struct list_head block_list;
142 struct rhashtable counter_ht;
143 struct rhashtable counter_id_ht;
144 struct rhashtable encap_match_ht;
145 struct rhashtable match_action_ht;
146 u32 reps_mport_id, reps_mport_vport_id;
147 s32 reps_filter_uc, reps_filter_mc;
149 u32 flush_gen[EFX_TC_COUNTER_TYPE_MAX];
150 u32 seen_gen[EFX_TC_COUNTER_TYPE_MAX];
151 wait_queue_head_t flush_wq;
153 struct efx_tc_flow_rule pf;
154 struct efx_tc_flow_rule wire;
161 int efx_tc_configure_default_rule_rep(struct efx_rep *efv);
162 void efx_tc_deconfigure_default_rule(struct efx_nic *efx,
163 struct efx_tc_flow_rule *rule);
164 int efx_tc_flower(struct efx_nic *efx, struct net_device *net_dev,
165 struct flow_cls_offload *tc, struct efx_rep *efv);
167 int efx_tc_insert_rep_filters(struct efx_nic *efx);
168 void efx_tc_remove_rep_filters(struct efx_nic *efx);
170 int efx_init_tc(struct efx_nic *efx);
171 void efx_fini_tc(struct efx_nic *efx);
173 int efx_init_struct_tc(struct efx_nic *efx);
174 void efx_fini_struct_tc(struct efx_nic *efx);
176 #endif /* EFX_TC_H */