drivers/net/ethernet/intel/e1000e/hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 #ifndef _E1000E_HW_H_
   5 #define _E1000E_HW_H_
   6
   7 #include "regs.h"
   8 #include "defines.h"
   9
  10 struct e1000_hw;
  11
  12 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  13 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  14 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  15 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  16 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  17 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  19 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  20 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  21 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  22 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  23 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  24 #define E1000_DEV_ID_82572EI                    0x10B9
  25 #define E1000_DEV_ID_82573E                     0x108B
  26 #define E1000_DEV_ID_82573E_IAMT                0x108C
  27 #define E1000_DEV_ID_82573L                     0x109A
  28 #define E1000_DEV_ID_82574L                     0x10D3
  29 #define E1000_DEV_ID_82574LA                    0x10F6
  30 #define E1000_DEV_ID_82583V                     0x150C
  31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
  33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
  34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
  35 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
  36 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
  37 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
  38 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
  39 #define E1000_DEV_ID_ICH8_IFE                   0x104C
  40 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
  41 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
  42 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
  43 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
  44 #define E1000_DEV_ID_ICH9_BM                    0x10E5
  45 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
  46 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
  47 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
  48 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
  49 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
  50 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
  51 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
  52 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
  53 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
  54 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
  55 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
  56 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
  57 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
  58 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
  59 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
  60 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
  61 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
  62 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
  63 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
  64 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
  65 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
  66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
  67 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
  68 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
  69 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
  70 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2  /* Wildcat Point PCH */
  71 #define E1000_DEV_ID_PCH_I218_V3                0x15A3  /* Wildcat Point PCH */
  72 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F  /* SPT PCH */
  73 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570  /* SPT PCH */
  74 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7  /* SPT-H PCH */
  75 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8  /* SPT-H PCH */
  76 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9  /* LBG PCH */
  77 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
  78 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
  79 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
  80 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
  81 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
  82 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
  83 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
  84 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
  85 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
  86 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
  87 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
  88 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
  89 #define E1000_DEV_ID_PCH_CMP_I219_LM10          0x0D4E
  90 #define E1000_DEV_ID_PCH_CMP_I219_V10           0x0D4F
  91 #define E1000_DEV_ID_PCH_CMP_I219_LM11          0x0D4C
  92 #define E1000_DEV_ID_PCH_CMP_I219_V11           0x0D4D
  93 #define E1000_DEV_ID_PCH_CMP_I219_LM12          0x0D53
  94 #define E1000_DEV_ID_PCH_CMP_I219_V12           0x0D55
  95 #define E1000_DEV_ID_PCH_TGP_I219_LM13          0x15FB
  96 #define E1000_DEV_ID_PCH_TGP_I219_V13           0x15FC
  97 #define E1000_DEV_ID_PCH_TGP_I219_LM14          0x15F9
  98 #define E1000_DEV_ID_PCH_TGP_I219_V14           0x15FA
  99 #define E1000_DEV_ID_PCH_TGP_I219_LM15          0x15F4
 100 #define E1000_DEV_ID_PCH_TGP_I219_V15           0x15F5
 101 #define E1000_DEV_ID_PCH_RPL_I219_LM23          0x0DC5
 102 #define E1000_DEV_ID_PCH_RPL_I219_V23           0x0DC6
 103 #define E1000_DEV_ID_PCH_ADP_I219_LM16          0x1A1E
 104 #define E1000_DEV_ID_PCH_ADP_I219_V16           0x1A1F
 105 #define E1000_DEV_ID_PCH_ADP_I219_LM17          0x1A1C
 106 #define E1000_DEV_ID_PCH_ADP_I219_V17           0x1A1D
 107 #define E1000_DEV_ID_PCH_RPL_I219_LM22          0x0DC7
 108 #define E1000_DEV_ID_PCH_RPL_I219_V22           0x0DC8
 109 #define E1000_DEV_ID_PCH_MTP_I219_LM18          0x550A
 110 #define E1000_DEV_ID_PCH_MTP_I219_V18           0x550B
 111 #define E1000_DEV_ID_PCH_MTP_I219_LM19          0x550C
 112 #define E1000_DEV_ID_PCH_MTP_I219_V19           0x550D
 113 #define E1000_DEV_ID_PCH_LNP_I219_LM20          0x550E
 114 #define E1000_DEV_ID_PCH_LNP_I219_V20           0x550F
 115 #define E1000_DEV_ID_PCH_LNP_I219_LM21          0x5510
 116 #define E1000_DEV_ID_PCH_LNP_I219_V21           0x5511
 117 #define E1000_DEV_ID_PCH_ARL_I219_LM24          0x57A0
 118 #define E1000_DEV_ID_PCH_ARL_I219_V24           0x57A1
 119 #define E1000_DEV_ID_PCH_PTP_I219_LM25          0x57B3
 120 #define E1000_DEV_ID_PCH_PTP_I219_V25           0x57B4
 121 #define E1000_DEV_ID_PCH_PTP_I219_LM26          0x57B5
 122 #define E1000_DEV_ID_PCH_PTP_I219_V26           0x57B6
 123 #define E1000_DEV_ID_PCH_PTP_I219_LM27          0x57B7
 124 #define E1000_DEV_ID_PCH_PTP_I219_V27           0x57B8
 125
 126 #define E1000_REVISION_4        4
 127
 128 #define E1000_FUNC_1            1
 129
 130 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 131 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 132
 133 enum e1000_mac_type {
 134         e1000_82571,
 135         e1000_82572,
 136         e1000_82573,
 137         e1000_82574,
 138         e1000_82583,
 139         e1000_80003es2lan,
 140         e1000_ich8lan,
 141         e1000_ich9lan,
 142         e1000_ich10lan,
 143         e1000_pchlan,
 144         e1000_pch2lan,
 145         e1000_pch_lpt,
 146         e1000_pch_spt,
 147         e1000_pch_cnp,
 148         e1000_pch_tgp,
 149         e1000_pch_adp,
 150         e1000_pch_mtp,
 151         e1000_pch_lnp,
 152         e1000_pch_ptp,
 153 };
 154
 155 enum e1000_media_type {
 156         e1000_media_type_unknown = 0,
 157         e1000_media_type_copper = 1,
 158         e1000_media_type_fiber = 2,
 159         e1000_media_type_internal_serdes = 3,
 160         e1000_num_media_types
 161 };
 162
 163 enum e1000_nvm_type {
 164         e1000_nvm_unknown = 0,
 165         e1000_nvm_none,
 166         e1000_nvm_eeprom_spi,
 167         e1000_nvm_flash_hw,
 168         e1000_nvm_flash_sw
 169 };
 170
 171 enum e1000_nvm_override {
 172         e1000_nvm_override_none = 0,
 173         e1000_nvm_override_spi_small,
 174         e1000_nvm_override_spi_large
 175 };
 176
 177 enum e1000_phy_type {
 178         e1000_phy_unknown = 0,
 179         e1000_phy_none,
 180         e1000_phy_m88,
 181         e1000_phy_igp,
 182         e1000_phy_igp_2,
 183         e1000_phy_gg82563,
 184         e1000_phy_igp_3,
 185         e1000_phy_ife,
 186         e1000_phy_bm,
 187         e1000_phy_82578,
 188         e1000_phy_82577,
 189         e1000_phy_82579,
 190         e1000_phy_i217,
 191 };
 192
 193 enum e1000_bus_width {
 194         e1000_bus_width_unknown = 0,
 195         e1000_bus_width_pcie_x1,
 196         e1000_bus_width_pcie_x2,
 197         e1000_bus_width_pcie_x4 = 4,
 198         e1000_bus_width_pcie_x8 = 8,
 199         e1000_bus_width_32,
 200         e1000_bus_width_64,
 201         e1000_bus_width_reserved
 202 };
 203
 204 enum e1000_1000t_rx_status {
 205         e1000_1000t_rx_status_not_ok = 0,
 206         e1000_1000t_rx_status_ok,
 207         e1000_1000t_rx_status_undefined = 0xFF
 208 };
 209
 210 enum e1000_rev_polarity {
 211         e1000_rev_polarity_normal = 0,
 212         e1000_rev_polarity_reversed,
 213         e1000_rev_polarity_undefined = 0xFF
 214 };
 215
 216 enum e1000_fc_mode {
 217         e1000_fc_none = 0,
 218         e1000_fc_rx_pause,
 219         e1000_fc_tx_pause,
 220         e1000_fc_full,
 221         e1000_fc_default = 0xFF
 222 };
 223
 224 enum e1000_ms_type {
 225         e1000_ms_hw_default = 0,
 226         e1000_ms_force_master,
 227         e1000_ms_force_slave,
 228         e1000_ms_auto
 229 };
 230
 231 enum e1000_smart_speed {
 232         e1000_smart_speed_default = 0,
 233         e1000_smart_speed_on,
 234         e1000_smart_speed_off
 235 };
 236
 237 enum e1000_serdes_link_state {
 238         e1000_serdes_link_down = 0,
 239         e1000_serdes_link_autoneg_progress,
 240         e1000_serdes_link_autoneg_complete,
 241         e1000_serdes_link_forced_up
 242 };
 243
 244 /* Receive Descriptor - Extended */
 245 union e1000_rx_desc_extended {
 246         struct {
 247                 __le64 buffer_addr;
 248                 __le64 reserved;
 249         } read;
 250         struct {
 251                 struct {
 252                         __le32 mrq;           /* Multiple Rx Queues */
 253                         union {
 254                                 __le32 rss;         /* RSS Hash */
 255                                 struct {
 256                                         __le16 ip_id;  /* IP id */
 257                                         __le16 csum;   /* Packet Checksum */
 258                                 } csum_ip;
 259                         } hi_dword;
 260                 } lower;
 261                 struct {
 262                         __le32 status_error;     /* ext status/error */
 263                         __le16 length;
 264                         __le16 vlan;         /* VLAN tag */
 265                 } upper;
 266         } wb;  /* writeback */
 267 };
 268
 269 #define MAX_PS_BUFFERS 4
 270
 271 /* Number of packet split data buffers (not including the header buffer) */
 272 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 273
 274 /* Receive Descriptor - Packet Split */
 275 union e1000_rx_desc_packet_split {
 276         struct {
 277                 /* one buffer for protocol header(s), three data buffers */
 278                 __le64 buffer_addr[MAX_PS_BUFFERS];
 279         } read;
 280         struct {
 281                 struct {
 282                         __le32 mrq;           /* Multiple Rx Queues */
 283                         union {
 284                                 __le32 rss;           /* RSS Hash */
 285                                 struct {
 286                                         __le16 ip_id;    /* IP id */
 287                                         __le16 csum;     /* Packet Checksum */
 288                                 } csum_ip;
 289                         } hi_dword;
 290                 } lower;
 291                 struct {
 292                         __le32 status_error;     /* ext status/error */
 293                         __le16 length0;   /* length of buffer 0 */
 294                         __le16 vlan;         /* VLAN tag */
 295                 } middle;
 296                 struct {
 297                         __le16 header_status;
 298                         /* length of buffers 1-3 */
 299                         __le16 length[PS_PAGE_BUFFERS];
 300                 } upper;
 301                 __le64 reserved;
 302         } wb; /* writeback */
 303 };
 304
 305 /* Transmit Descriptor */
 306 struct e1000_tx_desc {
 307         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
 308         union {
 309                 __le32 data;
 310                 struct {
 311                         __le16 length;    /* Data buffer length */
 312                         u8 cso; /* Checksum offset */
 313                         u8 cmd; /* Descriptor control */
 314                 } flags;
 315         } lower;
 316         union {
 317                 __le32 data;
 318                 struct {
 319                         u8 status;     /* Descriptor status */
 320                         u8 css; /* Checksum start */
 321                         __le16 special;
 322                 } fields;
 323         } upper;
 324 };
 325
 326 /* Offload Context Descriptor */
 327 struct e1000_context_desc {
 328         union {
 329                 __le32 ip_config;
 330                 struct {
 331                         u8 ipcss;      /* IP checksum start */
 332                         u8 ipcso;      /* IP checksum offset */
 333                         __le16 ipcse;     /* IP checksum end */
 334                 } ip_fields;
 335         } lower_setup;
 336         union {
 337                 __le32 tcp_config;
 338                 struct {
 339                         u8 tucss;      /* TCP checksum start */
 340                         u8 tucso;      /* TCP checksum offset */
 341                         __le16 tucse;     /* TCP checksum end */
 342                 } tcp_fields;
 343         } upper_setup;
 344         __le32 cmd_and_length;
 345         union {
 346                 __le32 data;
 347                 struct {
 348                         u8 status;     /* Descriptor status */
 349                         u8 hdr_len;    /* Header length */
 350                         __le16 mss;       /* Maximum segment size */
 351                 } fields;
 352         } tcp_seg_setup;
 353 };
 354
 355 /* Offload data descriptor */
 356 struct e1000_data_desc {
 357         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 358         union {
 359                 __le32 data;
 360                 struct {
 361                         __le16 length;    /* Data buffer length */
 362                         u8 typ_len_ext;
 363                         u8 cmd;
 364                 } flags;
 365         } lower;
 366         union {
 367                 __le32 data;
 368                 struct {
 369                         u8 status;     /* Descriptor status */
 370                         u8 popts;      /* Packet Options */
 371                         __le16 special;
 372                 } fields;
 373         } upper;
 374 };
 375
 376 /* Statistics counters collected by the MAC */
 377 struct e1000_hw_stats {
 378         u64 crcerrs;
 379         u64 algnerrc;
 380         u64 symerrs;
 381         u64 rxerrc;
 382         u64 mpc;
 383         u64 scc;
 384         u64 ecol;
 385         u64 mcc;
 386         u64 latecol;
 387         u64 colc;
 388         u64 dc;
 389         u64 tncrs;
 390         u64 sec;
 391         u64 cexterr;
 392         u64 rlec;
 393         u64 xonrxc;
 394         u64 xontxc;
 395         u64 xoffrxc;
 396         u64 xofftxc;
 397         u64 fcruc;
 398         u64 prc64;
 399         u64 prc127;
 400         u64 prc255;
 401         u64 prc511;
 402         u64 prc1023;
 403         u64 prc1522;
 404         u64 gprc;
 405         u64 bprc;
 406         u64 mprc;
 407         u64 gptc;
 408         u64 gorc;
 409         u64 gotc;
 410         u64 rnbc;
 411         u64 ruc;
 412         u64 rfc;
 413         u64 roc;
 414         u64 rjc;
 415         u64 mgprc;
 416         u64 mgpdc;
 417         u64 mgptc;
 418         u64 tor;
 419         u64 tot;
 420         u64 tpr;
 421         u64 tpt;
 422         u64 ptc64;
 423         u64 ptc127;
 424         u64 ptc255;
 425         u64 ptc511;
 426         u64 ptc1023;
 427         u64 ptc1522;
 428         u64 mptc;
 429         u64 bptc;
 430         u64 tsctc;
 431         u64 tsctfc;
 432         u64 iac;
 433         u64 icrxptc;
 434         u64 icrxatc;
 435         u64 ictxptc;
 436         u64 ictxatc;
 437         u64 ictxqec;
 438         u64 ictxqmtc;
 439         u64 icrxdmtc;
 440         u64 icrxoc;
 441 };
 442
 443 struct e1000_phy_stats {
 444         u32 idle_errors;
 445         u32 receive_errors;
 446 };
 447
 448 struct e1000_host_mng_dhcp_cookie {
 449         u32 signature;
 450         u8 status;
 451         u8 reserved0;
 452         u16 vlan_id;
 453         u32 reserved1;
 454         u16 reserved2;
 455         u8 reserved3;
 456         u8 checksum;
 457 };
 458
 459 /* Host Interface "Rev 1" */
 460 struct e1000_host_command_header {
 461         u8 command_id;
 462         u8 command_length;
 463         u8 command_options;
 464         u8 checksum;
 465 };
 466
 467 #define E1000_HI_MAX_DATA_LENGTH        252
 468 struct e1000_host_command_info {
 469         struct e1000_host_command_header command_header;
 470         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 471 };
 472
 473 /* Host Interface "Rev 2" */
 474 struct e1000_host_mng_command_header {
 475         u8 command_id;
 476         u8 checksum;
 477         u16 reserved1;
 478         u16 reserved2;
 479         u16 command_length;
 480 };
 481
 482 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 483 struct e1000_host_mng_command_info {
 484         struct e1000_host_mng_command_header command_header;
 485         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 486 };
 487
 488 #include "mac.h"
 489 #include "phy.h"
 490 #include "nvm.h"
 491 #include "manage.h"
 492
 493 /* Function pointers for the MAC. */
 494 struct e1000_mac_operations {
 495         s32  (*id_led_init)(struct e1000_hw *);
 496         s32  (*blink_led)(struct e1000_hw *);
 497         bool (*check_mng_mode)(struct e1000_hw *);
 498         s32  (*check_for_link)(struct e1000_hw *);
 499         s32  (*cleanup_led)(struct e1000_hw *);
 500         void (*clear_hw_cntrs)(struct e1000_hw *);
 501         void (*clear_vfta)(struct e1000_hw *);
 502         s32  (*get_bus_info)(struct e1000_hw *);
 503         void (*set_lan_id)(struct e1000_hw *);
 504         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 505         s32  (*led_on)(struct e1000_hw *);
 506         s32  (*led_off)(struct e1000_hw *);
 507         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 508         s32  (*reset_hw)(struct e1000_hw *);
 509         s32  (*init_hw)(struct e1000_hw *);
 510         s32  (*setup_link)(struct e1000_hw *);
 511         s32  (*setup_physical_interface)(struct e1000_hw *);
 512         s32  (*setup_led)(struct e1000_hw *);
 513         void (*write_vfta)(struct e1000_hw *, u32, u32);
 514         void (*config_collision_dist)(struct e1000_hw *);
 515         int  (*rar_set)(struct e1000_hw *, u8 *, u32);
 516         s32  (*read_mac_addr)(struct e1000_hw *);
 517         u32  (*rar_get_count)(struct e1000_hw *);
 518 };
 519
 520 /* When to use various PHY register access functions:
 521  *
 522  *                 Func   Caller
 523  *   Function      Does   Does    When to use
 524  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 525  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 526  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 527  *                                on different pages
 528  *   X_reg_page    A      L,P     for multiple accesses of different regs
 529  *                                on the same page
 530  *
 531  * Where X=[read|write], L=locking, P=sets page, A=register access
 532  *
 533  */
 534 struct e1000_phy_operations {
 535         s32  (*acquire)(struct e1000_hw *);
 536         s32  (*cfg_on_link_up)(struct e1000_hw *);
 537         s32  (*check_polarity)(struct e1000_hw *);
 538         s32  (*check_reset_block)(struct e1000_hw *);
 539         s32  (*commit)(struct e1000_hw *);
 540         s32  (*force_speed_duplex)(struct e1000_hw *);
 541         s32  (*get_cfg_done)(struct e1000_hw *hw);
 542         s32  (*get_cable_length)(struct e1000_hw *);
 543         s32  (*get_info)(struct e1000_hw *);
 544         s32  (*set_page)(struct e1000_hw *, u16);
 545         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 546         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 547         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 548         void (*release)(struct e1000_hw *);
 549         s32  (*reset)(struct e1000_hw *);
 550         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 551         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 552         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 553         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 554         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 555         void (*power_up)(struct e1000_hw *);
 556         void (*power_down)(struct e1000_hw *);
 557 };
 558
 559 /* Function pointers for the NVM. */
 560 struct e1000_nvm_operations {
 561         s32  (*acquire)(struct e1000_hw *);
 562         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 563         void (*release)(struct e1000_hw *);
 564         void (*reload)(struct e1000_hw *);
 565         s32  (*update)(struct e1000_hw *);
 566         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 567         s32  (*validate)(struct e1000_hw *);
 568         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 569 };
 570
 571 struct e1000_mac_info {
 572         struct e1000_mac_operations ops;
 573         u8 addr[ETH_ALEN];
 574         u8 perm_addr[ETH_ALEN];
 575
 576         enum e1000_mac_type type;
 577
 578         u32 collision_delta;
 579         u32 ledctl_default;
 580         u32 ledctl_mode1;
 581         u32 ledctl_mode2;
 582         u32 mc_filter_type;
 583         u32 tx_packet_delta;
 584         u32 txcw;
 585
 586         u16 current_ifs_val;
 587         u16 ifs_max_val;
 588         u16 ifs_min_val;
 589         u16 ifs_ratio;
 590         u16 ifs_step_size;
 591         u16 mta_reg_count;
 592
 593         /* Maximum size of the MTA register table in all supported adapters */
 594 #define MAX_MTA_REG 128
 595         u32 mta_shadow[MAX_MTA_REG];
 596         u16 rar_entry_count;
 597
 598         u8 forced_speed_duplex;
 599
 600         bool adaptive_ifs;
 601         bool has_fwsm;
 602         bool arc_subsystem_valid;
 603         bool autoneg;
 604         bool autoneg_failed;
 605         bool get_link_status;
 606         bool in_ifs_mode;
 607         bool serdes_has_link;
 608         bool tx_pkt_filtering;
 609         enum e1000_serdes_link_state serdes_link_state;
 610 };
 611
 612 struct e1000_phy_info {
 613         struct e1000_phy_operations ops;
 614
 615         enum e1000_phy_type type;
 616
 617         enum e1000_1000t_rx_status local_rx;
 618         enum e1000_1000t_rx_status remote_rx;
 619         enum e1000_ms_type ms_type;
 620         enum e1000_ms_type original_ms_type;
 621         enum e1000_rev_polarity cable_polarity;
 622         enum e1000_smart_speed smart_speed;
 623
 624         u32 addr;
 625         u32 id;
 626         u32 reset_delay_us;     /* in usec */
 627         u32 revision;
 628
 629         enum e1000_media_type media_type;
 630
 631         u16 autoneg_advertised;
 632         u16 autoneg_mask;
 633         u16 cable_length;
 634         u16 max_cable_length;
 635         u16 min_cable_length;
 636
 637         u8 mdix;
 638
 639         bool disable_polarity_correction;
 640         bool is_mdix;
 641         bool polarity_correction;
 642         bool speed_downgraded;
 643         bool autoneg_wait_to_complete;
 644 };
 645
 646 struct e1000_nvm_info {
 647         struct e1000_nvm_operations ops;
 648
 649         enum e1000_nvm_type type;
 650         enum e1000_nvm_override override;
 651
 652         u32 flash_bank_size;
 653         u32 flash_base_addr;
 654
 655         u16 word_size;
 656         u16 delay_usec;
 657         u16 address_bits;
 658         u16 opcode_bits;
 659         u16 page_size;
 660 };
 661
 662 struct e1000_bus_info {
 663         enum e1000_bus_width width;
 664
 665         u16 func;
 666 };
 667
 668 struct e1000_fc_info {
 669         u32 high_water;          /* Flow control high-water mark */
 670         u32 low_water;           /* Flow control low-water mark */
 671         u16 pause_time;          /* Flow control pause timer */
 672         u16 refresh_time;        /* Flow control refresh timer */
 673         bool send_xon;           /* Flow control send XON */
 674         bool strict_ieee;        /* Strict IEEE mode */
 675         enum e1000_fc_mode current_mode; /* FC mode in effect */
 676         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 677 };
 678
 679 struct e1000_dev_spec_82571 {
 680         bool laa_is_present;
 681         u32 smb_counter;
 682 };
 683
 684 struct e1000_dev_spec_80003es2lan {
 685         bool mdic_wa_enable;
 686 };
 687
 688 struct e1000_shadow_ram {
 689         u16 value;
 690         bool modified;
 691 };
 692
 693 #define E1000_ICH8_SHADOW_RAM_WORDS             2048
 694
 695 /* I218 PHY Ultra Low Power (ULP) states */
 696 enum e1000_ulp_state {
 697         e1000_ulp_state_unknown,
 698         e1000_ulp_state_off,
 699         e1000_ulp_state_on,
 700 };
 701
 702 struct e1000_dev_spec_ich8lan {
 703         bool kmrn_lock_loss_workaround_enabled;
 704         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
 705         bool nvm_k1_enabled;
 706         bool eee_disable;
 707         u16 eee_lp_ability;
 708         enum e1000_ulp_state ulp_state;
 709 };
 710
 711 struct e1000_hw {
 712         struct e1000_adapter *adapter;
 713
 714         void __iomem *hw_addr;
 715         void __iomem *flash_address;
 716
 717         struct e1000_mac_info mac;
 718         struct e1000_fc_info fc;
 719         struct e1000_phy_info phy;
 720         struct e1000_nvm_info nvm;
 721         struct e1000_bus_info bus;
 722         struct e1000_host_mng_dhcp_cookie mng_cookie;
 723
 724         union {
 725                 struct e1000_dev_spec_82571 e82571;
 726                 struct e1000_dev_spec_80003es2lan e80003es2lan;
 727                 struct e1000_dev_spec_ich8lan ich8lan;
 728         } dev_spec;
 729 };
 730
 731 #include "82571.h"
 732 #include "80003es2lan.h"
 733 #include "ich8lan.h"
 734
 735 #endif /* _E1000E_HW_H_ */