drivers/net/can/grcan.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
   4  *
   5  * 2012 (c) Aeroflex Gaisler AB
   6  *
   7  * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
   8  * VHDL IP core library.
   9  *
  10  * Full documentation of the GRCAN core can be found here:
  11  * http://www.gaisler.com/products/grlib/grip.pdf
  12  *
  13  * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
  14  * open firmware properties.
  15  *
  16  * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
  17  * sysfs interface.
  18  *
  19  * See "Documentation/admin-guide/kernel-parameters.rst" for information on the module
  20  * parameters.
  21  *
  22  * Contributors: Andreas Larsson <[email protected]>
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/delay.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/io.h>
  32 #include <linux/can/dev.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/of_irq.h>
  36
  37 #include <linux/dma-mapping.h>
  38
  39 #define DRV_NAME        "grcan"
  40
  41 #define GRCAN_NAPI_WEIGHT       32
  42
  43 #define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
  44
  45 struct grcan_registers {
  46         u32 conf;       /* 0x00 */
  47         u32 stat;       /* 0x04 */
  48         u32 ctrl;       /* 0x08 */
  49         u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
  50         u32 smask;      /* 0x18 - CanMASK */
  51         u32 scode;      /* 0x1c - CanCODE */
  52         u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
  53         u32 pimsr;      /* 0x100 */
  54         u32 pimr;       /* 0x104 */
  55         u32 pisr;       /* 0x108 */
  56         u32 pir;        /* 0x10C */
  57         u32 imr;        /* 0x110 */
  58         u32 picr;       /* 0x114 */
  59         u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
  60         u32 txctrl;     /* 0x200 */
  61         u32 txaddr;     /* 0x204 */
  62         u32 txsize;     /* 0x208 */
  63         u32 txwr;       /* 0x20C */
  64         u32 txrd;       /* 0x210 */
  65         u32 txirq;      /* 0x214 */
  66         u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
  67         u32 rxctrl;     /* 0x300 */
  68         u32 rxaddr;     /* 0x304 */
  69         u32 rxsize;     /* 0x308 */
  70         u32 rxwr;       /* 0x30C */
  71         u32 rxrd;       /* 0x310 */
  72         u32 rxirq;      /* 0x314 */
  73         u32 rxmask;     /* 0x318 */
  74         u32 rxcode;     /* 0x31C */
  75 };
  76
  77 #define GRCAN_CONF_ABORT        0x00000001
  78 #define GRCAN_CONF_ENABLE0      0x00000002
  79 #define GRCAN_CONF_ENABLE1      0x00000004
  80 #define GRCAN_CONF_SELECT       0x00000008
  81 #define GRCAN_CONF_SILENT       0x00000010
  82 #define GRCAN_CONF_SAM          0x00000020 /* Available in some hardware */
  83 #define GRCAN_CONF_BPR          0x00000300 /* Note: not BRP */
  84 #define GRCAN_CONF_RSJ          0x00007000
  85 #define GRCAN_CONF_PS1          0x00f00000
  86 #define GRCAN_CONF_PS2          0x000f0000
  87 #define GRCAN_CONF_SCALER       0xff000000
  88 #define GRCAN_CONF_OPERATION                                            \
  89         (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1     \
  90          | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
  91 #define GRCAN_CONF_TIMING                                               \
  92         (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1               \
  93          | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
  94
  95 #define GRCAN_CONF_RSJ_MIN      1
  96 #define GRCAN_CONF_RSJ_MAX      4
  97 #define GRCAN_CONF_PS1_MIN      1
  98 #define GRCAN_CONF_PS1_MAX      15
  99 #define GRCAN_CONF_PS2_MIN      2
 100 #define GRCAN_CONF_PS2_MAX      8
 101 #define GRCAN_CONF_SCALER_MIN   0
 102 #define GRCAN_CONF_SCALER_MAX   255
 103 #define GRCAN_CONF_SCALER_INC   1
 104
 105 #define GRCAN_CONF_BPR_BIT      8
 106 #define GRCAN_CONF_RSJ_BIT      12
 107 #define GRCAN_CONF_PS1_BIT      20
 108 #define GRCAN_CONF_PS2_BIT      16
 109 #define GRCAN_CONF_SCALER_BIT   24
 110
 111 #define GRCAN_STAT_PASS         0x000001
 112 #define GRCAN_STAT_OFF          0x000002
 113 #define GRCAN_STAT_OR           0x000004
 114 #define GRCAN_STAT_AHBERR       0x000008
 115 #define GRCAN_STAT_ACTIVE       0x000010
 116 #define GRCAN_STAT_RXERRCNT     0x00ff00
 117 #define GRCAN_STAT_TXERRCNT     0xff0000
 118
 119 #define GRCAN_STAT_ERRCTR_RELATED       (GRCAN_STAT_PASS | GRCAN_STAT_OFF)
 120
 121 #define GRCAN_STAT_RXERRCNT_BIT 8
 122 #define GRCAN_STAT_TXERRCNT_BIT 16
 123
 124 #define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96
 125 #define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127
 126
 127 #define GRCAN_CTRL_RESET        0x2
 128 #define GRCAN_CTRL_ENABLE       0x1
 129
 130 #define GRCAN_TXCTRL_ENABLE     0x1
 131 #define GRCAN_TXCTRL_ONGOING    0x2
 132 #define GRCAN_TXCTRL_SINGLE     0x4
 133
 134 #define GRCAN_RXCTRL_ENABLE     0x1
 135 #define GRCAN_RXCTRL_ONGOING    0x2
 136
 137 /* Relative offset of IRQ sources to AMBA Plug&Play */
 138 #define GRCAN_IRQIX_IRQ         0
 139 #define GRCAN_IRQIX_TXSYNC      1
 140 #define GRCAN_IRQIX_RXSYNC      2
 141
 142 #define GRCAN_IRQ_PASS          0x00001
 143 #define GRCAN_IRQ_OFF           0x00002
 144 #define GRCAN_IRQ_OR            0x00004
 145 #define GRCAN_IRQ_RXAHBERR      0x00008
 146 #define GRCAN_IRQ_TXAHBERR      0x00010
 147 #define GRCAN_IRQ_RXIRQ         0x00020
 148 #define GRCAN_IRQ_TXIRQ         0x00040
 149 #define GRCAN_IRQ_RXFULL        0x00080
 150 #define GRCAN_IRQ_TXEMPTY       0x00100
 151 #define GRCAN_IRQ_RX            0x00200
 152 #define GRCAN_IRQ_TX            0x00400
 153 #define GRCAN_IRQ_RXSYNC        0x00800
 154 #define GRCAN_IRQ_TXSYNC        0x01000
 155 #define GRCAN_IRQ_RXERRCTR      0x02000
 156 #define GRCAN_IRQ_TXERRCTR      0x04000
 157 #define GRCAN_IRQ_RXMISS        0x08000
 158 #define GRCAN_IRQ_TXLOSS        0x10000
 159
 160 #define GRCAN_IRQ_NONE  0
 161 #define GRCAN_IRQ_ALL                                                   \
 162         (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR                  \
 163          | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR                      \
 164          | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ                            \
 165          | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY                         \
 166          | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC               \
 167          | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR                        \
 168          | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS                        \
 169          | GRCAN_IRQ_TXLOSS)
 170
 171 #define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
 172                                   | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
 173 #define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR       \
 174                           | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR     \
 175                           | GRCAN_IRQ_TXLOSS)
 176 #define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
 177
 178 #define GRCAN_MSG_SIZE          16
 179
 180 #define GRCAN_MSG_IDE           0x80000000
 181 #define GRCAN_MSG_RTR           0x40000000
 182 #define GRCAN_MSG_BID           0x1ffc0000
 183 #define GRCAN_MSG_EID           0x1fffffff
 184 #define GRCAN_MSG_IDE_BIT       31
 185 #define GRCAN_MSG_RTR_BIT       30
 186 #define GRCAN_MSG_BID_BIT       18
 187 #define GRCAN_MSG_EID_BIT       0
 188
 189 #define GRCAN_MSG_DLC           0xf0000000
 190 #define GRCAN_MSG_TXERRC        0x00ff0000
 191 #define GRCAN_MSG_RXERRC        0x0000ff00
 192 #define GRCAN_MSG_DLC_BIT       28
 193 #define GRCAN_MSG_TXERRC_BIT    16
 194 #define GRCAN_MSG_RXERRC_BIT    8
 195 #define GRCAN_MSG_AHBERR        0x00000008
 196 #define GRCAN_MSG_OR            0x00000004
 197 #define GRCAN_MSG_OFF           0x00000002
 198 #define GRCAN_MSG_PASS          0x00000001
 199
 200 #define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
 201 #define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
 202
 203 #define GRCAN_BUFFER_ALIGNMENT          1024
 204 #define GRCAN_DEFAULT_BUFFER_SIZE       1024
 205 #define GRCAN_VALID_TR_SIZE_MASK        0x001fffc0
 206
 207 #define GRCAN_INVALID_BUFFER_SIZE(s)                    \
 208         ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
 209
 210 #if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
 211 #error "Invalid default buffer size"
 212 #endif
 213
 214 struct grcan_dma_buffer {
 215         size_t size;
 216         void *buf;
 217         dma_addr_t handle;
 218 };
 219
 220 struct grcan_dma {
 221         size_t base_size;
 222         void *base_buf;
 223         dma_addr_t base_handle;
 224         struct grcan_dma_buffer tx;
 225         struct grcan_dma_buffer rx;
 226 };
 227
 228 /* GRCAN configuration parameters */
 229 struct grcan_device_config {
 230         unsigned short enable0;
 231         unsigned short enable1;
 232         unsigned short select;
 233         unsigned int txsize;
 234         unsigned int rxsize;
 235 };
 236
 237 #define GRCAN_DEFAULT_DEVICE_CONFIG {                           \
 238                 .enable0        = 0,                            \
 239                 .enable1        = 0,                            \
 240                 .select         = 0,                            \
 241                 .txsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 242                 .rxsize         = GRCAN_DEFAULT_BUFFER_SIZE,    \
 243                 }
 244
 245 #define GRCAN_TXBUG_SAFE_GRLIB_VERSION  4100
 246 #define GRLIB_VERSION_MASK              0xffff
 247
 248 /* GRCAN private data structure */
 249 struct grcan_priv {
 250         struct can_priv can;    /* must be the first member */
 251         struct net_device *dev;
 252         struct device *ofdev_dev;
 253         struct napi_struct napi;
 254
 255         struct grcan_registers __iomem *regs;   /* ioremap'ed registers */
 256         struct grcan_device_config config;
 257         struct grcan_dma dma;
 258
 259         struct sk_buff **echo_skb;      /* We allocate this on our own */
 260
 261         /* The echo skb pointer, pointing into echo_skb and indicating which
 262          * frames can be echoed back. See the "Notes on the tx cyclic buffer
 263          * handling"-comment for grcan_start_xmit for more details.
 264          */
 265         u32 eskbp;
 266
 267         /* Lock for controlling changes to the netif tx queue state, accesses to
 268          * the echo_skb pointer eskbp and for making sure that a running reset
 269          * and/or a close of the interface is done without interference from
 270          * other parts of the code.
 271          *
 272          * The echo_skb pointer, eskbp, should only be accessed under this lock
 273          * as it can be changed in several places and together with decisions on
 274          * whether to wake up the tx queue.
 275          *
 276          * The tx queue must never be woken up if there is a running reset or
 277          * close in progress.
 278          *
 279          * A running reset (see below on need_txbug_workaround) should never be
 280          * done if the interface is closing down and several running resets
 281          * should never be scheduled simultaneously.
 282          */
 283         spinlock_t lock;
 284
 285         /* Whether a workaround is needed due to a bug in older hardware. In
 286          * this case, the driver both tries to prevent the bug from being
 287          * triggered and recovers, if the bug nevertheless happens, by doing a
 288          * running reset. A running reset, resets the device and continues from
 289          * where it were without being noticeable from outside the driver (apart
 290          * from slight delays).
 291          */
 292         bool need_txbug_workaround;
 293
 294         /* To trigger initization of running reset and to trigger running reset
 295          * respectively in the case of a hanged device due to a txbug.
 296          */
 297         struct timer_list hang_timer;
 298         struct timer_list rr_timer;
 299
 300         /* To avoid waking up the netif queue and restarting timers
 301          * when a reset is scheduled or when closing of the device is
 302          * undergoing
 303          */
 304         bool resetting;
 305         bool closing;
 306 };
 307
 308 /* Wait time for a short wait for ongoing to clear */
 309 #define GRCAN_SHORTWAIT_USECS   10
 310
 311 /* Limit on the number of transmitted bits of an eff frame according to the CAN
 312  * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
 313  * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
 314  * bits end of frame
 315  */
 316 #define GRCAN_EFF_FRAME_MAX_BITS        (1+32+6+8*8+16+2+7)
 317
 318 #if defined(__BIG_ENDIAN)
 319 static inline u32 grcan_read_reg(u32 __iomem *reg)
 320 {
 321         return ioread32be(reg);
 322 }
 323
 324 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 325 {
 326         iowrite32be(val, reg);
 327 }
 328 #else
 329 static inline u32 grcan_read_reg(u32 __iomem *reg)
 330 {
 331         return ioread32(reg);
 332 }
 333
 334 static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
 335 {
 336         iowrite32(val, reg);
 337 }
 338 #endif
 339
 340 static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
 341 {
 342         grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
 343 }
 344
 345 static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
 346 {
 347         grcan_write_reg(reg, grcan_read_reg(reg) | mask);
 348 }
 349
 350 static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
 351 {
 352         return grcan_read_reg(reg) & mask;
 353 }
 354
 355 static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
 356 {
 357         u32 old = grcan_read_reg(reg);
 358
 359         grcan_write_reg(reg, (old & ~mask) | (value & mask));
 360 }
 361
 362 /* a and b should both be in [0,size] and a == b == size should not hold */
 363 static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
 364 {
 365         u32 sum = a + b;
 366
 367         if (sum < size)
 368                 return sum;
 369         else
 370                 return sum - size;
 371 }
 372
 373 /* a and b should both be in [0,size) */
 374 static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
 375 {
 376         return grcan_ring_add(a, size - b, size);
 377 }
 378
 379 /* Available slots for new transmissions */
 380 static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
 381 {
 382         u32 slots = txsize / GRCAN_MSG_SIZE - 1;
 383         u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
 384
 385         return slots - used;
 386 }
 387
 388 /* Configuration parameters that can be set via module parameters */
 389 static struct grcan_device_config grcan_module_config =
 390         GRCAN_DEFAULT_DEVICE_CONFIG;
 391
 392 static const struct can_bittiming_const grcan_bittiming_const = {
 393         .name           = DRV_NAME,
 394         .tseg1_min      = GRCAN_CONF_PS1_MIN + 1,
 395         .tseg1_max      = GRCAN_CONF_PS1_MAX + 1,
 396         .tseg2_min      = GRCAN_CONF_PS2_MIN,
 397         .tseg2_max      = GRCAN_CONF_PS2_MAX,
 398         .sjw_max        = GRCAN_CONF_RSJ_MAX,
 399         .brp_min        = GRCAN_CONF_SCALER_MIN + 1,
 400         .brp_max        = GRCAN_CONF_SCALER_MAX + 1,
 401         .brp_inc        = GRCAN_CONF_SCALER_INC,
 402 };
 403
 404 static int grcan_set_bittiming(struct net_device *dev)
 405 {
 406         struct grcan_priv *priv = netdev_priv(dev);
 407         struct grcan_registers __iomem *regs = priv->regs;
 408         struct can_bittiming *bt = &priv->can.bittiming;
 409         u32 timing = 0;
 410         int bpr, rsj, ps1, ps2, scaler;
 411
 412         /* Should never happen - function will not be called when
 413          * device is up
 414          */
 415         if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
 416                 return -EBUSY;
 417
 418         bpr = 0; /* Note bpr and brp are different concepts */
 419         rsj = bt->sjw;
 420         ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
 421         ps2 = bt->phase_seg2;
 422         scaler = (bt->brp - 1);
 423         netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
 424                    bpr, rsj, ps1, ps2, scaler);
 425         if (!(ps1 > ps2)) {
 426                 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
 427                            ps1, ps2);
 428                 return -EINVAL;
 429         }
 430         if (!(ps2 >= rsj)) {
 431                 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
 432                            ps2, rsj);
 433                 return -EINVAL;
 434         }
 435
 436         timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
 437         timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
 438         timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
 439         timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
 440         timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
 441         netdev_info(dev, "setting timing=0x%x\n", timing);
 442         grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
 443
 444         return 0;
 445 }
 446
 447 static int grcan_get_berr_counter(const struct net_device *dev,
 448                                   struct can_berr_counter *bec)
 449 {
 450         struct grcan_priv *priv = netdev_priv(dev);
 451         struct grcan_registers __iomem *regs = priv->regs;
 452         u32 status = grcan_read_reg(&regs->stat);
 453
 454         bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
 455         bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
 456         return 0;
 457 }
 458
 459 static int grcan_poll(struct napi_struct *napi, int budget);
 460
 461 /* Reset device, but keep configuration information */
 462 static void grcan_reset(struct net_device *dev)
 463 {
 464         struct grcan_priv *priv = netdev_priv(dev);
 465         struct grcan_registers __iomem *regs = priv->regs;
 466         u32 config = grcan_read_reg(&regs->conf);
 467
 468         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
 469         grcan_write_reg(&regs->conf, config);
 470
 471         priv->eskbp = grcan_read_reg(&regs->txrd);
 472         priv->can.state = CAN_STATE_STOPPED;
 473
 474         /* Turn off hardware filtering - regs->rxcode set to 0 by reset */
 475         grcan_write_reg(&regs->rxmask, 0);
 476 }
 477
 478 /* stop device without changing any configurations */
 479 static void grcan_stop_hardware(struct net_device *dev)
 480 {
 481         struct grcan_priv *priv = netdev_priv(dev);
 482         struct grcan_registers __iomem *regs = priv->regs;
 483
 484         grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
 485         grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 486         grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 487         grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
 488 }
 489
 490 /* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
 491  * is true and free them otherwise.
 492  *
 493  * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
 494  * continue until priv->eskbp catches up to regs->txrd.
 495  *
 496  * priv->lock *must* be held when calling this function
 497  */
 498 static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
 499 {
 500         struct grcan_priv *priv = netdev_priv(dev);
 501         struct grcan_registers __iomem *regs = priv->regs;
 502         struct grcan_dma *dma = &priv->dma;
 503         struct net_device_stats *stats = &dev->stats;
 504         int i, work_done;
 505
 506         /* Updates to priv->eskbp and wake-ups of the queue needs to
 507          * be atomic towards the reads of priv->eskbp and shut-downs
 508          * of the queue in grcan_start_xmit.
 509          */
 510         u32 txrd = grcan_read_reg(&regs->txrd);
 511
 512         for (work_done = 0; work_done < budget || budget < 0; work_done++) {
 513                 if (priv->eskbp == txrd)
 514                         break;
 515                 i = priv->eskbp / GRCAN_MSG_SIZE;
 516                 if (echo) {
 517                         /* Normal echo of messages */
 518                         stats->tx_packets++;
 519                         stats->tx_bytes += can_get_echo_skb(dev, i, NULL);
 520                 } else {
 521                         /* For cleanup of untransmitted messages */
 522                         can_free_echo_skb(dev, i, NULL);
 523                 }
 524
 525                 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
 526                                              dma->tx.size);
 527                 txrd = grcan_read_reg(&regs->txrd);
 528         }
 529         return work_done;
 530 }
 531
 532 static void grcan_lost_one_shot_frame(struct net_device *dev)
 533 {
 534         struct grcan_priv *priv = netdev_priv(dev);
 535         struct grcan_registers __iomem *regs = priv->regs;
 536         struct grcan_dma *dma = &priv->dma;
 537         u32 txrd;
 538         unsigned long flags;
 539
 540         spin_lock_irqsave(&priv->lock, flags);
 541
 542         catch_up_echo_skb(dev, -1, true);
 543
 544         if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
 545                 /* Should never happen */
 546                 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
 547         } else {
 548                 /* By the time an GRCAN_IRQ_TXLOSS is generated in
 549                  * one-shot mode there is no problem in writing
 550                  * to TXRD even in versions of the hardware in
 551                  * which GRCAN_TXCTRL_ONGOING is not cleared properly
 552                  * in one-shot mode.
 553                  */
 554
 555                 /* Skip message and discard echo-skb */
 556                 txrd = grcan_read_reg(&regs->txrd);
 557                 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
 558                 grcan_write_reg(&regs->txrd, txrd);
 559                 catch_up_echo_skb(dev, -1, false);
 560
 561                 if (!priv->resetting && !priv->closing &&
 562                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
 563                         netif_wake_queue(dev);
 564                         grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 565                 }
 566         }
 567
 568         spin_unlock_irqrestore(&priv->lock, flags);
 569 }
 570
 571 static void grcan_err(struct net_device *dev, u32 sources, u32 status)
 572 {
 573         struct grcan_priv *priv = netdev_priv(dev);
 574         struct grcan_registers __iomem *regs = priv->regs;
 575         struct grcan_dma *dma = &priv->dma;
 576         struct net_device_stats *stats = &dev->stats;
 577         struct can_frame cf;
 578
 579         /* Zero potential error_frame */
 580         memset(&cf, 0, sizeof(cf));
 581
 582         /* Message lost interrupt. This might be due to arbitration error, but
 583          * is also triggered when there is no one else on the can bus or when
 584          * there is a problem with the hardware interface or the bus itself. As
 585          * arbitration errors can not be singled out, no error frames are
 586          * generated reporting this event as an arbitration error.
 587          */
 588         if (sources & GRCAN_IRQ_TXLOSS) {
 589                 /* Take care of failed one-shot transmit */
 590                 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
 591                         grcan_lost_one_shot_frame(dev);
 592
 593                 /* Stop printing as soon as error passive or bus off is in
 594                  * effect to limit the amount of txloss debug printouts.
 595                  */
 596                 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
 597                         netdev_dbg(dev, "tx message lost\n");
 598                         stats->tx_errors++;
 599                 }
 600         }
 601
 602         /* Conditions dealing with the error counters. There is no interrupt for
 603          * error warning, but there are interrupts for increases of the error
 604          * counters.
 605          */
 606         if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
 607             (status & GRCAN_STAT_ERRCTR_RELATED)) {
 608                 enum can_state state = priv->can.state;
 609                 enum can_state oldstate = state;
 610                 u32 txerr = (status & GRCAN_STAT_TXERRCNT)
 611                         >> GRCAN_STAT_TXERRCNT_BIT;
 612                 u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
 613                         >> GRCAN_STAT_RXERRCNT_BIT;
 614
 615                 /* Figure out current state */
 616                 if (status & GRCAN_STAT_OFF) {
 617                         state = CAN_STATE_BUS_OFF;
 618                 } else if (status & GRCAN_STAT_PASS) {
 619                         state = CAN_STATE_ERROR_PASSIVE;
 620                 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
 621                            rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
 622                         state = CAN_STATE_ERROR_WARNING;
 623                 } else {
 624                         state = CAN_STATE_ERROR_ACTIVE;
 625                 }
 626
 627                 /* Handle and report state changes */
 628                 if (state != oldstate) {
 629                         switch (state) {
 630                         case CAN_STATE_BUS_OFF:
 631                                 netdev_dbg(dev, "bus-off\n");
 632                                 netif_carrier_off(dev);
 633                                 priv->can.can_stats.bus_off++;
 634
 635                                 /* Prevent the hardware from recovering from bus
 636                                  * off on its own if restart is disabled.
 637                                  */
 638                                 if (!priv->can.restart_ms)
 639                                         grcan_stop_hardware(dev);
 640
 641                                 cf.can_id |= CAN_ERR_BUSOFF;
 642                                 break;
 643
 644                         case CAN_STATE_ERROR_PASSIVE:
 645                                 netdev_dbg(dev, "Error passive condition\n");
 646                                 priv->can.can_stats.error_passive++;
 647
 648                                 cf.can_id |= CAN_ERR_CRTL;
 649                                 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 650                                         cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 651                                 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
 652                                         cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 653                                 break;
 654
 655                         case CAN_STATE_ERROR_WARNING:
 656                                 netdev_dbg(dev, "Error warning condition\n");
 657                                 priv->can.can_stats.error_warning++;
 658
 659                                 cf.can_id |= CAN_ERR_CRTL;
 660                                 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 661                                         cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
 662                                 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
 663                                         cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
 664                                 break;
 665
 666                         case CAN_STATE_ERROR_ACTIVE:
 667                                 netdev_dbg(dev, "Error active condition\n");
 668                                 cf.can_id |= CAN_ERR_CRTL;
 669                                 break;
 670
 671                         default:
 672                                 /* There are no others at this point */
 673                                 break;
 674                         }
 675                         cf.can_id |= CAN_ERR_CNT;
 676                         cf.data[6] = txerr;
 677                         cf.data[7] = rxerr;
 678                         priv->can.state = state;
 679                 }
 680
 681                 /* Report automatic restarts */
 682                 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
 683                         unsigned long flags;
 684
 685                         cf.can_id |= CAN_ERR_RESTARTED;
 686                         netdev_dbg(dev, "restarted\n");
 687                         priv->can.can_stats.restarts++;
 688                         netif_carrier_on(dev);
 689
 690                         spin_lock_irqsave(&priv->lock, flags);
 691
 692                         if (!priv->resetting && !priv->closing) {
 693                                 u32 txwr = grcan_read_reg(&regs->txwr);
 694
 695                                 if (grcan_txspace(dma->tx.size, txwr,
 696                                                   priv->eskbp))
 697                                         netif_wake_queue(dev);
 698                         }
 699
 700                         spin_unlock_irqrestore(&priv->lock, flags);
 701                 }
 702         }
 703
 704         /* Data overrun interrupt */
 705         if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
 706                 netdev_dbg(dev, "got data overrun interrupt\n");
 707                 stats->rx_over_errors++;
 708                 stats->rx_errors++;
 709
 710                 cf.can_id |= CAN_ERR_CRTL;
 711                 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
 712         }
 713
 714         /* AHB bus error interrupts (not CAN bus errors) - shut down the
 715          * device.
 716          */
 717         if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
 718             (status & GRCAN_STAT_AHBERR)) {
 719                 char *txrx = "";
 720                 unsigned long flags;
 721
 722                 if (sources & GRCAN_IRQ_TXAHBERR) {
 723                         txrx = "on tx ";
 724                         stats->tx_errors++;
 725                 } else if (sources & GRCAN_IRQ_RXAHBERR) {
 726                         txrx = "on rx ";
 727                         stats->rx_errors++;
 728                 }
 729                 netdev_err(dev, "Fatal AHB bus error %s- halting device\n",
 730                            txrx);
 731
 732                 spin_lock_irqsave(&priv->lock, flags);
 733
 734                 /* Prevent anything to be enabled again and halt device */
 735                 priv->closing = true;
 736                 netif_stop_queue(dev);
 737                 grcan_stop_hardware(dev);
 738                 priv->can.state = CAN_STATE_STOPPED;
 739
 740                 spin_unlock_irqrestore(&priv->lock, flags);
 741         }
 742
 743         /* Pass on error frame if something to report,
 744          * i.e. id contains some information
 745          */
 746         if (cf.can_id) {
 747                 struct can_frame *skb_cf;
 748                 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
 749
 750                 if (skb == NULL) {
 751                         netdev_dbg(dev, "could not allocate error frame\n");
 752                         return;
 753                 }
 754                 skb_cf->can_id |= cf.can_id;
 755                 memcpy(skb_cf->data, cf.data, sizeof(cf.data));
 756
 757                 netif_rx(skb);
 758         }
 759 }
 760
 761 static irqreturn_t grcan_interrupt(int irq, void *dev_id)
 762 {
 763         struct net_device *dev = dev_id;
 764         struct grcan_priv *priv = netdev_priv(dev);
 765         struct grcan_registers __iomem *regs = priv->regs;
 766         u32 sources, status;
 767
 768         /* Find out the source */
 769         sources = grcan_read_reg(&regs->pimsr);
 770         if (!sources)
 771                 return IRQ_NONE;
 772         grcan_write_reg(&regs->picr, sources);
 773         status = grcan_read_reg(&regs->stat);
 774
 775         /* If we got TX progress, the device has not hanged,
 776          * so disable the hang timer
 777          */
 778         if (priv->need_txbug_workaround &&
 779             (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
 780                 del_timer(&priv->hang_timer);
 781         }
 782
 783         /* Frame(s) received or transmitted */
 784         if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
 785                 /* Disable tx/rx interrupts and schedule poll(). No need for
 786                  * locking as interference from a running reset at worst leads
 787                  * to an extra interrupt.
 788                  */
 789                 grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
 790                 napi_schedule(&priv->napi);
 791         }
 792
 793         /* (Potential) error conditions to take care of */
 794         if (sources & GRCAN_IRQ_ERRORS)
 795                 grcan_err(dev, sources, status);
 796
 797         return IRQ_HANDLED;
 798 }
 799
 800 /* Reset device and restart operations from where they were.
 801  *
 802  * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
 803  * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
 804  * for single shot)
 805  */
 806 static void grcan_running_reset(struct timer_list *t)
 807 {
 808         struct grcan_priv *priv = from_timer(priv, t, rr_timer);
 809         struct net_device *dev = priv->dev;
 810         struct grcan_registers __iomem *regs = priv->regs;
 811         unsigned long flags;
 812
 813         /* This temporarily messes with eskbp, so we need to lock
 814          * priv->lock
 815          */
 816         spin_lock_irqsave(&priv->lock, flags);
 817
 818         priv->resetting = false;
 819         del_timer(&priv->hang_timer);
 820         del_timer(&priv->rr_timer);
 821
 822         if (!priv->closing) {
 823                 /* Save and reset - config register preserved by grcan_reset */
 824                 u32 imr = grcan_read_reg(&regs->imr);
 825
 826                 u32 txaddr = grcan_read_reg(&regs->txaddr);
 827                 u32 txsize = grcan_read_reg(&regs->txsize);
 828                 u32 txwr = grcan_read_reg(&regs->txwr);
 829                 u32 txrd = grcan_read_reg(&regs->txrd);
 830                 u32 eskbp = priv->eskbp;
 831
 832                 u32 rxaddr = grcan_read_reg(&regs->rxaddr);
 833                 u32 rxsize = grcan_read_reg(&regs->rxsize);
 834                 u32 rxwr = grcan_read_reg(&regs->rxwr);
 835                 u32 rxrd = grcan_read_reg(&regs->rxrd);
 836
 837                 grcan_reset(dev);
 838
 839                 /* Restore */
 840                 grcan_write_reg(&regs->txaddr, txaddr);
 841                 grcan_write_reg(&regs->txsize, txsize);
 842                 grcan_write_reg(&regs->txwr, txwr);
 843                 grcan_write_reg(&regs->txrd, txrd);
 844                 priv->eskbp = eskbp;
 845
 846                 grcan_write_reg(&regs->rxaddr, rxaddr);
 847                 grcan_write_reg(&regs->rxsize, rxsize);
 848                 grcan_write_reg(&regs->rxwr, rxwr);
 849                 grcan_write_reg(&regs->rxrd, rxrd);
 850
 851                 /* Turn on device again */
 852                 grcan_write_reg(&regs->imr, imr);
 853                 priv->can.state = CAN_STATE_ERROR_ACTIVE;
 854                 grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
 855                                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
 856                                    ? GRCAN_TXCTRL_SINGLE : 0));
 857                 grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 858                 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
 859
 860                 /* Start queue if there is size and listen-onle mode is not
 861                  * enabled
 862                  */
 863                 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
 864                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
 865                         netif_wake_queue(dev);
 866         }
 867
 868         spin_unlock_irqrestore(&priv->lock, flags);
 869
 870         netdev_err(dev, "Device reset and restored\n");
 871 }
 872
 873 /* Waiting time in usecs corresponding to the transmission of three maximum
 874  * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
 875  * of time makes sure that the can controller have time to finish sending or
 876  * receiving a frame with a good margin.
 877  *
 878  * usecs/sec * number of frames * bits/frame / bits/sec
 879  */
 880 static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
 881 {
 882         return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
 883 }
 884
 885 /* Set timer so that it will not fire until after a period in which the can
 886  * controller have a good margin to finish transmitting a frame unless it has
 887  * hanged
 888  */
 889 static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
 890 {
 891         u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
 892
 893         mod_timer(timer, jiffies + wait_jiffies);
 894 }
 895
 896 /* Disable channels and schedule a running reset */
 897 static void grcan_initiate_running_reset(struct timer_list *t)
 898 {
 899         struct grcan_priv *priv = from_timer(priv, t, hang_timer);
 900         struct net_device *dev = priv->dev;
 901         struct grcan_registers __iomem *regs = priv->regs;
 902         unsigned long flags;
 903
 904         netdev_err(dev, "Device seems hanged - reset scheduled\n");
 905
 906         spin_lock_irqsave(&priv->lock, flags);
 907
 908         /* The main body of this function must never be executed again
 909          * until after an execution of grcan_running_reset
 910          */
 911         if (!priv->resetting && !priv->closing) {
 912                 priv->resetting = true;
 913                 netif_stop_queue(dev);
 914                 grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
 915                 grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
 916                 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
 917         }
 918
 919         spin_unlock_irqrestore(&priv->lock, flags);
 920 }
 921
 922 static void grcan_free_dma_buffers(struct net_device *dev)
 923 {
 924         struct grcan_priv *priv = netdev_priv(dev);
 925         struct grcan_dma *dma = &priv->dma;
 926
 927         dma_free_coherent(priv->ofdev_dev, dma->base_size, dma->base_buf,
 928                           dma->base_handle);
 929         memset(dma, 0, sizeof(*dma));
 930 }
 931
 932 static int grcan_allocate_dma_buffers(struct net_device *dev,
 933                                       size_t tsize, size_t rsize)
 934 {
 935         struct grcan_priv *priv = netdev_priv(dev);
 936         struct grcan_dma *dma = &priv->dma;
 937         struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
 938         struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
 939         size_t shift;
 940
 941         /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
 942          * i.e. first buffer
 943          */
 944         size_t maxs = max(tsize, rsize);
 945         size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
 946
 947         /* Put the small buffer after that */
 948         size_t ssize = min(tsize, rsize);
 949
 950         /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
 951         dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
 952         dma->base_buf = dma_alloc_coherent(priv->ofdev_dev,
 953                                            dma->base_size,
 954                                            &dma->base_handle,
 955                                            GFP_KERNEL);
 956
 957         if (!dma->base_buf)
 958                 return -ENOMEM;
 959
 960         dma->tx.size = tsize;
 961         dma->rx.size = rsize;
 962
 963         large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
 964         small->handle = large->handle + lsize;
 965         shift = large->handle - dma->base_handle;
 966
 967         large->buf = dma->base_buf + shift;
 968         small->buf = large->buf + lsize;
 969
 970         return 0;
 971 }
 972
 973 /* priv->lock *must* be held when calling this function */
 974 static int grcan_start(struct net_device *dev)
 975 {
 976         struct grcan_priv *priv = netdev_priv(dev);
 977         struct grcan_registers __iomem *regs = priv->regs;
 978         u32 confop, txctrl;
 979
 980         grcan_reset(dev);
 981
 982         grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
 983         grcan_write_reg(&regs->txsize, priv->dma.tx.size);
 984         /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
 985
 986         grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
 987         grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
 988         /* regs->rxwr and regs->rxrd already set to 0 by reset */
 989
 990         /* Enable interrupts */
 991         grcan_read_reg(&regs->pir);
 992         grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
 993
 994         /* Enable interfaces, channels and device */
 995         confop = GRCAN_CONF_ABORT
 996                 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
 997                 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
 998                 | (priv->config.select ? GRCAN_CONF_SELECT : 0)
 999                 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
1000                    GRCAN_CONF_SILENT : 0)
1001                 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
1002                    GRCAN_CONF_SAM : 0);
1003         grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1004         txctrl = GRCAN_TXCTRL_ENABLE
1005                 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1006                    ? GRCAN_TXCTRL_SINGLE : 0);
1007         grcan_write_reg(&regs->txctrl, txctrl);
1008         grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1009         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1010
1011         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1012
1013         return 0;
1014 }
1015
1016 static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1017 {
1018         struct grcan_priv *priv = netdev_priv(dev);
1019         unsigned long flags;
1020         int err = 0;
1021
1022         if (mode == CAN_MODE_START) {
1023                 /* This might be called to restart the device to recover from
1024                  * bus off errors
1025                  */
1026                 spin_lock_irqsave(&priv->lock, flags);
1027                 if (priv->closing || priv->resetting) {
1028                         err = -EBUSY;
1029                 } else {
1030                         netdev_info(dev, "Restarting device\n");
1031                         grcan_start(dev);
1032                         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1033                                 netif_wake_queue(dev);
1034                 }
1035                 spin_unlock_irqrestore(&priv->lock, flags);
1036                 return err;
1037         }
1038         return -EOPNOTSUPP;
1039 }
1040
1041 static int grcan_open(struct net_device *dev)
1042 {
1043         struct grcan_priv *priv = netdev_priv(dev);
1044         struct grcan_dma *dma = &priv->dma;
1045         unsigned long flags;
1046         int err;
1047
1048         /* Allocate memory */
1049         err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1050                                          priv->config.rxsize);
1051         if (err) {
1052                 netdev_err(dev, "could not allocate DMA buffers\n");
1053                 return err;
1054         }
1055
1056         priv->echo_skb = kcalloc(dma->tx.size, sizeof(*priv->echo_skb),
1057                                  GFP_KERNEL);
1058         if (!priv->echo_skb) {
1059                 err = -ENOMEM;
1060                 goto exit_free_dma_buffers;
1061         }
1062         priv->can.echo_skb_max = dma->tx.size;
1063         priv->can.echo_skb = priv->echo_skb;
1064
1065         /* Get can device up */
1066         err = open_candev(dev);
1067         if (err)
1068                 goto exit_free_echo_skb;
1069
1070         err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1071                           dev->name, dev);
1072         if (err)
1073                 goto exit_close_candev;
1074
1075         spin_lock_irqsave(&priv->lock, flags);
1076
1077         napi_enable(&priv->napi);
1078         grcan_start(dev);
1079         if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1080                 netif_start_queue(dev);
1081         priv->resetting = false;
1082         priv->closing = false;
1083
1084         spin_unlock_irqrestore(&priv->lock, flags);
1085
1086         return 0;
1087
1088 exit_close_candev:
1089         close_candev(dev);
1090 exit_free_echo_skb:
1091         kfree(priv->echo_skb);
1092 exit_free_dma_buffers:
1093         grcan_free_dma_buffers(dev);
1094         return err;
1095 }
1096
1097 static int grcan_close(struct net_device *dev)
1098 {
1099         struct grcan_priv *priv = netdev_priv(dev);
1100         unsigned long flags;
1101
1102         napi_disable(&priv->napi);
1103
1104         spin_lock_irqsave(&priv->lock, flags);
1105
1106         priv->closing = true;
1107         if (priv->need_txbug_workaround) {
1108                 spin_unlock_irqrestore(&priv->lock, flags);
1109                 del_timer_sync(&priv->hang_timer);
1110                 del_timer_sync(&priv->rr_timer);
1111                 spin_lock_irqsave(&priv->lock, flags);
1112         }
1113         netif_stop_queue(dev);
1114         grcan_stop_hardware(dev);
1115         priv->can.state = CAN_STATE_STOPPED;
1116
1117         spin_unlock_irqrestore(&priv->lock, flags);
1118
1119         free_irq(dev->irq, dev);
1120         close_candev(dev);
1121
1122         grcan_free_dma_buffers(dev);
1123         priv->can.echo_skb_max = 0;
1124         priv->can.echo_skb = NULL;
1125         kfree(priv->echo_skb);
1126
1127         return 0;
1128 }
1129
1130 static void grcan_transmit_catch_up(struct net_device *dev)
1131 {
1132         struct grcan_priv *priv = netdev_priv(dev);
1133         unsigned long flags;
1134         int work_done;
1135
1136         spin_lock_irqsave(&priv->lock, flags);
1137
1138         work_done = catch_up_echo_skb(dev, -1, true);
1139         if (work_done) {
1140                 if (!priv->resetting && !priv->closing &&
1141                     !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1142                         netif_wake_queue(dev);
1143
1144                 /* With napi we don't get TX interrupts for a while,
1145                  * so prevent a running reset while catching up
1146                  */
1147                 if (priv->need_txbug_workaround)
1148                         del_timer(&priv->hang_timer);
1149         }
1150
1151         spin_unlock_irqrestore(&priv->lock, flags);
1152 }
1153
1154 static int grcan_receive(struct net_device *dev, int budget)
1155 {
1156         struct grcan_priv *priv = netdev_priv(dev);
1157         struct grcan_registers __iomem *regs = priv->regs;
1158         struct grcan_dma *dma = &priv->dma;
1159         struct net_device_stats *stats = &dev->stats;
1160         struct can_frame *cf;
1161         struct sk_buff *skb;
1162         u32 wr, rd, startrd;
1163         u32 *slot;
1164         u32 i, rtr, eff, j, shift;
1165         int work_done = 0;
1166
1167         rd = grcan_read_reg(&regs->rxrd);
1168         startrd = rd;
1169         for (work_done = 0; work_done < budget; work_done++) {
1170                 /* Check for packet to receive */
1171                 wr = grcan_read_reg(&regs->rxwr);
1172                 if (rd == wr)
1173                         break;
1174
1175                 /* Take care of packet */
1176                 skb = alloc_can_skb(dev, &cf);
1177                 if (skb == NULL) {
1178                         netdev_err(dev,
1179                                    "dropping frame: skb allocation failed\n");
1180                         stats->rx_dropped++;
1181                         continue;
1182                 }
1183
1184                 slot = dma->rx.buf + rd;
1185                 eff = slot[0] & GRCAN_MSG_IDE;
1186                 rtr = slot[0] & GRCAN_MSG_RTR;
1187                 if (eff) {
1188                         cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1189                                       >> GRCAN_MSG_EID_BIT);
1190                         cf->can_id |= CAN_EFF_FLAG;
1191                 } else {
1192                         cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1193                                       >> GRCAN_MSG_BID_BIT);
1194                 }
1195                 cf->len = can_cc_dlc2len((slot[1] & GRCAN_MSG_DLC)
1196                                           >> GRCAN_MSG_DLC_BIT);
1197                 if (rtr) {
1198                         cf->can_id |= CAN_RTR_FLAG;
1199                 } else {
1200                         for (i = 0; i < cf->len; i++) {
1201                                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1202                                 shift = GRCAN_MSG_DATA_SHIFT(i);
1203                                 cf->data[i] = (u8)(slot[j] >> shift);
1204                         }
1205
1206                         stats->rx_bytes += cf->len;
1207                 }
1208                 stats->rx_packets++;
1209
1210                 netif_receive_skb(skb);
1211
1212                 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1213         }
1214
1215         /* Make sure everything is read before allowing hardware to
1216          * use the memory
1217          */
1218         mb();
1219
1220         /* Update read pointer - no need to check for ongoing */
1221         if (likely(rd != startrd))
1222                 grcan_write_reg(&regs->rxrd, rd);
1223
1224         return work_done;
1225 }
1226
1227 static int grcan_poll(struct napi_struct *napi, int budget)
1228 {
1229         struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1230         struct net_device *dev = priv->dev;
1231         struct grcan_registers __iomem *regs = priv->regs;
1232         unsigned long flags;
1233         int work_done;
1234
1235         work_done = grcan_receive(dev, budget);
1236
1237         grcan_transmit_catch_up(dev);
1238
1239         if (work_done < budget) {
1240                 napi_complete(napi);
1241
1242                 /* Guarantee no interference with a running reset that otherwise
1243                  * could turn off interrupts.
1244                  */
1245                 spin_lock_irqsave(&priv->lock, flags);
1246
1247                 /* Enable tx and rx interrupts again. No need to check
1248                  * priv->closing as napi_disable in grcan_close is waiting for
1249                  * scheduled napi calls to finish.
1250                  */
1251                 grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1252
1253                 spin_unlock_irqrestore(&priv->lock, flags);
1254         }
1255
1256         return work_done;
1257 }
1258
1259 /* Work tx bug by waiting while for the risky situation to clear. If that fails,
1260  * drop a frame in one-shot mode or indicate a busy device otherwise.
1261  *
1262  * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1263  * value that should be returned by grcan_start_xmit when aborting the xmit.
1264  */
1265 static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1266                                   u32 txwr, u32 oneshotmode,
1267                                   netdev_tx_t *netdev_tx_status)
1268 {
1269         struct grcan_priv *priv = netdev_priv(dev);
1270         struct grcan_registers __iomem *regs = priv->regs;
1271         struct grcan_dma *dma = &priv->dma;
1272         int i;
1273         unsigned long flags;
1274
1275         /* Wait a while for ongoing to be cleared or read pointer to catch up to
1276          * write pointer. The latter is needed due to a bug in older versions of
1277          * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1278          * transmission fails.
1279          */
1280         for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1281                 udelay(1);
1282                 if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1283                     grcan_read_reg(&regs->txrd) == txwr) {
1284                         return 0;
1285                 }
1286         }
1287
1288         /* Clean up, in case the situation was not resolved */
1289         spin_lock_irqsave(&priv->lock, flags);
1290         if (!priv->resetting && !priv->closing) {
1291                 /* Queue might have been stopped earlier in grcan_start_xmit */
1292                 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1293                         netif_wake_queue(dev);
1294                 /* Set a timer to resolve a hanged tx controller */
1295                 if (!timer_pending(&priv->hang_timer))
1296                         grcan_reset_timer(&priv->hang_timer,
1297                                           priv->can.bittiming.bitrate);
1298         }
1299         spin_unlock_irqrestore(&priv->lock, flags);
1300
1301         if (oneshotmode) {
1302                 /* In one-shot mode we should never end up here because
1303                  * then the interrupt handler increases txrd on TXLOSS,
1304                  * but it is consistent with one-shot mode to drop the
1305                  * frame in this case.
1306                  */
1307                 kfree_skb(skb);
1308                 *netdev_tx_status = NETDEV_TX_OK;
1309         } else {
1310                 /* In normal mode the socket-can transmission queue get
1311                  * to keep the frame so that it can be retransmitted
1312                  * later
1313                  */
1314                 *netdev_tx_status = NETDEV_TX_BUSY;
1315         }
1316         return -EBUSY;
1317 }
1318
1319 /* Notes on the tx cyclic buffer handling:
1320  *
1321  * regs->txwr   - the next slot for the driver to put data to be sent
1322  * regs->txrd   - the next slot for the device to read data
1323  * priv->eskbp  - the next slot for the driver to call can_put_echo_skb for
1324  *
1325  * grcan_start_xmit can enter more messages as long as regs->txwr does
1326  * not reach priv->eskbp (within 1 message gap)
1327  *
1328  * The device sends messages until regs->txrd reaches regs->txwr
1329  *
1330  * The interrupt calls handler calls can_put_echo_skb until
1331  * priv->eskbp reaches regs->txrd
1332  */
1333 static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1334                                     struct net_device *dev)
1335 {
1336         struct grcan_priv *priv = netdev_priv(dev);
1337         struct grcan_registers __iomem *regs = priv->regs;
1338         struct grcan_dma *dma = &priv->dma;
1339         struct can_frame *cf = (struct can_frame *)skb->data;
1340         u32 id, txwr, txrd, space, txctrl;
1341         int slotindex;
1342         u32 *slot;
1343         u32 i, rtr, eff, dlc, tmp, err;
1344         int j, shift;
1345         unsigned long flags;
1346         u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1347
1348         if (can_dev_dropped_skb(dev, skb))
1349                 return NETDEV_TX_OK;
1350
1351         /* Trying to transmit in silent mode will generate error interrupts, but
1352          * this should never happen - the queue should not have been started.
1353          */
1354         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1355                 return NETDEV_TX_BUSY;
1356
1357         /* Reads of priv->eskbp and shut-downs of the queue needs to
1358          * be atomic towards the updates to priv->eskbp and wake-ups
1359          * of the queue in the interrupt handler.
1360          */
1361         spin_lock_irqsave(&priv->lock, flags);
1362
1363         txwr = grcan_read_reg(&regs->txwr);
1364         space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1365
1366         slotindex = txwr / GRCAN_MSG_SIZE;
1367         slot = dma->tx.buf + txwr;
1368
1369         if (unlikely(space == 1))
1370                 netif_stop_queue(dev);
1371
1372         spin_unlock_irqrestore(&priv->lock, flags);
1373         /* End of critical section*/
1374
1375         /* This should never happen. If circular buffer is full, the
1376          * netif_stop_queue should have been stopped already.
1377          */
1378         if (unlikely(!space)) {
1379                 netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1380                 return NETDEV_TX_BUSY;
1381         }
1382
1383         /* Convert and write CAN message to DMA buffer */
1384         eff = cf->can_id & CAN_EFF_FLAG;
1385         rtr = cf->can_id & CAN_RTR_FLAG;
1386         id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1387         dlc = cf->len;
1388         if (eff)
1389                 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1390         else
1391                 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1392         slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1393
1394         slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1395         slot[2] = 0;
1396         slot[3] = 0;
1397         for (i = 0; i < dlc; i++) {
1398                 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1399                 shift = GRCAN_MSG_DATA_SHIFT(i);
1400                 slot[j] |= cf->data[i] << shift;
1401         }
1402
1403         /* Checking that channel has not been disabled. These cases
1404          * should never happen
1405          */
1406         txctrl = grcan_read_reg(&regs->txctrl);
1407         if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1408                 netdev_err(dev, "tx channel spuriously disabled\n");
1409
1410         if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1411                 netdev_err(dev, "one-shot mode spuriously disabled\n");
1412
1413         /* Bug workaround for old version of grcan where updating txwr
1414          * in the same clock cycle as the controller updates txrd to
1415          * the current txwr could hang the can controller
1416          */
1417         if (priv->need_txbug_workaround) {
1418                 txrd = grcan_read_reg(&regs->txrd);
1419                 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1420                         netdev_tx_t txstatus;
1421
1422                         err = grcan_txbug_workaround(dev, skb, txwr,
1423                                                      oneshotmode, &txstatus);
1424                         if (err)
1425                                 return txstatus;
1426                 }
1427         }
1428
1429         /* Prepare skb for echoing. This must be after the bug workaround above
1430          * as ownership of the skb is passed on by calling can_put_echo_skb.
1431          * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1432          * can_put_echo_skb would be an error unless other measures are
1433          * taken.
1434          */
1435         can_put_echo_skb(skb, dev, slotindex, 0);
1436
1437         /* Make sure everything is written before allowing hardware to
1438          * read from the memory
1439          */
1440         wmb();
1441
1442         /* Update write pointer to start transmission */
1443         grcan_write_reg(&regs->txwr,
1444                         grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1445
1446         return NETDEV_TX_OK;
1447 }
1448
1449 /* ========== Setting up sysfs interface and module parameters ========== */
1450
1451 #define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1452
1453 #define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc)                \
1454         static void grcan_sanitize_##name(struct platform_device *pd)   \
1455         {                                                               \
1456                 struct grcan_device_config grcan_default_config         \
1457                         = GRCAN_DEFAULT_DEVICE_CONFIG;                  \
1458                 if (valcheckf(grcan_module_config.name)) {              \
1459                         dev_err(&pd->dev,                               \
1460                                 "Invalid module parameter value for "   \
1461                                 #name " - setting default\n");          \
1462                         grcan_module_config.name =                      \
1463                                 grcan_default_config.name;              \
1464                 }                                                       \
1465         }                                                               \
1466         module_param_named(name, grcan_module_config.name,              \
1467                            mtype, 0444);                                \
1468         MODULE_PARM_DESC(name, desc)
1469
1470 #define GRCAN_CONFIG_ATTR(name, desc)                                   \
1471         static ssize_t grcan_store_##name(struct device *sdev,          \
1472                                           struct device_attribute *att, \
1473                                           const char *buf,              \
1474                                           size_t count)                 \
1475         {                                                               \
1476                 struct net_device *dev = to_net_dev(sdev);              \
1477                 struct grcan_priv *priv = netdev_priv(dev);             \
1478                 u8 val;                                                 \
1479                 int ret;                                                \
1480                 if (dev->flags & IFF_UP)                                \
1481                         return -EBUSY;                                  \
1482                 ret = kstrtou8(buf, 0, &val);                           \
1483                 if (ret < 0 || val > 1)                                 \
1484                         return -EINVAL;                                 \
1485                 priv->config.name = val;                                \
1486                 return count;                                           \
1487         }                                                               \
1488         static ssize_t grcan_show_##name(struct device *sdev,           \
1489                                          struct device_attribute *att,  \
1490                                          char *buf)                     \
1491         {                                                               \
1492                 struct net_device *dev = to_net_dev(sdev);              \
1493                 struct grcan_priv *priv = netdev_priv(dev);             \
1494                 return sprintf(buf, "%d\n", priv->config.name);         \
1495         }                                                               \
1496         static DEVICE_ATTR(name, 0644,                                  \
1497                            grcan_show_##name,                           \
1498                            grcan_store_##name);                         \
1499         GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1500
1501 /* The following configuration options are made available both via module
1502  * parameters and writable sysfs files. See the chapter about GRCAN in the
1503  * documentation for the GRLIB VHDL library for further details.
1504  */
1505 GRCAN_CONFIG_ATTR(enable0,
1506                   "Configuration of physical interface 0. Determines\n" \
1507                   "the \"Enable 0\" bit of the configuration register.\n" \
1508                   "Format: 0 | 1\nDefault: 0\n");
1509
1510 GRCAN_CONFIG_ATTR(enable1,
1511                   "Configuration of physical interface 1. Determines\n" \
1512                   "the \"Enable 1\" bit of the configuration register.\n" \
1513                   "Format: 0 | 1\nDefault: 0\n");
1514
1515 GRCAN_CONFIG_ATTR(select,
1516                   "Select which physical interface to use.\n"   \
1517                   "Format: 0 | 1\nDefault: 0\n");
1518
1519 /* The tx and rx buffer size configuration options are only available via module
1520  * parameters.
1521  */
1522 GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1523                    "Sets the size of the tx buffer.\n"                  \
1524                    "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1525                    "Default: 1024\n");
1526 GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1527                    "Sets the size of the rx buffer.\n"                  \
1528                    "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1529                    "Default: 1024\n");
1530
1531 /* Function that makes sure that configuration done using
1532  * module parameters are set to valid values
1533  */
1534 static void grcan_sanitize_module_config(struct platform_device *ofdev)
1535 {
1536         grcan_sanitize_enable0(ofdev);
1537         grcan_sanitize_enable1(ofdev);
1538         grcan_sanitize_select(ofdev);
1539         grcan_sanitize_txsize(ofdev);
1540         grcan_sanitize_rxsize(ofdev);
1541 }
1542
1543 static const struct attribute *const sysfs_grcan_attrs[] = {
1544         /* Config attrs */
1545         &dev_attr_enable0.attr,
1546         &dev_attr_enable1.attr,
1547         &dev_attr_select.attr,
1548         NULL,
1549 };
1550
1551 static const struct attribute_group sysfs_grcan_group = {
1552         .name   = "grcan",
1553         .attrs  = (struct attribute **)sysfs_grcan_attrs,
1554 };
1555
1556 /* ========== Setting up the driver ========== */
1557
1558 static const struct net_device_ops grcan_netdev_ops = {
1559         .ndo_open       = grcan_open,
1560         .ndo_stop       = grcan_close,
1561         .ndo_start_xmit = grcan_start_xmit,
1562         .ndo_change_mtu = can_change_mtu,
1563 };
1564
1565 static const struct ethtool_ops grcan_ethtool_ops = {
1566         .get_ts_info = ethtool_op_get_ts_info,
1567 };
1568
1569 static int grcan_setup_netdev(struct platform_device *ofdev,
1570                               void __iomem *base,
1571                               int irq, u32 ambafreq, bool txbug)
1572 {
1573         struct net_device *dev;
1574         struct grcan_priv *priv;
1575         struct grcan_registers __iomem *regs;
1576         int err;
1577
1578         dev = alloc_candev(sizeof(struct grcan_priv), 0);
1579         if (!dev)
1580                 return -ENOMEM;
1581
1582         dev->irq = irq;
1583         dev->flags |= IFF_ECHO;
1584         dev->netdev_ops = &grcan_netdev_ops;
1585         dev->ethtool_ops = &grcan_ethtool_ops;
1586         dev->sysfs_groups[0] = &sysfs_grcan_group;
1587
1588         priv = netdev_priv(dev);
1589         memcpy(&priv->config, &grcan_module_config,
1590                sizeof(struct grcan_device_config));
1591         priv->dev = dev;
1592         priv->ofdev_dev = &ofdev->dev;
1593         priv->regs = base;
1594         priv->can.bittiming_const = &grcan_bittiming_const;
1595         priv->can.do_set_bittiming = grcan_set_bittiming;
1596         priv->can.do_set_mode = grcan_set_mode;
1597         priv->can.do_get_berr_counter = grcan_get_berr_counter;
1598         priv->can.clock.freq = ambafreq;
1599         priv->can.ctrlmode_supported =
1600                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1601         priv->need_txbug_workaround = txbug;
1602
1603         /* Discover if triple sampling is supported by hardware */
1604         regs = priv->regs;
1605         grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1606         grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1607         if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1608                 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1609                 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1610         }
1611
1612         spin_lock_init(&priv->lock);
1613
1614         if (priv->need_txbug_workaround) {
1615                 timer_setup(&priv->rr_timer, grcan_running_reset, 0);
1616                 timer_setup(&priv->hang_timer, grcan_initiate_running_reset, 0);
1617         }
1618
1619         netif_napi_add_weight(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1620
1621         SET_NETDEV_DEV(dev, &ofdev->dev);
1622         dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1623                  priv->regs, dev->irq, priv->can.clock.freq);
1624
1625         err = register_candev(dev);
1626         if (err)
1627                 goto exit_free_candev;
1628
1629         platform_set_drvdata(ofdev, dev);
1630
1631         /* Reset device to allow bit-timing to be set. No need to call
1632          * grcan_reset at this stage. That is done in grcan_open.
1633          */
1634         grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1635
1636         return 0;
1637 exit_free_candev:
1638         free_candev(dev);
1639         return err;
1640 }
1641
1642 static int grcan_probe(struct platform_device *ofdev)
1643 {
1644         struct device_node *np = ofdev->dev.of_node;
1645         struct device_node *sysid_parent;
1646         u32 sysid, ambafreq;
1647         int irq, err;
1648         void __iomem *base;
1649         bool txbug = true;
1650
1651         /* Compare GRLIB version number with the first that does not
1652          * have the tx bug (see start_xmit)
1653          */
1654         sysid_parent = of_find_node_by_path("/ambapp0");
1655         if (sysid_parent) {
1656                 err = of_property_read_u32(sysid_parent, "systemid", &sysid);
1657                 if (!err && ((sysid & GRLIB_VERSION_MASK) >=
1658                              GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1659                         txbug = false;
1660                 of_node_put(sysid_parent);
1661         }
1662
1663         err = of_property_read_u32(np, "freq", &ambafreq);
1664         if (err) {
1665                 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1666                 goto exit_error;
1667         }
1668
1669         base = devm_platform_ioremap_resource(ofdev, 0);
1670         if (IS_ERR(base)) {
1671                 err = PTR_ERR(base);
1672                 goto exit_error;
1673         }
1674
1675         irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1676         if (!irq) {
1677                 dev_err(&ofdev->dev, "no irq found\n");
1678                 err = -ENODEV;
1679                 goto exit_error;
1680         }
1681
1682         grcan_sanitize_module_config(ofdev);
1683
1684         err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1685         if (err)
1686                 goto exit_dispose_irq;
1687
1688         return 0;
1689
1690 exit_dispose_irq:
1691         irq_dispose_mapping(irq);
1692 exit_error:
1693         dev_err(&ofdev->dev,
1694                 "%s socket CAN driver initialization failed with error %d\n",
1695                 DRV_NAME, err);
1696         return err;
1697 }
1698
1699 static int grcan_remove(struct platform_device *ofdev)
1700 {
1701         struct net_device *dev = platform_get_drvdata(ofdev);
1702         struct grcan_priv *priv = netdev_priv(dev);
1703
1704         unregister_candev(dev); /* Will in turn call grcan_close */
1705
1706         irq_dispose_mapping(dev->irq);
1707         netif_napi_del(&priv->napi);
1708         free_candev(dev);
1709
1710         return 0;
1711 }
1712
1713 static const struct of_device_id grcan_match[] = {
1714         {.name = "GAISLER_GRCAN"},
1715         {.name = "01_03d"},
1716         {.name = "GAISLER_GRHCAN"},
1717         {.name = "01_034"},
1718         {},
1719 };
1720
1721 MODULE_DEVICE_TABLE(of, grcan_match);
1722
1723 static struct platform_driver grcan_driver = {
1724         .driver = {
1725                 .name = DRV_NAME,
1726                 .of_match_table = grcan_match,
1727         },
1728         .probe = grcan_probe,
1729         .remove = grcan_remove,
1730 };
1731
1732 module_platform_driver(grcan_driver);
1733
1734 MODULE_AUTHOR("Aeroflex Gaisler AB.");
1735 MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1736 MODULE_LICENSE("GPL");