drivers/net/dsa/microchip/ksz_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Microchip switch driver main logic
   4  *
   5  * Copyright (C) 2017-2019 Microchip Technology Inc.
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/export.h>
  10 #include <linux/gpio/consumer.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_data/microchip-ksz.h>
  14 #include <linux/phy.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/if_bridge.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_net.h>
  19 #include <linux/micrel_phy.h>
  20 #include <net/dsa.h>
  21 #include <net/switchdev.h>
  22
  23 #include "ksz_common.h"
  24 #include "ksz8.h"
  25 #include "ksz9477.h"
  26 #include "lan937x.h"
  27
  28 #define MIB_COUNTER_NUM 0x20
  29
  30 struct ksz_stats_raw {
  31         u64 rx_hi;
  32         u64 rx_undersize;
  33         u64 rx_fragments;
  34         u64 rx_oversize;
  35         u64 rx_jabbers;
  36         u64 rx_symbol_err;
  37         u64 rx_crc_err;
  38         u64 rx_align_err;
  39         u64 rx_mac_ctrl;
  40         u64 rx_pause;
  41         u64 rx_bcast;
  42         u64 rx_mcast;
  43         u64 rx_ucast;
  44         u64 rx_64_or_less;
  45         u64 rx_65_127;
  46         u64 rx_128_255;
  47         u64 rx_256_511;
  48         u64 rx_512_1023;
  49         u64 rx_1024_1522;
  50         u64 rx_1523_2000;
  51         u64 rx_2001;
  52         u64 tx_hi;
  53         u64 tx_late_col;
  54         u64 tx_pause;
  55         u64 tx_bcast;
  56         u64 tx_mcast;
  57         u64 tx_ucast;
  58         u64 tx_deferred;
  59         u64 tx_total_col;
  60         u64 tx_exc_col;
  61         u64 tx_single_col;
  62         u64 tx_mult_col;
  63         u64 rx_total;
  64         u64 tx_total;
  65         u64 rx_discards;
  66         u64 tx_discards;
  67 };
  68
  69 static const struct ksz_mib_names ksz88xx_mib_names[] = {
  70         { 0x00, "rx" },
  71         { 0x01, "rx_hi" },
  72         { 0x02, "rx_undersize" },
  73         { 0x03, "rx_fragments" },
  74         { 0x04, "rx_oversize" },
  75         { 0x05, "rx_jabbers" },
  76         { 0x06, "rx_symbol_err" },
  77         { 0x07, "rx_crc_err" },
  78         { 0x08, "rx_align_err" },
  79         { 0x09, "rx_mac_ctrl" },
  80         { 0x0a, "rx_pause" },
  81         { 0x0b, "rx_bcast" },
  82         { 0x0c, "rx_mcast" },
  83         { 0x0d, "rx_ucast" },
  84         { 0x0e, "rx_64_or_less" },
  85         { 0x0f, "rx_65_127" },
  86         { 0x10, "rx_128_255" },
  87         { 0x11, "rx_256_511" },
  88         { 0x12, "rx_512_1023" },
  89         { 0x13, "rx_1024_1522" },
  90         { 0x14, "tx" },
  91         { 0x15, "tx_hi" },
  92         { 0x16, "tx_late_col" },
  93         { 0x17, "tx_pause" },
  94         { 0x18, "tx_bcast" },
  95         { 0x19, "tx_mcast" },
  96         { 0x1a, "tx_ucast" },
  97         { 0x1b, "tx_deferred" },
  98         { 0x1c, "tx_total_col" },
  99         { 0x1d, "tx_exc_col" },
 100         { 0x1e, "tx_single_col" },
 101         { 0x1f, "tx_mult_col" },
 102         { 0x100, "rx_discards" },
 103         { 0x101, "tx_discards" },
 104 };
 105
 106 static const struct ksz_mib_names ksz9477_mib_names[] = {
 107         { 0x00, "rx_hi" },
 108         { 0x01, "rx_undersize" },
 109         { 0x02, "rx_fragments" },
 110         { 0x03, "rx_oversize" },
 111         { 0x04, "rx_jabbers" },
 112         { 0x05, "rx_symbol_err" },
 113         { 0x06, "rx_crc_err" },
 114         { 0x07, "rx_align_err" },
 115         { 0x08, "rx_mac_ctrl" },
 116         { 0x09, "rx_pause" },
 117         { 0x0A, "rx_bcast" },
 118         { 0x0B, "rx_mcast" },
 119         { 0x0C, "rx_ucast" },
 120         { 0x0D, "rx_64_or_less" },
 121         { 0x0E, "rx_65_127" },
 122         { 0x0F, "rx_128_255" },
 123         { 0x10, "rx_256_511" },
 124         { 0x11, "rx_512_1023" },
 125         { 0x12, "rx_1024_1522" },
 126         { 0x13, "rx_1523_2000" },
 127         { 0x14, "rx_2001" },
 128         { 0x15, "tx_hi" },
 129         { 0x16, "tx_late_col" },
 130         { 0x17, "tx_pause" },
 131         { 0x18, "tx_bcast" },
 132         { 0x19, "tx_mcast" },
 133         { 0x1A, "tx_ucast" },
 134         { 0x1B, "tx_deferred" },
 135         { 0x1C, "tx_total_col" },
 136         { 0x1D, "tx_exc_col" },
 137         { 0x1E, "tx_single_col" },
 138         { 0x1F, "tx_mult_col" },
 139         { 0x80, "rx_total" },
 140         { 0x81, "tx_total" },
 141         { 0x82, "rx_discards" },
 142         { 0x83, "tx_discards" },
 143 };
 144
 145 static const struct ksz_dev_ops ksz8_dev_ops = {
 146         .setup = ksz8_setup,
 147         .get_port_addr = ksz8_get_port_addr,
 148         .cfg_port_member = ksz8_cfg_port_member,
 149         .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
 150         .port_setup = ksz8_port_setup,
 151         .r_phy = ksz8_r_phy,
 152         .w_phy = ksz8_w_phy,
 153         .r_mib_cnt = ksz8_r_mib_cnt,
 154         .r_mib_pkt = ksz8_r_mib_pkt,
 155         .freeze_mib = ksz8_freeze_mib,
 156         .port_init_cnt = ksz8_port_init_cnt,
 157         .fdb_dump = ksz8_fdb_dump,
 158         .mdb_add = ksz8_mdb_add,
 159         .mdb_del = ksz8_mdb_del,
 160         .vlan_filtering = ksz8_port_vlan_filtering,
 161         .vlan_add = ksz8_port_vlan_add,
 162         .vlan_del = ksz8_port_vlan_del,
 163         .mirror_add = ksz8_port_mirror_add,
 164         .mirror_del = ksz8_port_mirror_del,
 165         .get_caps = ksz8_get_caps,
 166         .config_cpu_port = ksz8_config_cpu_port,
 167         .enable_stp_addr = ksz8_enable_stp_addr,
 168         .reset = ksz8_reset_switch,
 169         .init = ksz8_switch_init,
 170         .exit = ksz8_switch_exit,
 171 };
 172
 173 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
 174                                         unsigned int mode,
 175                                         phy_interface_t interface,
 176                                         struct phy_device *phydev, int speed,
 177                                         int duplex, bool tx_pause,
 178                                         bool rx_pause);
 179
 180 static const struct ksz_dev_ops ksz9477_dev_ops = {
 181         .setup = ksz9477_setup,
 182         .get_port_addr = ksz9477_get_port_addr,
 183         .cfg_port_member = ksz9477_cfg_port_member,
 184         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 185         .port_setup = ksz9477_port_setup,
 186         .r_phy = ksz9477_r_phy,
 187         .w_phy = ksz9477_w_phy,
 188         .r_mib_cnt = ksz9477_r_mib_cnt,
 189         .r_mib_pkt = ksz9477_r_mib_pkt,
 190         .r_mib_stat64 = ksz_r_mib_stats64,
 191         .freeze_mib = ksz9477_freeze_mib,
 192         .port_init_cnt = ksz9477_port_init_cnt,
 193         .vlan_filtering = ksz9477_port_vlan_filtering,
 194         .vlan_add = ksz9477_port_vlan_add,
 195         .vlan_del = ksz9477_port_vlan_del,
 196         .mirror_add = ksz9477_port_mirror_add,
 197         .mirror_del = ksz9477_port_mirror_del,
 198         .get_caps = ksz9477_get_caps,
 199         .fdb_dump = ksz9477_fdb_dump,
 200         .fdb_add = ksz9477_fdb_add,
 201         .fdb_del = ksz9477_fdb_del,
 202         .mdb_add = ksz9477_mdb_add,
 203         .mdb_del = ksz9477_mdb_del,
 204         .change_mtu = ksz9477_change_mtu,
 205         .max_mtu = ksz9477_max_mtu,
 206         .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
 207         .config_cpu_port = ksz9477_config_cpu_port,
 208         .enable_stp_addr = ksz9477_enable_stp_addr,
 209         .reset = ksz9477_reset_switch,
 210         .init = ksz9477_switch_init,
 211         .exit = ksz9477_switch_exit,
 212 };
 213
 214 static const struct ksz_dev_ops lan937x_dev_ops = {
 215         .setup = lan937x_setup,
 216         .teardown = lan937x_teardown,
 217         .get_port_addr = ksz9477_get_port_addr,
 218         .cfg_port_member = ksz9477_cfg_port_member,
 219         .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
 220         .port_setup = lan937x_port_setup,
 221         .r_phy = lan937x_r_phy,
 222         .w_phy = lan937x_w_phy,
 223         .r_mib_cnt = ksz9477_r_mib_cnt,
 224         .r_mib_pkt = ksz9477_r_mib_pkt,
 225         .r_mib_stat64 = ksz_r_mib_stats64,
 226         .freeze_mib = ksz9477_freeze_mib,
 227         .port_init_cnt = ksz9477_port_init_cnt,
 228         .vlan_filtering = ksz9477_port_vlan_filtering,
 229         .vlan_add = ksz9477_port_vlan_add,
 230         .vlan_del = ksz9477_port_vlan_del,
 231         .mirror_add = ksz9477_port_mirror_add,
 232         .mirror_del = ksz9477_port_mirror_del,
 233         .get_caps = lan937x_phylink_get_caps,
 234         .setup_rgmii_delay = lan937x_setup_rgmii_delay,
 235         .fdb_dump = ksz9477_fdb_dump,
 236         .fdb_add = ksz9477_fdb_add,
 237         .fdb_del = ksz9477_fdb_del,
 238         .mdb_add = ksz9477_mdb_add,
 239         .mdb_del = ksz9477_mdb_del,
 240         .change_mtu = lan937x_change_mtu,
 241         .max_mtu = ksz9477_max_mtu,
 242         .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
 243         .config_cpu_port = lan937x_config_cpu_port,
 244         .enable_stp_addr = ksz9477_enable_stp_addr,
 245         .reset = lan937x_reset_switch,
 246         .init = lan937x_switch_init,
 247         .exit = lan937x_switch_exit,
 248 };
 249
 250 static const u16 ksz8795_regs[] = {
 251         [REG_IND_CTRL_0]                = 0x6E,
 252         [REG_IND_DATA_8]                = 0x70,
 253         [REG_IND_DATA_CHECK]            = 0x72,
 254         [REG_IND_DATA_HI]               = 0x71,
 255         [REG_IND_DATA_LO]               = 0x75,
 256         [REG_IND_MIB_CHECK]             = 0x74,
 257         [REG_IND_BYTE]                  = 0xA0,
 258         [P_FORCE_CTRL]                  = 0x0C,
 259         [P_LINK_STATUS]                 = 0x0E,
 260         [P_LOCAL_CTRL]                  = 0x07,
 261         [P_NEG_RESTART_CTRL]            = 0x0D,
 262         [P_REMOTE_STATUS]               = 0x08,
 263         [P_SPEED_STATUS]                = 0x09,
 264         [S_TAIL_TAG_CTRL]               = 0x0C,
 265         [P_STP_CTRL]                    = 0x02,
 266         [S_START_CTRL]                  = 0x01,
 267         [S_BROADCAST_CTRL]              = 0x06,
 268         [S_MULTICAST_CTRL]              = 0x04,
 269         [P_XMII_CTRL_0]                 = 0x06,
 270         [P_XMII_CTRL_1]                 = 0x56,
 271 };
 272
 273 static const u32 ksz8795_masks[] = {
 274         [PORT_802_1P_REMAPPING]         = BIT(7),
 275         [SW_TAIL_TAG_ENABLE]            = BIT(1),
 276         [MIB_COUNTER_OVERFLOW]          = BIT(6),
 277         [MIB_COUNTER_VALID]             = BIT(5),
 278         [VLAN_TABLE_FID]                = GENMASK(6, 0),
 279         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(11, 7),
 280         [VLAN_TABLE_VALID]              = BIT(12),
 281         [STATIC_MAC_TABLE_VALID]        = BIT(21),
 282         [STATIC_MAC_TABLE_USE_FID]      = BIT(23),
 283         [STATIC_MAC_TABLE_FID]          = GENMASK(30, 24),
 284         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(26),
 285         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(24, 20),
 286         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(6, 0),
 287         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(8),
 288         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 289         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 29),
 290         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(26, 20),
 291         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(26, 24),
 292         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(28, 27),
 293         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 294         [P_MII_RX_FLOW_CTRL]            = BIT(5),
 295 };
 296
 297 static const u8 ksz8795_xmii_ctrl0[] = {
 298         [P_MII_100MBIT]                 = 0,
 299         [P_MII_10MBIT]                  = 1,
 300         [P_MII_FULL_DUPLEX]             = 0,
 301         [P_MII_HALF_DUPLEX]             = 1,
 302 };
 303
 304 static const u8 ksz8795_xmii_ctrl1[] = {
 305         [P_RGMII_SEL]                   = 3,
 306         [P_GMII_SEL]                    = 2,
 307         [P_RMII_SEL]                    = 1,
 308         [P_MII_SEL]                     = 0,
 309         [P_GMII_1GBIT]                  = 1,
 310         [P_GMII_NOT_1GBIT]              = 0,
 311 };
 312
 313 static const u8 ksz8795_shifts[] = {
 314         [VLAN_TABLE_MEMBERSHIP_S]       = 7,
 315         [VLAN_TABLE]                    = 16,
 316         [STATIC_MAC_FWD_PORTS]          = 16,
 317         [STATIC_MAC_FID]                = 24,
 318         [DYNAMIC_MAC_ENTRIES_H]         = 3,
 319         [DYNAMIC_MAC_ENTRIES]           = 29,
 320         [DYNAMIC_MAC_FID]               = 16,
 321         [DYNAMIC_MAC_TIMESTAMP]         = 27,
 322         [DYNAMIC_MAC_SRC_PORT]          = 24,
 323 };
 324
 325 static const u16 ksz8863_regs[] = {
 326         [REG_IND_CTRL_0]                = 0x79,
 327         [REG_IND_DATA_8]                = 0x7B,
 328         [REG_IND_DATA_CHECK]            = 0x7B,
 329         [REG_IND_DATA_HI]               = 0x7C,
 330         [REG_IND_DATA_LO]               = 0x80,
 331         [REG_IND_MIB_CHECK]             = 0x80,
 332         [P_FORCE_CTRL]                  = 0x0C,
 333         [P_LINK_STATUS]                 = 0x0E,
 334         [P_LOCAL_CTRL]                  = 0x0C,
 335         [P_NEG_RESTART_CTRL]            = 0x0D,
 336         [P_REMOTE_STATUS]               = 0x0E,
 337         [P_SPEED_STATUS]                = 0x0F,
 338         [S_TAIL_TAG_CTRL]               = 0x03,
 339         [P_STP_CTRL]                    = 0x02,
 340         [S_START_CTRL]                  = 0x01,
 341         [S_BROADCAST_CTRL]              = 0x06,
 342         [S_MULTICAST_CTRL]              = 0x04,
 343 };
 344
 345 static const u32 ksz8863_masks[] = {
 346         [PORT_802_1P_REMAPPING]         = BIT(3),
 347         [SW_TAIL_TAG_ENABLE]            = BIT(6),
 348         [MIB_COUNTER_OVERFLOW]          = BIT(7),
 349         [MIB_COUNTER_VALID]             = BIT(6),
 350         [VLAN_TABLE_FID]                = GENMASK(15, 12),
 351         [VLAN_TABLE_MEMBERSHIP]         = GENMASK(18, 16),
 352         [VLAN_TABLE_VALID]              = BIT(19),
 353         [STATIC_MAC_TABLE_VALID]        = BIT(19),
 354         [STATIC_MAC_TABLE_USE_FID]      = BIT(21),
 355         [STATIC_MAC_TABLE_FID]          = GENMASK(29, 26),
 356         [STATIC_MAC_TABLE_OVERRIDE]     = BIT(20),
 357         [STATIC_MAC_TABLE_FWD_PORTS]    = GENMASK(18, 16),
 358         [DYNAMIC_MAC_TABLE_ENTRIES_H]   = GENMASK(5, 0),
 359         [DYNAMIC_MAC_TABLE_MAC_EMPTY]   = BIT(7),
 360         [DYNAMIC_MAC_TABLE_NOT_READY]   = BIT(7),
 361         [DYNAMIC_MAC_TABLE_ENTRIES]     = GENMASK(31, 28),
 362         [DYNAMIC_MAC_TABLE_FID]         = GENMASK(19, 16),
 363         [DYNAMIC_MAC_TABLE_SRC_PORT]    = GENMASK(21, 20),
 364         [DYNAMIC_MAC_TABLE_TIMESTAMP]   = GENMASK(23, 22),
 365 };
 366
 367 static u8 ksz8863_shifts[] = {
 368         [VLAN_TABLE_MEMBERSHIP_S]       = 16,
 369         [STATIC_MAC_FWD_PORTS]          = 16,
 370         [STATIC_MAC_FID]                = 22,
 371         [DYNAMIC_MAC_ENTRIES_H]         = 3,
 372         [DYNAMIC_MAC_ENTRIES]           = 24,
 373         [DYNAMIC_MAC_FID]               = 16,
 374         [DYNAMIC_MAC_TIMESTAMP]         = 24,
 375         [DYNAMIC_MAC_SRC_PORT]          = 20,
 376 };
 377
 378 static const u16 ksz9477_regs[] = {
 379         [P_STP_CTRL]                    = 0x0B04,
 380         [S_START_CTRL]                  = 0x0300,
 381         [S_BROADCAST_CTRL]              = 0x0332,
 382         [S_MULTICAST_CTRL]              = 0x0331,
 383         [P_XMII_CTRL_0]                 = 0x0300,
 384         [P_XMII_CTRL_1]                 = 0x0301,
 385 };
 386
 387 static const u32 ksz9477_masks[] = {
 388         [ALU_STAT_WRITE]                = 0,
 389         [ALU_STAT_READ]                 = 1,
 390         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 391         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 392 };
 393
 394 static const u8 ksz9477_shifts[] = {
 395         [ALU_STAT_INDEX]                = 16,
 396 };
 397
 398 static const u8 ksz9477_xmii_ctrl0[] = {
 399         [P_MII_100MBIT]                 = 1,
 400         [P_MII_10MBIT]                  = 0,
 401         [P_MII_FULL_DUPLEX]             = 1,
 402         [P_MII_HALF_DUPLEX]             = 0,
 403 };
 404
 405 static const u8 ksz9477_xmii_ctrl1[] = {
 406         [P_RGMII_SEL]                   = 0,
 407         [P_RMII_SEL]                    = 1,
 408         [P_GMII_SEL]                    = 2,
 409         [P_MII_SEL]                     = 3,
 410         [P_GMII_1GBIT]                  = 0,
 411         [P_GMII_NOT_1GBIT]              = 1,
 412 };
 413
 414 static const u32 lan937x_masks[] = {
 415         [ALU_STAT_WRITE]                = 1,
 416         [ALU_STAT_READ]                 = 2,
 417         [P_MII_TX_FLOW_CTRL]            = BIT(5),
 418         [P_MII_RX_FLOW_CTRL]            = BIT(3),
 419 };
 420
 421 static const u8 lan937x_shifts[] = {
 422         [ALU_STAT_INDEX]                = 8,
 423 };
 424
 425 static const struct regmap_range ksz8563_valid_regs[] = {
 426         regmap_reg_range(0x0000, 0x0003),
 427         regmap_reg_range(0x0006, 0x0006),
 428         regmap_reg_range(0x000f, 0x001f),
 429         regmap_reg_range(0x0100, 0x0100),
 430         regmap_reg_range(0x0104, 0x0107),
 431         regmap_reg_range(0x010d, 0x010d),
 432         regmap_reg_range(0x0110, 0x0113),
 433         regmap_reg_range(0x0120, 0x012b),
 434         regmap_reg_range(0x0201, 0x0201),
 435         regmap_reg_range(0x0210, 0x0213),
 436         regmap_reg_range(0x0300, 0x0300),
 437         regmap_reg_range(0x0302, 0x031b),
 438         regmap_reg_range(0x0320, 0x032b),
 439         regmap_reg_range(0x0330, 0x0336),
 440         regmap_reg_range(0x0338, 0x033e),
 441         regmap_reg_range(0x0340, 0x035f),
 442         regmap_reg_range(0x0370, 0x0370),
 443         regmap_reg_range(0x0378, 0x0378),
 444         regmap_reg_range(0x037c, 0x037d),
 445         regmap_reg_range(0x0390, 0x0393),
 446         regmap_reg_range(0x0400, 0x040e),
 447         regmap_reg_range(0x0410, 0x042f),
 448         regmap_reg_range(0x0500, 0x0519),
 449         regmap_reg_range(0x0520, 0x054b),
 450         regmap_reg_range(0x0550, 0x05b3),
 451
 452         /* port 1 */
 453         regmap_reg_range(0x1000, 0x1001),
 454         regmap_reg_range(0x1004, 0x100b),
 455         regmap_reg_range(0x1013, 0x1013),
 456         regmap_reg_range(0x1017, 0x1017),
 457         regmap_reg_range(0x101b, 0x101b),
 458         regmap_reg_range(0x101f, 0x1021),
 459         regmap_reg_range(0x1030, 0x1030),
 460         regmap_reg_range(0x1100, 0x1111),
 461         regmap_reg_range(0x111a, 0x111d),
 462         regmap_reg_range(0x1122, 0x1127),
 463         regmap_reg_range(0x112a, 0x112b),
 464         regmap_reg_range(0x1136, 0x1139),
 465         regmap_reg_range(0x113e, 0x113f),
 466         regmap_reg_range(0x1400, 0x1401),
 467         regmap_reg_range(0x1403, 0x1403),
 468         regmap_reg_range(0x1410, 0x1417),
 469         regmap_reg_range(0x1420, 0x1423),
 470         regmap_reg_range(0x1500, 0x1507),
 471         regmap_reg_range(0x1600, 0x1612),
 472         regmap_reg_range(0x1800, 0x180f),
 473         regmap_reg_range(0x1900, 0x1907),
 474         regmap_reg_range(0x1914, 0x191b),
 475         regmap_reg_range(0x1a00, 0x1a03),
 476         regmap_reg_range(0x1a04, 0x1a08),
 477         regmap_reg_range(0x1b00, 0x1b01),
 478         regmap_reg_range(0x1b04, 0x1b04),
 479         regmap_reg_range(0x1c00, 0x1c05),
 480         regmap_reg_range(0x1c08, 0x1c1b),
 481
 482         /* port 2 */
 483         regmap_reg_range(0x2000, 0x2001),
 484         regmap_reg_range(0x2004, 0x200b),
 485         regmap_reg_range(0x2013, 0x2013),
 486         regmap_reg_range(0x2017, 0x2017),
 487         regmap_reg_range(0x201b, 0x201b),
 488         regmap_reg_range(0x201f, 0x2021),
 489         regmap_reg_range(0x2030, 0x2030),
 490         regmap_reg_range(0x2100, 0x2111),
 491         regmap_reg_range(0x211a, 0x211d),
 492         regmap_reg_range(0x2122, 0x2127),
 493         regmap_reg_range(0x212a, 0x212b),
 494         regmap_reg_range(0x2136, 0x2139),
 495         regmap_reg_range(0x213e, 0x213f),
 496         regmap_reg_range(0x2400, 0x2401),
 497         regmap_reg_range(0x2403, 0x2403),
 498         regmap_reg_range(0x2410, 0x2417),
 499         regmap_reg_range(0x2420, 0x2423),
 500         regmap_reg_range(0x2500, 0x2507),
 501         regmap_reg_range(0x2600, 0x2612),
 502         regmap_reg_range(0x2800, 0x280f),
 503         regmap_reg_range(0x2900, 0x2907),
 504         regmap_reg_range(0x2914, 0x291b),
 505         regmap_reg_range(0x2a00, 0x2a03),
 506         regmap_reg_range(0x2a04, 0x2a08),
 507         regmap_reg_range(0x2b00, 0x2b01),
 508         regmap_reg_range(0x2b04, 0x2b04),
 509         regmap_reg_range(0x2c00, 0x2c05),
 510         regmap_reg_range(0x2c08, 0x2c1b),
 511
 512         /* port 3 */
 513         regmap_reg_range(0x3000, 0x3001),
 514         regmap_reg_range(0x3004, 0x300b),
 515         regmap_reg_range(0x3013, 0x3013),
 516         regmap_reg_range(0x3017, 0x3017),
 517         regmap_reg_range(0x301b, 0x301b),
 518         regmap_reg_range(0x301f, 0x3021),
 519         regmap_reg_range(0x3030, 0x3030),
 520         regmap_reg_range(0x3300, 0x3301),
 521         regmap_reg_range(0x3303, 0x3303),
 522         regmap_reg_range(0x3400, 0x3401),
 523         regmap_reg_range(0x3403, 0x3403),
 524         regmap_reg_range(0x3410, 0x3417),
 525         regmap_reg_range(0x3420, 0x3423),
 526         regmap_reg_range(0x3500, 0x3507),
 527         regmap_reg_range(0x3600, 0x3612),
 528         regmap_reg_range(0x3800, 0x380f),
 529         regmap_reg_range(0x3900, 0x3907),
 530         regmap_reg_range(0x3914, 0x391b),
 531         regmap_reg_range(0x3a00, 0x3a03),
 532         regmap_reg_range(0x3a04, 0x3a08),
 533         regmap_reg_range(0x3b00, 0x3b01),
 534         regmap_reg_range(0x3b04, 0x3b04),
 535         regmap_reg_range(0x3c00, 0x3c05),
 536         regmap_reg_range(0x3c08, 0x3c1b),
 537 };
 538
 539 static const struct regmap_access_table ksz8563_register_set = {
 540         .yes_ranges = ksz8563_valid_regs,
 541         .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
 542 };
 543
 544 static const struct regmap_range ksz9477_valid_regs[] = {
 545         regmap_reg_range(0x0000, 0x0003),
 546         regmap_reg_range(0x0006, 0x0006),
 547         regmap_reg_range(0x0010, 0x001f),
 548         regmap_reg_range(0x0100, 0x0100),
 549         regmap_reg_range(0x0103, 0x0107),
 550         regmap_reg_range(0x010d, 0x010d),
 551         regmap_reg_range(0x0110, 0x0113),
 552         regmap_reg_range(0x0120, 0x012b),
 553         regmap_reg_range(0x0201, 0x0201),
 554         regmap_reg_range(0x0210, 0x0213),
 555         regmap_reg_range(0x0300, 0x0300),
 556         regmap_reg_range(0x0302, 0x031b),
 557         regmap_reg_range(0x0320, 0x032b),
 558         regmap_reg_range(0x0330, 0x0336),
 559         regmap_reg_range(0x0338, 0x033b),
 560         regmap_reg_range(0x033e, 0x033e),
 561         regmap_reg_range(0x0340, 0x035f),
 562         regmap_reg_range(0x0370, 0x0370),
 563         regmap_reg_range(0x0378, 0x0378),
 564         regmap_reg_range(0x037c, 0x037d),
 565         regmap_reg_range(0x0390, 0x0393),
 566         regmap_reg_range(0x0400, 0x040e),
 567         regmap_reg_range(0x0410, 0x042f),
 568         regmap_reg_range(0x0444, 0x044b),
 569         regmap_reg_range(0x0450, 0x046f),
 570         regmap_reg_range(0x0500, 0x0519),
 571         regmap_reg_range(0x0520, 0x054b),
 572         regmap_reg_range(0x0550, 0x05b3),
 573         regmap_reg_range(0x0604, 0x060b),
 574         regmap_reg_range(0x0610, 0x0612),
 575         regmap_reg_range(0x0614, 0x062c),
 576         regmap_reg_range(0x0640, 0x0645),
 577         regmap_reg_range(0x0648, 0x064d),
 578
 579         /* port 1 */
 580         regmap_reg_range(0x1000, 0x1001),
 581         regmap_reg_range(0x1013, 0x1013),
 582         regmap_reg_range(0x1017, 0x1017),
 583         regmap_reg_range(0x101b, 0x101b),
 584         regmap_reg_range(0x101f, 0x1020),
 585         regmap_reg_range(0x1030, 0x1030),
 586         regmap_reg_range(0x1100, 0x1115),
 587         regmap_reg_range(0x111a, 0x111f),
 588         regmap_reg_range(0x1122, 0x1127),
 589         regmap_reg_range(0x112a, 0x112b),
 590         regmap_reg_range(0x1136, 0x1139),
 591         regmap_reg_range(0x113e, 0x113f),
 592         regmap_reg_range(0x1400, 0x1401),
 593         regmap_reg_range(0x1403, 0x1403),
 594         regmap_reg_range(0x1410, 0x1417),
 595         regmap_reg_range(0x1420, 0x1423),
 596         regmap_reg_range(0x1500, 0x1507),
 597         regmap_reg_range(0x1600, 0x1613),
 598         regmap_reg_range(0x1800, 0x180f),
 599         regmap_reg_range(0x1820, 0x1827),
 600         regmap_reg_range(0x1830, 0x1837),
 601         regmap_reg_range(0x1840, 0x184b),
 602         regmap_reg_range(0x1900, 0x1907),
 603         regmap_reg_range(0x1914, 0x191b),
 604         regmap_reg_range(0x1920, 0x1920),
 605         regmap_reg_range(0x1923, 0x1927),
 606         regmap_reg_range(0x1a00, 0x1a03),
 607         regmap_reg_range(0x1a04, 0x1a07),
 608         regmap_reg_range(0x1b00, 0x1b01),
 609         regmap_reg_range(0x1b04, 0x1b04),
 610         regmap_reg_range(0x1c00, 0x1c05),
 611         regmap_reg_range(0x1c08, 0x1c1b),
 612
 613         /* port 2 */
 614         regmap_reg_range(0x2000, 0x2001),
 615         regmap_reg_range(0x2013, 0x2013),
 616         regmap_reg_range(0x2017, 0x2017),
 617         regmap_reg_range(0x201b, 0x201b),
 618         regmap_reg_range(0x201f, 0x2020),
 619         regmap_reg_range(0x2030, 0x2030),
 620         regmap_reg_range(0x2100, 0x2115),
 621         regmap_reg_range(0x211a, 0x211f),
 622         regmap_reg_range(0x2122, 0x2127),
 623         regmap_reg_range(0x212a, 0x212b),
 624         regmap_reg_range(0x2136, 0x2139),
 625         regmap_reg_range(0x213e, 0x213f),
 626         regmap_reg_range(0x2400, 0x2401),
 627         regmap_reg_range(0x2403, 0x2403),
 628         regmap_reg_range(0x2410, 0x2417),
 629         regmap_reg_range(0x2420, 0x2423),
 630         regmap_reg_range(0x2500, 0x2507),
 631         regmap_reg_range(0x2600, 0x2613),
 632         regmap_reg_range(0x2800, 0x280f),
 633         regmap_reg_range(0x2820, 0x2827),
 634         regmap_reg_range(0x2830, 0x2837),
 635         regmap_reg_range(0x2840, 0x284b),
 636         regmap_reg_range(0x2900, 0x2907),
 637         regmap_reg_range(0x2914, 0x291b),
 638         regmap_reg_range(0x2920, 0x2920),
 639         regmap_reg_range(0x2923, 0x2927),
 640         regmap_reg_range(0x2a00, 0x2a03),
 641         regmap_reg_range(0x2a04, 0x2a07),
 642         regmap_reg_range(0x2b00, 0x2b01),
 643         regmap_reg_range(0x2b04, 0x2b04),
 644         regmap_reg_range(0x2c00, 0x2c05),
 645         regmap_reg_range(0x2c08, 0x2c1b),
 646
 647         /* port 3 */
 648         regmap_reg_range(0x3000, 0x3001),
 649         regmap_reg_range(0x3013, 0x3013),
 650         regmap_reg_range(0x3017, 0x3017),
 651         regmap_reg_range(0x301b, 0x301b),
 652         regmap_reg_range(0x301f, 0x3020),
 653         regmap_reg_range(0x3030, 0x3030),
 654         regmap_reg_range(0x3100, 0x3115),
 655         regmap_reg_range(0x311a, 0x311f),
 656         regmap_reg_range(0x3122, 0x3127),
 657         regmap_reg_range(0x312a, 0x312b),
 658         regmap_reg_range(0x3136, 0x3139),
 659         regmap_reg_range(0x313e, 0x313f),
 660         regmap_reg_range(0x3400, 0x3401),
 661         regmap_reg_range(0x3403, 0x3403),
 662         regmap_reg_range(0x3410, 0x3417),
 663         regmap_reg_range(0x3420, 0x3423),
 664         regmap_reg_range(0x3500, 0x3507),
 665         regmap_reg_range(0x3600, 0x3613),
 666         regmap_reg_range(0x3800, 0x380f),
 667         regmap_reg_range(0x3820, 0x3827),
 668         regmap_reg_range(0x3830, 0x3837),
 669         regmap_reg_range(0x3840, 0x384b),
 670         regmap_reg_range(0x3900, 0x3907),
 671         regmap_reg_range(0x3914, 0x391b),
 672         regmap_reg_range(0x3920, 0x3920),
 673         regmap_reg_range(0x3923, 0x3927),
 674         regmap_reg_range(0x3a00, 0x3a03),
 675         regmap_reg_range(0x3a04, 0x3a07),
 676         regmap_reg_range(0x3b00, 0x3b01),
 677         regmap_reg_range(0x3b04, 0x3b04),
 678         regmap_reg_range(0x3c00, 0x3c05),
 679         regmap_reg_range(0x3c08, 0x3c1b),
 680
 681         /* port 4 */
 682         regmap_reg_range(0x4000, 0x4001),
 683         regmap_reg_range(0x4013, 0x4013),
 684         regmap_reg_range(0x4017, 0x4017),
 685         regmap_reg_range(0x401b, 0x401b),
 686         regmap_reg_range(0x401f, 0x4020),
 687         regmap_reg_range(0x4030, 0x4030),
 688         regmap_reg_range(0x4100, 0x4115),
 689         regmap_reg_range(0x411a, 0x411f),
 690         regmap_reg_range(0x4122, 0x4127),
 691         regmap_reg_range(0x412a, 0x412b),
 692         regmap_reg_range(0x4136, 0x4139),
 693         regmap_reg_range(0x413e, 0x413f),
 694         regmap_reg_range(0x4400, 0x4401),
 695         regmap_reg_range(0x4403, 0x4403),
 696         regmap_reg_range(0x4410, 0x4417),
 697         regmap_reg_range(0x4420, 0x4423),
 698         regmap_reg_range(0x4500, 0x4507),
 699         regmap_reg_range(0x4600, 0x4613),
 700         regmap_reg_range(0x4800, 0x480f),
 701         regmap_reg_range(0x4820, 0x4827),
 702         regmap_reg_range(0x4830, 0x4837),
 703         regmap_reg_range(0x4840, 0x484b),
 704         regmap_reg_range(0x4900, 0x4907),
 705         regmap_reg_range(0x4914, 0x491b),
 706         regmap_reg_range(0x4920, 0x4920),
 707         regmap_reg_range(0x4923, 0x4927),
 708         regmap_reg_range(0x4a00, 0x4a03),
 709         regmap_reg_range(0x4a04, 0x4a07),
 710         regmap_reg_range(0x4b00, 0x4b01),
 711         regmap_reg_range(0x4b04, 0x4b04),
 712         regmap_reg_range(0x4c00, 0x4c05),
 713         regmap_reg_range(0x4c08, 0x4c1b),
 714
 715         /* port 5 */
 716         regmap_reg_range(0x5000, 0x5001),
 717         regmap_reg_range(0x5013, 0x5013),
 718         regmap_reg_range(0x5017, 0x5017),
 719         regmap_reg_range(0x501b, 0x501b),
 720         regmap_reg_range(0x501f, 0x5020),
 721         regmap_reg_range(0x5030, 0x5030),
 722         regmap_reg_range(0x5100, 0x5115),
 723         regmap_reg_range(0x511a, 0x511f),
 724         regmap_reg_range(0x5122, 0x5127),
 725         regmap_reg_range(0x512a, 0x512b),
 726         regmap_reg_range(0x5136, 0x5139),
 727         regmap_reg_range(0x513e, 0x513f),
 728         regmap_reg_range(0x5400, 0x5401),
 729         regmap_reg_range(0x5403, 0x5403),
 730         regmap_reg_range(0x5410, 0x5417),
 731         regmap_reg_range(0x5420, 0x5423),
 732         regmap_reg_range(0x5500, 0x5507),
 733         regmap_reg_range(0x5600, 0x5613),
 734         regmap_reg_range(0x5800, 0x580f),
 735         regmap_reg_range(0x5820, 0x5827),
 736         regmap_reg_range(0x5830, 0x5837),
 737         regmap_reg_range(0x5840, 0x584b),
 738         regmap_reg_range(0x5900, 0x5907),
 739         regmap_reg_range(0x5914, 0x591b),
 740         regmap_reg_range(0x5920, 0x5920),
 741         regmap_reg_range(0x5923, 0x5927),
 742         regmap_reg_range(0x5a00, 0x5a03),
 743         regmap_reg_range(0x5a04, 0x5a07),
 744         regmap_reg_range(0x5b00, 0x5b01),
 745         regmap_reg_range(0x5b04, 0x5b04),
 746         regmap_reg_range(0x5c00, 0x5c05),
 747         regmap_reg_range(0x5c08, 0x5c1b),
 748
 749         /* port 6 */
 750         regmap_reg_range(0x6000, 0x6001),
 751         regmap_reg_range(0x6013, 0x6013),
 752         regmap_reg_range(0x6017, 0x6017),
 753         regmap_reg_range(0x601b, 0x601b),
 754         regmap_reg_range(0x601f, 0x6020),
 755         regmap_reg_range(0x6030, 0x6030),
 756         regmap_reg_range(0x6300, 0x6301),
 757         regmap_reg_range(0x6400, 0x6401),
 758         regmap_reg_range(0x6403, 0x6403),
 759         regmap_reg_range(0x6410, 0x6417),
 760         regmap_reg_range(0x6420, 0x6423),
 761         regmap_reg_range(0x6500, 0x6507),
 762         regmap_reg_range(0x6600, 0x6613),
 763         regmap_reg_range(0x6800, 0x680f),
 764         regmap_reg_range(0x6820, 0x6827),
 765         regmap_reg_range(0x6830, 0x6837),
 766         regmap_reg_range(0x6840, 0x684b),
 767         regmap_reg_range(0x6900, 0x6907),
 768         regmap_reg_range(0x6914, 0x691b),
 769         regmap_reg_range(0x6920, 0x6920),
 770         regmap_reg_range(0x6923, 0x6927),
 771         regmap_reg_range(0x6a00, 0x6a03),
 772         regmap_reg_range(0x6a04, 0x6a07),
 773         regmap_reg_range(0x6b00, 0x6b01),
 774         regmap_reg_range(0x6b04, 0x6b04),
 775         regmap_reg_range(0x6c00, 0x6c05),
 776         regmap_reg_range(0x6c08, 0x6c1b),
 777
 778         /* port 7 */
 779         regmap_reg_range(0x7000, 0x7001),
 780         regmap_reg_range(0x7013, 0x7013),
 781         regmap_reg_range(0x7017, 0x7017),
 782         regmap_reg_range(0x701b, 0x701b),
 783         regmap_reg_range(0x701f, 0x7020),
 784         regmap_reg_range(0x7030, 0x7030),
 785         regmap_reg_range(0x7200, 0x7203),
 786         regmap_reg_range(0x7206, 0x7207),
 787         regmap_reg_range(0x7300, 0x7301),
 788         regmap_reg_range(0x7400, 0x7401),
 789         regmap_reg_range(0x7403, 0x7403),
 790         regmap_reg_range(0x7410, 0x7417),
 791         regmap_reg_range(0x7420, 0x7423),
 792         regmap_reg_range(0x7500, 0x7507),
 793         regmap_reg_range(0x7600, 0x7613),
 794         regmap_reg_range(0x7800, 0x780f),
 795         regmap_reg_range(0x7820, 0x7827),
 796         regmap_reg_range(0x7830, 0x7837),
 797         regmap_reg_range(0x7840, 0x784b),
 798         regmap_reg_range(0x7900, 0x7907),
 799         regmap_reg_range(0x7914, 0x791b),
 800         regmap_reg_range(0x7920, 0x7920),
 801         regmap_reg_range(0x7923, 0x7927),
 802         regmap_reg_range(0x7a00, 0x7a03),
 803         regmap_reg_range(0x7a04, 0x7a07),
 804         regmap_reg_range(0x7b00, 0x7b01),
 805         regmap_reg_range(0x7b04, 0x7b04),
 806         regmap_reg_range(0x7c00, 0x7c05),
 807         regmap_reg_range(0x7c08, 0x7c1b),
 808 };
 809
 810 static const struct regmap_access_table ksz9477_register_set = {
 811         .yes_ranges = ksz9477_valid_regs,
 812         .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
 813 };
 814
 815 static const struct regmap_range ksz9896_valid_regs[] = {
 816         regmap_reg_range(0x0000, 0x0003),
 817         regmap_reg_range(0x0006, 0x0006),
 818         regmap_reg_range(0x0010, 0x001f),
 819         regmap_reg_range(0x0100, 0x0100),
 820         regmap_reg_range(0x0103, 0x0107),
 821         regmap_reg_range(0x010d, 0x010d),
 822         regmap_reg_range(0x0110, 0x0113),
 823         regmap_reg_range(0x0120, 0x0127),
 824         regmap_reg_range(0x0201, 0x0201),
 825         regmap_reg_range(0x0210, 0x0213),
 826         regmap_reg_range(0x0300, 0x0300),
 827         regmap_reg_range(0x0302, 0x030b),
 828         regmap_reg_range(0x0310, 0x031b),
 829         regmap_reg_range(0x0320, 0x032b),
 830         regmap_reg_range(0x0330, 0x0336),
 831         regmap_reg_range(0x0338, 0x033b),
 832         regmap_reg_range(0x033e, 0x033e),
 833         regmap_reg_range(0x0340, 0x035f),
 834         regmap_reg_range(0x0370, 0x0370),
 835         regmap_reg_range(0x0378, 0x0378),
 836         regmap_reg_range(0x037c, 0x037d),
 837         regmap_reg_range(0x0390, 0x0393),
 838         regmap_reg_range(0x0400, 0x040e),
 839         regmap_reg_range(0x0410, 0x042f),
 840
 841         /* port 1 */
 842         regmap_reg_range(0x1000, 0x1001),
 843         regmap_reg_range(0x1013, 0x1013),
 844         regmap_reg_range(0x1017, 0x1017),
 845         regmap_reg_range(0x101b, 0x101b),
 846         regmap_reg_range(0x101f, 0x1020),
 847         regmap_reg_range(0x1030, 0x1030),
 848         regmap_reg_range(0x1100, 0x1115),
 849         regmap_reg_range(0x111a, 0x111f),
 850         regmap_reg_range(0x1122, 0x1127),
 851         regmap_reg_range(0x112a, 0x112b),
 852         regmap_reg_range(0x1136, 0x1139),
 853         regmap_reg_range(0x113e, 0x113f),
 854         regmap_reg_range(0x1400, 0x1401),
 855         regmap_reg_range(0x1403, 0x1403),
 856         regmap_reg_range(0x1410, 0x1417),
 857         regmap_reg_range(0x1420, 0x1423),
 858         regmap_reg_range(0x1500, 0x1507),
 859         regmap_reg_range(0x1600, 0x1612),
 860         regmap_reg_range(0x1800, 0x180f),
 861         regmap_reg_range(0x1820, 0x1827),
 862         regmap_reg_range(0x1830, 0x1837),
 863         regmap_reg_range(0x1840, 0x184b),
 864         regmap_reg_range(0x1900, 0x1907),
 865         regmap_reg_range(0x1914, 0x1915),
 866         regmap_reg_range(0x1a00, 0x1a03),
 867         regmap_reg_range(0x1a04, 0x1a07),
 868         regmap_reg_range(0x1b00, 0x1b01),
 869         regmap_reg_range(0x1b04, 0x1b04),
 870
 871         /* port 2 */
 872         regmap_reg_range(0x2000, 0x2001),
 873         regmap_reg_range(0x2013, 0x2013),
 874         regmap_reg_range(0x2017, 0x2017),
 875         regmap_reg_range(0x201b, 0x201b),
 876         regmap_reg_range(0x201f, 0x2020),
 877         regmap_reg_range(0x2030, 0x2030),
 878         regmap_reg_range(0x2100, 0x2115),
 879         regmap_reg_range(0x211a, 0x211f),
 880         regmap_reg_range(0x2122, 0x2127),
 881         regmap_reg_range(0x212a, 0x212b),
 882         regmap_reg_range(0x2136, 0x2139),
 883         regmap_reg_range(0x213e, 0x213f),
 884         regmap_reg_range(0x2400, 0x2401),
 885         regmap_reg_range(0x2403, 0x2403),
 886         regmap_reg_range(0x2410, 0x2417),
 887         regmap_reg_range(0x2420, 0x2423),
 888         regmap_reg_range(0x2500, 0x2507),
 889         regmap_reg_range(0x2600, 0x2612),
 890         regmap_reg_range(0x2800, 0x280f),
 891         regmap_reg_range(0x2820, 0x2827),
 892         regmap_reg_range(0x2830, 0x2837),
 893         regmap_reg_range(0x2840, 0x284b),
 894         regmap_reg_range(0x2900, 0x2907),
 895         regmap_reg_range(0x2914, 0x2915),
 896         regmap_reg_range(0x2a00, 0x2a03),
 897         regmap_reg_range(0x2a04, 0x2a07),
 898         regmap_reg_range(0x2b00, 0x2b01),
 899         regmap_reg_range(0x2b04, 0x2b04),
 900
 901         /* port 3 */
 902         regmap_reg_range(0x3000, 0x3001),
 903         regmap_reg_range(0x3013, 0x3013),
 904         regmap_reg_range(0x3017, 0x3017),
 905         regmap_reg_range(0x301b, 0x301b),
 906         regmap_reg_range(0x301f, 0x3020),
 907         regmap_reg_range(0x3030, 0x3030),
 908         regmap_reg_range(0x3100, 0x3115),
 909         regmap_reg_range(0x311a, 0x311f),
 910         regmap_reg_range(0x3122, 0x3127),
 911         regmap_reg_range(0x312a, 0x312b),
 912         regmap_reg_range(0x3136, 0x3139),
 913         regmap_reg_range(0x313e, 0x313f),
 914         regmap_reg_range(0x3400, 0x3401),
 915         regmap_reg_range(0x3403, 0x3403),
 916         regmap_reg_range(0x3410, 0x3417),
 917         regmap_reg_range(0x3420, 0x3423),
 918         regmap_reg_range(0x3500, 0x3507),
 919         regmap_reg_range(0x3600, 0x3612),
 920         regmap_reg_range(0x3800, 0x380f),
 921         regmap_reg_range(0x3820, 0x3827),
 922         regmap_reg_range(0x3830, 0x3837),
 923         regmap_reg_range(0x3840, 0x384b),
 924         regmap_reg_range(0x3900, 0x3907),
 925         regmap_reg_range(0x3914, 0x3915),
 926         regmap_reg_range(0x3a00, 0x3a03),
 927         regmap_reg_range(0x3a04, 0x3a07),
 928         regmap_reg_range(0x3b00, 0x3b01),
 929         regmap_reg_range(0x3b04, 0x3b04),
 930
 931         /* port 4 */
 932         regmap_reg_range(0x4000, 0x4001),
 933         regmap_reg_range(0x4013, 0x4013),
 934         regmap_reg_range(0x4017, 0x4017),
 935         regmap_reg_range(0x401b, 0x401b),
 936         regmap_reg_range(0x401f, 0x4020),
 937         regmap_reg_range(0x4030, 0x4030),
 938         regmap_reg_range(0x4100, 0x4115),
 939         regmap_reg_range(0x411a, 0x411f),
 940         regmap_reg_range(0x4122, 0x4127),
 941         regmap_reg_range(0x412a, 0x412b),
 942         regmap_reg_range(0x4136, 0x4139),
 943         regmap_reg_range(0x413e, 0x413f),
 944         regmap_reg_range(0x4400, 0x4401),
 945         regmap_reg_range(0x4403, 0x4403),
 946         regmap_reg_range(0x4410, 0x4417),
 947         regmap_reg_range(0x4420, 0x4423),
 948         regmap_reg_range(0x4500, 0x4507),
 949         regmap_reg_range(0x4600, 0x4612),
 950         regmap_reg_range(0x4800, 0x480f),
 951         regmap_reg_range(0x4820, 0x4827),
 952         regmap_reg_range(0x4830, 0x4837),
 953         regmap_reg_range(0x4840, 0x484b),
 954         regmap_reg_range(0x4900, 0x4907),
 955         regmap_reg_range(0x4914, 0x4915),
 956         regmap_reg_range(0x4a00, 0x4a03),
 957         regmap_reg_range(0x4a04, 0x4a07),
 958         regmap_reg_range(0x4b00, 0x4b01),
 959         regmap_reg_range(0x4b04, 0x4b04),
 960
 961         /* port 5 */
 962         regmap_reg_range(0x5000, 0x5001),
 963         regmap_reg_range(0x5013, 0x5013),
 964         regmap_reg_range(0x5017, 0x5017),
 965         regmap_reg_range(0x501b, 0x501b),
 966         regmap_reg_range(0x501f, 0x5020),
 967         regmap_reg_range(0x5030, 0x5030),
 968         regmap_reg_range(0x5100, 0x5115),
 969         regmap_reg_range(0x511a, 0x511f),
 970         regmap_reg_range(0x5122, 0x5127),
 971         regmap_reg_range(0x512a, 0x512b),
 972         regmap_reg_range(0x5136, 0x5139),
 973         regmap_reg_range(0x513e, 0x513f),
 974         regmap_reg_range(0x5400, 0x5401),
 975         regmap_reg_range(0x5403, 0x5403),
 976         regmap_reg_range(0x5410, 0x5417),
 977         regmap_reg_range(0x5420, 0x5423),
 978         regmap_reg_range(0x5500, 0x5507),
 979         regmap_reg_range(0x5600, 0x5612),
 980         regmap_reg_range(0x5800, 0x580f),
 981         regmap_reg_range(0x5820, 0x5827),
 982         regmap_reg_range(0x5830, 0x5837),
 983         regmap_reg_range(0x5840, 0x584b),
 984         regmap_reg_range(0x5900, 0x5907),
 985         regmap_reg_range(0x5914, 0x5915),
 986         regmap_reg_range(0x5a00, 0x5a03),
 987         regmap_reg_range(0x5a04, 0x5a07),
 988         regmap_reg_range(0x5b00, 0x5b01),
 989         regmap_reg_range(0x5b04, 0x5b04),
 990
 991         /* port 6 */
 992         regmap_reg_range(0x6000, 0x6001),
 993         regmap_reg_range(0x6013, 0x6013),
 994         regmap_reg_range(0x6017, 0x6017),
 995         regmap_reg_range(0x601b, 0x601b),
 996         regmap_reg_range(0x601f, 0x6020),
 997         regmap_reg_range(0x6030, 0x6030),
 998         regmap_reg_range(0x6100, 0x6115),
 999         regmap_reg_range(0x611a, 0x611f),
1000         regmap_reg_range(0x6122, 0x6127),
1001         regmap_reg_range(0x612a, 0x612b),
1002         regmap_reg_range(0x6136, 0x6139),
1003         regmap_reg_range(0x613e, 0x613f),
1004         regmap_reg_range(0x6300, 0x6301),
1005         regmap_reg_range(0x6400, 0x6401),
1006         regmap_reg_range(0x6403, 0x6403),
1007         regmap_reg_range(0x6410, 0x6417),
1008         regmap_reg_range(0x6420, 0x6423),
1009         regmap_reg_range(0x6500, 0x6507),
1010         regmap_reg_range(0x6600, 0x6612),
1011         regmap_reg_range(0x6800, 0x680f),
1012         regmap_reg_range(0x6820, 0x6827),
1013         regmap_reg_range(0x6830, 0x6837),
1014         regmap_reg_range(0x6840, 0x684b),
1015         regmap_reg_range(0x6900, 0x6907),
1016         regmap_reg_range(0x6914, 0x6915),
1017         regmap_reg_range(0x6a00, 0x6a03),
1018         regmap_reg_range(0x6a04, 0x6a07),
1019         regmap_reg_range(0x6b00, 0x6b01),
1020         regmap_reg_range(0x6b04, 0x6b04),
1021 };
1022
1023 static const struct regmap_access_table ksz9896_register_set = {
1024         .yes_ranges = ksz9896_valid_regs,
1025         .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1026 };
1027
1028 const struct ksz_chip_data ksz_switch_chips[] = {
1029         [KSZ8563] = {
1030                 .chip_id = KSZ8563_CHIP_ID,
1031                 .dev_name = "KSZ8563",
1032                 .num_vlans = 4096,
1033                 .num_alus = 4096,
1034                 .num_statics = 16,
1035                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1036                 .port_cnt = 3,          /* total port count */
1037                 .ops = &ksz9477_dev_ops,
1038                 .mib_names = ksz9477_mib_names,
1039                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1040                 .reg_mib_cnt = MIB_COUNTER_NUM,
1041                 .regs = ksz9477_regs,
1042                 .masks = ksz9477_masks,
1043                 .shifts = ksz9477_shifts,
1044                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1045                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1046                 .supports_mii = {false, false, true},
1047                 .supports_rmii = {false, false, true},
1048                 .supports_rgmii = {false, false, true},
1049                 .internal_phy = {true, true, false},
1050                 .gbit_capable = {false, false, true},
1051                 .wr_table = &ksz8563_register_set,
1052                 .rd_table = &ksz8563_register_set,
1053         },
1054
1055         [KSZ8795] = {
1056                 .chip_id = KSZ8795_CHIP_ID,
1057                 .dev_name = "KSZ8795",
1058                 .num_vlans = 4096,
1059                 .num_alus = 0,
1060                 .num_statics = 8,
1061                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1062                 .port_cnt = 5,          /* total cpu and user ports */
1063                 .ops = &ksz8_dev_ops,
1064                 .ksz87xx_eee_link_erratum = true,
1065                 .mib_names = ksz9477_mib_names,
1066                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1067                 .reg_mib_cnt = MIB_COUNTER_NUM,
1068                 .regs = ksz8795_regs,
1069                 .masks = ksz8795_masks,
1070                 .shifts = ksz8795_shifts,
1071                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1072                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1073                 .supports_mii = {false, false, false, false, true},
1074                 .supports_rmii = {false, false, false, false, true},
1075                 .supports_rgmii = {false, false, false, false, true},
1076                 .internal_phy = {true, true, true, true, false},
1077         },
1078
1079         [KSZ8794] = {
1080                 /* WARNING
1081                  * =======
1082                  * KSZ8794 is similar to KSZ8795, except the port map
1083                  * contains a gap between external and CPU ports, the
1084                  * port map is NOT continuous. The per-port register
1085                  * map is shifted accordingly too, i.e. registers at
1086                  * offset 0x40 are NOT used on KSZ8794 and they ARE
1087                  * used on KSZ8795 for external port 3.
1088                  *           external  cpu
1089                  * KSZ8794   0,1,2      4
1090                  * KSZ8795   0,1,2,3    4
1091                  * KSZ8765   0,1,2,3    4
1092                  * port_cnt is configured as 5, even though it is 4
1093                  */
1094                 .chip_id = KSZ8794_CHIP_ID,
1095                 .dev_name = "KSZ8794",
1096                 .num_vlans = 4096,
1097                 .num_alus = 0,
1098                 .num_statics = 8,
1099                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1100                 .port_cnt = 5,          /* total cpu and user ports */
1101                 .ops = &ksz8_dev_ops,
1102                 .ksz87xx_eee_link_erratum = true,
1103                 .mib_names = ksz9477_mib_names,
1104                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1105                 .reg_mib_cnt = MIB_COUNTER_NUM,
1106                 .regs = ksz8795_regs,
1107                 .masks = ksz8795_masks,
1108                 .shifts = ksz8795_shifts,
1109                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1110                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1111                 .supports_mii = {false, false, false, false, true},
1112                 .supports_rmii = {false, false, false, false, true},
1113                 .supports_rgmii = {false, false, false, false, true},
1114                 .internal_phy = {true, true, true, false, false},
1115         },
1116
1117         [KSZ8765] = {
1118                 .chip_id = KSZ8765_CHIP_ID,
1119                 .dev_name = "KSZ8765",
1120                 .num_vlans = 4096,
1121                 .num_alus = 0,
1122                 .num_statics = 8,
1123                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1124                 .port_cnt = 5,          /* total cpu and user ports */
1125                 .ops = &ksz8_dev_ops,
1126                 .ksz87xx_eee_link_erratum = true,
1127                 .mib_names = ksz9477_mib_names,
1128                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1129                 .reg_mib_cnt = MIB_COUNTER_NUM,
1130                 .regs = ksz8795_regs,
1131                 .masks = ksz8795_masks,
1132                 .shifts = ksz8795_shifts,
1133                 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1134                 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1135                 .supports_mii = {false, false, false, false, true},
1136                 .supports_rmii = {false, false, false, false, true},
1137                 .supports_rgmii = {false, false, false, false, true},
1138                 .internal_phy = {true, true, true, true, false},
1139         },
1140
1141         [KSZ8830] = {
1142                 .chip_id = KSZ8830_CHIP_ID,
1143                 .dev_name = "KSZ8863/KSZ8873",
1144                 .num_vlans = 16,
1145                 .num_alus = 0,
1146                 .num_statics = 8,
1147                 .cpu_ports = 0x4,       /* can be configured as cpu port */
1148                 .port_cnt = 3,
1149                 .ops = &ksz8_dev_ops,
1150                 .mib_names = ksz88xx_mib_names,
1151                 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1152                 .reg_mib_cnt = MIB_COUNTER_NUM,
1153                 .regs = ksz8863_regs,
1154                 .masks = ksz8863_masks,
1155                 .shifts = ksz8863_shifts,
1156                 .supports_mii = {false, false, true},
1157                 .supports_rmii = {false, false, true},
1158                 .internal_phy = {true, true, false},
1159         },
1160
1161         [KSZ9477] = {
1162                 .chip_id = KSZ9477_CHIP_ID,
1163                 .dev_name = "KSZ9477",
1164                 .num_vlans = 4096,
1165                 .num_alus = 4096,
1166                 .num_statics = 16,
1167                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1168                 .port_cnt = 7,          /* total physical port count */
1169                 .ops = &ksz9477_dev_ops,
1170                 .phy_errata_9477 = true,
1171                 .mib_names = ksz9477_mib_names,
1172                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1173                 .reg_mib_cnt = MIB_COUNTER_NUM,
1174                 .regs = ksz9477_regs,
1175                 .masks = ksz9477_masks,
1176                 .shifts = ksz9477_shifts,
1177                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1178                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1179                 .supports_mii   = {false, false, false, false,
1180                                    false, true, false},
1181                 .supports_rmii  = {false, false, false, false,
1182                                    false, true, false},
1183                 .supports_rgmii = {false, false, false, false,
1184                                    false, true, false},
1185                 .internal_phy   = {true, true, true, true,
1186                                    true, false, false},
1187                 .gbit_capable   = {true, true, true, true, true, true, true},
1188                 .wr_table = &ksz9477_register_set,
1189                 .rd_table = &ksz9477_register_set,
1190         },
1191
1192         [KSZ9896] = {
1193                 .chip_id = KSZ9896_CHIP_ID,
1194                 .dev_name = "KSZ9896",
1195                 .num_vlans = 4096,
1196                 .num_alus = 4096,
1197                 .num_statics = 16,
1198                 .cpu_ports = 0x3F,      /* can be configured as cpu port */
1199                 .port_cnt = 6,          /* total physical port count */
1200                 .ops = &ksz9477_dev_ops,
1201                 .phy_errata_9477 = true,
1202                 .mib_names = ksz9477_mib_names,
1203                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1204                 .reg_mib_cnt = MIB_COUNTER_NUM,
1205                 .regs = ksz9477_regs,
1206                 .masks = ksz9477_masks,
1207                 .shifts = ksz9477_shifts,
1208                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1209                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1210                 .supports_mii   = {false, false, false, false,
1211                                    false, true},
1212                 .supports_rmii  = {false, false, false, false,
1213                                    false, true},
1214                 .supports_rgmii = {false, false, false, false,
1215                                    false, true},
1216                 .internal_phy   = {true, true, true, true,
1217                                    true, false},
1218                 .gbit_capable   = {true, true, true, true, true, true},
1219                 .wr_table = &ksz9896_register_set,
1220                 .rd_table = &ksz9896_register_set,
1221         },
1222
1223         [KSZ9897] = {
1224                 .chip_id = KSZ9897_CHIP_ID,
1225                 .dev_name = "KSZ9897",
1226                 .num_vlans = 4096,
1227                 .num_alus = 4096,
1228                 .num_statics = 16,
1229                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1230                 .port_cnt = 7,          /* total physical port count */
1231                 .ops = &ksz9477_dev_ops,
1232                 .phy_errata_9477 = true,
1233                 .mib_names = ksz9477_mib_names,
1234                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1235                 .reg_mib_cnt = MIB_COUNTER_NUM,
1236                 .regs = ksz9477_regs,
1237                 .masks = ksz9477_masks,
1238                 .shifts = ksz9477_shifts,
1239                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1240                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1241                 .supports_mii   = {false, false, false, false,
1242                                    false, true, true},
1243                 .supports_rmii  = {false, false, false, false,
1244                                    false, true, true},
1245                 .supports_rgmii = {false, false, false, false,
1246                                    false, true, true},
1247                 .internal_phy   = {true, true, true, true,
1248                                    true, false, false},
1249                 .gbit_capable   = {true, true, true, true, true, true, true},
1250         },
1251
1252         [KSZ9893] = {
1253                 .chip_id = KSZ9893_CHIP_ID,
1254                 .dev_name = "KSZ9893",
1255                 .num_vlans = 4096,
1256                 .num_alus = 4096,
1257                 .num_statics = 16,
1258                 .cpu_ports = 0x07,      /* can be configured as cpu port */
1259                 .port_cnt = 3,          /* total port count */
1260                 .ops = &ksz9477_dev_ops,
1261                 .mib_names = ksz9477_mib_names,
1262                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1263                 .reg_mib_cnt = MIB_COUNTER_NUM,
1264                 .regs = ksz9477_regs,
1265                 .masks = ksz9477_masks,
1266                 .shifts = ksz9477_shifts,
1267                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1268                 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1269                 .supports_mii = {false, false, true},
1270                 .supports_rmii = {false, false, true},
1271                 .supports_rgmii = {false, false, true},
1272                 .internal_phy = {true, true, false},
1273                 .gbit_capable = {true, true, true},
1274         },
1275
1276         [KSZ9567] = {
1277                 .chip_id = KSZ9567_CHIP_ID,
1278                 .dev_name = "KSZ9567",
1279                 .num_vlans = 4096,
1280                 .num_alus = 4096,
1281                 .num_statics = 16,
1282                 .cpu_ports = 0x7F,      /* can be configured as cpu port */
1283                 .port_cnt = 7,          /* total physical port count */
1284                 .ops = &ksz9477_dev_ops,
1285                 .phy_errata_9477 = true,
1286                 .mib_names = ksz9477_mib_names,
1287                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1288                 .reg_mib_cnt = MIB_COUNTER_NUM,
1289                 .regs = ksz9477_regs,
1290                 .masks = ksz9477_masks,
1291                 .shifts = ksz9477_shifts,
1292                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1293                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1294                 .supports_mii   = {false, false, false, false,
1295                                    false, true, true},
1296                 .supports_rmii  = {false, false, false, false,
1297                                    false, true, true},
1298                 .supports_rgmii = {false, false, false, false,
1299                                    false, true, true},
1300                 .internal_phy   = {true, true, true, true,
1301                                    true, false, false},
1302                 .gbit_capable   = {true, true, true, true, true, true, true},
1303         },
1304
1305         [LAN9370] = {
1306                 .chip_id = LAN9370_CHIP_ID,
1307                 .dev_name = "LAN9370",
1308                 .num_vlans = 4096,
1309                 .num_alus = 1024,
1310                 .num_statics = 256,
1311                 .cpu_ports = 0x10,      /* can be configured as cpu port */
1312                 .port_cnt = 5,          /* total physical port count */
1313                 .ops = &lan937x_dev_ops,
1314                 .mib_names = ksz9477_mib_names,
1315                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1316                 .reg_mib_cnt = MIB_COUNTER_NUM,
1317                 .regs = ksz9477_regs,
1318                 .masks = lan937x_masks,
1319                 .shifts = lan937x_shifts,
1320                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1321                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1322                 .supports_mii = {false, false, false, false, true},
1323                 .supports_rmii = {false, false, false, false, true},
1324                 .supports_rgmii = {false, false, false, false, true},
1325                 .internal_phy = {true, true, true, true, false},
1326         },
1327
1328         [LAN9371] = {
1329                 .chip_id = LAN9371_CHIP_ID,
1330                 .dev_name = "LAN9371",
1331                 .num_vlans = 4096,
1332                 .num_alus = 1024,
1333                 .num_statics = 256,
1334                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1335                 .port_cnt = 6,          /* total physical port count */
1336                 .ops = &lan937x_dev_ops,
1337                 .mib_names = ksz9477_mib_names,
1338                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1339                 .reg_mib_cnt = MIB_COUNTER_NUM,
1340                 .regs = ksz9477_regs,
1341                 .masks = lan937x_masks,
1342                 .shifts = lan937x_shifts,
1343                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1344                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1345                 .supports_mii = {false, false, false, false, true, true},
1346                 .supports_rmii = {false, false, false, false, true, true},
1347                 .supports_rgmii = {false, false, false, false, true, true},
1348                 .internal_phy = {true, true, true, true, false, false},
1349         },
1350
1351         [LAN9372] = {
1352                 .chip_id = LAN9372_CHIP_ID,
1353                 .dev_name = "LAN9372",
1354                 .num_vlans = 4096,
1355                 .num_alus = 1024,
1356                 .num_statics = 256,
1357                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1358                 .port_cnt = 8,          /* total physical port count */
1359                 .ops = &lan937x_dev_ops,
1360                 .mib_names = ksz9477_mib_names,
1361                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1362                 .reg_mib_cnt = MIB_COUNTER_NUM,
1363                 .regs = ksz9477_regs,
1364                 .masks = lan937x_masks,
1365                 .shifts = lan937x_shifts,
1366                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1367                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1368                 .supports_mii   = {false, false, false, false,
1369                                    true, true, false, false},
1370                 .supports_rmii  = {false, false, false, false,
1371                                    true, true, false, false},
1372                 .supports_rgmii = {false, false, false, false,
1373                                    true, true, false, false},
1374                 .internal_phy   = {true, true, true, true,
1375                                    false, false, true, true},
1376         },
1377
1378         [LAN9373] = {
1379                 .chip_id = LAN9373_CHIP_ID,
1380                 .dev_name = "LAN9373",
1381                 .num_vlans = 4096,
1382                 .num_alus = 1024,
1383                 .num_statics = 256,
1384                 .cpu_ports = 0x38,      /* can be configured as cpu port */
1385                 .port_cnt = 5,          /* total physical port count */
1386                 .ops = &lan937x_dev_ops,
1387                 .mib_names = ksz9477_mib_names,
1388                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1389                 .reg_mib_cnt = MIB_COUNTER_NUM,
1390                 .regs = ksz9477_regs,
1391                 .masks = lan937x_masks,
1392                 .shifts = lan937x_shifts,
1393                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1394                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1395                 .supports_mii   = {false, false, false, false,
1396                                    true, true, false, false},
1397                 .supports_rmii  = {false, false, false, false,
1398                                    true, true, false, false},
1399                 .supports_rgmii = {false, false, false, false,
1400                                    true, true, false, false},
1401                 .internal_phy   = {true, true, true, false,
1402                                    false, false, true, true},
1403         },
1404
1405         [LAN9374] = {
1406                 .chip_id = LAN9374_CHIP_ID,
1407                 .dev_name = "LAN9374",
1408                 .num_vlans = 4096,
1409                 .num_alus = 1024,
1410                 .num_statics = 256,
1411                 .cpu_ports = 0x30,      /* can be configured as cpu port */
1412                 .port_cnt = 8,          /* total physical port count */
1413                 .ops = &lan937x_dev_ops,
1414                 .mib_names = ksz9477_mib_names,
1415                 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1416                 .reg_mib_cnt = MIB_COUNTER_NUM,
1417                 .regs = ksz9477_regs,
1418                 .masks = lan937x_masks,
1419                 .shifts = lan937x_shifts,
1420                 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1421                 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1422                 .supports_mii   = {false, false, false, false,
1423                                    true, true, false, false},
1424                 .supports_rmii  = {false, false, false, false,
1425                                    true, true, false, false},
1426                 .supports_rgmii = {false, false, false, false,
1427                                    true, true, false, false},
1428                 .internal_phy   = {true, true, true, true,
1429                                    false, false, true, true},
1430         },
1431 };
1432 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1433
1434 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1435 {
1436         int i;
1437
1438         for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1439                 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1440
1441                 if (chip->chip_id == prod_num)
1442                         return chip;
1443         }
1444
1445         return NULL;
1446 }
1447
1448 static int ksz_check_device_id(struct ksz_device *dev)
1449 {
1450         const struct ksz_chip_data *dt_chip_data;
1451
1452         dt_chip_data = of_device_get_match_data(dev->dev);
1453
1454         /* Check for Device Tree and Chip ID */
1455         if (dt_chip_data->chip_id != dev->chip_id) {
1456                 dev_err(dev->dev,
1457                         "Device tree specifies chip %s but found %s, please fix it!\n",
1458                         dt_chip_data->dev_name, dev->info->dev_name);
1459                 return -ENODEV;
1460         }
1461
1462         return 0;
1463 }
1464
1465 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1466                                  struct phylink_config *config)
1467 {
1468         struct ksz_device *dev = ds->priv;
1469
1470         config->legacy_pre_march2020 = false;
1471
1472         if (dev->info->supports_mii[port])
1473                 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1474
1475         if (dev->info->supports_rmii[port])
1476                 __set_bit(PHY_INTERFACE_MODE_RMII,
1477                           config->supported_interfaces);
1478
1479         if (dev->info->supports_rgmii[port])
1480                 phy_interface_set_rgmii(config->supported_interfaces);
1481
1482         if (dev->info->internal_phy[port]) {
1483                 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1484                           config->supported_interfaces);
1485                 /* Compatibility for phylib's default interface type when the
1486                  * phy-mode property is absent
1487                  */
1488                 __set_bit(PHY_INTERFACE_MODE_GMII,
1489                           config->supported_interfaces);
1490         }
1491
1492         if (dev->dev_ops->get_caps)
1493                 dev->dev_ops->get_caps(dev, port, config);
1494 }
1495
1496 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1497 {
1498         struct ethtool_pause_stats *pstats;
1499         struct rtnl_link_stats64 *stats;
1500         struct ksz_stats_raw *raw;
1501         struct ksz_port_mib *mib;
1502
1503         mib = &dev->ports[port].mib;
1504         stats = &mib->stats64;
1505         pstats = &mib->pause_stats;
1506         raw = (struct ksz_stats_raw *)mib->counters;
1507
1508         spin_lock(&mib->stats64_lock);
1509
1510         stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1511                 raw->rx_pause;
1512         stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1513                 raw->tx_pause;
1514
1515         /* HW counters are counting bytes + FCS which is not acceptable
1516          * for rtnl_link_stats64 interface
1517          */
1518         stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1519         stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1520
1521         stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1522                 raw->rx_oversize;
1523
1524         stats->rx_crc_errors = raw->rx_crc_err;
1525         stats->rx_frame_errors = raw->rx_align_err;
1526         stats->rx_dropped = raw->rx_discards;
1527         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1528                 stats->rx_frame_errors  + stats->rx_dropped;
1529
1530         stats->tx_window_errors = raw->tx_late_col;
1531         stats->tx_fifo_errors = raw->tx_discards;
1532         stats->tx_aborted_errors = raw->tx_exc_col;
1533         stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1534                 stats->tx_aborted_errors;
1535
1536         stats->multicast = raw->rx_mcast;
1537         stats->collisions = raw->tx_total_col;
1538
1539         pstats->tx_pause_frames = raw->tx_pause;
1540         pstats->rx_pause_frames = raw->rx_pause;
1541
1542         spin_unlock(&mib->stats64_lock);
1543 }
1544
1545 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1546                             struct rtnl_link_stats64 *s)
1547 {
1548         struct ksz_device *dev = ds->priv;
1549         struct ksz_port_mib *mib;
1550
1551         mib = &dev->ports[port].mib;
1552
1553         spin_lock(&mib->stats64_lock);
1554         memcpy(s, &mib->stats64, sizeof(*s));
1555         spin_unlock(&mib->stats64_lock);
1556 }
1557
1558 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1559                                 struct ethtool_pause_stats *pause_stats)
1560 {
1561         struct ksz_device *dev = ds->priv;
1562         struct ksz_port_mib *mib;
1563
1564         mib = &dev->ports[port].mib;
1565
1566         spin_lock(&mib->stats64_lock);
1567         memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1568         spin_unlock(&mib->stats64_lock);
1569 }
1570
1571 static void ksz_get_strings(struct dsa_switch *ds, int port,
1572                             u32 stringset, uint8_t *buf)
1573 {
1574         struct ksz_device *dev = ds->priv;
1575         int i;
1576
1577         if (stringset != ETH_SS_STATS)
1578                 return;
1579
1580         for (i = 0; i < dev->info->mib_cnt; i++) {
1581                 memcpy(buf + i * ETH_GSTRING_LEN,
1582                        dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1583         }
1584 }
1585
1586 static void ksz_update_port_member(struct ksz_device *dev, int port)
1587 {
1588         struct ksz_port *p = &dev->ports[port];
1589         struct dsa_switch *ds = dev->ds;
1590         u8 port_member = 0, cpu_port;
1591         const struct dsa_port *dp;
1592         int i, j;
1593
1594         if (!dsa_is_user_port(ds, port))
1595                 return;
1596
1597         dp = dsa_to_port(ds, port);
1598         cpu_port = BIT(dsa_upstream_port(ds, port));
1599
1600         for (i = 0; i < ds->num_ports; i++) {
1601                 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1602                 struct ksz_port *other_p = &dev->ports[i];
1603                 u8 val = 0;
1604
1605                 if (!dsa_is_user_port(ds, i))
1606                         continue;
1607                 if (port == i)
1608                         continue;
1609                 if (!dsa_port_bridge_same(dp, other_dp))
1610                         continue;
1611                 if (other_p->stp_state != BR_STATE_FORWARDING)
1612                         continue;
1613
1614                 if (p->stp_state == BR_STATE_FORWARDING) {
1615                         val |= BIT(port);
1616                         port_member |= BIT(i);
1617                 }
1618
1619                 /* Retain port [i]'s relationship to other ports than [port] */
1620                 for (j = 0; j < ds->num_ports; j++) {
1621                         const struct dsa_port *third_dp;
1622                         struct ksz_port *third_p;
1623
1624                         if (j == i)
1625                                 continue;
1626                         if (j == port)
1627                                 continue;
1628                         if (!dsa_is_user_port(ds, j))
1629                                 continue;
1630                         third_p = &dev->ports[j];
1631                         if (third_p->stp_state != BR_STATE_FORWARDING)
1632                                 continue;
1633                         third_dp = dsa_to_port(ds, j);
1634                         if (dsa_port_bridge_same(other_dp, third_dp))
1635                                 val |= BIT(j);
1636                 }
1637
1638                 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1639         }
1640
1641         dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1642 }
1643
1644 static int ksz_setup(struct dsa_switch *ds)
1645 {
1646         struct ksz_device *dev = ds->priv;
1647         struct ksz_port *p;
1648         const u16 *regs;
1649         int ret;
1650
1651         regs = dev->info->regs;
1652
1653         dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1654                                        dev->info->num_vlans, GFP_KERNEL);
1655         if (!dev->vlan_cache)
1656                 return -ENOMEM;
1657
1658         ret = dev->dev_ops->reset(dev);
1659         if (ret) {
1660                 dev_err(ds->dev, "failed to reset switch\n");
1661                 return ret;
1662         }
1663
1664         /* set broadcast storm protection 10% rate */
1665         regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
1666                            BROADCAST_STORM_RATE,
1667                            (BROADCAST_STORM_VALUE *
1668                            BROADCAST_STORM_PROT_RATE) / 100);
1669
1670         dev->dev_ops->config_cpu_port(ds);
1671
1672         dev->dev_ops->enable_stp_addr(dev);
1673
1674         regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
1675                            MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
1676
1677         ksz_init_mib_timer(dev);
1678
1679         ds->configure_vlan_while_not_filtering = false;
1680
1681         if (dev->dev_ops->setup) {
1682                 ret = dev->dev_ops->setup(ds);
1683                 if (ret)
1684                         return ret;
1685         }
1686
1687         /* Start with learning disabled on standalone user ports, and enabled
1688          * on the CPU port. In lack of other finer mechanisms, learning on the
1689          * CPU port will avoid flooding bridge local addresses on the network
1690          * in some cases.
1691          */
1692         p = &dev->ports[dev->cpu_port];
1693         p->learning = true;
1694
1695         /* start switch */
1696         regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
1697                            SW_START, SW_START);
1698
1699         return 0;
1700 }
1701
1702 static void ksz_teardown(struct dsa_switch *ds)
1703 {
1704         struct ksz_device *dev = ds->priv;
1705
1706         if (dev->dev_ops->teardown)
1707                 dev->dev_ops->teardown(ds);
1708 }
1709
1710 static void port_r_cnt(struct ksz_device *dev, int port)
1711 {
1712         struct ksz_port_mib *mib = &dev->ports[port].mib;
1713         u64 *dropped;
1714
1715         /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
1716         while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
1717                 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
1718                                         &mib->counters[mib->cnt_ptr]);
1719                 ++mib->cnt_ptr;
1720         }
1721
1722         /* last one in storage */
1723         dropped = &mib->counters[dev->info->mib_cnt];
1724
1725         /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
1726         while (mib->cnt_ptr < dev->info->mib_cnt) {
1727                 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
1728                                         dropped, &mib->counters[mib->cnt_ptr]);
1729                 ++mib->cnt_ptr;
1730         }
1731         mib->cnt_ptr = 0;
1732 }
1733
1734 static void ksz_mib_read_work(struct work_struct *work)
1735 {
1736         struct ksz_device *dev = container_of(work, struct ksz_device,
1737                                               mib_read.work);
1738         struct ksz_port_mib *mib;
1739         struct ksz_port *p;
1740         int i;
1741
1742         for (i = 0; i < dev->info->port_cnt; i++) {
1743                 if (dsa_is_unused_port(dev->ds, i))
1744                         continue;
1745
1746                 p = &dev->ports[i];
1747                 mib = &p->mib;
1748                 mutex_lock(&mib->cnt_mutex);
1749
1750                 /* Only read MIB counters when the port is told to do.
1751                  * If not, read only dropped counters when link is not up.
1752                  */
1753                 if (!p->read) {
1754                         const struct dsa_port *dp = dsa_to_port(dev->ds, i);
1755
1756                         if (!netif_carrier_ok(dp->slave))
1757                                 mib->cnt_ptr = dev->info->reg_mib_cnt;
1758                 }
1759                 port_r_cnt(dev, i);
1760                 p->read = false;
1761
1762                 if (dev->dev_ops->r_mib_stat64)
1763                         dev->dev_ops->r_mib_stat64(dev, i);
1764
1765                 mutex_unlock(&mib->cnt_mutex);
1766         }
1767
1768         schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
1769 }
1770
1771 void ksz_init_mib_timer(struct ksz_device *dev)
1772 {
1773         int i;
1774
1775         INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
1776
1777         for (i = 0; i < dev->info->port_cnt; i++) {
1778                 struct ksz_port_mib *mib = &dev->ports[i].mib;
1779
1780                 dev->dev_ops->port_init_cnt(dev, i);
1781
1782                 mib->cnt_ptr = 0;
1783                 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
1784         }
1785 }
1786
1787 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
1788 {
1789         struct ksz_device *dev = ds->priv;
1790         u16 val = 0xffff;
1791         int ret;
1792
1793         ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
1794         if (ret)
1795                 return ret;
1796
1797         return val;
1798 }
1799
1800 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
1801 {
1802         struct ksz_device *dev = ds->priv;
1803         int ret;
1804
1805         ret = dev->dev_ops->w_phy(dev, addr, reg, val);
1806         if (ret)
1807                 return ret;
1808
1809         return 0;
1810 }
1811
1812 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
1813 {
1814         struct ksz_device *dev = ds->priv;
1815
1816         if (dev->chip_id == KSZ8830_CHIP_ID) {
1817                 /* Silicon Errata Sheet (DS80000830A):
1818                  * Port 1 does not work with LinkMD Cable-Testing.
1819                  * Port 1 does not respond to received PAUSE control frames.
1820                  */
1821                 if (!port)
1822                         return MICREL_KSZ8_P1_ERRATA;
1823         }
1824
1825         return 0;
1826 }
1827
1828 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
1829                               unsigned int mode, phy_interface_t interface)
1830 {
1831         struct ksz_device *dev = ds->priv;
1832         struct ksz_port *p = &dev->ports[port];
1833
1834         /* Read all MIB counters when the link is going down. */
1835         p->read = true;
1836         /* timer started */
1837         if (dev->mib_read_interval)
1838                 schedule_delayed_work(&dev->mib_read, 0);
1839 }
1840
1841 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
1842 {
1843         struct ksz_device *dev = ds->priv;
1844
1845         if (sset != ETH_SS_STATS)
1846                 return 0;
1847
1848         return dev->info->mib_cnt;
1849 }
1850
1851 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
1852                                   uint64_t *buf)
1853 {
1854         const struct dsa_port *dp = dsa_to_port(ds, port);
1855         struct ksz_device *dev = ds->priv;
1856         struct ksz_port_mib *mib;
1857
1858         mib = &dev->ports[port].mib;
1859         mutex_lock(&mib->cnt_mutex);
1860
1861         /* Only read dropped counters if no link. */
1862         if (!netif_carrier_ok(dp->slave))
1863                 mib->cnt_ptr = dev->info->reg_mib_cnt;
1864         port_r_cnt(dev, port);
1865         memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
1866         mutex_unlock(&mib->cnt_mutex);
1867 }
1868
1869 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
1870                                 struct dsa_bridge bridge,
1871                                 bool *tx_fwd_offload,
1872                                 struct netlink_ext_ack *extack)
1873 {
1874         /* port_stp_state_set() will be called after to put the port in
1875          * appropriate state so there is no need to do anything.
1876          */
1877
1878         return 0;
1879 }
1880
1881 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
1882                                   struct dsa_bridge bridge)
1883 {
1884         /* port_stp_state_set() will be called after to put the port in
1885          * forwarding state so there is no need to do anything.
1886          */
1887 }
1888
1889 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
1890 {
1891         struct ksz_device *dev = ds->priv;
1892
1893         dev->dev_ops->flush_dyn_mac_table(dev, port);
1894 }
1895
1896 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
1897                             const unsigned char *addr, u16 vid,
1898                             struct dsa_db db)
1899 {
1900         struct ksz_device *dev = ds->priv;
1901
1902         if (!dev->dev_ops->fdb_add)
1903                 return -EOPNOTSUPP;
1904
1905         return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
1906 }
1907
1908 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
1909                             const unsigned char *addr,
1910                             u16 vid, struct dsa_db db)
1911 {
1912         struct ksz_device *dev = ds->priv;
1913
1914         if (!dev->dev_ops->fdb_del)
1915                 return -EOPNOTSUPP;
1916
1917         return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
1918 }
1919
1920 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
1921                              dsa_fdb_dump_cb_t *cb, void *data)
1922 {
1923         struct ksz_device *dev = ds->priv;
1924
1925         if (!dev->dev_ops->fdb_dump)
1926                 return -EOPNOTSUPP;
1927
1928         return dev->dev_ops->fdb_dump(dev, port, cb, data);
1929 }
1930
1931 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
1932                             const struct switchdev_obj_port_mdb *mdb,
1933                             struct dsa_db db)
1934 {
1935         struct ksz_device *dev = ds->priv;
1936
1937         if (!dev->dev_ops->mdb_add)
1938                 return -EOPNOTSUPP;
1939
1940         return dev->dev_ops->mdb_add(dev, port, mdb, db);
1941 }
1942
1943 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
1944                             const struct switchdev_obj_port_mdb *mdb,
1945                             struct dsa_db db)
1946 {
1947         struct ksz_device *dev = ds->priv;
1948
1949         if (!dev->dev_ops->mdb_del)
1950                 return -EOPNOTSUPP;
1951
1952         return dev->dev_ops->mdb_del(dev, port, mdb, db);
1953 }
1954
1955 static int ksz_enable_port(struct dsa_switch *ds, int port,
1956                            struct phy_device *phy)
1957 {
1958         struct ksz_device *dev = ds->priv;
1959
1960         if (!dsa_is_user_port(ds, port))
1961                 return 0;
1962
1963         /* setup slave port */
1964         dev->dev_ops->port_setup(dev, port, false);
1965
1966         /* port_stp_state_set() will be called after to enable the port so
1967          * there is no need to do anything.
1968          */
1969
1970         return 0;
1971 }
1972
1973 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1974 {
1975         struct ksz_device *dev = ds->priv;
1976         struct ksz_port *p;
1977         const u16 *regs;
1978         u8 data;
1979
1980         regs = dev->info->regs;
1981
1982         ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
1983         data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1984
1985         p = &dev->ports[port];
1986
1987         switch (state) {
1988         case BR_STATE_DISABLED:
1989                 data |= PORT_LEARN_DISABLE;
1990                 break;
1991         case BR_STATE_LISTENING:
1992                 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1993                 break;
1994         case BR_STATE_LEARNING:
1995                 data |= PORT_RX_ENABLE;
1996                 if (!p->learning)
1997                         data |= PORT_LEARN_DISABLE;
1998                 break;
1999         case BR_STATE_FORWARDING:
2000                 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2001                 if (!p->learning)
2002                         data |= PORT_LEARN_DISABLE;
2003                 break;
2004         case BR_STATE_BLOCKING:
2005                 data |= PORT_LEARN_DISABLE;
2006                 break;
2007         default:
2008                 dev_err(ds->dev, "invalid STP state: %d\n", state);
2009                 return;
2010         }
2011
2012         ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2013
2014         p->stp_state = state;
2015
2016         ksz_update_port_member(dev, port);
2017 }
2018
2019 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2020                                      struct switchdev_brport_flags flags,
2021                                      struct netlink_ext_ack *extack)
2022 {
2023         if (flags.mask & ~BR_LEARNING)
2024                 return -EINVAL;
2025
2026         return 0;
2027 }
2028
2029 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2030                                  struct switchdev_brport_flags flags,
2031                                  struct netlink_ext_ack *extack)
2032 {
2033         struct ksz_device *dev = ds->priv;
2034         struct ksz_port *p = &dev->ports[port];
2035
2036         if (flags.mask & BR_LEARNING) {
2037                 p->learning = !!(flags.val & BR_LEARNING);
2038
2039                 /* Make the change take effect immediately */
2040                 ksz_port_stp_state_set(ds, port, p->stp_state);
2041         }
2042
2043         return 0;
2044 }
2045
2046 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2047                                                   int port,
2048                                                   enum dsa_tag_protocol mp)
2049 {
2050         struct ksz_device *dev = ds->priv;
2051         enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2052
2053         if (dev->chip_id == KSZ8795_CHIP_ID ||
2054             dev->chip_id == KSZ8794_CHIP_ID ||
2055             dev->chip_id == KSZ8765_CHIP_ID)
2056                 proto = DSA_TAG_PROTO_KSZ8795;
2057
2058         if (dev->chip_id == KSZ8830_CHIP_ID ||
2059             dev->chip_id == KSZ8563_CHIP_ID ||
2060             dev->chip_id == KSZ9893_CHIP_ID)
2061                 proto = DSA_TAG_PROTO_KSZ9893;
2062
2063         if (dev->chip_id == KSZ9477_CHIP_ID ||
2064             dev->chip_id == KSZ9896_CHIP_ID ||
2065             dev->chip_id == KSZ9897_CHIP_ID ||
2066             dev->chip_id == KSZ9567_CHIP_ID)
2067                 proto = DSA_TAG_PROTO_KSZ9477;
2068
2069         if (is_lan937x(dev))
2070                 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2071
2072         return proto;
2073 }
2074
2075 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2076                                    bool flag, struct netlink_ext_ack *extack)
2077 {
2078         struct ksz_device *dev = ds->priv;
2079
2080         if (!dev->dev_ops->vlan_filtering)
2081                 return -EOPNOTSUPP;
2082
2083         return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2084 }
2085
2086 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2087                              const struct switchdev_obj_port_vlan *vlan,
2088                              struct netlink_ext_ack *extack)
2089 {
2090         struct ksz_device *dev = ds->priv;
2091
2092         if (!dev->dev_ops->vlan_add)
2093                 return -EOPNOTSUPP;
2094
2095         return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2096 }
2097
2098 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2099                              const struct switchdev_obj_port_vlan *vlan)
2100 {
2101         struct ksz_device *dev = ds->priv;
2102
2103         if (!dev->dev_ops->vlan_del)
2104                 return -EOPNOTSUPP;
2105
2106         return dev->dev_ops->vlan_del(dev, port, vlan);
2107 }
2108
2109 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2110                                struct dsa_mall_mirror_tc_entry *mirror,
2111                                bool ingress, struct netlink_ext_ack *extack)
2112 {
2113         struct ksz_device *dev = ds->priv;
2114
2115         if (!dev->dev_ops->mirror_add)
2116                 return -EOPNOTSUPP;
2117
2118         return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2119 }
2120
2121 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2122                                 struct dsa_mall_mirror_tc_entry *mirror)
2123 {
2124         struct ksz_device *dev = ds->priv;
2125
2126         if (dev->dev_ops->mirror_del)
2127                 dev->dev_ops->mirror_del(dev, port, mirror);
2128 }
2129
2130 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2131 {
2132         struct ksz_device *dev = ds->priv;
2133
2134         if (!dev->dev_ops->change_mtu)
2135                 return -EOPNOTSUPP;
2136
2137         return dev->dev_ops->change_mtu(dev, port, mtu);
2138 }
2139
2140 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2141 {
2142         struct ksz_device *dev = ds->priv;
2143
2144         if (!dev->dev_ops->max_mtu)
2145                 return -EOPNOTSUPP;
2146
2147         return dev->dev_ops->max_mtu(dev, port);
2148 }
2149
2150 static void ksz_set_xmii(struct ksz_device *dev, int port,
2151                          phy_interface_t interface)
2152 {
2153         const u8 *bitval = dev->info->xmii_ctrl1;
2154         struct ksz_port *p = &dev->ports[port];
2155         const u16 *regs = dev->info->regs;
2156         u8 data8;
2157
2158         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2159
2160         data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2161                    P_RGMII_ID_EG_ENABLE);
2162
2163         switch (interface) {
2164         case PHY_INTERFACE_MODE_MII:
2165                 data8 |= bitval[P_MII_SEL];
2166                 break;
2167         case PHY_INTERFACE_MODE_RMII:
2168                 data8 |= bitval[P_RMII_SEL];
2169                 break;
2170         case PHY_INTERFACE_MODE_GMII:
2171                 data8 |= bitval[P_GMII_SEL];
2172                 break;
2173         case PHY_INTERFACE_MODE_RGMII:
2174         case PHY_INTERFACE_MODE_RGMII_ID:
2175         case PHY_INTERFACE_MODE_RGMII_TXID:
2176         case PHY_INTERFACE_MODE_RGMII_RXID:
2177                 data8 |= bitval[P_RGMII_SEL];
2178                 /* On KSZ9893, disable RGMII in-band status support */
2179                 if (dev->chip_id == KSZ9893_CHIP_ID ||
2180                     dev->chip_id == KSZ8563_CHIP_ID)
2181                         data8 &= ~P_MII_MAC_MODE;
2182                 break;
2183         default:
2184                 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2185                         phy_modes(interface), port);
2186                 return;
2187         }
2188
2189         if (p->rgmii_tx_val)
2190                 data8 |= P_RGMII_ID_EG_ENABLE;
2191
2192         if (p->rgmii_rx_val)
2193                 data8 |= P_RGMII_ID_IG_ENABLE;
2194
2195         /* Write the updated value */
2196         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2197 }
2198
2199 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2200 {
2201         const u8 *bitval = dev->info->xmii_ctrl1;
2202         const u16 *regs = dev->info->regs;
2203         phy_interface_t interface;
2204         u8 data8;
2205         u8 val;
2206
2207         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2208
2209         val = FIELD_GET(P_MII_SEL_M, data8);
2210
2211         if (val == bitval[P_MII_SEL]) {
2212                 if (gbit)
2213                         interface = PHY_INTERFACE_MODE_GMII;
2214                 else
2215                         interface = PHY_INTERFACE_MODE_MII;
2216         } else if (val == bitval[P_RMII_SEL]) {
2217                 interface = PHY_INTERFACE_MODE_RGMII;
2218         } else {
2219                 interface = PHY_INTERFACE_MODE_RGMII;
2220                 if (data8 & P_RGMII_ID_EG_ENABLE)
2221                         interface = PHY_INTERFACE_MODE_RGMII_TXID;
2222                 if (data8 & P_RGMII_ID_IG_ENABLE) {
2223                         interface = PHY_INTERFACE_MODE_RGMII_RXID;
2224                         if (data8 & P_RGMII_ID_EG_ENABLE)
2225                                 interface = PHY_INTERFACE_MODE_RGMII_ID;
2226                 }
2227         }
2228
2229         return interface;
2230 }
2231
2232 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2233                                    unsigned int mode,
2234                                    const struct phylink_link_state *state)
2235 {
2236         struct ksz_device *dev = ds->priv;
2237
2238         if (ksz_is_ksz88x3(dev))
2239                 return;
2240
2241         /* Internal PHYs */
2242         if (dev->info->internal_phy[port])
2243                 return;
2244
2245         if (phylink_autoneg_inband(mode)) {
2246                 dev_err(dev->dev, "In-band AN not supported!\n");
2247                 return;
2248         }
2249
2250         ksz_set_xmii(dev, port, state->interface);
2251
2252         if (dev->dev_ops->phylink_mac_config)
2253                 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2254
2255         if (dev->dev_ops->setup_rgmii_delay)
2256                 dev->dev_ops->setup_rgmii_delay(dev, port);
2257 }
2258
2259 bool ksz_get_gbit(struct ksz_device *dev, int port)
2260 {
2261         const u8 *bitval = dev->info->xmii_ctrl1;
2262         const u16 *regs = dev->info->regs;
2263         bool gbit = false;
2264         u8 data8;
2265         bool val;
2266
2267         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2268
2269         val = FIELD_GET(P_GMII_1GBIT_M, data8);
2270
2271         if (val == bitval[P_GMII_1GBIT])
2272                 gbit = true;
2273
2274         return gbit;
2275 }
2276
2277 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2278 {
2279         const u8 *bitval = dev->info->xmii_ctrl1;
2280         const u16 *regs = dev->info->regs;
2281         u8 data8;
2282
2283         ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2284
2285         data8 &= ~P_GMII_1GBIT_M;
2286
2287         if (gbit)
2288                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2289         else
2290                 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2291
2292         /* Write the updated value */
2293         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2294 }
2295
2296 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2297 {
2298         const u8 *bitval = dev->info->xmii_ctrl0;
2299         const u16 *regs = dev->info->regs;
2300         u8 data8;
2301
2302         ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2303
2304         data8 &= ~P_MII_100MBIT_M;
2305
2306         if (speed == SPEED_100)
2307                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2308         else
2309                 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2310
2311         /* Write the updated value */
2312         ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2313 }
2314
2315 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2316 {
2317         if (speed == SPEED_1000)
2318                 ksz_set_gbit(dev, port, true);
2319         else
2320                 ksz_set_gbit(dev, port, false);
2321
2322         if (speed == SPEED_100 || speed == SPEED_10)
2323                 ksz_set_100_10mbit(dev, port, speed);
2324 }
2325
2326 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2327                                 bool tx_pause, bool rx_pause)
2328 {
2329         const u8 *bitval = dev->info->xmii_ctrl0;
2330         const u32 *masks = dev->info->masks;
2331         const u16 *regs = dev->info->regs;
2332         u8 mask;
2333         u8 val;
2334
2335         mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2336                masks[P_MII_RX_FLOW_CTRL];
2337
2338         if (duplex == DUPLEX_FULL)
2339                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2340         else
2341                 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2342
2343         if (tx_pause)
2344                 val |= masks[P_MII_TX_FLOW_CTRL];
2345
2346         if (rx_pause)
2347                 val |= masks[P_MII_RX_FLOW_CTRL];
2348
2349         ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2350 }
2351
2352 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2353                                         unsigned int mode,
2354                                         phy_interface_t interface,
2355                                         struct phy_device *phydev, int speed,
2356                                         int duplex, bool tx_pause,
2357                                         bool rx_pause)
2358 {
2359         struct ksz_port *p;
2360
2361         p = &dev->ports[port];
2362
2363         /* Internal PHYs */
2364         if (dev->info->internal_phy[port])
2365                 return;
2366
2367         p->phydev.speed = speed;
2368
2369         ksz_port_set_xmii_speed(dev, port, speed);
2370
2371         ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
2372 }
2373
2374 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
2375                                     unsigned int mode,
2376                                     phy_interface_t interface,
2377                                     struct phy_device *phydev, int speed,
2378                                     int duplex, bool tx_pause, bool rx_pause)
2379 {
2380         struct ksz_device *dev = ds->priv;
2381
2382         if (dev->dev_ops->phylink_mac_link_up)
2383                 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
2384                                                   phydev, speed, duplex,
2385                                                   tx_pause, rx_pause);
2386 }
2387
2388 static int ksz_switch_detect(struct ksz_device *dev)
2389 {
2390         u8 id1, id2, id4;
2391         u16 id16;
2392         u32 id32;
2393         int ret;
2394
2395         /* read chip id */
2396         ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
2397         if (ret)
2398                 return ret;
2399
2400         id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
2401         id2 = FIELD_GET(SW_CHIP_ID_M, id16);
2402
2403         switch (id1) {
2404         case KSZ87_FAMILY_ID:
2405                 if (id2 == KSZ87_CHIP_ID_95) {
2406                         u8 val;
2407
2408                         dev->chip_id = KSZ8795_CHIP_ID;
2409
2410                         ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
2411                         if (val & KSZ8_PORT_FIBER_MODE)
2412                                 dev->chip_id = KSZ8765_CHIP_ID;
2413                 } else if (id2 == KSZ87_CHIP_ID_94) {
2414                         dev->chip_id = KSZ8794_CHIP_ID;
2415                 } else {
2416                         return -ENODEV;
2417                 }
2418                 break;
2419         case KSZ88_FAMILY_ID:
2420                 if (id2 == KSZ88_CHIP_ID_63)
2421                         dev->chip_id = KSZ8830_CHIP_ID;
2422                 else
2423                         return -ENODEV;
2424                 break;
2425         default:
2426                 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
2427                 if (ret)
2428                         return ret;
2429
2430                 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
2431                 id32 &= ~0xFF;
2432
2433                 switch (id32) {
2434                 case KSZ9477_CHIP_ID:
2435                 case KSZ9896_CHIP_ID:
2436                 case KSZ9897_CHIP_ID:
2437                 case KSZ9567_CHIP_ID:
2438                 case LAN9370_CHIP_ID:
2439                 case LAN9371_CHIP_ID:
2440                 case LAN9372_CHIP_ID:
2441                 case LAN9373_CHIP_ID:
2442                 case LAN9374_CHIP_ID:
2443                         dev->chip_id = id32;
2444                         break;
2445                 case KSZ9893_CHIP_ID:
2446                         ret = ksz_read8(dev, REG_CHIP_ID4,
2447                                         &id4);
2448                         if (ret)
2449                                 return ret;
2450
2451                         if (id4 == SKU_ID_KSZ8563)
2452                                 dev->chip_id = KSZ8563_CHIP_ID;
2453                         else
2454                                 dev->chip_id = KSZ9893_CHIP_ID;
2455
2456                         break;
2457                 default:
2458                         dev_err(dev->dev,
2459                                 "unsupported switch detected %x)\n", id32);
2460                         return -ENODEV;
2461                 }
2462         }
2463         return 0;
2464 }
2465
2466 static const struct dsa_switch_ops ksz_switch_ops = {
2467         .get_tag_protocol       = ksz_get_tag_protocol,
2468         .get_phy_flags          = ksz_get_phy_flags,
2469         .setup                  = ksz_setup,
2470         .teardown               = ksz_teardown,
2471         .phy_read               = ksz_phy_read16,
2472         .phy_write              = ksz_phy_write16,
2473         .phylink_get_caps       = ksz_phylink_get_caps,
2474         .phylink_mac_config     = ksz_phylink_mac_config,
2475         .phylink_mac_link_up    = ksz_phylink_mac_link_up,
2476         .phylink_mac_link_down  = ksz_mac_link_down,
2477         .port_enable            = ksz_enable_port,
2478         .get_strings            = ksz_get_strings,
2479         .get_ethtool_stats      = ksz_get_ethtool_stats,
2480         .get_sset_count         = ksz_sset_count,
2481         .port_bridge_join       = ksz_port_bridge_join,
2482         .port_bridge_leave      = ksz_port_bridge_leave,
2483         .port_stp_state_set     = ksz_port_stp_state_set,
2484         .port_pre_bridge_flags  = ksz_port_pre_bridge_flags,
2485         .port_bridge_flags      = ksz_port_bridge_flags,
2486         .port_fast_age          = ksz_port_fast_age,
2487         .port_vlan_filtering    = ksz_port_vlan_filtering,
2488         .port_vlan_add          = ksz_port_vlan_add,
2489         .port_vlan_del          = ksz_port_vlan_del,
2490         .port_fdb_dump          = ksz_port_fdb_dump,
2491         .port_fdb_add           = ksz_port_fdb_add,
2492         .port_fdb_del           = ksz_port_fdb_del,
2493         .port_mdb_add           = ksz_port_mdb_add,
2494         .port_mdb_del           = ksz_port_mdb_del,
2495         .port_mirror_add        = ksz_port_mirror_add,
2496         .port_mirror_del        = ksz_port_mirror_del,
2497         .get_stats64            = ksz_get_stats64,
2498         .get_pause_stats        = ksz_get_pause_stats,
2499         .port_change_mtu        = ksz_change_mtu,
2500         .port_max_mtu           = ksz_max_mtu,
2501 };
2502
2503 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
2504 {
2505         struct dsa_switch *ds;
2506         struct ksz_device *swdev;
2507
2508         ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2509         if (!ds)
2510                 return NULL;
2511
2512         ds->dev = base;
2513         ds->num_ports = DSA_MAX_PORTS;
2514         ds->ops = &ksz_switch_ops;
2515
2516         swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
2517         if (!swdev)
2518                 return NULL;
2519
2520         ds->priv = swdev;
2521         swdev->dev = base;
2522
2523         swdev->ds = ds;
2524         swdev->priv = priv;
2525
2526         return swdev;
2527 }
2528 EXPORT_SYMBOL(ksz_switch_alloc);
2529
2530 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
2531                                   struct device_node *port_dn)
2532 {
2533         phy_interface_t phy_mode = dev->ports[port_num].interface;
2534         int rx_delay = -1, tx_delay = -1;
2535
2536         if (!phy_interface_mode_is_rgmii(phy_mode))
2537                 return;
2538
2539         of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
2540         of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
2541
2542         if (rx_delay == -1 && tx_delay == -1) {
2543                 dev_warn(dev->dev,
2544                          "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
2545                          "please update device tree to specify \"rx-internal-delay-ps\" and "
2546                          "\"tx-internal-delay-ps\"",
2547                          port_num);
2548
2549                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
2550                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
2551                         rx_delay = 2000;
2552
2553                 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
2554                     phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
2555                         tx_delay = 2000;
2556         }
2557
2558         if (rx_delay < 0)
2559                 rx_delay = 0;
2560         if (tx_delay < 0)
2561                 tx_delay = 0;
2562
2563         dev->ports[port_num].rgmii_rx_val = rx_delay;
2564         dev->ports[port_num].rgmii_tx_val = tx_delay;
2565 }
2566
2567 int ksz_switch_register(struct ksz_device *dev)
2568 {
2569         const struct ksz_chip_data *info;
2570         struct device_node *port, *ports;
2571         phy_interface_t interface;
2572         unsigned int port_num;
2573         int ret;
2574         int i;
2575
2576         if (dev->pdata)
2577                 dev->chip_id = dev->pdata->chip_id;
2578
2579         dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
2580                                                   GPIOD_OUT_LOW);
2581         if (IS_ERR(dev->reset_gpio))
2582                 return PTR_ERR(dev->reset_gpio);
2583
2584         if (dev->reset_gpio) {
2585                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
2586                 usleep_range(10000, 12000);
2587                 gpiod_set_value_cansleep(dev->reset_gpio, 0);
2588                 msleep(100);
2589         }
2590
2591         mutex_init(&dev->dev_mutex);
2592         mutex_init(&dev->regmap_mutex);
2593         mutex_init(&dev->alu_mutex);
2594         mutex_init(&dev->vlan_mutex);
2595
2596         ret = ksz_switch_detect(dev);
2597         if (ret)
2598                 return ret;
2599
2600         info = ksz_lookup_info(dev->chip_id);
2601         if (!info)
2602                 return -ENODEV;
2603
2604         /* Update the compatible info with the probed one */
2605         dev->info = info;
2606
2607         dev_info(dev->dev, "found switch: %s, rev %i\n",
2608                  dev->info->dev_name, dev->chip_rev);
2609
2610         ret = ksz_check_device_id(dev);
2611         if (ret)
2612                 return ret;
2613
2614         dev->dev_ops = dev->info->ops;
2615
2616         ret = dev->dev_ops->init(dev);
2617         if (ret)
2618                 return ret;
2619
2620         dev->ports = devm_kzalloc(dev->dev,
2621                                   dev->info->port_cnt * sizeof(struct ksz_port),
2622                                   GFP_KERNEL);
2623         if (!dev->ports)
2624                 return -ENOMEM;
2625
2626         for (i = 0; i < dev->info->port_cnt; i++) {
2627                 spin_lock_init(&dev->ports[i].mib.stats64_lock);
2628                 mutex_init(&dev->ports[i].mib.cnt_mutex);
2629                 dev->ports[i].mib.counters =
2630                         devm_kzalloc(dev->dev,
2631                                      sizeof(u64) * (dev->info->mib_cnt + 1),
2632                                      GFP_KERNEL);
2633                 if (!dev->ports[i].mib.counters)
2634                         return -ENOMEM;
2635
2636                 dev->ports[i].ksz_dev = dev;
2637                 dev->ports[i].num = i;
2638         }
2639
2640         /* set the real number of ports */
2641         dev->ds->num_ports = dev->info->port_cnt;
2642
2643         /* Host port interface will be self detected, or specifically set in
2644          * device tree.
2645          */
2646         for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
2647                 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
2648         if (dev->dev->of_node) {
2649                 ret = of_get_phy_mode(dev->dev->of_node, &interface);
2650                 if (ret == 0)
2651                         dev->compat_interface = interface;
2652                 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
2653                 if (!ports)
2654                         ports = of_get_child_by_name(dev->dev->of_node, "ports");
2655                 if (ports) {
2656                         for_each_available_child_of_node(ports, port) {
2657                                 if (of_property_read_u32(port, "reg",
2658                                                          &port_num))
2659                                         continue;
2660                                 if (!(dev->port_mask & BIT(port_num))) {
2661                                         of_node_put(port);
2662                                         of_node_put(ports);
2663                                         return -EINVAL;
2664                                 }
2665                                 of_get_phy_mode(port,
2666                                                 &dev->ports[port_num].interface);
2667
2668                                 ksz_parse_rgmii_delay(dev, port_num, port);
2669                         }
2670                         of_node_put(ports);
2671                 }
2672                 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
2673                                                          "microchip,synclko-125");
2674                 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
2675                                                              "microchip,synclko-disable");
2676                 if (dev->synclko_125 && dev->synclko_disable) {
2677                         dev_err(dev->dev, "inconsistent synclko settings\n");
2678                         return -EINVAL;
2679                 }
2680         }
2681
2682         ret = dsa_register_switch(dev->ds);
2683         if (ret) {
2684                 dev->dev_ops->exit(dev);
2685                 return ret;
2686         }
2687
2688         /* Read MIB counters every 30 seconds to avoid overflow. */
2689         dev->mib_read_interval = msecs_to_jiffies(5000);
2690
2691         /* Start the MIB timer. */
2692         schedule_delayed_work(&dev->mib_read, 0);
2693
2694         return ret;
2695 }
2696 EXPORT_SYMBOL(ksz_switch_register);
2697
2698 void ksz_switch_remove(struct ksz_device *dev)
2699 {
2700         /* timer started */
2701         if (dev->mib_read_interval) {
2702                 dev->mib_read_interval = 0;
2703                 cancel_delayed_work_sync(&dev->mib_read);
2704         }
2705
2706         dev->dev_ops->exit(dev);
2707         dsa_unregister_switch(dev->ds);
2708
2709         if (dev->reset_gpio)
2710                 gpiod_set_value_cansleep(dev->reset_gpio, 1);
2711
2712 }
2713 EXPORT_SYMBOL(ksz_switch_remove);
2714
2715 MODULE_AUTHOR("Woojung Huh <[email protected]>");
2716 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
2717 MODULE_LICENSE("GPL");