2 * IOSF-SB MailBox Interface Driver
3 * Copyright (c) 2013, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * The IOSF-SB is a fabric bus available on Atom based SOC's that uses a
16 * mailbox interface (MBI) to communicate with mutiple devices. This
17 * driver implements access to this interface for those platforms that can
18 * enumerate the device using PCI.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/spinlock.h>
24 #include <linux/pci.h>
25 #include <linux/debugfs.h>
26 #include <linux/capability.h>
28 #include <asm/iosf_mbi.h>
30 #define PCI_DEVICE_ID_BAYTRAIL 0x0F00
31 #define PCI_DEVICE_ID_BRASWELL 0x2280
32 #define PCI_DEVICE_ID_QUARK_X1000 0x0958
34 static DEFINE_SPINLOCK(iosf_mbi_lock);
36 static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
38 return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
41 static struct pci_dev *mbi_pdev; /* one mbi device */
43 static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
51 result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
57 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
61 result = pci_read_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
68 dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
72 static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr)
79 result = pci_write_config_dword(mbi_pdev, MBI_MDR_OFFSET, mdr);
84 result = pci_write_config_dword(mbi_pdev, MBI_MCRX_OFFSET,
90 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr);
97 dev_err(&mbi_pdev->dev, "PCI config access failed with %d\n", result);
101 int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
107 /*Access to the GFX unit is handled by GPU code */
108 if (port == BT_MBI_UNIT_GFX) {
113 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
114 mcrx = offset & MBI_MASK_HI;
116 spin_lock_irqsave(&iosf_mbi_lock, flags);
117 ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr);
118 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
122 EXPORT_SYMBOL(iosf_mbi_read);
124 int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
130 /*Access to the GFX unit is handled by GPU code */
131 if (port == BT_MBI_UNIT_GFX) {
136 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
137 mcrx = offset & MBI_MASK_HI;
139 spin_lock_irqsave(&iosf_mbi_lock, flags);
140 ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr);
141 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
145 EXPORT_SYMBOL(iosf_mbi_write);
147 int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
154 /*Access to the GFX unit is handled by GPU code */
155 if (port == BT_MBI_UNIT_GFX) {
160 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO);
161 mcrx = offset & MBI_MASK_HI;
163 spin_lock_irqsave(&iosf_mbi_lock, flags);
165 /* Read current mdr value */
166 ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value);
168 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
178 ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value);
180 spin_unlock_irqrestore(&iosf_mbi_lock, flags);
184 EXPORT_SYMBOL(iosf_mbi_modify);
186 bool iosf_mbi_available(void)
188 /* Mbi isn't hot-pluggable. No remove routine is provided */
191 EXPORT_SYMBOL(iosf_mbi_available);
193 #ifdef CONFIG_IOSF_MBI_DEBUG
198 static int mcr_get(void *data, u64 *val)
204 static int mcr_set(void *data, u64 val)
206 u8 command = ((u32)val & 0xFF000000) >> 24,
207 port = ((u32)val & 0x00FF0000) >> 16,
208 offset = ((u32)val & 0x0000FF00) >> 8;
213 if (!capable(CAP_SYS_RAWIO))
217 err = iosf_mbi_write(port,
222 err = iosf_mbi_read(port,
229 DEFINE_SIMPLE_ATTRIBUTE(iosf_mcr_fops, mcr_get, mcr_set , "%llx\n");
231 static struct dentry *iosf_dbg;
233 static void iosf_sideband_debug_init(void)
237 iosf_dbg = debugfs_create_dir("iosf_sb", NULL);
238 if (IS_ERR_OR_NULL(iosf_dbg))
242 d = debugfs_create_x32("mdr", 0660, iosf_dbg, &dbg_mdr);
243 if (IS_ERR_OR_NULL(d))
247 debugfs_create_x32("mcrx", 0660, iosf_dbg, &dbg_mcrx);
248 if (IS_ERR_OR_NULL(d))
251 /* mcr - initiates mailbox tranaction */
252 debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops);
253 if (IS_ERR_OR_NULL(d))
259 debugfs_remove_recursive(d);
262 static void iosf_debugfs_init(void)
264 iosf_sideband_debug_init();
267 static void iosf_debugfs_remove(void)
269 debugfs_remove_recursive(iosf_dbg);
272 static inline void iosf_debugfs_init(void) { }
273 static inline void iosf_debugfs_remove(void) { }
274 #endif /* CONFIG_IOSF_MBI_DEBUG */
276 static int iosf_mbi_probe(struct pci_dev *pdev,
277 const struct pci_device_id *unused)
281 ret = pci_enable_device(pdev);
283 dev_err(&pdev->dev, "error: could not enable device\n");
287 mbi_pdev = pci_dev_get(pdev);
291 static const struct pci_device_id iosf_mbi_pci_ids[] = {
292 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BAYTRAIL) },
293 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_BRASWELL) },
294 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_QUARK_X1000) },
297 MODULE_DEVICE_TABLE(pci, iosf_mbi_pci_ids);
299 static struct pci_driver iosf_mbi_pci_driver = {
300 .name = "iosf_mbi_pci",
301 .probe = iosf_mbi_probe,
302 .id_table = iosf_mbi_pci_ids,
305 static int __init iosf_mbi_init(void)
309 return pci_register_driver(&iosf_mbi_pci_driver);
312 static void __exit iosf_mbi_exit(void)
314 iosf_debugfs_remove();
316 pci_unregister_driver(&iosf_mbi_pci_driver);
318 pci_dev_put(mbi_pdev);
323 module_init(iosf_mbi_init);
324 module_exit(iosf_mbi_exit);
327 MODULE_DESCRIPTION("IOSF Mailbox Interface accessor");
328 MODULE_LICENSE("GPL v2");