drivers/platform/goldfish/goldfish_pipe.c

   1 /*
   2  * Copyright (C) 2011 Google, Inc.
   3  * Copyright (C) 2012 Intel, Inc.
   4  * Copyright (C) 2013 Intel, Inc.
   5  * Copyright (C) 2014 Linaro Limited
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 /* This source file contains the implementation of a special device driver
  19  * that intends to provide a *very* fast communication channel between the
  20  * guest system and the QEMU emulator.
  21  *
  22  * Usage from the guest is simply the following (error handling simplified):
  23  *
  24  *    int  fd = open("/dev/qemu_pipe",O_RDWR);
  25  *    .... write() or read() through the pipe.
  26  *
  27  * This driver doesn't deal with the exact protocol used during the session.
  28  * It is intended to be as simple as something like:
  29  *
  30  *    // do this _just_ after opening the fd to connect to a specific
  31  *    // emulator service.
  32  *    const char*  msg = "<pipename>";
  33  *    if (write(fd, msg, strlen(msg)+1) < 0) {
  34  *       ... could not connect to <pipename> service
  35  *       close(fd);
  36  *    }
  37  *
  38  *    // after this, simply read() and write() to communicate with the
  39  *    // service. Exact protocol details left as an exercise to the reader.
  40  *
  41  * This driver is very fast because it doesn't copy any data through
  42  * intermediate buffers, since the emulator is capable of translating
  43  * guest user addresses into host ones.
  44  *
  45  * Note that we must however ensure that each user page involved in the
  46  * exchange is properly mapped during a transfer.
  47  */
  48
  49 #include <linux/module.h>
  50 #include <linux/interrupt.h>
  51 #include <linux/kernel.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/miscdevice.h>
  54 #include <linux/platform_device.h>
  55 #include <linux/poll.h>
  56 #include <linux/sched.h>
  57 #include <linux/bitops.h>
  58 #include <linux/slab.h>
  59 #include <linux/io.h>
  60 #include <linux/goldfish.h>
  61 #include <linux/dma-mapping.h>
  62 #include <linux/mm.h>
  63 #include <linux/acpi.h>
  64
  65 /*
  66  * IMPORTANT: The following constants must match the ones used and defined
  67  * in external/qemu/hw/goldfish_pipe.c in the Android source tree.
  68  */
  69
  70 /* pipe device registers */
  71 #define PIPE_REG_COMMAND                0x00  /* write: value = command */
  72 #define PIPE_REG_STATUS                 0x04  /* read */
  73 #define PIPE_REG_CHANNEL                0x08  /* read/write: channel id */
  74 #define PIPE_REG_CHANNEL_HIGH           0x30  /* read/write: channel id */
  75 #define PIPE_REG_SIZE                   0x0c  /* read/write: buffer size */
  76 #define PIPE_REG_ADDRESS                0x10  /* write: physical address */
  77 #define PIPE_REG_ADDRESS_HIGH           0x34  /* write: physical address */
  78 #define PIPE_REG_WAKES                  0x14  /* read: wake flags */
  79 #define PIPE_REG_PARAMS_ADDR_LOW        0x18  /* read/write: batch data address */
  80 #define PIPE_REG_PARAMS_ADDR_HIGH       0x1c  /* read/write: batch data address */
  81 #define PIPE_REG_ACCESS_PARAMS          0x20  /* write: batch access */
  82 #define PIPE_REG_VERSION                0x24  /* read: device version */
  83
  84 /* list of commands for PIPE_REG_COMMAND */
  85 #define CMD_OPEN                        1  /* open new channel */
  86 #define CMD_CLOSE                       2  /* close channel (from guest) */
  87 #define CMD_POLL                        3  /* poll read/write status */
  88
  89 /* List of bitflags returned in status of CMD_POLL command */
  90 #define PIPE_POLL_IN                    (1 << 0)
  91 #define PIPE_POLL_OUT                   (1 << 1)
  92 #define PIPE_POLL_HUP                   (1 << 2)
  93
  94 /* The following commands are related to write operations */
  95 #define CMD_WRITE_BUFFER        4  /* send a user buffer to the emulator */
  96 #define CMD_WAKE_ON_WRITE       5  /* tell the emulator to wake us when writing
  97                                      is possible */
  98 #define CMD_READ_BUFFER        6  /* receive a user buffer from the emulator */
  99 #define CMD_WAKE_ON_READ       7  /* tell the emulator to wake us when reading
 100                                    * is possible */
 101
 102 /* Possible status values used to signal errors - see goldfish_pipe_error_convert */
 103 #define PIPE_ERROR_INVAL       -1
 104 #define PIPE_ERROR_AGAIN       -2
 105 #define PIPE_ERROR_NOMEM       -3
 106 #define PIPE_ERROR_IO          -4
 107
 108 /* Bit-flags used to signal events from the emulator */
 109 #define PIPE_WAKE_CLOSED       (1 << 0)  /* emulator closed pipe */
 110 #define PIPE_WAKE_READ         (1 << 1)  /* pipe can now be read from */
 111 #define PIPE_WAKE_WRITE        (1 << 2)  /* pipe can now be written to */
 112
 113 struct access_params {
 114         unsigned long channel;
 115         u32 size;
 116         unsigned long address;
 117         u32 cmd;
 118         u32 result;
 119         /* reserved for future extension */
 120         u32 flags;
 121 };
 122
 123 /* The global driver data. Holds a reference to the i/o page used to
 124  * communicate with the emulator, and a wake queue for blocked tasks
 125  * waiting to be awoken.
 126  */
 127 struct goldfish_pipe_dev {
 128         spinlock_t lock;
 129         unsigned char __iomem *base;
 130         struct access_params *aps;
 131         int irq;
 132         u32 version;
 133 };
 134
 135 static struct goldfish_pipe_dev   pipe_dev[1];
 136
 137 /* This data type models a given pipe instance */
 138 struct goldfish_pipe {
 139         struct goldfish_pipe_dev *dev;
 140         struct mutex lock;
 141         unsigned long flags;
 142         wait_queue_head_t wake_queue;
 143 };
 144
 145
 146 /* Bit flags for the 'flags' field */
 147 enum {
 148         BIT_CLOSED_ON_HOST = 0,  /* pipe closed by host */
 149         BIT_WAKE_ON_WRITE  = 1,  /* want to be woken on writes */
 150         BIT_WAKE_ON_READ   = 2,  /* want to be woken on reads */
 151 };
 152
 153
 154 static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd)
 155 {
 156         unsigned long flags;
 157         u32 status;
 158         struct goldfish_pipe_dev *dev = pipe->dev;
 159
 160         spin_lock_irqsave(&dev->lock, flags);
 161         gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
 162                      dev->base + PIPE_REG_CHANNEL_HIGH);
 163         writel(cmd, dev->base + PIPE_REG_COMMAND);
 164         status = readl(dev->base + PIPE_REG_STATUS);
 165         spin_unlock_irqrestore(&dev->lock, flags);
 166         return status;
 167 }
 168
 169 static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd)
 170 {
 171         unsigned long flags;
 172         struct goldfish_pipe_dev *dev = pipe->dev;
 173
 174         spin_lock_irqsave(&dev->lock, flags);
 175         gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
 176                      dev->base + PIPE_REG_CHANNEL_HIGH);
 177         writel(cmd, dev->base + PIPE_REG_COMMAND);
 178         spin_unlock_irqrestore(&dev->lock, flags);
 179 }
 180
 181 /* This function converts an error code returned by the emulator through
 182  * the PIPE_REG_STATUS i/o register into a valid negative errno value.
 183  */
 184 static int goldfish_pipe_error_convert(int status)
 185 {
 186         switch (status) {
 187         case PIPE_ERROR_AGAIN:
 188                 return -EAGAIN;
 189         case PIPE_ERROR_NOMEM:
 190                 return -ENOMEM;
 191         case PIPE_ERROR_IO:
 192                 return -EIO;
 193         default:
 194                 return -EINVAL;
 195         }
 196 }
 197
 198 /*
 199  * Notice: QEMU will return 0 for un-known register access, indicating
 200  * param_acess is supported or not
 201  */
 202 static int valid_batchbuffer_addr(struct goldfish_pipe_dev *dev,
 203                                   struct access_params *aps)
 204 {
 205         u32 aph, apl;
 206         u64 paddr;
 207         aph = readl(dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
 208         apl = readl(dev->base + PIPE_REG_PARAMS_ADDR_LOW);
 209
 210         paddr = ((u64)aph << 32) | apl;
 211         if (paddr != (__pa(aps)))
 212                 return 0;
 213         return 1;
 214 }
 215
 216 /* 0 on success */
 217 static int setup_access_params_addr(struct platform_device *pdev,
 218                                         struct goldfish_pipe_dev *dev)
 219 {
 220         dma_addr_t dma_handle;
 221         struct access_params *aps;
 222
 223         aps = dmam_alloc_coherent(&pdev->dev, sizeof(struct access_params),
 224                                   &dma_handle, GFP_KERNEL);
 225         if (!aps)
 226                 return -ENOMEM;
 227
 228         writel(upper_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
 229         writel(lower_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_LOW);
 230
 231         if (valid_batchbuffer_addr(dev, aps)) {
 232                 dev->aps = aps;
 233                 return 0;
 234         } else
 235                 return -1;
 236 }
 237
 238 /* A value that will not be set by qemu emulator */
 239 #define INITIAL_BATCH_RESULT (0xdeadbeaf)
 240 static int access_with_param(struct goldfish_pipe_dev *dev, const int cmd,
 241                                 unsigned long address, unsigned long avail,
 242                                 struct goldfish_pipe *pipe, int *status)
 243 {
 244         struct access_params *aps = dev->aps;
 245
 246         if (aps == NULL)
 247                 return -1;
 248
 249         aps->result = INITIAL_BATCH_RESULT;
 250         aps->channel = (unsigned long)pipe;
 251         aps->size = avail;
 252         aps->address = address;
 253         aps->cmd = cmd;
 254         writel(cmd, dev->base + PIPE_REG_ACCESS_PARAMS);
 255         /*
 256          * If the aps->result has not changed, that means
 257          * that the batch command failed
 258          */
 259         if (aps->result == INITIAL_BATCH_RESULT)
 260                 return -1;
 261         *status = aps->result;
 262         return 0;
 263 }
 264
 265 static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer,
 266                                        size_t bufflen, int is_write)
 267 {
 268         unsigned long irq_flags;
 269         struct goldfish_pipe *pipe = filp->private_data;
 270         struct goldfish_pipe_dev *dev = pipe->dev;
 271         unsigned long address, address_end;
 272         int count = 0, ret = -EINVAL;
 273
 274         /* If the emulator already closed the pipe, no need to go further */
 275         if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
 276                 return -EIO;
 277
 278         /* Null reads or writes succeeds */
 279         if (unlikely(bufflen == 0))
 280                 return 0;
 281
 282         /* Check the buffer range for access */
 283         if (!access_ok(is_write ? VERIFY_WRITE : VERIFY_READ,
 284                         buffer, bufflen))
 285                 return -EFAULT;
 286
 287         /* Serialize access to the pipe */
 288         if (mutex_lock_interruptible(&pipe->lock))
 289                 return -ERESTARTSYS;
 290
 291         address = (unsigned long)(void *)buffer;
 292         address_end = address + bufflen;
 293
 294         while (address < address_end) {
 295                 unsigned long page_end = (address & PAGE_MASK) + PAGE_SIZE;
 296                 unsigned long next     = page_end < address_end ? page_end
 297                                                                 : address_end;
 298                 unsigned long avail    = next - address;
 299                 int status, wakeBit;
 300                 struct page *page;
 301
 302                 /* Either vaddr or paddr depending on the device version */
 303                 unsigned long xaddr;
 304
 305                 /*
 306                  * We grab the pages on a page-by-page basis in case user
 307                  * space gives us a potentially huge buffer but the read only
 308                  * returns a small amount, then there's no need to pin that
 309                  * much memory to the process.
 310                  */
 311                 ret = get_user_pages_unlocked(address, 1, &page,
 312                                 is_write ? 0 : FOLL_WRITE);
 313                 if (ret < 0)
 314                         break;
 315
 316                 if (dev->version) {
 317                         /* Device version 1 or newer (qemu-android) expects the
 318                          * physical address.
 319                          */
 320                         xaddr = page_to_phys(page) | (address & ~PAGE_MASK);
 321                 } else {
 322                         /* Device version 0 (classic emulator) expects the
 323                          * virtual address.
 324                          */
 325                         xaddr = address;
 326                 }
 327
 328                 /* Now, try to transfer the bytes in the current page */
 329                 spin_lock_irqsave(&dev->lock, irq_flags);
 330                 if (access_with_param(dev,
 331                                 is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
 332                                 xaddr, avail, pipe, &status)) {
 333                         gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
 334                                      dev->base + PIPE_REG_CHANNEL_HIGH);
 335                         writel(avail, dev->base + PIPE_REG_SIZE);
 336                         gf_write_ptr((void *)xaddr,
 337                                      dev->base + PIPE_REG_ADDRESS,
 338                                      dev->base + PIPE_REG_ADDRESS_HIGH);
 339                         writel(is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
 340                                         dev->base + PIPE_REG_COMMAND);
 341                         status = readl(dev->base + PIPE_REG_STATUS);
 342                 }
 343                 spin_unlock_irqrestore(&dev->lock, irq_flags);
 344
 345                 if (status > 0 && !is_write)
 346                         set_page_dirty(page);
 347                 put_page(page);
 348
 349                 if (status > 0) { /* Correct transfer */
 350                         count += status;
 351                         address += status;
 352                         continue;
 353                 } else if (status == 0) { /* EOF */
 354                         ret = 0;
 355                         break;
 356                 } else if (status < 0 && count > 0) {
 357                         /*
 358                          * An error occurred and we already transferred
 359                          * something on one of the previous pages.
 360                          * Just return what we already copied and log this
 361                          * err.
 362                          *
 363                          * Note: This seems like an incorrect approach but
 364                          * cannot change it until we check if any user space
 365                          * ABI relies on this behavior.
 366                          */
 367                         if (status != PIPE_ERROR_AGAIN)
 368                                 pr_info_ratelimited("goldfish_pipe: backend returned error %d on %s\n",
 369                                         status, is_write ? "write" : "read");
 370                         ret = 0;
 371                         break;
 372                 }
 373
 374                 /*
 375                  * If the error is not PIPE_ERROR_AGAIN, or if we are not in
 376                  * non-blocking mode, just return the error code.
 377                  */
 378                 if (status != PIPE_ERROR_AGAIN ||
 379                         (filp->f_flags & O_NONBLOCK) != 0) {
 380                         ret = goldfish_pipe_error_convert(status);
 381                         break;
 382                 }
 383
 384                 /*
 385                  * The backend blocked the read/write, wait until the backend
 386                  * tells us it's ready to process more data.
 387                  */
 388                 wakeBit = is_write ? BIT_WAKE_ON_WRITE : BIT_WAKE_ON_READ;
 389                 set_bit(wakeBit, &pipe->flags);
 390
 391                 /* Tell the emulator we're going to wait for a wake event */
 392                 goldfish_cmd(pipe,
 393                         is_write ? CMD_WAKE_ON_WRITE : CMD_WAKE_ON_READ);
 394
 395                 /* Unlock the pipe, then wait for the wake signal */
 396                 mutex_unlock(&pipe->lock);
 397
 398                 while (test_bit(wakeBit, &pipe->flags)) {
 399                         if (wait_event_interruptible(
 400                                         pipe->wake_queue,
 401                                         !test_bit(wakeBit, &pipe->flags)))
 402                                 return -ERESTARTSYS;
 403
 404                         if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
 405                                 return -EIO;
 406                 }
 407
 408                 /* Try to re-acquire the lock */
 409                 if (mutex_lock_interruptible(&pipe->lock))
 410                         return -ERESTARTSYS;
 411         }
 412         mutex_unlock(&pipe->lock);
 413
 414         if (ret < 0)
 415                 return ret;
 416         else
 417                 return count;
 418 }
 419
 420 static ssize_t goldfish_pipe_read(struct file *filp, char __user *buffer,
 421                               size_t bufflen, loff_t *ppos)
 422 {
 423         return goldfish_pipe_read_write(filp, buffer, bufflen, 0);
 424 }
 425
 426 static ssize_t goldfish_pipe_write(struct file *filp,
 427                                 const char __user *buffer, size_t bufflen,
 428                                 loff_t *ppos)
 429 {
 430         return goldfish_pipe_read_write(filp, (char __user *)buffer,
 431                                                                 bufflen, 1);
 432 }
 433
 434
 435 static unsigned int goldfish_pipe_poll(struct file *filp, poll_table *wait)
 436 {
 437         struct goldfish_pipe *pipe = filp->private_data;
 438         unsigned int mask = 0;
 439         int status;
 440
 441         mutex_lock(&pipe->lock);
 442
 443         poll_wait(filp, &pipe->wake_queue, wait);
 444
 445         status = goldfish_cmd_status(pipe, CMD_POLL);
 446
 447         mutex_unlock(&pipe->lock);
 448
 449         if (status & PIPE_POLL_IN)
 450                 mask |= POLLIN | POLLRDNORM;
 451
 452         if (status & PIPE_POLL_OUT)
 453                 mask |= POLLOUT | POLLWRNORM;
 454
 455         if (status & PIPE_POLL_HUP)
 456                 mask |= POLLHUP;
 457
 458         if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
 459                 mask |= POLLERR;
 460
 461         return mask;
 462 }
 463
 464 static irqreturn_t goldfish_pipe_interrupt(int irq, void *dev_id)
 465 {
 466         struct goldfish_pipe_dev *dev = dev_id;
 467         unsigned long irq_flags;
 468         int count = 0;
 469
 470         /*
 471          * We're going to read from the emulator a list of (channel,flags)
 472          * pairs corresponding to the wake events that occurred on each
 473          * blocked pipe (i.e. channel).
 474          */
 475         spin_lock_irqsave(&dev->lock, irq_flags);
 476         for (;;) {
 477                 /* First read the channel, 0 means the end of the list */
 478                 struct goldfish_pipe *pipe;
 479                 unsigned long wakes;
 480                 unsigned long channel = 0;
 481
 482 #ifdef CONFIG_64BIT
 483                 channel = (u64)readl(dev->base + PIPE_REG_CHANNEL_HIGH) << 32;
 484
 485                 if (channel == 0)
 486                         break;
 487 #endif
 488                 channel |= readl(dev->base + PIPE_REG_CHANNEL);
 489
 490                 if (channel == 0)
 491                         break;
 492
 493                 /* Convert channel to struct pipe pointer + read wake flags */
 494                 wakes = readl(dev->base + PIPE_REG_WAKES);
 495                 pipe  = (struct goldfish_pipe *)(ptrdiff_t)channel;
 496
 497                 /* Did the emulator just closed a pipe? */
 498                 if (wakes & PIPE_WAKE_CLOSED) {
 499                         set_bit(BIT_CLOSED_ON_HOST, &pipe->flags);
 500                         wakes |= PIPE_WAKE_READ | PIPE_WAKE_WRITE;
 501                 }
 502                 if (wakes & PIPE_WAKE_READ)
 503                         clear_bit(BIT_WAKE_ON_READ, &pipe->flags);
 504                 if (wakes & PIPE_WAKE_WRITE)
 505                         clear_bit(BIT_WAKE_ON_WRITE, &pipe->flags);
 506
 507                 wake_up_interruptible(&pipe->wake_queue);
 508                 count++;
 509         }
 510         spin_unlock_irqrestore(&dev->lock, irq_flags);
 511
 512         return (count == 0) ? IRQ_NONE : IRQ_HANDLED;
 513 }
 514
 515 /**
 516  *      goldfish_pipe_open      -       open a channel to the AVD
 517  *      @inode: inode of device
 518  *      @file: file struct of opener
 519  *
 520  *      Create a new pipe link between the emulator and the use application.
 521  *      Each new request produces a new pipe.
 522  *
 523  *      Note: we use the pipe ID as a mux. All goldfish emulations are 32bit
 524  *      right now so this is fine. A move to 64bit will need this addressing
 525  */
 526 static int goldfish_pipe_open(struct inode *inode, struct file *file)
 527 {
 528         struct goldfish_pipe *pipe;
 529         struct goldfish_pipe_dev *dev = pipe_dev;
 530         int32_t status;
 531
 532         /* Allocate new pipe kernel object */
 533         pipe = kzalloc(sizeof(*pipe), GFP_KERNEL);
 534         if (pipe == NULL)
 535                 return -ENOMEM;
 536
 537         pipe->dev = dev;
 538         mutex_init(&pipe->lock);
 539         init_waitqueue_head(&pipe->wake_queue);
 540
 541         /*
 542          * Now, tell the emulator we're opening a new pipe. We use the
 543          * pipe object's address as the channel identifier for simplicity.
 544          */
 545
 546         status = goldfish_cmd_status(pipe, CMD_OPEN);
 547         if (status < 0) {
 548                 kfree(pipe);
 549                 return status;
 550         }
 551
 552         /* All is done, save the pipe into the file's private data field */
 553         file->private_data = pipe;
 554         return 0;
 555 }
 556
 557 static int goldfish_pipe_release(struct inode *inode, struct file *filp)
 558 {
 559         struct goldfish_pipe *pipe = filp->private_data;
 560
 561         /* The guest is closing the channel, so tell the emulator right now */
 562         goldfish_cmd(pipe, CMD_CLOSE);
 563         kfree(pipe);
 564         filp->private_data = NULL;
 565         return 0;
 566 }
 567
 568 static const struct file_operations goldfish_pipe_fops = {
 569         .owner = THIS_MODULE,
 570         .read = goldfish_pipe_read,
 571         .write = goldfish_pipe_write,
 572         .poll = goldfish_pipe_poll,
 573         .open = goldfish_pipe_open,
 574         .release = goldfish_pipe_release,
 575 };
 576
 577 static struct miscdevice goldfish_pipe_device = {
 578         .minor = MISC_DYNAMIC_MINOR,
 579         .name = "goldfish_pipe",
 580         .fops = &goldfish_pipe_fops,
 581 };
 582
 583 static int goldfish_pipe_probe(struct platform_device *pdev)
 584 {
 585         int err;
 586         struct resource *r;
 587         struct goldfish_pipe_dev *dev = pipe_dev;
 588
 589         /* not thread safe, but this should not happen */
 590         WARN_ON(dev->base != NULL);
 591
 592         spin_lock_init(&dev->lock);
 593
 594         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 595         if (r == NULL || resource_size(r) < PAGE_SIZE) {
 596                 dev_err(&pdev->dev, "can't allocate i/o page\n");
 597                 return -EINVAL;
 598         }
 599         dev->base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
 600         if (dev->base == NULL) {
 601                 dev_err(&pdev->dev, "ioremap failed\n");
 602                 return -EINVAL;
 603         }
 604
 605         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 606         if (r == NULL) {
 607                 err = -EINVAL;
 608                 goto error;
 609         }
 610         dev->irq = r->start;
 611
 612         err = devm_request_irq(&pdev->dev, dev->irq, goldfish_pipe_interrupt,
 613                                 IRQF_SHARED, "goldfish_pipe", dev);
 614         if (err) {
 615                 dev_err(&pdev->dev, "unable to allocate IRQ\n");
 616                 goto error;
 617         }
 618
 619         err = misc_register(&goldfish_pipe_device);
 620         if (err) {
 621                 dev_err(&pdev->dev, "unable to register device\n");
 622                 goto error;
 623         }
 624         setup_access_params_addr(pdev, dev);
 625
 626         /* Although the pipe device in the classic Android emulator does not
 627          * recognize the 'version' register, it won't treat this as an error
 628          * either and will simply return 0, which is fine.
 629          */
 630         dev->version = readl(dev->base + PIPE_REG_VERSION);
 631         return 0;
 632
 633 error:
 634         dev->base = NULL;
 635         return err;
 636 }
 637
 638 static int goldfish_pipe_remove(struct platform_device *pdev)
 639 {
 640         struct goldfish_pipe_dev *dev = pipe_dev;
 641         misc_deregister(&goldfish_pipe_device);
 642         dev->base = NULL;
 643         return 0;
 644 }
 645
 646 static const struct acpi_device_id goldfish_pipe_acpi_match[] = {
 647         { "GFSH0003", 0 },
 648         { },
 649 };
 650 MODULE_DEVICE_TABLE(acpi, goldfish_pipe_acpi_match);
 651
 652 static const struct of_device_id goldfish_pipe_of_match[] = {
 653         { .compatible = "google,android-pipe", },
 654         {},
 655 };
 656 MODULE_DEVICE_TABLE(of, goldfish_pipe_of_match);
 657
 658 static struct platform_driver goldfish_pipe = {
 659         .probe = goldfish_pipe_probe,
 660         .remove = goldfish_pipe_remove,
 661         .driver = {
 662                 .name = "goldfish_pipe",
 663                 .owner = THIS_MODULE,
 664                 .of_match_table = goldfish_pipe_of_match,
 665                 .acpi_match_table = ACPI_PTR(goldfish_pipe_acpi_match),
 666         }
 667 };
 668
 669 module_platform_driver(goldfish_pipe);
 670 MODULE_AUTHOR("David Turner <[email protected]>");
 671 MODULE_LICENSE("GPL");