drivers/gpu/drm/gma500/psb_irq.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**************************************************************************
   3  * Copyright (c) 2007, Intel Corporation.
   4  * All Rights Reserved.
   5  *
   6  * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   7  * develop this driver.
   8  *
   9  **************************************************************************/
  10
  11 #include <drm/drm_vblank.h>
  12
  13 #include "power.h"
  14 #include "psb_drv.h"
  15 #include "psb_intel_reg.h"
  16 #include "psb_irq.h"
  17 #include "psb_reg.h"
  18
  19 /*
  20  * inline functions
  21  */
  22
  23 static inline u32
  24 psb_pipestat(int pipe)
  25 {
  26         if (pipe == 0)
  27                 return PIPEASTAT;
  28         if (pipe == 1)
  29                 return PIPEBSTAT;
  30         if (pipe == 2)
  31                 return PIPECSTAT;
  32         BUG();
  33 }
  34
  35 static inline u32
  36 mid_pipe_event(int pipe)
  37 {
  38         if (pipe == 0)
  39                 return _PSB_PIPEA_EVENT_FLAG;
  40         if (pipe == 1)
  41                 return _MDFLD_PIPEB_EVENT_FLAG;
  42         if (pipe == 2)
  43                 return _MDFLD_PIPEC_EVENT_FLAG;
  44         BUG();
  45 }
  46
  47 static inline u32
  48 mid_pipe_vsync(int pipe)
  49 {
  50         if (pipe == 0)
  51                 return _PSB_VSYNC_PIPEA_FLAG;
  52         if (pipe == 1)
  53                 return _PSB_VSYNC_PIPEB_FLAG;
  54         if (pipe == 2)
  55                 return _MDFLD_PIPEC_VBLANK_FLAG;
  56         BUG();
  57 }
  58
  59 static inline u32
  60 mid_pipeconf(int pipe)
  61 {
  62         if (pipe == 0)
  63                 return PIPEACONF;
  64         if (pipe == 1)
  65                 return PIPEBCONF;
  66         if (pipe == 2)
  67                 return PIPECCONF;
  68         BUG();
  69 }
  70
  71 void
  72 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  73 {
  74         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  75                 u32 reg = psb_pipestat(pipe);
  76                 dev_priv->pipestat[pipe] |= mask;
  77                 /* Enable the interrupt, clear any pending status */
  78                 if (gma_power_begin(dev_priv->dev, false)) {
  79                         u32 writeVal = PSB_RVDC32(reg);
  80                         writeVal |= (mask | (mask >> 16));
  81                         PSB_WVDC32(writeVal, reg);
  82                         (void) PSB_RVDC32(reg);
  83                         gma_power_end(dev_priv->dev);
  84                 }
  85         }
  86 }
  87
  88 void
  89 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
  90 {
  91         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  92                 u32 reg = psb_pipestat(pipe);
  93                 dev_priv->pipestat[pipe] &= ~mask;
  94                 if (gma_power_begin(dev_priv->dev, false)) {
  95                         u32 writeVal = PSB_RVDC32(reg);
  96                         writeVal &= ~mask;
  97                         PSB_WVDC32(writeVal, reg);
  98                         (void) PSB_RVDC32(reg);
  99                         gma_power_end(dev_priv->dev);
 100                 }
 101         }
 102 }
 103
 104 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 105 {
 106         if (gma_power_begin(dev_priv->dev, false)) {
 107                 u32 pipe_event = mid_pipe_event(pipe);
 108                 dev_priv->vdc_irq_mask |= pipe_event;
 109                 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 110                 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 111                 gma_power_end(dev_priv->dev);
 112         }
 113 }
 114
 115 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
 116 {
 117         if (dev_priv->pipestat[pipe] == 0) {
 118                 if (gma_power_begin(dev_priv->dev, false)) {
 119                         u32 pipe_event = mid_pipe_event(pipe);
 120                         dev_priv->vdc_irq_mask &= ~pipe_event;
 121                         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 122                         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 123                         gma_power_end(dev_priv->dev);
 124                 }
 125         }
 126 }
 127
 128 /*
 129  * Display controller interrupt handler for pipe event.
 130  */
 131 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
 132 {
 133         struct drm_psb_private *dev_priv =
 134             (struct drm_psb_private *) dev->dev_private;
 135
 136         uint32_t pipe_stat_val = 0;
 137         uint32_t pipe_stat_reg = psb_pipestat(pipe);
 138         uint32_t pipe_enable = dev_priv->pipestat[pipe];
 139         uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
 140         uint32_t pipe_clear;
 141         uint32_t i = 0;
 142
 143         spin_lock(&dev_priv->irqmask_lock);
 144
 145         pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
 146         pipe_stat_val &= pipe_enable | pipe_status;
 147         pipe_stat_val &= pipe_stat_val >> 16;
 148
 149         spin_unlock(&dev_priv->irqmask_lock);
 150
 151         /* Clear the 2nd level interrupt status bits
 152          * Sometimes the bits are very sticky so we repeat until they unstick */
 153         for (i = 0; i < 0xffff; i++) {
 154                 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
 155                 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
 156
 157                 if (pipe_clear == 0)
 158                         break;
 159         }
 160
 161         if (pipe_clear)
 162                 dev_err(dev->dev,
 163                 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
 164                 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
 165
 166         if (pipe_stat_val & PIPE_VBLANK_STATUS) {
 167                 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
 168                 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 169                 unsigned long flags;
 170
 171                 drm_handle_vblank(dev, pipe);
 172
 173                 spin_lock_irqsave(&dev->event_lock, flags);
 174                 if (gma_crtc->page_flip_event) {
 175                         drm_crtc_send_vblank_event(crtc,
 176                                                    gma_crtc->page_flip_event);
 177                         gma_crtc->page_flip_event = NULL;
 178                         drm_crtc_vblank_put(crtc);
 179                 }
 180                 spin_unlock_irqrestore(&dev->event_lock, flags);
 181         }
 182 }
 183
 184 /*
 185  * Display controller interrupt handler.
 186  */
 187 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
 188 {
 189         if (vdc_stat & _PSB_IRQ_ASLE)
 190                 psb_intel_opregion_asle_intr(dev);
 191
 192         if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
 193                 mid_pipe_event_handler(dev, 0);
 194
 195         if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
 196                 mid_pipe_event_handler(dev, 1);
 197 }
 198
 199 /*
 200  * SGX interrupt handler
 201  */
 202 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
 203 {
 204         struct drm_psb_private *dev_priv = dev->dev_private;
 205         u32 val, addr;
 206
 207         if (stat_1 & _PSB_CE_TWOD_COMPLETE)
 208                 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
 209
 210         if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
 211                 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
 212                 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
 213                 if (val) {
 214                         if (val & _PSB_CBI_STAT_PF_N_RW)
 215                                 DRM_ERROR("SGX MMU page fault:");
 216                         else
 217                                 DRM_ERROR("SGX MMU read / write protection fault:");
 218
 219                         if (val & _PSB_CBI_STAT_FAULT_CACHE)
 220                                 DRM_ERROR("\tCache requestor");
 221                         if (val & _PSB_CBI_STAT_FAULT_TA)
 222                                 DRM_ERROR("\tTA requestor");
 223                         if (val & _PSB_CBI_STAT_FAULT_VDM)
 224                                 DRM_ERROR("\tVDM requestor");
 225                         if (val & _PSB_CBI_STAT_FAULT_2D)
 226                                 DRM_ERROR("\t2D requestor");
 227                         if (val & _PSB_CBI_STAT_FAULT_PBE)
 228                                 DRM_ERROR("\tPBE requestor");
 229                         if (val & _PSB_CBI_STAT_FAULT_TSP)
 230                                 DRM_ERROR("\tTSP requestor");
 231                         if (val & _PSB_CBI_STAT_FAULT_ISP)
 232                                 DRM_ERROR("\tISP requestor");
 233                         if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
 234                                 DRM_ERROR("\tUSSEPDS requestor");
 235                         if (val & _PSB_CBI_STAT_FAULT_HOST)
 236                                 DRM_ERROR("\tHost requestor");
 237
 238                         DRM_ERROR("\tMMU failing address is 0x%08x.\n",
 239                                   (unsigned int)addr);
 240                 }
 241         }
 242
 243         /* Clear bits */
 244         PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
 245         PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
 246         PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
 247 }
 248
 249 irqreturn_t psb_irq_handler(int irq, void *arg)
 250 {
 251         struct drm_device *dev = arg;
 252         struct drm_psb_private *dev_priv = dev->dev_private;
 253         uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
 254         u32 sgx_stat_1, sgx_stat_2;
 255         int handled = 0;
 256
 257         spin_lock(&dev_priv->irqmask_lock);
 258
 259         vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
 260
 261         if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
 262                 dsp_int = 1;
 263
 264         if (vdc_stat & _PSB_IRQ_SGX_FLAG)
 265                 sgx_int = 1;
 266         if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
 267                 hotplug_int = 1;
 268
 269         vdc_stat &= dev_priv->vdc_irq_mask;
 270         spin_unlock(&dev_priv->irqmask_lock);
 271
 272         if (dsp_int && gma_power_is_on(dev)) {
 273                 psb_vdc_interrupt(dev, vdc_stat);
 274                 handled = 1;
 275         }
 276
 277         if (sgx_int) {
 278                 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
 279                 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
 280                 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
 281                 handled = 1;
 282         }
 283
 284         /* Note: this bit has other meanings on some devices, so we will
 285            need to address that later if it ever matters */
 286         if (hotplug_int && dev_priv->ops->hotplug) {
 287                 handled = dev_priv->ops->hotplug(dev);
 288                 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
 289         }
 290
 291         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
 292         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
 293         rmb();
 294
 295         if (!handled)
 296                 return IRQ_NONE;
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 void psb_irq_preinstall(struct drm_device *dev)
 302 {
 303         struct drm_psb_private *dev_priv =
 304             (struct drm_psb_private *) dev->dev_private;
 305         unsigned long irqflags;
 306
 307         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 308
 309         if (gma_power_is_on(dev)) {
 310                 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 311                 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
 312                 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 313                 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
 314                 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
 315         }
 316         if (dev->vblank[0].enabled)
 317                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 318         if (dev->vblank[1].enabled)
 319                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 320
 321         /* Revisit this area - want per device masks ? */
 322         if (dev_priv->ops->hotplug)
 323                 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
 324         dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
 325
 326         /* This register is safe even if display island is off */
 327         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 328         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 329 }
 330
 331 int psb_irq_postinstall(struct drm_device *dev)
 332 {
 333         struct drm_psb_private *dev_priv = dev->dev_private;
 334         unsigned long irqflags;
 335         unsigned int i;
 336
 337         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 338
 339         /* Enable 2D and MMU fault interrupts */
 340         PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
 341         PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
 342         PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
 343
 344         /* This register is safe even if display island is off */
 345         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 346         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 347
 348         for (i = 0; i < dev->num_crtcs; ++i) {
 349                 if (dev->vblank[i].enabled)
 350                         psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 351                 else
 352                         psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 353         }
 354
 355         if (dev_priv->ops->hotplug_enable)
 356                 dev_priv->ops->hotplug_enable(dev, true);
 357
 358         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 359         return 0;
 360 }
 361
 362 void psb_irq_uninstall(struct drm_device *dev)
 363 {
 364         struct drm_psb_private *dev_priv = dev->dev_private;
 365         unsigned long irqflags;
 366         unsigned int i;
 367
 368         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 369
 370         if (dev_priv->ops->hotplug_enable)
 371                 dev_priv->ops->hotplug_enable(dev, false);
 372
 373         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 374
 375         for (i = 0; i < dev->num_crtcs; ++i) {
 376                 if (dev->vblank[i].enabled)
 377                         psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
 378         }
 379
 380         dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
 381                                   _PSB_IRQ_MSVDX_FLAG |
 382                                   _LNC_IRQ_TOPAZ_FLAG;
 383
 384         /* These two registers are safe even if display island is off */
 385         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 386         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 387
 388         wmb();
 389
 390         /* This register is safe even if display island is off */
 391         PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
 392         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 393 }
 394
 395 void psb_irq_turn_on_dpst(struct drm_device *dev)
 396 {
 397         struct drm_psb_private *dev_priv =
 398                 (struct drm_psb_private *) dev->dev_private;
 399         u32 hist_reg;
 400         u32 pwm_reg;
 401
 402         if (gma_power_begin(dev, false)) {
 403                 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
 404                 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
 405                 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
 406                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 407
 408                 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
 409                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 410                 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
 411                                                 | PWM_PHASEIN_INT_ENABLE,
 412                                                            PWM_CONTROL_LOGIC);
 413                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 414
 415                 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 416
 417                 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 418                 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
 419                                                         HISTOGRAM_INT_CONTROL);
 420                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 421                 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
 422                                                         PWM_CONTROL_LOGIC);
 423
 424                 gma_power_end(dev);
 425         }
 426 }
 427
 428 int psb_irq_enable_dpst(struct drm_device *dev)
 429 {
 430         struct drm_psb_private *dev_priv =
 431                 (struct drm_psb_private *) dev->dev_private;
 432         unsigned long irqflags;
 433
 434         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 435
 436         /* enable DPST */
 437         mid_enable_pipe_event(dev_priv, 0);
 438         psb_irq_turn_on_dpst(dev);
 439
 440         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 441         return 0;
 442 }
 443
 444 void psb_irq_turn_off_dpst(struct drm_device *dev)
 445 {
 446         struct drm_psb_private *dev_priv =
 447             (struct drm_psb_private *) dev->dev_private;
 448         u32 pwm_reg;
 449
 450         if (gma_power_begin(dev, false)) {
 451                 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
 452                 PSB_RVDC32(HISTOGRAM_INT_CONTROL);
 453
 454                 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
 455
 456                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 457                 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
 458                                                         PWM_CONTROL_LOGIC);
 459                 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
 460
 461                 gma_power_end(dev);
 462         }
 463 }
 464
 465 int psb_irq_disable_dpst(struct drm_device *dev)
 466 {
 467         struct drm_psb_private *dev_priv =
 468             (struct drm_psb_private *) dev->dev_private;
 469         unsigned long irqflags;
 470
 471         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 472
 473         mid_disable_pipe_event(dev_priv, 0);
 474         psb_irq_turn_off_dpst(dev);
 475
 476         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 477
 478         return 0;
 479 }
 480
 481 /*
 482  * It is used to enable VBLANK interrupt
 483  */
 484 int psb_enable_vblank(struct drm_crtc *crtc)
 485 {
 486         struct drm_device *dev = crtc->dev;
 487         unsigned int pipe = crtc->index;
 488         struct drm_psb_private *dev_priv = dev->dev_private;
 489         unsigned long irqflags;
 490         uint32_t reg_val = 0;
 491         uint32_t pipeconf_reg = mid_pipeconf(pipe);
 492
 493         if (gma_power_begin(dev, false)) {
 494                 reg_val = REG_READ(pipeconf_reg);
 495                 gma_power_end(dev);
 496         }
 497
 498         if (!(reg_val & PIPEACONF_ENABLE))
 499                 return -EINVAL;
 500
 501         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 502
 503         if (pipe == 0)
 504                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
 505         else if (pipe == 1)
 506                 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
 507
 508         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 509         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 510         psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 511
 512         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 513
 514         return 0;
 515 }
 516
 517 /*
 518  * It is used to disable VBLANK interrupt
 519  */
 520 void psb_disable_vblank(struct drm_crtc *crtc)
 521 {
 522         struct drm_device *dev = crtc->dev;
 523         unsigned int pipe = crtc->index;
 524         struct drm_psb_private *dev_priv = dev->dev_private;
 525         unsigned long irqflags;
 526
 527         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 528
 529         if (pipe == 0)
 530                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
 531         else if (pipe == 1)
 532                 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
 533
 534         PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
 535         PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
 536         psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
 537
 538         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 539 }
 540
 541 /* Called from drm generic code, passed a 'crtc', which
 542  * we use as a pipe index
 543  */
 544 u32 psb_get_vblank_counter(struct drm_crtc *crtc)
 545 {
 546         struct drm_device *dev = crtc->dev;
 547         unsigned int pipe = crtc->index;
 548         uint32_t high_frame = PIPEAFRAMEHIGH;
 549         uint32_t low_frame = PIPEAFRAMEPIXEL;
 550         uint32_t pipeconf_reg = PIPEACONF;
 551         uint32_t reg_val = 0;
 552         uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
 553
 554         switch (pipe) {
 555         case 0:
 556                 break;
 557         case 1:
 558                 high_frame = PIPEBFRAMEHIGH;
 559                 low_frame = PIPEBFRAMEPIXEL;
 560                 pipeconf_reg = PIPEBCONF;
 561                 break;
 562         case 2:
 563                 high_frame = PIPECFRAMEHIGH;
 564                 low_frame = PIPECFRAMEPIXEL;
 565                 pipeconf_reg = PIPECCONF;
 566                 break;
 567         default:
 568                 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
 569                 return 0;
 570         }
 571
 572         if (!gma_power_begin(dev, false))
 573                 return 0;
 574
 575         reg_val = REG_READ(pipeconf_reg);
 576
 577         if (!(reg_val & PIPEACONF_ENABLE)) {
 578                 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
 579                                                                 pipe);
 580                 goto psb_get_vblank_counter_exit;
 581         }
 582
 583         /*
 584          * High & low register fields aren't synchronized, so make sure
 585          * we get a low value that's stable across two reads of the high
 586          * register.
 587          */
 588         do {
 589                 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 590                          PIPE_FRAME_HIGH_SHIFT);
 591                 low =  ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 592                         PIPE_FRAME_LOW_SHIFT);
 593                 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 594                          PIPE_FRAME_HIGH_SHIFT);
 595         } while (high1 != high2);
 596
 597         count = (high1 << 8) | low;
 598
 599 psb_get_vblank_counter_exit:
 600
 601         gma_power_end(dev);
 602
 603         return count;
 604 }
 605