drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "drmP.h"
  24 #include "amdgpu.h"
  25 #include "amdgpu_pm.h"
  26 #include "amdgpu_i2c.h"
  27 #include "cikd.h"
  28 #include "atom.h"
  29 #include "amdgpu_atombios.h"
  30 #include "atombios_crtc.h"
  31 #include "atombios_encoders.h"
  32 #include "amdgpu_pll.h"
  33 #include "amdgpu_connectors.h"
  34
  35 #include "dce/dce_8_0_d.h"
  36 #include "dce/dce_8_0_sh_mask.h"
  37
  38 #include "gca/gfx_7_2_enum.h"
  39
  40 #include "gmc/gmc_7_1_d.h"
  41 #include "gmc/gmc_7_1_sh_mask.h"
  42
  43 #include "oss/oss_2_0_d.h"
  44 #include "oss/oss_2_0_sh_mask.h"
  45
  46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev);
  47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev);
  48
  49 static const u32 crtc_offsets[6] =
  50 {
  51         CRTC0_REGISTER_OFFSET,
  52         CRTC1_REGISTER_OFFSET,
  53         CRTC2_REGISTER_OFFSET,
  54         CRTC3_REGISTER_OFFSET,
  55         CRTC4_REGISTER_OFFSET,
  56         CRTC5_REGISTER_OFFSET
  57 };
  58
  59 static const uint32_t dig_offsets[] = {
  60         CRTC0_REGISTER_OFFSET,
  61         CRTC1_REGISTER_OFFSET,
  62         CRTC2_REGISTER_OFFSET,
  63         CRTC3_REGISTER_OFFSET,
  64         CRTC4_REGISTER_OFFSET,
  65         CRTC5_REGISTER_OFFSET,
  66         (0x13830 - 0x7030) >> 2,
  67 };
  68
  69 static const struct {
  70         uint32_t        reg;
  71         uint32_t        vblank;
  72         uint32_t        vline;
  73         uint32_t        hpd;
  74
  75 } interrupt_status_offsets[6] = { {
  76         .reg = mmDISP_INTERRUPT_STATUS,
  77         .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  78         .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  79         .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  80 }, {
  81         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  82         .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  83         .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  84         .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  85 }, {
  86         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  87         .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  88         .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  89         .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  90 }, {
  91         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
  92         .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
  93         .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
  94         .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
  95 }, {
  96         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
  97         .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
  98         .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
  99         .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
 100 }, {
 101         .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
 102         .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
 103         .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
 104         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 105 } };
 106
 107 static const uint32_t hpd_int_control_offsets[6] = {
 108         mmDC_HPD1_INT_CONTROL,
 109         mmDC_HPD2_INT_CONTROL,
 110         mmDC_HPD3_INT_CONTROL,
 111         mmDC_HPD4_INT_CONTROL,
 112         mmDC_HPD5_INT_CONTROL,
 113         mmDC_HPD6_INT_CONTROL,
 114 };
 115
 116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev,
 117                                      u32 block_offset, u32 reg)
 118 {
 119         unsigned long flags;
 120         u32 r;
 121
 122         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 123         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 124         r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
 125         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 126
 127         return r;
 128 }
 129
 130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev,
 131                                       u32 block_offset, u32 reg, u32 v)
 132 {
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
 136         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
 137         WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
 138         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 139 }
 140
 141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
 142 {
 143         if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
 144                         CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
 145                 return true;
 146         else
 147                 return false;
 148 }
 149
 150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
 151 {
 152         u32 pos1, pos2;
 153
 154         pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 155         pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 156
 157         if (pos1 != pos2)
 158                 return true;
 159         else
 160                 return false;
 161 }
 162
 163 /**
 164  * dce_v8_0_vblank_wait - vblank wait asic callback.
 165  *
 166  * @adev: amdgpu_device pointer
 167  * @crtc: crtc to wait for vblank on
 168  *
 169  * Wait for vblank on the requested crtc (evergreen+).
 170  */
 171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc)
 172 {
 173         unsigned i = 0;
 174
 175         if (crtc >= adev->mode_info.num_crtc)
 176                 return;
 177
 178         if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
 179                 return;
 180
 181         /* depending on when we hit vblank, we may be close to active; if so,
 182          * wait for another frame.
 183          */
 184         while (dce_v8_0_is_in_vblank(adev, crtc)) {
 185                 if (i++ % 100 == 0) {
 186                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 187                                 break;
 188                 }
 189         }
 190
 191         while (!dce_v8_0_is_in_vblank(adev, crtc)) {
 192                 if (i++ % 100 == 0) {
 193                         if (!dce_v8_0_is_counter_moving(adev, crtc))
 194                                 break;
 195                 }
 196         }
 197 }
 198
 199 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 200 {
 201         if (crtc >= adev->mode_info.num_crtc)
 202                 return 0;
 203         else
 204                 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
 205 }
 206
 207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev)
 208 {
 209         unsigned i;
 210
 211         /* Enable pflip interrupts */
 212         for (i = 0; i < adev->mode_info.num_crtc; i++)
 213                 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
 214 }
 215
 216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
 217 {
 218         unsigned i;
 219
 220         /* Disable pflip interrupts */
 221         for (i = 0; i < adev->mode_info.num_crtc; i++)
 222                 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
 223 }
 224
 225 /**
 226  * dce_v8_0_page_flip - pageflip callback.
 227  *
 228  * @adev: amdgpu_device pointer
 229  * @crtc_id: crtc to cleanup pageflip on
 230  * @crtc_base: new address of the crtc (GPU MC address)
 231  *
 232  * Triggers the actual pageflip by updating the primary
 233  * surface base address.
 234  */
 235 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
 236                               int crtc_id, u64 crtc_base)
 237 {
 238         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 239
 240         /* update the primary scanout addresses */
 241         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
 242                upper_32_bits(crtc_base));
 243         /* writing to the low address triggers the update */
 244         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
 245                lower_32_bits(crtc_base));
 246         /* post the write */
 247         RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 248 }
 249
 250 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 251                                         u32 *vbl, u32 *position)
 252 {
 253         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 254                 return -EINVAL;
 255
 256         *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
 257         *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
 258
 259         return 0;
 260 }
 261
 262 /**
 263  * dce_v8_0_hpd_sense - hpd sense callback.
 264  *
 265  * @adev: amdgpu_device pointer
 266  * @hpd: hpd (hotplug detect) pin
 267  *
 268  * Checks if a digital monitor is connected (evergreen+).
 269  * Returns true if connected, false if not connected.
 270  */
 271 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev,
 272                                enum amdgpu_hpd_id hpd)
 273 {
 274         bool connected = false;
 275
 276         switch (hpd) {
 277         case AMDGPU_HPD_1:
 278                 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
 279                         connected = true;
 280                 break;
 281         case AMDGPU_HPD_2:
 282                 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK)
 283                         connected = true;
 284                 break;
 285         case AMDGPU_HPD_3:
 286                 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK)
 287                         connected = true;
 288                 break;
 289         case AMDGPU_HPD_4:
 290                 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK)
 291                         connected = true;
 292                 break;
 293         case AMDGPU_HPD_5:
 294                 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK)
 295                         connected = true;
 296                 break;
 297         case AMDGPU_HPD_6:
 298                 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK)
 299                         connected = true;
 300                 break;
 301         default:
 302                 break;
 303         }
 304
 305         return connected;
 306 }
 307
 308 /**
 309  * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
 310  *
 311  * @adev: amdgpu_device pointer
 312  * @hpd: hpd (hotplug detect) pin
 313  *
 314  * Set the polarity of the hpd pin (evergreen+).
 315  */
 316 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev,
 317                                       enum amdgpu_hpd_id hpd)
 318 {
 319         u32 tmp;
 320         bool connected = dce_v8_0_hpd_sense(adev, hpd);
 321
 322         switch (hpd) {
 323         case AMDGPU_HPD_1:
 324                 tmp = RREG32(mmDC_HPD1_INT_CONTROL);
 325                 if (connected)
 326                         tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 327                 else
 328                         tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
 329                 WREG32(mmDC_HPD1_INT_CONTROL, tmp);
 330                 break;
 331         case AMDGPU_HPD_2:
 332                 tmp = RREG32(mmDC_HPD2_INT_CONTROL);
 333                 if (connected)
 334                         tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
 335                 else
 336                         tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK;
 337                 WREG32(mmDC_HPD2_INT_CONTROL, tmp);
 338                 break;
 339         case AMDGPU_HPD_3:
 340                 tmp = RREG32(mmDC_HPD3_INT_CONTROL);
 341                 if (connected)
 342                         tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
 343                 else
 344                         tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK;
 345                 WREG32(mmDC_HPD3_INT_CONTROL, tmp);
 346                 break;
 347         case AMDGPU_HPD_4:
 348                 tmp = RREG32(mmDC_HPD4_INT_CONTROL);
 349                 if (connected)
 350                         tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
 351                 else
 352                         tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK;
 353                 WREG32(mmDC_HPD4_INT_CONTROL, tmp);
 354                 break;
 355         case AMDGPU_HPD_5:
 356                 tmp = RREG32(mmDC_HPD5_INT_CONTROL);
 357                 if (connected)
 358                         tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
 359                 else
 360                         tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK;
 361                 WREG32(mmDC_HPD5_INT_CONTROL, tmp);
 362                         break;
 363         case AMDGPU_HPD_6:
 364                 tmp = RREG32(mmDC_HPD6_INT_CONTROL);
 365                 if (connected)
 366                         tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
 367                 else
 368                         tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK;
 369                 WREG32(mmDC_HPD6_INT_CONTROL, tmp);
 370                 break;
 371         default:
 372                 break;
 373         }
 374 }
 375
 376 /**
 377  * dce_v8_0_hpd_init - hpd setup callback.
 378  *
 379  * @adev: amdgpu_device pointer
 380  *
 381  * Setup the hpd pins used by the card (evergreen+).
 382  * Enable the pin, set the polarity, and enable the hpd interrupts.
 383  */
 384 static void dce_v8_0_hpd_init(struct amdgpu_device *adev)
 385 {
 386         struct drm_device *dev = adev->ddev;
 387         struct drm_connector *connector;
 388         u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) |
 389                 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) |
 390                 DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
 391
 392         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 393                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 394
 395                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 396                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 397                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 398                          * aux dp channel on imac and help (but not completely fix)
 399                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 400                          * also avoid interrupt storms during dpms.
 401                          */
 402                         continue;
 403                 }
 404                 switch (amdgpu_connector->hpd.hpd) {
 405                 case AMDGPU_HPD_1:
 406                         WREG32(mmDC_HPD1_CONTROL, tmp);
 407                         break;
 408                 case AMDGPU_HPD_2:
 409                         WREG32(mmDC_HPD2_CONTROL, tmp);
 410                         break;
 411                 case AMDGPU_HPD_3:
 412                         WREG32(mmDC_HPD3_CONTROL, tmp);
 413                         break;
 414                 case AMDGPU_HPD_4:
 415                         WREG32(mmDC_HPD4_CONTROL, tmp);
 416                         break;
 417                 case AMDGPU_HPD_5:
 418                         WREG32(mmDC_HPD5_CONTROL, tmp);
 419                         break;
 420                 case AMDGPU_HPD_6:
 421                         WREG32(mmDC_HPD6_CONTROL, tmp);
 422                         break;
 423                 default:
 424                         break;
 425                 }
 426                 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
 427                 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 428         }
 429 }
 430
 431 /**
 432  * dce_v8_0_hpd_fini - hpd tear down callback.
 433  *
 434  * @adev: amdgpu_device pointer
 435  *
 436  * Tear down the hpd pins used by the card (evergreen+).
 437  * Disable the hpd interrupts.
 438  */
 439 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 440 {
 441         struct drm_device *dev = adev->ddev;
 442         struct drm_connector *connector;
 443
 444         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 445                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 446
 447                 switch (amdgpu_connector->hpd.hpd) {
 448                 case AMDGPU_HPD_1:
 449                         WREG32(mmDC_HPD1_CONTROL, 0);
 450                         break;
 451                 case AMDGPU_HPD_2:
 452                         WREG32(mmDC_HPD2_CONTROL, 0);
 453                         break;
 454                 case AMDGPU_HPD_3:
 455                         WREG32(mmDC_HPD3_CONTROL, 0);
 456                         break;
 457                 case AMDGPU_HPD_4:
 458                         WREG32(mmDC_HPD4_CONTROL, 0);
 459                         break;
 460                 case AMDGPU_HPD_5:
 461                         WREG32(mmDC_HPD5_CONTROL, 0);
 462                         break;
 463                 case AMDGPU_HPD_6:
 464                         WREG32(mmDC_HPD6_CONTROL, 0);
 465                         break;
 466                 default:
 467                         break;
 468                 }
 469                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 470         }
 471 }
 472
 473 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
 474 {
 475         return mmDC_GPIO_HPD_A;
 476 }
 477
 478 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev)
 479 {
 480         u32 crtc_hung = 0;
 481         u32 crtc_status[6];
 482         u32 i, j, tmp;
 483
 484         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 485                 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
 486                         crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 487                         crtc_hung |= (1 << i);
 488                 }
 489         }
 490
 491         for (j = 0; j < 10; j++) {
 492                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
 493                         if (crtc_hung & (1 << i)) {
 494                                 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
 495                                 if (tmp != crtc_status[i])
 496                                         crtc_hung &= ~(1 << i);
 497                         }
 498                 }
 499                 if (crtc_hung == 0)
 500                         return false;
 501                 udelay(100);
 502         }
 503
 504         return true;
 505 }
 506
 507 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev,
 508                                     struct amdgpu_mode_mc_save *save)
 509 {
 510         u32 crtc_enabled, tmp;
 511         int i;
 512
 513         save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 514         save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
 515
 516         /* disable VGA render */
 517         tmp = RREG32(mmVGA_RENDER_CONTROL);
 518         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 519         WREG32(mmVGA_RENDER_CONTROL, tmp);
 520
 521         /* blank the display controllers */
 522         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 523                 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
 524                                              CRTC_CONTROL, CRTC_MASTER_EN);
 525                 if (crtc_enabled) {
 526 #if 0
 527                         u32 frame_count;
 528                         int j;
 529
 530                         save->crtc_enabled[i] = true;
 531                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 532                         if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
 533                                 amdgpu_display_vblank_wait(adev, i);
 534                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 535                                 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
 536                                 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 537                                 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 538                         }
 539                         /* wait for the next frame */
 540                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 541                         for (j = 0; j < adev->usec_timeout; j++) {
 542                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 543                                         break;
 544                                 udelay(1);
 545                         }
 546                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 547                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
 548                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
 549                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 550                         }
 551                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 552                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
 553                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
 554                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 555                         }
 556 #else
 557                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 558                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 559                         tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
 560                         tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
 561                         WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
 562                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 563                         save->crtc_enabled[i] = false;
 564                         /* ***** */
 565 #endif
 566                 } else {
 567                         save->crtc_enabled[i] = false;
 568                 }
 569         }
 570 }
 571
 572 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev,
 573                                       struct amdgpu_mode_mc_save *save)
 574 {
 575         u32 tmp, frame_count;
 576         int i, j;
 577
 578         /* update crtc base addresses */
 579         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 580                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 581                        upper_32_bits(adev->mc.vram_start));
 582                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
 583                        upper_32_bits(adev->mc.vram_start));
 584                 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 585                        (u32)adev->mc.vram_start);
 586                 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 587                        (u32)adev->mc.vram_start);
 588
 589                 if (save->crtc_enabled[i]) {
 590                         tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
 591                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) {
 592                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3);
 593                                 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 594                         }
 595                         tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 596                         if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
 597                                 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
 598                                 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
 599                         }
 600                         tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
 601                         if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
 602                                 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
 603                                 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 604                         }
 605                         for (j = 0; j < adev->usec_timeout; j++) {
 606                                 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
 607                                 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
 608                                         break;
 609                                 udelay(1);
 610                         }
 611                         tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
 612                         tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
 613                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 614                         WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
 615                         WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 616                         /* wait for the next frame */
 617                         frame_count = amdgpu_display_vblank_get_counter(adev, i);
 618                         for (j = 0; j < adev->usec_timeout; j++) {
 619                                 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
 620                                         break;
 621                                 udelay(1);
 622                         }
 623                 }
 624         }
 625
 626         WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
 627         WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
 628
 629         /* Unlock vga access */
 630         WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
 631         mdelay(1);
 632         WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
 633 }
 634
 635 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev,
 636                                           bool render)
 637 {
 638         u32 tmp;
 639
 640         /* Lockout access through VGA aperture*/
 641         tmp = RREG32(mmVGA_HDP_CONTROL);
 642         if (render)
 643                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
 644         else
 645                 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
 646         WREG32(mmVGA_HDP_CONTROL, tmp);
 647
 648         /* disable VGA render */
 649         tmp = RREG32(mmVGA_RENDER_CONTROL);
 650         if (render)
 651                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
 652         else
 653                 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
 654         WREG32(mmVGA_RENDER_CONTROL, tmp);
 655 }
 656
 657 static void dce_v8_0_program_fmt(struct drm_encoder *encoder)
 658 {
 659         struct drm_device *dev = encoder->dev;
 660         struct amdgpu_device *adev = dev->dev_private;
 661         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 662         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
 663         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
 664         int bpc = 0;
 665         u32 tmp = 0;
 666         enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
 667
 668         if (connector) {
 669                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 670                 bpc = amdgpu_connector_get_monitor_bpc(connector);
 671                 dither = amdgpu_connector->dither;
 672         }
 673
 674         /* LVDS/eDP FMT is set up by atom */
 675         if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 676                 return;
 677
 678         /* not needed for analog */
 679         if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 680             (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 681                 return;
 682
 683         if (bpc == 0)
 684                 return;
 685
 686         switch (bpc) {
 687         case 6:
 688                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 689                         /* XXX sort out optimal dither settings */
 690                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 691                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 692                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 693                                 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 694                 else
 695                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 696                         (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 697                 break;
 698         case 8:
 699                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 700                         /* XXX sort out optimal dither settings */
 701                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 702                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 703                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 704                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 705                                 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 706                 else
 707                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 708                         (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 709                 break;
 710         case 10:
 711                 if (dither == AMDGPU_FMT_DITHER_ENABLE)
 712                         /* XXX sort out optimal dither settings */
 713                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
 714                                 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
 715                                 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
 716                                 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
 717                                 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT));
 718                 else
 719                         tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
 720                         (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT));
 721                 break;
 722         default:
 723                 /* not needed */
 724                 break;
 725         }
 726
 727         WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 728 }
 729
 730
 731 /* display watermark setup */
 732 /**
 733  * dce_v8_0_line_buffer_adjust - Set up the line buffer
 734  *
 735  * @adev: amdgpu_device pointer
 736  * @amdgpu_crtc: the selected display controller
 737  * @mode: the current display mode on the selected display
 738  * controller
 739  *
 740  * Setup up the line buffer allocation for
 741  * the selected display controller (CIK).
 742  * Returns the line buffer size in pixels.
 743  */
 744 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
 745                                        struct amdgpu_crtc *amdgpu_crtc,
 746                                        struct drm_display_mode *mode)
 747 {
 748         u32 tmp, buffer_alloc, i;
 749         u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
 750         /*
 751          * Line Buffer Setup
 752          * There are 6 line buffers, one for each display controllers.
 753          * There are 3 partitions per LB. Select the number of partitions
 754          * to enable based on the display width.  For display widths larger
 755          * than 4096, you need use to use 2 display controllers and combine
 756          * them using the stereo blender.
 757          */
 758         if (amdgpu_crtc->base.enabled && mode) {
 759                 if (mode->crtc_hdisplay < 1920) {
 760                         tmp = 1;
 761                         buffer_alloc = 2;
 762                 } else if (mode->crtc_hdisplay < 2560) {
 763                         tmp = 2;
 764                         buffer_alloc = 2;
 765                 } else if (mode->crtc_hdisplay < 4096) {
 766                         tmp = 0;
 767                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 768                 } else {
 769                         DRM_DEBUG_KMS("Mode too big for LB!\n");
 770                         tmp = 0;
 771                         buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
 772                 }
 773         } else {
 774                 tmp = 1;
 775                 buffer_alloc = 0;
 776         }
 777
 778         WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,
 779               (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) |
 780               (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT));
 781
 782         WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
 783                (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
 784         for (i = 0; i < adev->usec_timeout; i++) {
 785                 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
 786                     PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
 787                         break;
 788                 udelay(1);
 789         }
 790
 791         if (amdgpu_crtc->base.enabled && mode) {
 792                 switch (tmp) {
 793                 case 0:
 794                 default:
 795                         return 4096 * 2;
 796                 case 1:
 797                         return 1920 * 2;
 798                 case 2:
 799                         return 2560 * 2;
 800                 }
 801         }
 802
 803         /* controller not enabled, so no lb used */
 804         return 0;
 805 }
 806
 807 /**
 808  * cik_get_number_of_dram_channels - get the number of dram channels
 809  *
 810  * @adev: amdgpu_device pointer
 811  *
 812  * Look up the number of video ram channels (CIK).
 813  * Used for display watermark bandwidth calculations
 814  * Returns the number of dram channels
 815  */
 816 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
 817 {
 818         u32 tmp = RREG32(mmMC_SHARED_CHMAP);
 819
 820         switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
 821         case 0:
 822         default:
 823                 return 1;
 824         case 1:
 825                 return 2;
 826         case 2:
 827                 return 4;
 828         case 3:
 829                 return 8;
 830         case 4:
 831                 return 3;
 832         case 5:
 833                 return 6;
 834         case 6:
 835                 return 10;
 836         case 7:
 837                 return 12;
 838         case 8:
 839                 return 16;
 840         }
 841 }
 842
 843 struct dce8_wm_params {
 844         u32 dram_channels; /* number of dram channels */
 845         u32 yclk;          /* bandwidth per dram data pin in kHz */
 846         u32 sclk;          /* engine clock in kHz */
 847         u32 disp_clk;      /* display clock in kHz */
 848         u32 src_width;     /* viewport width */
 849         u32 active_time;   /* active display time in ns */
 850         u32 blank_time;    /* blank time in ns */
 851         bool interlaced;    /* mode is interlaced */
 852         fixed20_12 vsc;    /* vertical scale ratio */
 853         u32 num_heads;     /* number of active crtcs */
 854         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 855         u32 lb_size;       /* line buffer allocated to pipe */
 856         u32 vtaps;         /* vertical scaler taps */
 857 };
 858
 859 /**
 860  * dce_v8_0_dram_bandwidth - get the dram bandwidth
 861  *
 862  * @wm: watermark calculation data
 863  *
 864  * Calculate the raw dram bandwidth (CIK).
 865  * Used for display watermark bandwidth calculations
 866  * Returns the dram bandwidth in MBytes/s
 867  */
 868 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm)
 869 {
 870         /* Calculate raw DRAM Bandwidth */
 871         fixed20_12 dram_efficiency; /* 0.7 */
 872         fixed20_12 yclk, dram_channels, bandwidth;
 873         fixed20_12 a;
 874
 875         a.full = dfixed_const(1000);
 876         yclk.full = dfixed_const(wm->yclk);
 877         yclk.full = dfixed_div(yclk, a);
 878         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 879         a.full = dfixed_const(10);
 880         dram_efficiency.full = dfixed_const(7);
 881         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 882         bandwidth.full = dfixed_mul(dram_channels, yclk);
 883         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 884
 885         return dfixed_trunc(bandwidth);
 886 }
 887
 888 /**
 889  * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
 890  *
 891  * @wm: watermark calculation data
 892  *
 893  * Calculate the dram bandwidth used for display (CIK).
 894  * Used for display watermark bandwidth calculations
 895  * Returns the dram bandwidth for display in MBytes/s
 896  */
 897 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm)
 898 {
 899         /* Calculate DRAM Bandwidth and the part allocated to display. */
 900         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 901         fixed20_12 yclk, dram_channels, bandwidth;
 902         fixed20_12 a;
 903
 904         a.full = dfixed_const(1000);
 905         yclk.full = dfixed_const(wm->yclk);
 906         yclk.full = dfixed_div(yclk, a);
 907         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 908         a.full = dfixed_const(10);
 909         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 910         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 911         bandwidth.full = dfixed_mul(dram_channels, yclk);
 912         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 913
 914         return dfixed_trunc(bandwidth);
 915 }
 916
 917 /**
 918  * dce_v8_0_data_return_bandwidth - get the data return bandwidth
 919  *
 920  * @wm: watermark calculation data
 921  *
 922  * Calculate the data return bandwidth used for display (CIK).
 923  * Used for display watermark bandwidth calculations
 924  * Returns the data return bandwidth in MBytes/s
 925  */
 926 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm)
 927 {
 928         /* Calculate the display Data return Bandwidth */
 929         fixed20_12 return_efficiency; /* 0.8 */
 930         fixed20_12 sclk, bandwidth;
 931         fixed20_12 a;
 932
 933         a.full = dfixed_const(1000);
 934         sclk.full = dfixed_const(wm->sclk);
 935         sclk.full = dfixed_div(sclk, a);
 936         a.full = dfixed_const(10);
 937         return_efficiency.full = dfixed_const(8);
 938         return_efficiency.full = dfixed_div(return_efficiency, a);
 939         a.full = dfixed_const(32);
 940         bandwidth.full = dfixed_mul(a, sclk);
 941         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 942
 943         return dfixed_trunc(bandwidth);
 944 }
 945
 946 /**
 947  * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
 948  *
 949  * @wm: watermark calculation data
 950  *
 951  * Calculate the dmif bandwidth used for display (CIK).
 952  * Used for display watermark bandwidth calculations
 953  * Returns the dmif bandwidth in MBytes/s
 954  */
 955 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm)
 956 {
 957         /* Calculate the DMIF Request Bandwidth */
 958         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 959         fixed20_12 disp_clk, bandwidth;
 960         fixed20_12 a, b;
 961
 962         a.full = dfixed_const(1000);
 963         disp_clk.full = dfixed_const(wm->disp_clk);
 964         disp_clk.full = dfixed_div(disp_clk, a);
 965         a.full = dfixed_const(32);
 966         b.full = dfixed_mul(a, disp_clk);
 967
 968         a.full = dfixed_const(10);
 969         disp_clk_request_efficiency.full = dfixed_const(8);
 970         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 971
 972         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
 973
 974         return dfixed_trunc(bandwidth);
 975 }
 976
 977 /**
 978  * dce_v8_0_available_bandwidth - get the min available bandwidth
 979  *
 980  * @wm: watermark calculation data
 981  *
 982  * Calculate the min available bandwidth used for display (CIK).
 983  * Used for display watermark bandwidth calculations
 984  * Returns the min available bandwidth in MBytes/s
 985  */
 986 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm)
 987 {
 988         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 989         u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm);
 990         u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm);
 991         u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm);
 992
 993         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 994 }
 995
 996 /**
 997  * dce_v8_0_average_bandwidth - get the average available bandwidth
 998  *
 999  * @wm: watermark calculation data
1000  *
1001  * Calculate the average available bandwidth used for display (CIK).
1002  * Used for display watermark bandwidth calculations
1003  * Returns the average available bandwidth in MBytes/s
1004  */
1005 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm)
1006 {
1007         /* Calculate the display mode Average Bandwidth
1008          * DisplayMode should contain the source and destination dimensions,
1009          * timing, etc.
1010          */
1011         fixed20_12 bpp;
1012         fixed20_12 line_time;
1013         fixed20_12 src_width;
1014         fixed20_12 bandwidth;
1015         fixed20_12 a;
1016
1017         a.full = dfixed_const(1000);
1018         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1019         line_time.full = dfixed_div(line_time, a);
1020         bpp.full = dfixed_const(wm->bytes_per_pixel);
1021         src_width.full = dfixed_const(wm->src_width);
1022         bandwidth.full = dfixed_mul(src_width, bpp);
1023         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1024         bandwidth.full = dfixed_div(bandwidth, line_time);
1025
1026         return dfixed_trunc(bandwidth);
1027 }
1028
1029 /**
1030  * dce_v8_0_latency_watermark - get the latency watermark
1031  *
1032  * @wm: watermark calculation data
1033  *
1034  * Calculate the latency watermark (CIK).
1035  * Used for display watermark bandwidth calculations
1036  * Returns the latency watermark in ns
1037  */
1038 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm)
1039 {
1040         /* First calculate the latency in ns */
1041         u32 mc_latency = 2000; /* 2000 ns. */
1042         u32 available_bandwidth = dce_v8_0_available_bandwidth(wm);
1043         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1044         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1045         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1046         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1047                 (wm->num_heads * cursor_line_pair_return_time);
1048         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1049         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1050         u32 tmp, dmif_size = 12288;
1051         fixed20_12 a, b, c;
1052
1053         if (wm->num_heads == 0)
1054                 return 0;
1055
1056         a.full = dfixed_const(2);
1057         b.full = dfixed_const(1);
1058         if ((wm->vsc.full > a.full) ||
1059             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1060             (wm->vtaps >= 5) ||
1061             ((wm->vsc.full >= a.full) && wm->interlaced))
1062                 max_src_lines_per_dst_line = 4;
1063         else
1064                 max_src_lines_per_dst_line = 2;
1065
1066         a.full = dfixed_const(available_bandwidth);
1067         b.full = dfixed_const(wm->num_heads);
1068         a.full = dfixed_div(a, b);
1069
1070         b.full = dfixed_const(mc_latency + 512);
1071         c.full = dfixed_const(wm->disp_clk);
1072         b.full = dfixed_div(b, c);
1073
1074         c.full = dfixed_const(dmif_size);
1075         b.full = dfixed_div(c, b);
1076
1077         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
1078
1079         b.full = dfixed_const(1000);
1080         c.full = dfixed_const(wm->disp_clk);
1081         b.full = dfixed_div(c, b);
1082         c.full = dfixed_const(wm->bytes_per_pixel);
1083         b.full = dfixed_mul(b, c);
1084
1085         lb_fill_bw = min(tmp, dfixed_trunc(b));
1086
1087         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1088         b.full = dfixed_const(1000);
1089         c.full = dfixed_const(lb_fill_bw);
1090         b.full = dfixed_div(c, b);
1091         a.full = dfixed_div(a, b);
1092         line_fill_time = dfixed_trunc(a);
1093
1094         if (line_fill_time < wm->active_time)
1095                 return latency;
1096         else
1097                 return latency + (line_fill_time - wm->active_time);
1098
1099 }
1100
1101 /**
1102  * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1103  * average and available dram bandwidth
1104  *
1105  * @wm: watermark calculation data
1106  *
1107  * Check if the display average bandwidth fits in the display
1108  * dram bandwidth (CIK).
1109  * Used for display watermark bandwidth calculations
1110  * Returns true if the display fits, false if not.
1111  */
1112 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
1113 {
1114         if (dce_v8_0_average_bandwidth(wm) <=
1115             (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads))
1116                 return true;
1117         else
1118                 return false;
1119 }
1120
1121 /**
1122  * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1123  * average and available bandwidth
1124  *
1125  * @wm: watermark calculation data
1126  *
1127  * Check if the display average bandwidth fits in the display
1128  * available bandwidth (CIK).
1129  * Used for display watermark bandwidth calculations
1130  * Returns true if the display fits, false if not.
1131  */
1132 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
1133 {
1134         if (dce_v8_0_average_bandwidth(wm) <=
1135             (dce_v8_0_available_bandwidth(wm) / wm->num_heads))
1136                 return true;
1137         else
1138                 return false;
1139 }
1140
1141 /**
1142  * dce_v8_0_check_latency_hiding - check latency hiding
1143  *
1144  * @wm: watermark calculation data
1145  *
1146  * Check latency hiding (CIK).
1147  * Used for display watermark bandwidth calculations
1148  * Returns true if the display fits, false if not.
1149  */
1150 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm)
1151 {
1152         u32 lb_partitions = wm->lb_size / wm->src_width;
1153         u32 line_time = wm->active_time + wm->blank_time;
1154         u32 latency_tolerant_lines;
1155         u32 latency_hiding;
1156         fixed20_12 a;
1157
1158         a.full = dfixed_const(1);
1159         if (wm->vsc.full > a.full)
1160                 latency_tolerant_lines = 1;
1161         else {
1162                 if (lb_partitions <= (wm->vtaps + 1))
1163                         latency_tolerant_lines = 1;
1164                 else
1165                         latency_tolerant_lines = 2;
1166         }
1167
1168         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1169
1170         if (dce_v8_0_latency_watermark(wm) <= latency_hiding)
1171                 return true;
1172         else
1173                 return false;
1174 }
1175
1176 /**
1177  * dce_v8_0_program_watermarks - program display watermarks
1178  *
1179  * @adev: amdgpu_device pointer
1180  * @amdgpu_crtc: the selected display controller
1181  * @lb_size: line buffer size
1182  * @num_heads: number of display controllers in use
1183  *
1184  * Calculate and program the display watermarks for the
1185  * selected display controller (CIK).
1186  */
1187 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev,
1188                                         struct amdgpu_crtc *amdgpu_crtc,
1189                                         u32 lb_size, u32 num_heads)
1190 {
1191         struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1192         struct dce8_wm_params wm_low, wm_high;
1193         u32 pixel_period;
1194         u32 line_time = 0;
1195         u32 latency_watermark_a = 0, latency_watermark_b = 0;
1196         u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1197
1198         if (amdgpu_crtc->base.enabled && num_heads && mode) {
1199                 pixel_period = 1000000 / (u32)mode->clock;
1200                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1201
1202                 /* watermark for high clocks */
1203                 if (adev->pm.dpm_enabled) {
1204                         wm_high.yclk =
1205                                 amdgpu_dpm_get_mclk(adev, false) * 10;
1206                         wm_high.sclk =
1207                                 amdgpu_dpm_get_sclk(adev, false) * 10;
1208                 } else {
1209                         wm_high.yclk = adev->pm.current_mclk * 10;
1210                         wm_high.sclk = adev->pm.current_sclk * 10;
1211                 }
1212
1213                 wm_high.disp_clk = mode->clock;
1214                 wm_high.src_width = mode->crtc_hdisplay;
1215                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1216                 wm_high.blank_time = line_time - wm_high.active_time;
1217                 wm_high.interlaced = false;
1218                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1219                         wm_high.interlaced = true;
1220                 wm_high.vsc = amdgpu_crtc->vsc;
1221                 wm_high.vtaps = 1;
1222                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1223                         wm_high.vtaps = 2;
1224                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1225                 wm_high.lb_size = lb_size;
1226                 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1227                 wm_high.num_heads = num_heads;
1228
1229                 /* set for high clocks */
1230                 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535);
1231
1232                 /* possibly force display priority to high */
1233                 /* should really do this at mode validation time... */
1234                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1235                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1236                     !dce_v8_0_check_latency_hiding(&wm_high) ||
1237                     (adev->mode_info.disp_priority == 2)) {
1238                         DRM_DEBUG_KMS("force priority to high\n");
1239                 }
1240
1241                 /* watermark for low clocks */
1242                 if (adev->pm.dpm_enabled) {
1243                         wm_low.yclk =
1244                                 amdgpu_dpm_get_mclk(adev, true) * 10;
1245                         wm_low.sclk =
1246                                 amdgpu_dpm_get_sclk(adev, true) * 10;
1247                 } else {
1248                         wm_low.yclk = adev->pm.current_mclk * 10;
1249                         wm_low.sclk = adev->pm.current_sclk * 10;
1250                 }
1251
1252                 wm_low.disp_clk = mode->clock;
1253                 wm_low.src_width = mode->crtc_hdisplay;
1254                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1255                 wm_low.blank_time = line_time - wm_low.active_time;
1256                 wm_low.interlaced = false;
1257                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1258                         wm_low.interlaced = true;
1259                 wm_low.vsc = amdgpu_crtc->vsc;
1260                 wm_low.vtaps = 1;
1261                 if (amdgpu_crtc->rmx_type != RMX_OFF)
1262                         wm_low.vtaps = 2;
1263                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1264                 wm_low.lb_size = lb_size;
1265                 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1266                 wm_low.num_heads = num_heads;
1267
1268                 /* set for low clocks */
1269                 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535);
1270
1271                 /* possibly force display priority to high */
1272                 /* should really do this at mode validation time... */
1273                 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1274                     !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1275                     !dce_v8_0_check_latency_hiding(&wm_low) ||
1276                     (adev->mode_info.disp_priority == 2)) {
1277                         DRM_DEBUG_KMS("force priority to high\n");
1278                 }
1279                 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1280         }
1281
1282         /* select wm A */
1283         wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1284         tmp = wm_mask;
1285         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1286         tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1287         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1288         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1289                ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1290                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1291         /* select wm B */
1292         tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1293         tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1294         tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT);
1295         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1296         WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1297                ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1298                 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1299         /* restore original selection */
1300         WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1301
1302         /* save values for DPM */
1303         amdgpu_crtc->line_time = line_time;
1304         amdgpu_crtc->wm_high = latency_watermark_a;
1305         amdgpu_crtc->wm_low = latency_watermark_b;
1306         /* Save number of lines the linebuffer leads before the scanout */
1307         amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1308 }
1309
1310 /**
1311  * dce_v8_0_bandwidth_update - program display watermarks
1312  *
1313  * @adev: amdgpu_device pointer
1314  *
1315  * Calculate and program the display watermarks and line
1316  * buffer allocation (CIK).
1317  */
1318 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev)
1319 {
1320         struct drm_display_mode *mode = NULL;
1321         u32 num_heads = 0, lb_size;
1322         int i;
1323
1324         amdgpu_update_display_priority(adev);
1325
1326         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1327                 if (adev->mode_info.crtcs[i]->base.enabled)
1328                         num_heads++;
1329         }
1330         for (i = 0; i < adev->mode_info.num_crtc; i++) {
1331                 mode = &adev->mode_info.crtcs[i]->base.mode;
1332                 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1333                 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1334                                             lb_size, num_heads);
1335         }
1336 }
1337
1338 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev)
1339 {
1340         int i;
1341         u32 offset, tmp;
1342
1343         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1344                 offset = adev->mode_info.audio.pin[i].offset;
1345                 tmp = RREG32_AUDIO_ENDPT(offset,
1346                                          ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1347                 if (((tmp &
1348                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1349                 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1350                         adev->mode_info.audio.pin[i].connected = false;
1351                 else
1352                         adev->mode_info.audio.pin[i].connected = true;
1353         }
1354 }
1355
1356 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev)
1357 {
1358         int i;
1359
1360         dce_v8_0_audio_get_connected_pins(adev);
1361
1362         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1363                 if (adev->mode_info.audio.pin[i].connected)
1364                         return &adev->mode_info.audio.pin[i];
1365         }
1366         DRM_ERROR("No connected audio pins found!\n");
1367         return NULL;
1368 }
1369
1370 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1371 {
1372         struct amdgpu_device *adev = encoder->dev->dev_private;
1373         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1374         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1375         u32 offset;
1376
1377         if (!dig || !dig->afmt || !dig->afmt->pin)
1378                 return;
1379
1380         offset = dig->afmt->offset;
1381
1382         WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,
1383                (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT));
1384 }
1385
1386 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder,
1387                                                 struct drm_display_mode *mode)
1388 {
1389         struct amdgpu_device *adev = encoder->dev->dev_private;
1390         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1391         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1392         struct drm_connector *connector;
1393         struct amdgpu_connector *amdgpu_connector = NULL;
1394         u32 tmp = 0, offset;
1395
1396         if (!dig || !dig->afmt || !dig->afmt->pin)
1397                 return;
1398
1399         offset = dig->afmt->pin->offset;
1400
1401         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1402                 if (connector->encoder == encoder) {
1403                         amdgpu_connector = to_amdgpu_connector(connector);
1404                         break;
1405                 }
1406         }
1407
1408         if (!amdgpu_connector) {
1409                 DRM_ERROR("Couldn't find encoder's connector\n");
1410                 return;
1411         }
1412
1413         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1414                 if (connector->latency_present[1])
1415                         tmp =
1416                         (connector->video_latency[1] <<
1417                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1418                         (connector->audio_latency[1] <<
1419                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1420                 else
1421                         tmp =
1422                         (0 <<
1423                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1424                         (0 <<
1425                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1426         } else {
1427                 if (connector->latency_present[0])
1428                         tmp =
1429                         (connector->video_latency[0] <<
1430                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1431                         (connector->audio_latency[0] <<
1432                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1433                 else
1434                         tmp =
1435                         (0 <<
1436                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) |
1437                         (0 <<
1438                          AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT);
1439
1440         }
1441         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1442 }
1443
1444 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1445 {
1446         struct amdgpu_device *adev = encoder->dev->dev_private;
1447         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1448         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1449         struct drm_connector *connector;
1450         struct amdgpu_connector *amdgpu_connector = NULL;
1451         u32 offset, tmp;
1452         u8 *sadb = NULL;
1453         int sad_count;
1454
1455         if (!dig || !dig->afmt || !dig->afmt->pin)
1456                 return;
1457
1458         offset = dig->afmt->pin->offset;
1459
1460         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1461                 if (connector->encoder == encoder) {
1462                         amdgpu_connector = to_amdgpu_connector(connector);
1463                         break;
1464                 }
1465         }
1466
1467         if (!amdgpu_connector) {
1468                 DRM_ERROR("Couldn't find encoder's connector\n");
1469                 return;
1470         }
1471
1472         sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1473         if (sad_count < 0) {
1474                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1475                 sad_count = 0;
1476         }
1477
1478         /* program the speaker allocation */
1479         tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1480         tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK |
1481                 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK);
1482         /* set HDMI mode */
1483         tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK;
1484         if (sad_count)
1485                 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT);
1486         else
1487                 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */
1488         WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1489
1490         kfree(sadb);
1491 }
1492
1493 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder)
1494 {
1495         struct amdgpu_device *adev = encoder->dev->dev_private;
1496         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1497         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1498         u32 offset;
1499         struct drm_connector *connector;
1500         struct amdgpu_connector *amdgpu_connector = NULL;
1501         struct cea_sad *sads;
1502         int i, sad_count;
1503
1504         static const u16 eld_reg_to_type[][2] = {
1505                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1506                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1507                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1508                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1509                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1510                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1511                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1512                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1513                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1514                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1515                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1516                 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1517         };
1518
1519         if (!dig || !dig->afmt || !dig->afmt->pin)
1520                 return;
1521
1522         offset = dig->afmt->pin->offset;
1523
1524         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1525                 if (connector->encoder == encoder) {
1526                         amdgpu_connector = to_amdgpu_connector(connector);
1527                         break;
1528                 }
1529         }
1530
1531         if (!amdgpu_connector) {
1532                 DRM_ERROR("Couldn't find encoder's connector\n");
1533                 return;
1534         }
1535
1536         sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1537         if (sad_count <= 0) {
1538                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1539                 return;
1540         }
1541         BUG_ON(!sads);
1542
1543         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1544                 u32 value = 0;
1545                 u8 stereo_freqs = 0;
1546                 int max_channels = -1;
1547                 int j;
1548
1549                 for (j = 0; j < sad_count; j++) {
1550                         struct cea_sad *sad = &sads[j];
1551
1552                         if (sad->format == eld_reg_to_type[i][1]) {
1553                                 if (sad->channels > max_channels) {
1554                                 value = (sad->channels <<
1555                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) |
1556                                 (sad->byte2 <<
1557                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) |
1558                                 (sad->freq <<
1559                                  AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT);
1560                                 max_channels = sad->channels;
1561                                 }
1562
1563                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1564                                         stereo_freqs |= sad->freq;
1565                                 else
1566                                         break;
1567                         }
1568                 }
1569
1570                 value |= (stereo_freqs <<
1571                         AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT);
1572
1573                 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value);
1574         }
1575
1576         kfree(sads);
1577 }
1578
1579 static void dce_v8_0_audio_enable(struct amdgpu_device *adev,
1580                                   struct amdgpu_audio_pin *pin,
1581                                   bool enable)
1582 {
1583         if (!pin)
1584                 return;
1585
1586         WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1587                 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1588 }
1589
1590 static const u32 pin_offsets[7] =
1591 {
1592         (0x1780 - 0x1780),
1593         (0x1786 - 0x1780),
1594         (0x178c - 0x1780),
1595         (0x1792 - 0x1780),
1596         (0x1798 - 0x1780),
1597         (0x179d - 0x1780),
1598         (0x17a4 - 0x1780),
1599 };
1600
1601 static int dce_v8_0_audio_init(struct amdgpu_device *adev)
1602 {
1603         int i;
1604
1605         if (!amdgpu_audio)
1606                 return 0;
1607
1608         adev->mode_info.audio.enabled = true;
1609
1610         if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */
1611                 adev->mode_info.audio.num_pins = 7;
1612         else if ((adev->asic_type == CHIP_KABINI) ||
1613                  (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */
1614                 adev->mode_info.audio.num_pins = 3;
1615         else if ((adev->asic_type == CHIP_BONAIRE) ||
1616                  (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */
1617                 adev->mode_info.audio.num_pins = 7;
1618         else
1619                 adev->mode_info.audio.num_pins = 3;
1620
1621         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1622                 adev->mode_info.audio.pin[i].channels = -1;
1623                 adev->mode_info.audio.pin[i].rate = -1;
1624                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1625                 adev->mode_info.audio.pin[i].status_bits = 0;
1626                 adev->mode_info.audio.pin[i].category_code = 0;
1627                 adev->mode_info.audio.pin[i].connected = false;
1628                 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1629                 adev->mode_info.audio.pin[i].id = i;
1630                 /* disable audio.  it will be set up later */
1631                 /* XXX remove once we switch to ip funcs */
1632                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1633         }
1634
1635         return 0;
1636 }
1637
1638 static void dce_v8_0_audio_fini(struct amdgpu_device *adev)
1639 {
1640         int i;
1641
1642         if (!adev->mode_info.audio.enabled)
1643                 return;
1644
1645         for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1646                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1647
1648         adev->mode_info.audio.enabled = false;
1649 }
1650
1651 /*
1652  * update the N and CTS parameters for a given pixel clock rate
1653  */
1654 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1655 {
1656         struct drm_device *dev = encoder->dev;
1657         struct amdgpu_device *adev = dev->dev_private;
1658         struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1659         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1660         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1661         uint32_t offset = dig->afmt->offset;
1662
1663         WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1664         WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
1665
1666         WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
1667         WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);
1668
1669         WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));
1670         WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);
1671 }
1672
1673 /*
1674  * build a HDMI Video Info Frame
1675  */
1676 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1677                                                void *buffer, size_t size)
1678 {
1679         struct drm_device *dev = encoder->dev;
1680         struct amdgpu_device *adev = dev->dev_private;
1681         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1682         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1683         uint32_t offset = dig->afmt->offset;
1684         uint8_t *frame = buffer + 3;
1685         uint8_t *header = buffer;
1686
1687         WREG32(mmAFMT_AVI_INFO0 + offset,
1688                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1689         WREG32(mmAFMT_AVI_INFO1 + offset,
1690                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1691         WREG32(mmAFMT_AVI_INFO2 + offset,
1692                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1693         WREG32(mmAFMT_AVI_INFO3 + offset,
1694                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1695 }
1696
1697 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1698 {
1699         struct drm_device *dev = encoder->dev;
1700         struct amdgpu_device *adev = dev->dev_private;
1701         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1702         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1703         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1704         u32 dto_phase = 24 * 1000;
1705         u32 dto_modulo = clock;
1706
1707         if (!dig || !dig->afmt)
1708                 return;
1709
1710         /* XXX two dtos; generally use dto0 for hdmi */
1711         /* Express [24MHz / target pixel clock] as an exact rational
1712          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1713          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1714          */
1715         WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));
1716         WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1717         WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1718 }
1719
1720 /*
1721  * update the info frames with the data from the current display mode
1722  */
1723 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder,
1724                                   struct drm_display_mode *mode)
1725 {
1726         struct drm_device *dev = encoder->dev;
1727         struct amdgpu_device *adev = dev->dev_private;
1728         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1729         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1730         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1731         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1732         struct hdmi_avi_infoframe frame;
1733         uint32_t offset, val;
1734         ssize_t err;
1735         int bpc = 8;
1736
1737         if (!dig || !dig->afmt)
1738                 return;
1739
1740         /* Silent, r600_hdmi_enable will raise WARN for us */
1741         if (!dig->afmt->enabled)
1742                 return;
1743         offset = dig->afmt->offset;
1744
1745         /* hdmi deep color mode general control packets setup, if bpc > 8 */
1746         if (encoder->crtc) {
1747                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1748                 bpc = amdgpu_crtc->bpc;
1749         }
1750
1751         /* disable audio prior to setting up hw */
1752         dig->afmt->pin = dce_v8_0_audio_get_pin(adev);
1753         dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1754
1755         dce_v8_0_audio_set_dto(encoder, mode->clock);
1756
1757         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1758                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */
1759
1760         WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
1761
1762         val = RREG32(mmHDMI_CONTROL + offset);
1763         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1764         val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK;
1765
1766         switch (bpc) {
1767         case 0:
1768         case 6:
1769         case 8:
1770         case 16:
1771         default:
1772                 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1773                           connector->name, bpc);
1774                 break;
1775         case 10:
1776                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1777                 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1778                 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1779                           connector->name);
1780                 break;
1781         case 12:
1782                 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK;
1783                 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT;
1784                 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1785                           connector->name);
1786                 break;
1787         }
1788
1789         WREG32(mmHDMI_CONTROL + offset, val);
1790
1791         WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,
1792                HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */
1793                HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */
1794                HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */
1795
1796         WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,
1797                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */
1798                HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */
1799
1800         WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,
1801                AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */
1802
1803         WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,
1804                (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */
1805
1806         WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
1807
1808         WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,
1809                (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */
1810                (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */
1811
1812         WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1813                AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */
1814
1815         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1816
1817         if (bpc > 8)
1818                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1819                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1820         else
1821                 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,
1822                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */
1823                        HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */
1824
1825         dce_v8_0_afmt_update_ACR(encoder, mode->clock);
1826
1827         WREG32(mmAFMT_60958_0 + offset,
1828                (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT));
1829
1830         WREG32(mmAFMT_60958_1 + offset,
1831                (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT));
1832
1833         WREG32(mmAFMT_60958_2 + offset,
1834                (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) |
1835                (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) |
1836                (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) |
1837                (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) |
1838                (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) |
1839                (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT));
1840
1841         dce_v8_0_audio_write_speaker_allocation(encoder);
1842
1843
1844         WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,
1845                (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1846
1847         dce_v8_0_afmt_audio_select_pin(encoder);
1848         dce_v8_0_audio_write_sad_regs(encoder);
1849         dce_v8_0_audio_write_latency_fields(encoder, mode);
1850
1851         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
1852         if (err < 0) {
1853                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1854                 return;
1855         }
1856
1857         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1858         if (err < 0) {
1859                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1860                 return;
1861         }
1862
1863         dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1864
1865         WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1866                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */
1867                   HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */
1868
1869         WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset,
1870                  (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */
1871                  ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK);
1872
1873         WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,
1874                   AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */
1875
1876         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1877         WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
1878         WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
1879         WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);
1880         WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);
1881
1882         /* enable audio after to setting up hw */
1883         dce_v8_0_audio_enable(adev, dig->afmt->pin, true);
1884 }
1885
1886 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1887 {
1888         struct drm_device *dev = encoder->dev;
1889         struct amdgpu_device *adev = dev->dev_private;
1890         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1891         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1892
1893         if (!dig || !dig->afmt)
1894                 return;
1895
1896         /* Silent, r600_hdmi_enable will raise WARN for us */
1897         if (enable && dig->afmt->enabled)
1898                 return;
1899         if (!enable && !dig->afmt->enabled)
1900                 return;
1901
1902         if (!enable && dig->afmt->pin) {
1903                 dce_v8_0_audio_enable(adev, dig->afmt->pin, false);
1904                 dig->afmt->pin = NULL;
1905         }
1906
1907         dig->afmt->enabled = enable;
1908
1909         DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1910                   enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1911 }
1912
1913 static void dce_v8_0_afmt_init(struct amdgpu_device *adev)
1914 {
1915         int i;
1916
1917         for (i = 0; i < adev->mode_info.num_dig; i++)
1918                 adev->mode_info.afmt[i] = NULL;
1919
1920         /* DCE8 has audio blocks tied to DIG encoders */
1921         for (i = 0; i < adev->mode_info.num_dig; i++) {
1922                 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1923                 if (adev->mode_info.afmt[i]) {
1924                         adev->mode_info.afmt[i]->offset = dig_offsets[i];
1925                         adev->mode_info.afmt[i]->id = i;
1926                 }
1927         }
1928 }
1929
1930 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev)
1931 {
1932         int i;
1933
1934         for (i = 0; i < adev->mode_info.num_dig; i++) {
1935                 kfree(adev->mode_info.afmt[i]);
1936                 adev->mode_info.afmt[i] = NULL;
1937         }
1938 }
1939
1940 static const u32 vga_control_regs[6] =
1941 {
1942         mmD1VGA_CONTROL,
1943         mmD2VGA_CONTROL,
1944         mmD3VGA_CONTROL,
1945         mmD4VGA_CONTROL,
1946         mmD5VGA_CONTROL,
1947         mmD6VGA_CONTROL,
1948 };
1949
1950 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable)
1951 {
1952         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1953         struct drm_device *dev = crtc->dev;
1954         struct amdgpu_device *adev = dev->dev_private;
1955         u32 vga_control;
1956
1957         vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1958         if (enable)
1959                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1960         else
1961                 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1962 }
1963
1964 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable)
1965 {
1966         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1967         struct drm_device *dev = crtc->dev;
1968         struct amdgpu_device *adev = dev->dev_private;
1969
1970         if (enable)
1971                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1972         else
1973                 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1974 }
1975
1976 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1977                                      struct drm_framebuffer *fb,
1978                                      int x, int y, int atomic)
1979 {
1980         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1981         struct drm_device *dev = crtc->dev;
1982         struct amdgpu_device *adev = dev->dev_private;
1983         struct amdgpu_framebuffer *amdgpu_fb;
1984         struct drm_framebuffer *target_fb;
1985         struct drm_gem_object *obj;
1986         struct amdgpu_bo *rbo;
1987         uint64_t fb_location, tiling_flags;
1988         uint32_t fb_format, fb_pitch_pixels;
1989         u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
1990         u32 pipe_config;
1991         u32 tmp, viewport_w, viewport_h;
1992         int r;
1993         bool bypass_lut = false;
1994
1995         /* no fb bound */
1996         if (!atomic && !crtc->primary->fb) {
1997                 DRM_DEBUG_KMS("No FB bound\n");
1998                 return 0;
1999         }
2000
2001         if (atomic) {
2002                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2003                 target_fb = fb;
2004         }
2005         else {
2006                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2007                 target_fb = crtc->primary->fb;
2008         }
2009
2010         /* If atomic, assume fb object is pinned & idle & fenced and
2011          * just update base pointers
2012          */
2013         obj = amdgpu_fb->obj;
2014         rbo = gem_to_amdgpu_bo(obj);
2015         r = amdgpu_bo_reserve(rbo, false);
2016         if (unlikely(r != 0))
2017                 return r;
2018
2019         if (atomic)
2020                 fb_location = amdgpu_bo_gpu_offset(rbo);
2021         else {
2022                 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
2023                 if (unlikely(r != 0)) {
2024                         amdgpu_bo_unreserve(rbo);
2025                         return -EINVAL;
2026                 }
2027         }
2028
2029         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
2030         amdgpu_bo_unreserve(rbo);
2031
2032         pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2033
2034         switch (target_fb->pixel_format) {
2035         case DRM_FORMAT_C8:
2036                 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2037                              (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2038                 break;
2039         case DRM_FORMAT_XRGB4444:
2040         case DRM_FORMAT_ARGB4444:
2041                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2042                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2043 #ifdef __BIG_ENDIAN
2044                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2045 #endif
2046                 break;
2047         case DRM_FORMAT_XRGB1555:
2048         case DRM_FORMAT_ARGB1555:
2049                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2050                              (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2051 #ifdef __BIG_ENDIAN
2052                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2053 #endif
2054                 break;
2055         case DRM_FORMAT_BGRX5551:
2056         case DRM_FORMAT_BGRA5551:
2057                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2058                              (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2059 #ifdef __BIG_ENDIAN
2060                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2061 #endif
2062                 break;
2063         case DRM_FORMAT_RGB565:
2064                 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2065                              (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2066 #ifdef __BIG_ENDIAN
2067                 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2068 #endif
2069                 break;
2070         case DRM_FORMAT_XRGB8888:
2071         case DRM_FORMAT_ARGB8888:
2072                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2073                              (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2074 #ifdef __BIG_ENDIAN
2075                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2076 #endif
2077                 break;
2078         case DRM_FORMAT_XRGB2101010:
2079         case DRM_FORMAT_ARGB2101010:
2080                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2081                              (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2082 #ifdef __BIG_ENDIAN
2083                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2084 #endif
2085                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2086                 bypass_lut = true;
2087                 break;
2088         case DRM_FORMAT_BGRX1010102:
2089         case DRM_FORMAT_BGRA1010102:
2090                 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
2091                              (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
2092 #ifdef __BIG_ENDIAN
2093                 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
2094 #endif
2095                 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2096                 bypass_lut = true;
2097                 break;
2098         default:
2099                 DRM_ERROR("Unsupported screen format %s\n",
2100                           drm_get_format_name(target_fb->pixel_format));
2101                 return -EINVAL;
2102         }
2103
2104         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2105                 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2106
2107                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2108                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2109                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2110                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2111                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2112
2113                 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);
2114                 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2115                 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);
2116                 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);
2117                 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);
2118                 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);
2119                 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT);
2120         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2121                 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);
2122         }
2123
2124         fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);
2125
2126         dce_v8_0_vga_enable(crtc, false);
2127
2128         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2129                upper_32_bits(fb_location));
2130         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2131                upper_32_bits(fb_location));
2132         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2133                (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2134         WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2135                (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2136         WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2137         WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2138
2139         /*
2140          * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2141          * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2142          * retain the full precision throughout the pipeline.
2143          */
2144         WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset,
2145                  (bypass_lut ? LUT_10BIT_BYPASS_EN : 0),
2146                  ~LUT_10BIT_BYPASS_EN);
2147
2148         if (bypass_lut)
2149                 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2150
2151         WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2152         WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2153         WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2154         WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2155         WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2156         WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2157
2158         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
2159         WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2160
2161         dce_v8_0_grph_enable(crtc, true);
2162
2163         WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2164                target_fb->height);
2165
2166         x &= ~3;
2167         y &= ~1;
2168         WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2169                (x << 16) | y);
2170         viewport_w = crtc->mode.hdisplay;
2171         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2172         WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2173                (viewport_w << 16) | viewport_h);
2174
2175         /* pageflip setup */
2176         /* make sure flip is at vb rather than hb */
2177         tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2178         tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK;
2179         WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2180
2181         /* set pageflip to happen only at start of vblank interval (front porch) */
2182         WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3);
2183
2184         if (!atomic && fb && fb != crtc->primary->fb) {
2185                 amdgpu_fb = to_amdgpu_framebuffer(fb);
2186                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2187                 r = amdgpu_bo_reserve(rbo, false);
2188                 if (unlikely(r != 0))
2189                         return r;
2190                 amdgpu_bo_unpin(rbo);
2191                 amdgpu_bo_unreserve(rbo);
2192         }
2193
2194         /* Bytes per pixel may have changed */
2195         dce_v8_0_bandwidth_update(adev);
2196
2197         return 0;
2198 }
2199
2200 static void dce_v8_0_set_interleave(struct drm_crtc *crtc,
2201                                     struct drm_display_mode *mode)
2202 {
2203         struct drm_device *dev = crtc->dev;
2204         struct amdgpu_device *adev = dev->dev_private;
2205         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2206
2207         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2208                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,
2209                        LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT);
2210         else
2211                 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2212 }
2213
2214 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc)
2215 {
2216         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2217         struct drm_device *dev = crtc->dev;
2218         struct amdgpu_device *adev = dev->dev_private;
2219         int i;
2220
2221         DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2222
2223         WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2224                ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2225                 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2226         WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2227                PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2228         WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2229                PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2230         WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2231                ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2232                 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2233
2234         WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2235
2236         WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2237         WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2238         WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2239
2240         WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2241         WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2242         WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2243
2244         WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2245         WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2246
2247         WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2248         for (i = 0; i < 256; i++) {
2249                 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2250                        (amdgpu_crtc->lut_r[i] << 20) |
2251                        (amdgpu_crtc->lut_g[i] << 10) |
2252                        (amdgpu_crtc->lut_b[i] << 0));
2253         }
2254
2255         WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2256                ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2257                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2258                 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2259         WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2260                ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2261                 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2262         WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2263                ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2264                 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2265         WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2266                ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2267                 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2268         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2269         WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2270         /* XXX this only needs to be programmed once per crtc at startup,
2271          * not sure where the best place for it is
2272          */
2273         WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,
2274                ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK);
2275 }
2276
2277 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder)
2278 {
2279         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2280         struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2281
2282         switch (amdgpu_encoder->encoder_id) {
2283         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2284                 if (dig->linkb)
2285                         return 1;
2286                 else
2287                         return 0;
2288                 break;
2289         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2290                 if (dig->linkb)
2291                         return 3;
2292                 else
2293                         return 2;
2294                 break;
2295         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2296                 if (dig->linkb)
2297                         return 5;
2298                 else
2299                         return 4;
2300                 break;
2301         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2302                 return 6;
2303                 break;
2304         default:
2305                 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2306                 return 0;
2307         }
2308 }
2309
2310 /**
2311  * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2312  *
2313  * @crtc: drm crtc
2314  *
2315  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2316  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2317  * monitors a dedicated PPLL must be used.  If a particular board has
2318  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2319  * as there is no need to program the PLL itself.  If we are not able to
2320  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2321  * avoid messing up an existing monitor.
2322  *
2323  * Asic specific PLL information
2324  *
2325  * DCE 8.x
2326  * KB/KV
2327  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2328  * CI
2329  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2330  *
2331  */
2332 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc)
2333 {
2334         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2335         struct drm_device *dev = crtc->dev;
2336         struct amdgpu_device *adev = dev->dev_private;
2337         u32 pll_in_use;
2338         int pll;
2339
2340         if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2341                 if (adev->clock.dp_extclk)
2342                         /* skip PPLL programming if using ext clock */
2343                         return ATOM_PPLL_INVALID;
2344                 else {
2345                         /* use the same PPLL for all DP monitors */
2346                         pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2347                         if (pll != ATOM_PPLL_INVALID)
2348                                 return pll;
2349                 }
2350         } else {
2351                 /* use the same PPLL for all monitors with the same clock */
2352                 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2353                 if (pll != ATOM_PPLL_INVALID)
2354                         return pll;
2355         }
2356         /* otherwise, pick one of the plls */
2357         if ((adev->asic_type == CHIP_KABINI) ||
2358             (adev->asic_type == CHIP_MULLINS)) {
2359                 /* KB/ML has PPLL1 and PPLL2 */
2360                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2361                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2362                         return ATOM_PPLL2;
2363                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2364                         return ATOM_PPLL1;
2365                 DRM_ERROR("unable to allocate a PPLL\n");
2366                 return ATOM_PPLL_INVALID;
2367         } else {
2368                 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2369                 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2370                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2371                         return ATOM_PPLL2;
2372                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2373                         return ATOM_PPLL1;
2374                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2375                         return ATOM_PPLL0;
2376                 DRM_ERROR("unable to allocate a PPLL\n");
2377                 return ATOM_PPLL_INVALID;
2378         }
2379         return ATOM_PPLL_INVALID;
2380 }
2381
2382 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2383 {
2384         struct amdgpu_device *adev = crtc->dev->dev_private;
2385         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2386         uint32_t cur_lock;
2387
2388         cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2389         if (lock)
2390                 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2391         else
2392                 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2393         WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2394 }
2395
2396 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc)
2397 {
2398         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2399         struct amdgpu_device *adev = crtc->dev->dev_private;
2400
2401         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2402                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2403                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2404 }
2405
2406 static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
2407 {
2408         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2409         struct amdgpu_device *adev = crtc->dev->dev_private;
2410
2411         WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2412                upper_32_bits(amdgpu_crtc->cursor_addr));
2413         WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2414                lower_32_bits(amdgpu_crtc->cursor_addr));
2415
2416         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2417                    CUR_CONTROL__CURSOR_EN_MASK |
2418                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2419                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2420 }
2421
2422 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2423                                        int x, int y)
2424 {
2425         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2426         struct amdgpu_device *adev = crtc->dev->dev_private;
2427         int xorigin = 0, yorigin = 0;
2428
2429         /* avivo cursor are offset into the total surface */
2430         x += crtc->x;
2431         y += crtc->y;
2432         DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2433
2434         if (x < 0) {
2435                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2436                 x = 0;
2437         }
2438         if (y < 0) {
2439                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2440                 y = 0;
2441         }
2442
2443         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2444         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2445         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2446                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2447
2448         amdgpu_crtc->cursor_x = x;
2449         amdgpu_crtc->cursor_y = y;
2450
2451         return 0;
2452 }
2453
2454 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
2455                                      int x, int y)
2456 {
2457         int ret;
2458
2459         dce_v8_0_lock_cursor(crtc, true);
2460         ret = dce_v8_0_cursor_move_locked(crtc, x, y);
2461         dce_v8_0_lock_cursor(crtc, false);
2462
2463         return ret;
2464 }
2465
2466 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2467                                      struct drm_file *file_priv,
2468                                      uint32_t handle,
2469                                      uint32_t width,
2470                                      uint32_t height,
2471                                      int32_t hot_x,
2472                                      int32_t hot_y)
2473 {
2474         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475         struct drm_gem_object *obj;
2476         struct amdgpu_bo *aobj;
2477         int ret;
2478
2479         if (!handle) {
2480                 /* turn off cursor */
2481                 dce_v8_0_hide_cursor(crtc);
2482                 obj = NULL;
2483                 goto unpin;
2484         }
2485
2486         if ((width > amdgpu_crtc->max_cursor_width) ||
2487             (height > amdgpu_crtc->max_cursor_height)) {
2488                 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2489                 return -EINVAL;
2490         }
2491
2492         obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
2493         if (!obj) {
2494                 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2495                 return -ENOENT;
2496         }
2497
2498         aobj = gem_to_amdgpu_bo(obj);
2499         ret = amdgpu_bo_reserve(aobj, false);
2500         if (ret != 0) {
2501                 drm_gem_object_unreference_unlocked(obj);
2502                 return ret;
2503         }
2504
2505         ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2506         amdgpu_bo_unreserve(aobj);
2507         if (ret) {
2508                 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2509                 drm_gem_object_unreference_unlocked(obj);
2510                 return ret;
2511         }
2512
2513         amdgpu_crtc->cursor_width = width;
2514         amdgpu_crtc->cursor_height = height;
2515
2516         dce_v8_0_lock_cursor(crtc, true);
2517
2518         if (hot_x != amdgpu_crtc->cursor_hot_x ||
2519             hot_y != amdgpu_crtc->cursor_hot_y) {
2520                 int x, y;
2521
2522                 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2523                 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2524
2525                 dce_v8_0_cursor_move_locked(crtc, x, y);
2526
2527                 amdgpu_crtc->cursor_hot_x = hot_x;
2528                 amdgpu_crtc->cursor_hot_y = hot_y;
2529         }
2530
2531         dce_v8_0_show_cursor(crtc);
2532         dce_v8_0_lock_cursor(crtc, false);
2533
2534 unpin:
2535         if (amdgpu_crtc->cursor_bo) {
2536                 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2537                 ret = amdgpu_bo_reserve(aobj, false);
2538                 if (likely(ret == 0)) {
2539                         amdgpu_bo_unpin(aobj);
2540                         amdgpu_bo_unreserve(aobj);
2541                 }
2542                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
2543         }
2544
2545         amdgpu_crtc->cursor_bo = obj;
2546         return 0;
2547 }
2548
2549 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2550 {
2551         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2552
2553         if (amdgpu_crtc->cursor_bo) {
2554                 dce_v8_0_lock_cursor(crtc, true);
2555
2556                 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2557                                             amdgpu_crtc->cursor_y);
2558
2559                 dce_v8_0_show_cursor(crtc);
2560
2561                 dce_v8_0_lock_cursor(crtc, false);
2562         }
2563 }
2564
2565 static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2566                                     u16 *blue, uint32_t start, uint32_t size)
2567 {
2568         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2569         int end = (start + size > 256) ? 256 : start + size, i;
2570
2571         /* userspace palettes are always correct as is */
2572         for (i = start; i < end; i++) {
2573                 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2574                 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2575                 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2576         }
2577         dce_v8_0_crtc_load_lut(crtc);
2578 }
2579
2580 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
2581 {
2582         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2583
2584         drm_crtc_cleanup(crtc);
2585         destroy_workqueue(amdgpu_crtc->pflip_queue);
2586         kfree(amdgpu_crtc);
2587 }
2588
2589 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
2590         .cursor_set2 = dce_v8_0_crtc_cursor_set2,
2591         .cursor_move = dce_v8_0_crtc_cursor_move,
2592         .gamma_set = dce_v8_0_crtc_gamma_set,
2593         .set_config = amdgpu_crtc_set_config,
2594         .destroy = dce_v8_0_crtc_destroy,
2595         .page_flip = amdgpu_crtc_page_flip,
2596 };
2597
2598 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2599 {
2600         struct drm_device *dev = crtc->dev;
2601         struct amdgpu_device *adev = dev->dev_private;
2602         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2603         unsigned type;
2604
2605         switch (mode) {
2606         case DRM_MODE_DPMS_ON:
2607                 amdgpu_crtc->enabled = true;
2608                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2609                 dce_v8_0_vga_enable(crtc, true);
2610                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2611                 dce_v8_0_vga_enable(crtc, false);
2612                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2613                 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2614                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2615                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2616                 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id);
2617                 dce_v8_0_crtc_load_lut(crtc);
2618                 break;
2619         case DRM_MODE_DPMS_STANDBY:
2620         case DRM_MODE_DPMS_SUSPEND:
2621         case DRM_MODE_DPMS_OFF:
2622                 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id);
2623                 if (amdgpu_crtc->enabled) {
2624                         dce_v8_0_vga_enable(crtc, true);
2625                         amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2626                         dce_v8_0_vga_enable(crtc, false);
2627                 }
2628                 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2629                 amdgpu_crtc->enabled = false;
2630                 break;
2631         }
2632         /* adjust pm to dpms */
2633         amdgpu_pm_compute_clocks(adev);
2634 }
2635
2636 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc)
2637 {
2638         /* disable crtc pair power gating before programming */
2639         amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2640         amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2641         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2642 }
2643
2644 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc)
2645 {
2646         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2647         amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2648 }
2649
2650 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc)
2651 {
2652         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2653         struct drm_device *dev = crtc->dev;
2654         struct amdgpu_device *adev = dev->dev_private;
2655         struct amdgpu_atom_ss ss;
2656         int i;
2657
2658         dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2659         if (crtc->primary->fb) {
2660                 int r;
2661                 struct amdgpu_framebuffer *amdgpu_fb;
2662                 struct amdgpu_bo *rbo;
2663
2664                 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2665                 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2666                 r = amdgpu_bo_reserve(rbo, false);
2667                 if (unlikely(r))
2668                         DRM_ERROR("failed to reserve rbo before unpin\n");
2669                 else {
2670                         amdgpu_bo_unpin(rbo);
2671                         amdgpu_bo_unreserve(rbo);
2672                 }
2673         }
2674         /* disable the GRPH */
2675         dce_v8_0_grph_enable(crtc, false);
2676
2677         amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2678
2679         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2680                 if (adev->mode_info.crtcs[i] &&
2681                     adev->mode_info.crtcs[i]->enabled &&
2682                     i != amdgpu_crtc->crtc_id &&
2683                     amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2684                         /* one other crtc is using this pll don't turn
2685                          * off the pll
2686                          */
2687                         goto done;
2688                 }
2689         }
2690
2691         switch (amdgpu_crtc->pll_id) {
2692         case ATOM_PPLL1:
2693         case ATOM_PPLL2:
2694                 /* disable the ppll */
2695                 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2696                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2697                 break;
2698         case ATOM_PPLL0:
2699                 /* disable the ppll */
2700                 if ((adev->asic_type == CHIP_KAVERI) ||
2701                     (adev->asic_type == CHIP_BONAIRE) ||
2702                     (adev->asic_type == CHIP_HAWAII))
2703                         amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2704                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2705                 break;
2706         default:
2707                 break;
2708         }
2709 done:
2710         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2711         amdgpu_crtc->adjusted_clock = 0;
2712         amdgpu_crtc->encoder = NULL;
2713         amdgpu_crtc->connector = NULL;
2714 }
2715
2716 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
2717                                   struct drm_display_mode *mode,
2718                                   struct drm_display_mode *adjusted_mode,
2719                                   int x, int y, struct drm_framebuffer *old_fb)
2720 {
2721         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2722
2723         if (!amdgpu_crtc->adjusted_clock)
2724                 return -EINVAL;
2725
2726         amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2727         amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2728         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2729         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2730         amdgpu_atombios_crtc_scaler_setup(crtc);
2731         dce_v8_0_cursor_reset(crtc);
2732         /* update the hw version fpr dpm */
2733         amdgpu_crtc->hw_mode = *adjusted_mode;
2734
2735         return 0;
2736 }
2737
2738 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc,
2739                                      const struct drm_display_mode *mode,
2740                                      struct drm_display_mode *adjusted_mode)
2741 {
2742         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2743         struct drm_device *dev = crtc->dev;
2744         struct drm_encoder *encoder;
2745
2746         /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2747         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2748                 if (encoder->crtc == crtc) {
2749                         amdgpu_crtc->encoder = encoder;
2750                         amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2751                         break;
2752                 }
2753         }
2754         if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2755                 amdgpu_crtc->encoder = NULL;
2756                 amdgpu_crtc->connector = NULL;
2757                 return false;
2758         }
2759         if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2760                 return false;
2761         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2762                 return false;
2763         /* pick pll */
2764         amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2765         /* if we can't get a PPLL for a non-DP encoder, fail */
2766         if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2767             !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2768                 return false;
2769
2770         return true;
2771 }
2772
2773 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2774                                   struct drm_framebuffer *old_fb)
2775 {
2776         return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2777 }
2778
2779 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2780                                          struct drm_framebuffer *fb,
2781                                          int x, int y, enum mode_set_atomic state)
2782 {
2783        return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1);
2784 }
2785
2786 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = {
2787         .dpms = dce_v8_0_crtc_dpms,
2788         .mode_fixup = dce_v8_0_crtc_mode_fixup,
2789         .mode_set = dce_v8_0_crtc_mode_set,
2790         .mode_set_base = dce_v8_0_crtc_set_base,
2791         .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic,
2792         .prepare = dce_v8_0_crtc_prepare,
2793         .commit = dce_v8_0_crtc_commit,
2794         .load_lut = dce_v8_0_crtc_load_lut,
2795         .disable = dce_v8_0_crtc_disable,
2796 };
2797
2798 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index)
2799 {
2800         struct amdgpu_crtc *amdgpu_crtc;
2801         int i;
2802
2803         amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2804                               (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2805         if (amdgpu_crtc == NULL)
2806                 return -ENOMEM;
2807
2808         drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
2809
2810         drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2811         amdgpu_crtc->crtc_id = index;
2812         amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue");
2813         adev->mode_info.crtcs[index] = amdgpu_crtc;
2814
2815         amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
2816         amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
2817         adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2818         adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2819
2820         for (i = 0; i < 256; i++) {
2821                 amdgpu_crtc->lut_r[i] = i << 2;
2822                 amdgpu_crtc->lut_g[i] = i << 2;
2823                 amdgpu_crtc->lut_b[i] = i << 2;
2824         }
2825
2826         amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2827
2828         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2829         amdgpu_crtc->adjusted_clock = 0;
2830         amdgpu_crtc->encoder = NULL;
2831         amdgpu_crtc->connector = NULL;
2832         drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs);
2833
2834         return 0;
2835 }
2836
2837 static int dce_v8_0_early_init(void *handle)
2838 {
2839         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2840
2841         adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg;
2842         adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg;
2843
2844         dce_v8_0_set_display_funcs(adev);
2845         dce_v8_0_set_irq_funcs(adev);
2846
2847         switch (adev->asic_type) {
2848         case CHIP_BONAIRE:
2849         case CHIP_HAWAII:
2850                 adev->mode_info.num_crtc = 6;
2851                 adev->mode_info.num_hpd = 6;
2852                 adev->mode_info.num_dig = 6;
2853                 break;
2854         case CHIP_KAVERI:
2855                 adev->mode_info.num_crtc = 4;
2856                 adev->mode_info.num_hpd = 6;
2857                 adev->mode_info.num_dig = 7;
2858                 break;
2859         case CHIP_KABINI:
2860         case CHIP_MULLINS:
2861                 adev->mode_info.num_crtc = 2;
2862                 adev->mode_info.num_hpd = 6;
2863                 adev->mode_info.num_dig = 6; /* ? */
2864                 break;
2865         default:
2866                 /* FIXME: not supported yet */
2867                 return -EINVAL;
2868         }
2869
2870         return 0;
2871 }
2872
2873 static int dce_v8_0_sw_init(void *handle)
2874 {
2875         int r, i;
2876         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2877
2878         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2879                 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2880                 if (r)
2881                         return r;
2882         }
2883
2884         for (i = 8; i < 20; i += 2) {
2885                 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2886                 if (r)
2887                         return r;
2888         }
2889
2890         /* HPD hotplug */
2891         r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2892         if (r)
2893                 return r;
2894
2895         adev->mode_info.mode_config_initialized = true;
2896
2897         adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2898
2899         adev->ddev->mode_config.max_width = 16384;
2900         adev->ddev->mode_config.max_height = 16384;
2901
2902         adev->ddev->mode_config.preferred_depth = 24;
2903         adev->ddev->mode_config.prefer_shadow = 1;
2904
2905         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2906
2907         r = amdgpu_modeset_create_props(adev);
2908         if (r)
2909                 return r;
2910
2911         adev->ddev->mode_config.max_width = 16384;
2912         adev->ddev->mode_config.max_height = 16384;
2913
2914         /* allocate crtcs */
2915         for (i = 0; i < adev->mode_info.num_crtc; i++) {
2916                 r = dce_v8_0_crtc_init(adev, i);
2917                 if (r)
2918                         return r;
2919         }
2920
2921         if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2922                 amdgpu_print_display_setup(adev->ddev);
2923         else
2924                 return -EINVAL;
2925
2926         /* setup afmt */
2927         dce_v8_0_afmt_init(adev);
2928
2929         r = dce_v8_0_audio_init(adev);
2930         if (r)
2931                 return r;
2932
2933         drm_kms_helper_poll_init(adev->ddev);
2934
2935         return r;
2936 }
2937
2938 static int dce_v8_0_sw_fini(void *handle)
2939 {
2940         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2941
2942         kfree(adev->mode_info.bios_hardcoded_edid);
2943
2944         drm_kms_helper_poll_fini(adev->ddev);
2945
2946         dce_v8_0_audio_fini(adev);
2947
2948         dce_v8_0_afmt_fini(adev);
2949
2950         drm_mode_config_cleanup(adev->ddev);
2951         adev->mode_info.mode_config_initialized = false;
2952
2953         return 0;
2954 }
2955
2956 static int dce_v8_0_hw_init(void *handle)
2957 {
2958         int i;
2959         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2960
2961         /* init dig PHYs, disp eng pll */
2962         amdgpu_atombios_encoder_init_dig(adev);
2963         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2964
2965         /* initialize hpd */
2966         dce_v8_0_hpd_init(adev);
2967
2968         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2969                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2970         }
2971
2972         dce_v8_0_pageflip_interrupt_init(adev);
2973
2974         return 0;
2975 }
2976
2977 static int dce_v8_0_hw_fini(void *handle)
2978 {
2979         int i;
2980         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2981
2982         dce_v8_0_hpd_fini(adev);
2983
2984         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2985                 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2986         }
2987
2988         dce_v8_0_pageflip_interrupt_fini(adev);
2989
2990         return 0;
2991 }
2992
2993 static int dce_v8_0_suspend(void *handle)
2994 {
2995         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2996
2997         amdgpu_atombios_scratch_regs_save(adev);
2998
2999         return dce_v8_0_hw_fini(handle);
3000 }
3001
3002 static int dce_v8_0_resume(void *handle)
3003 {
3004         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3005         int ret;
3006
3007         ret = dce_v8_0_hw_init(handle);
3008
3009         amdgpu_atombios_scratch_regs_restore(adev);
3010
3011         /* turn on the BL */
3012         if (adev->mode_info.bl_encoder) {
3013                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3014                                                                   adev->mode_info.bl_encoder);
3015                 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3016                                                     bl_level);
3017         }
3018
3019         return ret;
3020 }
3021
3022 static bool dce_v8_0_is_idle(void *handle)
3023 {
3024         return true;
3025 }
3026
3027 static int dce_v8_0_wait_for_idle(void *handle)
3028 {
3029         return 0;
3030 }
3031
3032 static void dce_v8_0_print_status(void *handle)
3033 {
3034         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3035
3036         dev_info(adev->dev, "DCE 8.x registers\n");
3037         /* XXX todo */
3038 }
3039
3040 static int dce_v8_0_soft_reset(void *handle)
3041 {
3042         u32 srbm_soft_reset = 0, tmp;
3043         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3044
3045         if (dce_v8_0_is_display_hung(adev))
3046                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3047
3048         if (srbm_soft_reset) {
3049                 dce_v8_0_print_status((void *)adev);
3050
3051                 tmp = RREG32(mmSRBM_SOFT_RESET);
3052                 tmp |= srbm_soft_reset;
3053                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3054                 WREG32(mmSRBM_SOFT_RESET, tmp);
3055                 tmp = RREG32(mmSRBM_SOFT_RESET);
3056
3057                 udelay(50);
3058
3059                 tmp &= ~srbm_soft_reset;
3060                 WREG32(mmSRBM_SOFT_RESET, tmp);
3061                 tmp = RREG32(mmSRBM_SOFT_RESET);
3062
3063                 /* Wait a little for things to settle down */
3064                 udelay(50);
3065                 dce_v8_0_print_status((void *)adev);
3066         }
3067         return 0;
3068 }
3069
3070 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3071                                                      int crtc,
3072                                                      enum amdgpu_interrupt_state state)
3073 {
3074         u32 reg_block, lb_interrupt_mask;
3075
3076         if (crtc >= adev->mode_info.num_crtc) {
3077                 DRM_DEBUG("invalid crtc %d\n", crtc);
3078                 return;
3079         }
3080
3081         switch (crtc) {
3082         case 0:
3083                 reg_block = CRTC0_REGISTER_OFFSET;
3084                 break;
3085         case 1:
3086                 reg_block = CRTC1_REGISTER_OFFSET;
3087                 break;
3088         case 2:
3089                 reg_block = CRTC2_REGISTER_OFFSET;
3090                 break;
3091         case 3:
3092                 reg_block = CRTC3_REGISTER_OFFSET;
3093                 break;
3094         case 4:
3095                 reg_block = CRTC4_REGISTER_OFFSET;
3096                 break;
3097         case 5:
3098                 reg_block = CRTC5_REGISTER_OFFSET;
3099                 break;
3100         default:
3101                 DRM_DEBUG("invalid crtc %d\n", crtc);
3102                 return;
3103         }
3104
3105         switch (state) {
3106         case AMDGPU_IRQ_STATE_DISABLE:
3107                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3108                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3109                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3110                 break;
3111         case AMDGPU_IRQ_STATE_ENABLE:
3112                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3113                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
3114                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3115                 break;
3116         default:
3117                 break;
3118         }
3119 }
3120
3121 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3122                                                     int crtc,
3123                                                     enum amdgpu_interrupt_state state)
3124 {
3125         u32 reg_block, lb_interrupt_mask;
3126
3127         if (crtc >= adev->mode_info.num_crtc) {
3128                 DRM_DEBUG("invalid crtc %d\n", crtc);
3129                 return;
3130         }
3131
3132         switch (crtc) {
3133         case 0:
3134                 reg_block = CRTC0_REGISTER_OFFSET;
3135                 break;
3136         case 1:
3137                 reg_block = CRTC1_REGISTER_OFFSET;
3138                 break;
3139         case 2:
3140                 reg_block = CRTC2_REGISTER_OFFSET;
3141                 break;
3142         case 3:
3143                 reg_block = CRTC3_REGISTER_OFFSET;
3144                 break;
3145         case 4:
3146                 reg_block = CRTC4_REGISTER_OFFSET;
3147                 break;
3148         case 5:
3149                 reg_block = CRTC5_REGISTER_OFFSET;
3150                 break;
3151         default:
3152                 DRM_DEBUG("invalid crtc %d\n", crtc);
3153                 return;
3154         }
3155
3156         switch (state) {
3157         case AMDGPU_IRQ_STATE_DISABLE:
3158                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3159                 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3160                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3161                 break;
3162         case AMDGPU_IRQ_STATE_ENABLE:
3163                 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
3164                 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK;
3165                 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
3166                 break;
3167         default:
3168                 break;
3169         }
3170 }
3171
3172 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
3173                                             struct amdgpu_irq_src *src,
3174                                             unsigned type,
3175                                             enum amdgpu_interrupt_state state)
3176 {
3177         u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
3178
3179         switch (type) {
3180         case AMDGPU_HPD_1:
3181                 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL;
3182                 break;
3183         case AMDGPU_HPD_2:
3184                 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL;
3185                 break;
3186         case AMDGPU_HPD_3:
3187                 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL;
3188                 break;
3189         case AMDGPU_HPD_4:
3190                 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL;
3191                 break;
3192         case AMDGPU_HPD_5:
3193                 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL;
3194                 break;
3195         case AMDGPU_HPD_6:
3196                 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL;
3197                 break;
3198         default:
3199                 DRM_DEBUG("invalid hdp %d\n", type);
3200                 return 0;
3201         }
3202
3203         switch (state) {
3204         case AMDGPU_IRQ_STATE_DISABLE:
3205                 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3206                 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3207                 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3208                 break;
3209         case AMDGPU_IRQ_STATE_ENABLE:
3210                 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
3211                 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
3212                 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
3213                 break;
3214         default:
3215                 break;
3216         }
3217
3218         return 0;
3219 }
3220
3221 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
3222                                              struct amdgpu_irq_src *src,
3223                                              unsigned type,
3224                                              enum amdgpu_interrupt_state state)
3225 {
3226         switch (type) {
3227         case AMDGPU_CRTC_IRQ_VBLANK1:
3228                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3229                 break;
3230         case AMDGPU_CRTC_IRQ_VBLANK2:
3231                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3232                 break;
3233         case AMDGPU_CRTC_IRQ_VBLANK3:
3234                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3235                 break;
3236         case AMDGPU_CRTC_IRQ_VBLANK4:
3237                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3238                 break;
3239         case AMDGPU_CRTC_IRQ_VBLANK5:
3240                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3241                 break;
3242         case AMDGPU_CRTC_IRQ_VBLANK6:
3243                 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3244                 break;
3245         case AMDGPU_CRTC_IRQ_VLINE1:
3246                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state);
3247                 break;
3248         case AMDGPU_CRTC_IRQ_VLINE2:
3249                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state);
3250                 break;
3251         case AMDGPU_CRTC_IRQ_VLINE3:
3252                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state);
3253                 break;
3254         case AMDGPU_CRTC_IRQ_VLINE4:
3255                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state);
3256                 break;
3257         case AMDGPU_CRTC_IRQ_VLINE5:
3258                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state);
3259                 break;
3260         case AMDGPU_CRTC_IRQ_VLINE6:
3261                 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state);
3262                 break;
3263         default:
3264                 break;
3265         }
3266         return 0;
3267 }
3268
3269 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev,
3270                              struct amdgpu_irq_src *source,
3271                              struct amdgpu_iv_entry *entry)
3272 {
3273         unsigned crtc = entry->src_id - 1;
3274         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3275         unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
3276
3277         switch (entry->src_data) {
3278         case 0: /* vblank */
3279                 if (disp_int & interrupt_status_offsets[crtc].vblank)
3280                         WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);
3281                 else
3282                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3283
3284                 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3285                         drm_handle_vblank(adev->ddev, crtc);
3286                 }
3287                 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3288
3289                 break;
3290         case 1: /* vline */
3291                 if (disp_int & interrupt_status_offsets[crtc].vline)
3292                         WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);
3293                 else
3294                         DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3295
3296                 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3297
3298                 break;
3299         default:
3300                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3301                 break;
3302         }
3303
3304         return 0;
3305 }
3306
3307 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3308                                                  struct amdgpu_irq_src *src,
3309                                                  unsigned type,
3310                                                  enum amdgpu_interrupt_state state)
3311 {
3312         u32 reg;
3313
3314         if (type >= adev->mode_info.num_crtc) {
3315                 DRM_ERROR("invalid pageflip crtc %d\n", type);
3316                 return -EINVAL;
3317         }
3318
3319         reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3320         if (state == AMDGPU_IRQ_STATE_DISABLE)
3321                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3322                        reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3323         else
3324                 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3325                        reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3326
3327         return 0;
3328 }
3329
3330 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
3331                                 struct amdgpu_irq_src *source,
3332                                 struct amdgpu_iv_entry *entry)
3333 {
3334         unsigned long flags;
3335         unsigned crtc_id;
3336         struct amdgpu_crtc *amdgpu_crtc;
3337         struct amdgpu_flip_work *works;
3338
3339         crtc_id = (entry->src_id - 8) >> 1;
3340         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3341
3342         if (crtc_id >= adev->mode_info.num_crtc) {
3343                 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3344                 return -EINVAL;
3345         }
3346
3347         if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3348             GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3349                 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3350                        GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3351
3352         /* IRQ could occur when in initial stage */
3353         if (amdgpu_crtc == NULL)
3354                 return 0;
3355
3356         spin_lock_irqsave(&adev->ddev->event_lock, flags);
3357         works = amdgpu_crtc->pflip_works;
3358         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3359                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3360                                                 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3361                                                 amdgpu_crtc->pflip_status,
3362                                                 AMDGPU_FLIP_SUBMITTED);
3363                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3364                 return 0;
3365         }
3366
3367         /* page flip completed. clean up */
3368         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3369         amdgpu_crtc->pflip_works = NULL;
3370
3371         /* wakeup usersapce */
3372         if (works->event)
3373                 drm_send_vblank_event(adev->ddev, crtc_id, works->event);
3374
3375         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3376
3377         drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id);
3378         queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work);
3379
3380         return 0;
3381 }
3382
3383 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev,
3384                             struct amdgpu_irq_src *source,
3385                             struct amdgpu_iv_entry *entry)
3386 {
3387         uint32_t disp_int, mask, int_control, tmp;
3388         unsigned hpd;
3389
3390         if (entry->src_data >= adev->mode_info.num_hpd) {
3391                 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
3392                 return 0;
3393         }
3394
3395         hpd = entry->src_data;
3396         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3397         mask = interrupt_status_offsets[hpd].hpd;
3398         int_control = hpd_int_control_offsets[hpd];
3399
3400         if (disp_int & mask) {
3401                 tmp = RREG32(int_control);
3402                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
3403                 WREG32(int_control, tmp);
3404                 schedule_work(&adev->hotplug_work);
3405                 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3406         }
3407
3408         return 0;
3409
3410 }
3411
3412 static int dce_v8_0_set_clockgating_state(void *handle,
3413                                           enum amd_clockgating_state state)
3414 {
3415         return 0;
3416 }
3417
3418 static int dce_v8_0_set_powergating_state(void *handle,
3419                                           enum amd_powergating_state state)
3420 {
3421         return 0;
3422 }
3423
3424 const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3425         .early_init = dce_v8_0_early_init,
3426         .late_init = NULL,
3427         .sw_init = dce_v8_0_sw_init,
3428         .sw_fini = dce_v8_0_sw_fini,
3429         .hw_init = dce_v8_0_hw_init,
3430         .hw_fini = dce_v8_0_hw_fini,
3431         .suspend = dce_v8_0_suspend,
3432         .resume = dce_v8_0_resume,
3433         .is_idle = dce_v8_0_is_idle,
3434         .wait_for_idle = dce_v8_0_wait_for_idle,
3435         .soft_reset = dce_v8_0_soft_reset,
3436         .print_status = dce_v8_0_print_status,
3437         .set_clockgating_state = dce_v8_0_set_clockgating_state,
3438         .set_powergating_state = dce_v8_0_set_powergating_state,
3439 };
3440
3441 static void
3442 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder,
3443                           struct drm_display_mode *mode,
3444                           struct drm_display_mode *adjusted_mode)
3445 {
3446         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3447
3448         amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3449
3450         /* need to call this here rather than in prepare() since we need some crtc info */
3451         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3452
3453         /* set scaler clears this on some chips */
3454         dce_v8_0_set_interleave(encoder->crtc, mode);
3455
3456         if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3457                 dce_v8_0_afmt_enable(encoder, true);
3458                 dce_v8_0_afmt_setmode(encoder, adjusted_mode);
3459         }
3460 }
3461
3462 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder)
3463 {
3464         struct amdgpu_device *adev = encoder->dev->dev_private;
3465         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3466         struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3467
3468         if ((amdgpu_encoder->active_device &
3469              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3470             (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3471              ENCODER_OBJECT_ID_NONE)) {
3472                 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3473                 if (dig) {
3474                         dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder);
3475                         if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3476                                 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3477                 }
3478         }
3479
3480         amdgpu_atombios_scratch_regs_lock(adev, true);
3481
3482         if (connector) {
3483                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3484
3485                 /* select the clock/data port if it uses a router */
3486                 if (amdgpu_connector->router.cd_valid)
3487                         amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3488
3489                 /* turn eDP panel on for mode set */
3490                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3491                         amdgpu_atombios_encoder_set_edp_panel_power(connector,
3492                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
3493         }
3494
3495         /* this is needed for the pll/ss setup to work correctly in some cases */
3496         amdgpu_atombios_encoder_set_crtc_source(encoder);
3497         /* set up the FMT blocks */
3498         dce_v8_0_program_fmt(encoder);
3499 }
3500
3501 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder)
3502 {
3503         struct drm_device *dev = encoder->dev;
3504         struct amdgpu_device *adev = dev->dev_private;
3505
3506         /* need to call this here as we need the crtc set up */
3507         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3508         amdgpu_atombios_scratch_regs_lock(adev, false);
3509 }
3510
3511 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder)
3512 {
3513         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3514         struct amdgpu_encoder_atom_dig *dig;
3515
3516         amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3517
3518         if (amdgpu_atombios_encoder_is_digital(encoder)) {
3519                 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3520                         dce_v8_0_afmt_enable(encoder, false);
3521                 dig = amdgpu_encoder->enc_priv;
3522                 dig->dig_encoder = -1;
3523         }
3524         amdgpu_encoder->active_device = 0;
3525 }
3526
3527 /* these are handled by the primary encoders */
3528 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder)
3529 {
3530
3531 }
3532
3533 static void dce_v8_0_ext_commit(struct drm_encoder *encoder)
3534 {
3535
3536 }
3537
3538 static void
3539 dce_v8_0_ext_mode_set(struct drm_encoder *encoder,
3540                       struct drm_display_mode *mode,
3541                       struct drm_display_mode *adjusted_mode)
3542 {
3543
3544 }
3545
3546 static void dce_v8_0_ext_disable(struct drm_encoder *encoder)
3547 {
3548
3549 }
3550
3551 static void
3552 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode)
3553 {
3554
3555 }
3556
3557 static bool dce_v8_0_ext_mode_fixup(struct drm_encoder *encoder,
3558                                     const struct drm_display_mode *mode,
3559                                     struct drm_display_mode *adjusted_mode)
3560 {
3561         return true;
3562 }
3563
3564 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = {
3565         .dpms = dce_v8_0_ext_dpms,
3566         .mode_fixup = dce_v8_0_ext_mode_fixup,
3567         .prepare = dce_v8_0_ext_prepare,
3568         .mode_set = dce_v8_0_ext_mode_set,
3569         .commit = dce_v8_0_ext_commit,
3570         .disable = dce_v8_0_ext_disable,
3571         /* no detect for TMDS/LVDS yet */
3572 };
3573
3574 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = {
3575         .dpms = amdgpu_atombios_encoder_dpms,
3576         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3577         .prepare = dce_v8_0_encoder_prepare,
3578         .mode_set = dce_v8_0_encoder_mode_set,
3579         .commit = dce_v8_0_encoder_commit,
3580         .disable = dce_v8_0_encoder_disable,
3581         .detect = amdgpu_atombios_encoder_dig_detect,
3582 };
3583
3584 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = {
3585         .dpms = amdgpu_atombios_encoder_dpms,
3586         .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3587         .prepare = dce_v8_0_encoder_prepare,
3588         .mode_set = dce_v8_0_encoder_mode_set,
3589         .commit = dce_v8_0_encoder_commit,
3590         .detect = amdgpu_atombios_encoder_dac_detect,
3591 };
3592
3593 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder)
3594 {
3595         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3596         if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3597                 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3598         kfree(amdgpu_encoder->enc_priv);
3599         drm_encoder_cleanup(encoder);
3600         kfree(amdgpu_encoder);
3601 }
3602
3603 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = {
3604         .destroy = dce_v8_0_encoder_destroy,
3605 };
3606
3607 static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
3608                                  uint32_t encoder_enum,
3609                                  uint32_t supported_device,
3610                                  u16 caps)
3611 {
3612         struct drm_device *dev = adev->ddev;
3613         struct drm_encoder *encoder;
3614         struct amdgpu_encoder *amdgpu_encoder;
3615
3616         /* see if we already added it */
3617         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3618                 amdgpu_encoder = to_amdgpu_encoder(encoder);
3619                 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3620                         amdgpu_encoder->devices |= supported_device;
3621                         return;
3622                 }
3623
3624         }
3625
3626         /* add a new one */
3627         amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3628         if (!amdgpu_encoder)
3629                 return;
3630
3631         encoder = &amdgpu_encoder->base;
3632         switch (adev->mode_info.num_crtc) {
3633         case 1:
3634                 encoder->possible_crtcs = 0x1;
3635                 break;
3636         case 2:
3637         default:
3638                 encoder->possible_crtcs = 0x3;
3639                 break;
3640         case 4:
3641                 encoder->possible_crtcs = 0xf;
3642                 break;
3643         case 6:
3644                 encoder->possible_crtcs = 0x3f;
3645                 break;
3646         }
3647
3648         amdgpu_encoder->enc_priv = NULL;
3649
3650         amdgpu_encoder->encoder_enum = encoder_enum;
3651         amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3652         amdgpu_encoder->devices = supported_device;
3653         amdgpu_encoder->rmx_type = RMX_OFF;
3654         amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3655         amdgpu_encoder->is_ext_encoder = false;
3656         amdgpu_encoder->caps = caps;
3657
3658         switch (amdgpu_encoder->encoder_id) {
3659         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3660         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3661                 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3662                                  DRM_MODE_ENCODER_DAC, NULL);
3663                 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs);
3664                 break;
3665         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3666         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3667         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3668         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3669         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3670                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3671                         amdgpu_encoder->rmx_type = RMX_FULL;
3672                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3673                                          DRM_MODE_ENCODER_LVDS, NULL);
3674                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3675                 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3676                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3677                                          DRM_MODE_ENCODER_DAC, NULL);
3678                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3679                 } else {
3680                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3681                                          DRM_MODE_ENCODER_TMDS, NULL);
3682                         amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3683                 }
3684                 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs);
3685                 break;
3686         case ENCODER_OBJECT_ID_SI170B:
3687         case ENCODER_OBJECT_ID_CH7303:
3688         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3689         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3690         case ENCODER_OBJECT_ID_TITFP513:
3691         case ENCODER_OBJECT_ID_VT1623:
3692         case ENCODER_OBJECT_ID_HDMI_SI1930:
3693         case ENCODER_OBJECT_ID_TRAVIS:
3694         case ENCODER_OBJECT_ID_NUTMEG:
3695                 /* these are handled by the primary encoders */
3696                 amdgpu_encoder->is_ext_encoder = true;
3697                 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3698                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3699                                          DRM_MODE_ENCODER_LVDS, NULL);
3700                 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3701                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3702                                          DRM_MODE_ENCODER_DAC, NULL);
3703                 else
3704                         drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs,
3705                                          DRM_MODE_ENCODER_TMDS, NULL);
3706                 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs);
3707                 break;
3708         }
3709 }
3710
3711 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = {
3712         .set_vga_render_state = &dce_v8_0_set_vga_render_state,
3713         .bandwidth_update = &dce_v8_0_bandwidth_update,
3714         .vblank_get_counter = &dce_v8_0_vblank_get_counter,
3715         .vblank_wait = &dce_v8_0_vblank_wait,
3716         .is_display_hung = &dce_v8_0_is_display_hung,
3717         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3718         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3719         .hpd_sense = &dce_v8_0_hpd_sense,
3720         .hpd_set_polarity = &dce_v8_0_hpd_set_polarity,
3721         .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg,
3722         .page_flip = &dce_v8_0_page_flip,
3723         .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos,
3724         .add_encoder = &dce_v8_0_encoder_add,
3725         .add_connector = &amdgpu_connector_add,
3726         .stop_mc_access = &dce_v8_0_stop_mc_access,
3727         .resume_mc_access = &dce_v8_0_resume_mc_access,
3728 };
3729
3730 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev)
3731 {
3732         if (adev->mode_info.funcs == NULL)
3733                 adev->mode_info.funcs = &dce_v8_0_display_funcs;
3734 }
3735
3736 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = {
3737         .set = dce_v8_0_set_crtc_interrupt_state,
3738         .process = dce_v8_0_crtc_irq,
3739 };
3740
3741 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = {
3742         .set = dce_v8_0_set_pageflip_interrupt_state,
3743         .process = dce_v8_0_pageflip_irq,
3744 };
3745
3746 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = {
3747         .set = dce_v8_0_set_hpd_interrupt_state,
3748         .process = dce_v8_0_hpd_irq,
3749 };
3750
3751 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev)
3752 {
3753         adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3754         adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs;
3755
3756         adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3757         adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs;
3758
3759         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3760         adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs;
3761 }