drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <[email protected]>,
   7  *          Sebastian Andrzej Siewior <[email protected]>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_ep_inc_trb() - Increment a TRB index.
 150  * @index - Pointer to the TRB index to increment.
 151  *
 152  * The index should never point to the link TRB. After incrementing,
 153  * if it is point to the link TRB, wrap around to the beginning. The
 154  * link TRB is always at the last TRB entry.
 155  */
 156 static void dwc3_ep_inc_trb(u8 *index)
 157 {
 158         (*index)++;
 159         if (*index == (DWC3_TRB_NUM - 1))
 160                 *index = 0;
 161 }
 162
 163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 164 {
 165         dwc3_ep_inc_trb(&dep->trb_enqueue);
 166 }
 167
 168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 169 {
 170         dwc3_ep_inc_trb(&dep->trb_dequeue);
 171 }
 172
 173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 174                 int status)
 175 {
 176         struct dwc3                     *dwc = dep->dwc;
 177
 178         req->started = false;
 179         list_del(&req->list);
 180         req->trb = NULL;
 181         req->remaining = 0;
 182
 183         if (req->request.status == -EINPROGRESS)
 184                 req->request.status = status;
 185
 186         if (dwc->ep0_bounced && dep->number == 0)
 187                 dwc->ep0_bounced = false;
 188         else
 189                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 190                                 req->direction);
 191
 192         trace_dwc3_gadget_giveback(req);
 193
 194         spin_unlock(&dwc->lock);
 195         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 196         spin_lock(&dwc->lock);
 197
 198         if (dep->number > 1)
 199                 pm_runtime_put(dwc->dev);
 200 }
 201
 202 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 203 {
 204         u32             timeout = 500;
 205         int             status = 0;
 206         int             ret = 0;
 207         u32             reg;
 208
 209         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 210         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 211
 212         do {
 213                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 214                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 215                         status = DWC3_DGCMD_STATUS(reg);
 216                         if (status)
 217                                 ret = -EINVAL;
 218                         break;
 219                 }
 220         } while (timeout--);
 221
 222         if (!timeout) {
 223                 ret = -ETIMEDOUT;
 224                 status = -ETIMEDOUT;
 225         }
 226
 227         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 228
 229         return ret;
 230 }
 231
 232 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 233
 234 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 235                 struct dwc3_gadget_ep_cmd_params *params)
 236 {
 237         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 238         struct dwc3             *dwc = dep->dwc;
 239         u32                     timeout = 500;
 240         u32                     reg;
 241
 242         int                     cmd_status = 0;
 243         int                     susphy = false;
 244         int                     ret = -EINVAL;
 245
 246         /*
 247          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 248          * we're issuing an endpoint command, we must check if
 249          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 250          *
 251          * We will also set SUSPHY bit to what it was before returning as stated
 252          * by the same section on Synopsys databook.
 253          */
 254         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 255                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 256                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 257                         susphy = true;
 258                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 259                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 260                 }
 261         }
 262
 263         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 264                 int             needs_wakeup;
 265
 266                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 267                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 268                                 dwc->link_state == DWC3_LINK_STATE_U3);
 269
 270                 if (unlikely(needs_wakeup)) {
 271                         ret = __dwc3_gadget_wakeup(dwc);
 272                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 273                                         ret);
 274                 }
 275         }
 276
 277         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 278         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 279         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 280
 281         /*
 282          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 283          * not relying on XferNotReady, we can make use of a special "No
 284          * Response Update Transfer" command where we should clear both CmdAct
 285          * and CmdIOC bits.
 286          *
 287          * With this, we don't need to wait for command completion and can
 288          * straight away issue further commands to the endpoint.
 289          *
 290          * NOTICE: We're making an assumption that control endpoints will never
 291          * make use of Update Transfer command. This is a safe assumption
 292          * because we can never have more than one request at a time with
 293          * Control Endpoints. If anybody changes that assumption, this chunk
 294          * needs to be updated accordingly.
 295          */
 296         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 297                         !usb_endpoint_xfer_isoc(desc))
 298                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 299         else
 300                 cmd |= DWC3_DEPCMD_CMDACT;
 301
 302         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 303         do {
 304                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 305                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 306                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 307
 308                         switch (cmd_status) {
 309                         case 0:
 310                                 ret = 0;
 311                                 break;
 312                         case DEPEVT_TRANSFER_NO_RESOURCE:
 313                                 ret = -EINVAL;
 314                                 break;
 315                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 316                                 /*
 317                                  * SW issues START TRANSFER command to
 318                                  * isochronous ep with future frame interval. If
 319                                  * future interval time has already passed when
 320                                  * core receives the command, it will respond
 321                                  * with an error status of 'Bus Expiry'.
 322                                  *
 323                                  * Instead of always returning -EINVAL, let's
 324                                  * give a hint to the gadget driver that this is
 325                                  * the case by returning -EAGAIN.
 326                                  */
 327                                 ret = -EAGAIN;
 328                                 break;
 329                         default:
 330                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 331                         }
 332
 333                         break;
 334                 }
 335         } while (--timeout);
 336
 337         if (timeout == 0) {
 338                 ret = -ETIMEDOUT;
 339                 cmd_status = -ETIMEDOUT;
 340         }
 341
 342         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 343
 344         if (ret == 0) {
 345                 switch (DWC3_DEPCMD_CMD(cmd)) {
 346                 case DWC3_DEPCMD_STARTTRANSFER:
 347                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 348                         break;
 349                 case DWC3_DEPCMD_ENDTRANSFER:
 350                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 351                         break;
 352                 default:
 353                         /* nothing */
 354                         break;
 355                 }
 356         }
 357
 358         if (unlikely(susphy)) {
 359                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 360                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 361                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 362         }
 363
 364         return ret;
 365 }
 366
 367 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 368 {
 369         struct dwc3 *dwc = dep->dwc;
 370         struct dwc3_gadget_ep_cmd_params params;
 371         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 372
 373         /*
 374          * As of core revision 2.60a the recommended programming model
 375          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 376          * command for IN endpoints. This is to prevent an issue where
 377          * some (non-compliant) hosts may not send ACK TPs for pending
 378          * IN transfers due to a mishandled error condition. Synopsys
 379          * STAR 9000614252.
 380          */
 381         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
 382             (dwc->gadget.speed >= USB_SPEED_SUPER))
 383                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 384
 385         memset(&params, 0, sizeof(params));
 386
 387         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 388 }
 389
 390 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 391                 struct dwc3_trb *trb)
 392 {
 393         u32             offset = (char *) trb - (char *) dep->trb_pool;
 394
 395         return dep->trb_pool_dma + offset;
 396 }
 397
 398 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 399 {
 400         struct dwc3             *dwc = dep->dwc;
 401
 402         if (dep->trb_pool)
 403                 return 0;
 404
 405         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 406                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 407                         &dep->trb_pool_dma, GFP_KERNEL);
 408         if (!dep->trb_pool) {
 409                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 410                                 dep->name);
 411                 return -ENOMEM;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 418 {
 419         struct dwc3             *dwc = dep->dwc;
 420
 421         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 422                         dep->trb_pool, dep->trb_pool_dma);
 423
 424         dep->trb_pool = NULL;
 425         dep->trb_pool_dma = 0;
 426 }
 427
 428 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 429
 430 /**
 431  * dwc3_gadget_start_config - Configure EP resources
 432  * @dwc: pointer to our controller context structure
 433  * @dep: endpoint that is being enabled
 434  *
 435  * The assignment of transfer resources cannot perfectly follow the
 436  * data book due to the fact that the controller driver does not have
 437  * all knowledge of the configuration in advance. It is given this
 438  * information piecemeal by the composite gadget framework after every
 439  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 440  * programming model in this scenario can cause errors. For two
 441  * reasons:
 442  *
 443  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 444  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 445  * multiple interfaces.
 446  *
 447  * 2) The databook does not mention doing more DEPXFERCFG for new
 448  * endpoint on alt setting (8.1.6).
 449  *
 450  * The following simplified method is used instead:
 451  *
 452  * All hardware endpoints can be assigned a transfer resource and this
 453  * setting will stay persistent until either a core reset or
 454  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 455  * do DEPXFERCFG for every hardware endpoint as well. We are
 456  * guaranteed that there are as many transfer resources as endpoints.
 457  *
 458  * This function is called for each endpoint when it is being enabled
 459  * but is triggered only when called for EP0-out, which always happens
 460  * first, and which should only happen in one of the above conditions.
 461  */
 462 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 463 {
 464         struct dwc3_gadget_ep_cmd_params params;
 465         u32                     cmd;
 466         int                     i;
 467         int                     ret;
 468
 469         if (dep->number)
 470                 return 0;
 471
 472         memset(&params, 0x00, sizeof(params));
 473         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 474
 475         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 476         if (ret)
 477                 return ret;
 478
 479         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 480                 struct dwc3_ep *dep = dwc->eps[i];
 481
 482                 if (!dep)
 483                         continue;
 484
 485                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         return 0;
 491 }
 492
 493 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 494                 const struct usb_endpoint_descriptor *desc,
 495                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 496                 bool modify, bool restore)
 497 {
 498         struct dwc3_gadget_ep_cmd_params params;
 499
 500         if (dev_WARN_ONCE(dwc->dev, modify && restore,
 501                                         "Can't modify and restore\n"))
 502                 return -EINVAL;
 503
 504         memset(&params, 0x00, sizeof(params));
 505
 506         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 507                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 508
 509         /* Burst size is only needed in SuperSpeed mode */
 510         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 511                 u32 burst = dep->endpoint.maxburst;
 512                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 513         }
 514
 515         if (modify) {
 516                 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
 517         } else if (restore) {
 518                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 519                 params.param2 |= dep->saved_state;
 520         } else {
 521                 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
 522         }
 523
 524         if (usb_endpoint_xfer_control(desc))
 525                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 526
 527         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 528                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 529
 530         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 531                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 532                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 533                 dep->stream_capable = true;
 534         }
 535
 536         if (!usb_endpoint_xfer_control(desc))
 537                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 538
 539         /*
 540          * We are doing 1:1 mapping for endpoints, meaning
 541          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 542          * so on. We consider the direction bit as part of the physical
 543          * endpoint number. So USB endpoint 0x81 is 0x03.
 544          */
 545         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 546
 547         /*
 548          * We must use the lower 16 TX FIFOs even though
 549          * HW might have more
 550          */
 551         if (dep->direction)
 552                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 553
 554         if (desc->bInterval) {
 555                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 556                 dep->interval = 1 << (desc->bInterval - 1);
 557         }
 558
 559         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 560 }
 561
 562 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 563 {
 564         struct dwc3_gadget_ep_cmd_params params;
 565
 566         memset(&params, 0x00, sizeof(params));
 567
 568         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 569
 570         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 571                         &params);
 572 }
 573
 574 /**
 575  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 576  * @dep: endpoint to be initialized
 577  * @desc: USB Endpoint Descriptor
 578  *
 579  * Caller should take care of locking
 580  */
 581 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 582                 const struct usb_endpoint_descriptor *desc,
 583                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 584                 bool modify, bool restore)
 585 {
 586         struct dwc3             *dwc = dep->dwc;
 587         u32                     reg;
 588         int                     ret;
 589
 590         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 591
 592         if (!(dep->flags & DWC3_EP_ENABLED)) {
 593                 ret = dwc3_gadget_start_config(dwc, dep);
 594                 if (ret)
 595                         return ret;
 596         }
 597
 598         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
 599                         restore);
 600         if (ret)
 601                 return ret;
 602
 603         if (!(dep->flags & DWC3_EP_ENABLED)) {
 604                 struct dwc3_trb *trb_st_hw;
 605                 struct dwc3_trb *trb_link;
 606
 607                 dep->endpoint.desc = desc;
 608                 dep->comp_desc = comp_desc;
 609                 dep->type = usb_endpoint_type(desc);
 610                 dep->flags |= DWC3_EP_ENABLED;
 611                 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
 612
 613                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 614                 reg |= DWC3_DALEPENA_EP(dep->number);
 615                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 616
 617                 init_waitqueue_head(&dep->wait_end_transfer);
 618
 619                 if (usb_endpoint_xfer_control(desc))
 620                         return 0;
 621
 622                 /* Initialize the TRB ring */
 623                 dep->trb_dequeue = 0;
 624                 dep->trb_enqueue = 0;
 625                 memset(dep->trb_pool, 0,
 626                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 627
 628                 /* Link TRB. The HWO bit is never reset */
 629                 trb_st_hw = &dep->trb_pool[0];
 630
 631                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 632                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 633                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 634                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 635                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 636         }
 637
 638         /*
 639          * Issue StartTransfer here with no-op TRB so we can always rely on No
 640          * Response Update Transfer command.
 641          */
 642         if (usb_endpoint_xfer_bulk(desc)) {
 643                 struct dwc3_gadget_ep_cmd_params params;
 644                 struct dwc3_trb *trb;
 645                 dma_addr_t trb_dma;
 646                 u32 cmd;
 647
 648                 memset(&params, 0, sizeof(params));
 649                 trb = &dep->trb_pool[0];
 650                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 651
 652                 params.param0 = upper_32_bits(trb_dma);
 653                 params.param1 = lower_32_bits(trb_dma);
 654
 655                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 656
 657                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 658                 if (ret < 0)
 659                         return ret;
 660
 661                 dep->flags |= DWC3_EP_BUSY;
 662
 663                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 664                 WARN_ON_ONCE(!dep->resource_index);
 665         }
 666
 667         return 0;
 668 }
 669
 670 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 671 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 672 {
 673         struct dwc3_request             *req;
 674
 675         dwc3_stop_active_transfer(dwc, dep->number, true);
 676
 677         /* - giveback all requests to gadget driver */
 678         while (!list_empty(&dep->started_list)) {
 679                 req = next_request(&dep->started_list);
 680
 681                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 682         }
 683
 684         while (!list_empty(&dep->pending_list)) {
 685                 req = next_request(&dep->pending_list);
 686
 687                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 688         }
 689 }
 690
 691 /**
 692  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 693  * @dep: the endpoint to disable
 694  *
 695  * This function also removes requests which are currently processed ny the
 696  * hardware and those which are not yet scheduled.
 697  * Caller should take care of locking.
 698  */
 699 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 700 {
 701         struct dwc3             *dwc = dep->dwc;
 702         u32                     reg;
 703
 704         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 705
 706         dwc3_remove_requests(dwc, dep);
 707
 708         /* make sure HW endpoint isn't stalled */
 709         if (dep->flags & DWC3_EP_STALL)
 710                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 711
 712         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 713         reg &= ~DWC3_DALEPENA_EP(dep->number);
 714         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 715
 716         dep->stream_capable = false;
 717         dep->endpoint.desc = NULL;
 718         dep->comp_desc = NULL;
 719         dep->type = 0;
 720         dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
 721
 722         return 0;
 723 }
 724
 725 /* -------------------------------------------------------------------------- */
 726
 727 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 728                 const struct usb_endpoint_descriptor *desc)
 729 {
 730         return -EINVAL;
 731 }
 732
 733 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 734 {
 735         return -EINVAL;
 736 }
 737
 738 /* -------------------------------------------------------------------------- */
 739
 740 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 741                 const struct usb_endpoint_descriptor *desc)
 742 {
 743         struct dwc3_ep                  *dep;
 744         struct dwc3                     *dwc;
 745         unsigned long                   flags;
 746         int                             ret;
 747
 748         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 749                 pr_debug("dwc3: invalid parameters\n");
 750                 return -EINVAL;
 751         }
 752
 753         if (!desc->wMaxPacketSize) {
 754                 pr_debug("dwc3: missing wMaxPacketSize\n");
 755                 return -EINVAL;
 756         }
 757
 758         dep = to_dwc3_ep(ep);
 759         dwc = dep->dwc;
 760
 761         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 762                                         "%s is already enabled\n",
 763                                         dep->name))
 764                 return 0;
 765
 766         spin_lock_irqsave(&dwc->lock, flags);
 767         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 768         spin_unlock_irqrestore(&dwc->lock, flags);
 769
 770         return ret;
 771 }
 772
 773 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 774 {
 775         struct dwc3_ep                  *dep;
 776         struct dwc3                     *dwc;
 777         unsigned long                   flags;
 778         int                             ret;
 779
 780         if (!ep) {
 781                 pr_debug("dwc3: invalid parameters\n");
 782                 return -EINVAL;
 783         }
 784
 785         dep = to_dwc3_ep(ep);
 786         dwc = dep->dwc;
 787
 788         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 789                                         "%s is already disabled\n",
 790                                         dep->name))
 791                 return 0;
 792
 793         spin_lock_irqsave(&dwc->lock, flags);
 794         ret = __dwc3_gadget_ep_disable(dep);
 795         spin_unlock_irqrestore(&dwc->lock, flags);
 796
 797         return ret;
 798 }
 799
 800 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 801         gfp_t gfp_flags)
 802 {
 803         struct dwc3_request             *req;
 804         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 805
 806         req = kzalloc(sizeof(*req), gfp_flags);
 807         if (!req)
 808                 return NULL;
 809
 810         req->epnum      = dep->number;
 811         req->dep        = dep;
 812
 813         dep->allocated_requests++;
 814
 815         trace_dwc3_alloc_request(req);
 816
 817         return &req->request;
 818 }
 819
 820 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 821                 struct usb_request *request)
 822 {
 823         struct dwc3_request             *req = to_dwc3_request(request);
 824         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 825
 826         dep->allocated_requests--;
 827         trace_dwc3_free_request(req);
 828         kfree(req);
 829 }
 830
 831 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
 832
 833 /**
 834  * dwc3_prepare_one_trb - setup one TRB from one request
 835  * @dep: endpoint for which this request is prepared
 836  * @req: dwc3_request pointer
 837  */
 838 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 839                 struct dwc3_request *req, dma_addr_t dma,
 840                 unsigned length, unsigned chain, unsigned node)
 841 {
 842         struct dwc3_trb         *trb;
 843         struct dwc3             *dwc = dep->dwc;
 844         struct usb_gadget       *gadget = &dwc->gadget;
 845         enum usb_device_speed   speed = gadget->speed;
 846
 847         trb = &dep->trb_pool[dep->trb_enqueue];
 848
 849         if (!req->trb) {
 850                 dwc3_gadget_move_started_request(req);
 851                 req->trb = trb;
 852                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 853                 dep->queued_requests++;
 854         }
 855
 856         dwc3_ep_inc_enq(dep);
 857
 858         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 859         trb->bpl = lower_32_bits(dma);
 860         trb->bph = upper_32_bits(dma);
 861
 862         switch (usb_endpoint_type(dep->endpoint.desc)) {
 863         case USB_ENDPOINT_XFER_CONTROL:
 864                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 865                 break;
 866
 867         case USB_ENDPOINT_XFER_ISOC:
 868                 if (!node) {
 869                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 870
 871                         if (speed == USB_SPEED_HIGH) {
 872                                 struct usb_ep *ep = &dep->endpoint;
 873                                 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
 874                         }
 875                 } else {
 876                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 877                 }
 878
 879                 /* always enable Interrupt on Missed ISOC */
 880                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 881                 break;
 882
 883         case USB_ENDPOINT_XFER_BULK:
 884         case USB_ENDPOINT_XFER_INT:
 885                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 886                 break;
 887         default:
 888                 /*
 889                  * This is only possible with faulty memory because we
 890                  * checked it already :)
 891                  */
 892                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
 893                                 usb_endpoint_type(dep->endpoint.desc));
 894         }
 895
 896         /* always enable Continue on Short Packet */
 897         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
 898                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 899
 900                 if (req->request.short_not_ok)
 901                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 902         }
 903
 904         if ((!req->request.no_interrupt && !chain) ||
 905                         (dwc3_calc_trbs_left(dep) == 0))
 906                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 907
 908         if (chain)
 909                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 910
 911         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 912                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 913
 914         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 915
 916         trace_dwc3_prepare_trb(dep, trb);
 917 }
 918
 919 /**
 920  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
 921  * @dep: The endpoint with the TRB ring
 922  * @index: The index of the current TRB in the ring
 923  *
 924  * Returns the TRB prior to the one pointed to by the index. If the
 925  * index is 0, we will wrap backwards, skip the link TRB, and return
 926  * the one just before that.
 927  */
 928 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 929 {
 930         u8 tmp = index;
 931
 932         if (!tmp)
 933                 tmp = DWC3_TRB_NUM - 1;
 934
 935         return &dep->trb_pool[tmp - 1];
 936 }
 937
 938 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 939 {
 940         struct dwc3_trb         *tmp;
 941         u8                      trbs_left;
 942
 943         /*
 944          * If enqueue & dequeue are equal than it is either full or empty.
 945          *
 946          * One way to know for sure is if the TRB right before us has HWO bit
 947          * set or not. If it has, then we're definitely full and can't fit any
 948          * more transfers in our ring.
 949          */
 950         if (dep->trb_enqueue == dep->trb_dequeue) {
 951                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 952                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 953                         return 0;
 954
 955                 return DWC3_TRB_NUM - 1;
 956         }
 957
 958         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 959         trbs_left &= (DWC3_TRB_NUM - 1);
 960
 961         if (dep->trb_dequeue < dep->trb_enqueue)
 962                 trbs_left--;
 963
 964         return trbs_left;
 965 }
 966
 967 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 968                 struct dwc3_request *req)
 969 {
 970         struct scatterlist *sg = req->sg;
 971         struct scatterlist *s;
 972         unsigned int    length;
 973         dma_addr_t      dma;
 974         int             i;
 975
 976         for_each_sg(sg, s, req->num_pending_sgs, i) {
 977                 unsigned chain = true;
 978
 979                 length = sg_dma_len(s);
 980                 dma = sg_dma_address(s);
 981
 982                 if (sg_is_last(s))
 983                         chain = false;
 984
 985                 dwc3_prepare_one_trb(dep, req, dma, length,
 986                                 chain, i);
 987
 988                 if (!dwc3_calc_trbs_left(dep))
 989                         break;
 990         }
 991 }
 992
 993 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 994                 struct dwc3_request *req)
 995 {
 996         unsigned int    length;
 997         dma_addr_t      dma;
 998
 999         dma = req->request.dma;
1000         length = req->request.length;
1001
1002         dwc3_prepare_one_trb(dep, req, dma, length,
1003                         false, 0);
1004 }
1005
1006 /*
1007  * dwc3_prepare_trbs - setup TRBs from requests
1008  * @dep: endpoint for which requests are being prepared
1009  *
1010  * The function goes through the requests list and sets up TRBs for the
1011  * transfers. The function returns once there are no more TRBs available or
1012  * it runs out of requests.
1013  */
1014 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1015 {
1016         struct dwc3_request     *req, *n;
1017
1018         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1019
1020         if (!dwc3_calc_trbs_left(dep))
1021                 return;
1022
1023         /*
1024          * We can get in a situation where there's a request in the started list
1025          * but there weren't enough TRBs to fully kick it in the first time
1026          * around, so it has been waiting for more TRBs to be freed up.
1027          *
1028          * In that case, we should check if we have a request with pending_sgs
1029          * in the started list and prepare TRBs for that request first,
1030          * otherwise we will prepare TRBs completely out of order and that will
1031          * break things.
1032          */
1033         list_for_each_entry(req, &dep->started_list, list) {
1034                 if (req->num_pending_sgs > 0)
1035                         dwc3_prepare_one_trb_sg(dep, req);
1036
1037                 if (!dwc3_calc_trbs_left(dep))
1038                         return;
1039         }
1040
1041         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1042                 if (req->num_pending_sgs > 0)
1043                         dwc3_prepare_one_trb_sg(dep, req);
1044                 else
1045                         dwc3_prepare_one_trb_linear(dep, req);
1046
1047                 if (!dwc3_calc_trbs_left(dep))
1048                         return;
1049         }
1050 }
1051
1052 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1053 {
1054         struct dwc3_gadget_ep_cmd_params params;
1055         struct dwc3_request             *req;
1056         int                             starting;
1057         int                             ret;
1058         u32                             cmd;
1059
1060         starting = !(dep->flags & DWC3_EP_BUSY);
1061
1062         dwc3_prepare_trbs(dep);
1063         req = next_request(&dep->started_list);
1064         if (!req) {
1065                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1066                 return 0;
1067         }
1068
1069         memset(&params, 0, sizeof(params));
1070
1071         if (starting) {
1072                 params.param0 = upper_32_bits(req->trb_dma);
1073                 params.param1 = lower_32_bits(req->trb_dma);
1074                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1075                         DWC3_DEPCMD_PARAM(cmd_param);
1076         } else {
1077                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1078                         DWC3_DEPCMD_PARAM(dep->resource_index);
1079         }
1080
1081         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1082         if (ret < 0) {
1083                 /*
1084                  * FIXME we need to iterate over the list of requests
1085                  * here and stop, unmap, free and del each of the linked
1086                  * requests instead of what we do now.
1087                  */
1088                 dwc3_gadget_giveback(dep, req, ret);
1089                 return ret;
1090         }
1091
1092         dep->flags |= DWC3_EP_BUSY;
1093
1094         if (starting) {
1095                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1096                 WARN_ON_ONCE(!dep->resource_index);
1097         }
1098
1099         return 0;
1100 }
1101
1102 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1103 {
1104         u32                     reg;
1105
1106         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1107         return DWC3_DSTS_SOFFN(reg);
1108 }
1109
1110 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1111                 struct dwc3_ep *dep, u32 cur_uf)
1112 {
1113         u32 uf;
1114
1115         if (list_empty(&dep->pending_list)) {
1116                 dwc3_trace(trace_dwc3_gadget,
1117                                 "ISOC ep %s run out for requests",
1118                                 dep->name);
1119                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1120                 return;
1121         }
1122
1123         /* 4 micro frames in the future */
1124         uf = cur_uf + dep->interval * 4;
1125
1126         __dwc3_gadget_kick_transfer(dep, uf);
1127 }
1128
1129 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1130                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1131 {
1132         u32 cur_uf, mask;
1133
1134         mask = ~(dep->interval - 1);
1135         cur_uf = event->parameters & mask;
1136
1137         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1138 }
1139
1140 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1141 {
1142         struct dwc3             *dwc = dep->dwc;
1143         int                     ret;
1144
1145         if (!dep->endpoint.desc) {
1146                 dwc3_trace(trace_dwc3_gadget,
1147                                 "trying to queue request %p to disabled %s",
1148                                 &req->request, dep->endpoint.name);
1149                 return -ESHUTDOWN;
1150         }
1151
1152         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1153                                 &req->request, req->dep->name)) {
1154                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1155                                 &req->request, req->dep->name);
1156                 return -EINVAL;
1157         }
1158
1159         pm_runtime_get(dwc->dev);
1160
1161         req->request.actual     = 0;
1162         req->request.status     = -EINPROGRESS;
1163         req->direction          = dep->direction;
1164         req->epnum              = dep->number;
1165
1166         trace_dwc3_ep_queue(req);
1167
1168         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1169                         dep->direction);
1170         if (ret)
1171                 return ret;
1172
1173         req->sg                 = req->request.sg;
1174         req->num_pending_sgs    = req->request.num_mapped_sgs;
1175
1176         list_add_tail(&req->list, &dep->pending_list);
1177
1178         /*
1179          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1180          * wait for a XferNotReady event so we will know what's the current
1181          * (micro-)frame number.
1182          *
1183          * Without this trick, we are very, very likely gonna get Bus Expiry
1184          * errors which will force us issue EndTransfer command.
1185          */
1186         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1187                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1188                         if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1189                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1190                                 dep->flags = DWC3_EP_ENABLED;
1191                         } else {
1192                                 u32 cur_uf;
1193
1194                                 cur_uf = __dwc3_gadget_get_frame(dwc);
1195                                 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1196                         }
1197                 }
1198                 return 0;
1199         }
1200
1201         if (!dwc3_calc_trbs_left(dep))
1202                 return 0;
1203
1204         ret = __dwc3_gadget_kick_transfer(dep, 0);
1205         if (ret && ret != -EBUSY)
1206                 dwc3_trace(trace_dwc3_gadget,
1207                                 "%s: failed to kick transfers",
1208                                 dep->name);
1209         if (ret == -EBUSY)
1210                 ret = 0;
1211
1212         return ret;
1213 }
1214
1215 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1216                 struct usb_request *request)
1217 {
1218         dwc3_gadget_ep_free_request(ep, request);
1219 }
1220
1221 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1222 {
1223         struct dwc3_request             *req;
1224         struct usb_request              *request;
1225         struct usb_ep                   *ep = &dep->endpoint;
1226
1227         dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1228         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1229         if (!request)
1230                 return -ENOMEM;
1231
1232         request->length = 0;
1233         request->buf = dwc->zlp_buf;
1234         request->complete = __dwc3_gadget_ep_zlp_complete;
1235
1236         req = to_dwc3_request(request);
1237
1238         return __dwc3_gadget_ep_queue(dep, req);
1239 }
1240
1241 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1242         gfp_t gfp_flags)
1243 {
1244         struct dwc3_request             *req = to_dwc3_request(request);
1245         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1246         struct dwc3                     *dwc = dep->dwc;
1247
1248         unsigned long                   flags;
1249
1250         int                             ret;
1251
1252         spin_lock_irqsave(&dwc->lock, flags);
1253         ret = __dwc3_gadget_ep_queue(dep, req);
1254
1255         /*
1256          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1257          * setting request->zero, instead of doing magic, we will just queue an
1258          * extra usb_request ourselves so that it gets handled the same way as
1259          * any other request.
1260          */
1261         if (ret == 0 && request->zero && request->length &&
1262             (request->length % ep->maxpacket == 0))
1263                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1264
1265         spin_unlock_irqrestore(&dwc->lock, flags);
1266
1267         return ret;
1268 }
1269
1270 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1271                 struct usb_request *request)
1272 {
1273         struct dwc3_request             *req = to_dwc3_request(request);
1274         struct dwc3_request             *r = NULL;
1275
1276         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1277         struct dwc3                     *dwc = dep->dwc;
1278
1279         unsigned long                   flags;
1280         int                             ret = 0;
1281
1282         trace_dwc3_ep_dequeue(req);
1283
1284         spin_lock_irqsave(&dwc->lock, flags);
1285
1286         list_for_each_entry(r, &dep->pending_list, list) {
1287                 if (r == req)
1288                         break;
1289         }
1290
1291         if (r != req) {
1292                 list_for_each_entry(r, &dep->started_list, list) {
1293                         if (r == req)
1294                                 break;
1295                 }
1296                 if (r == req) {
1297                         /* wait until it is processed */
1298                         dwc3_stop_active_transfer(dwc, dep->number, true);
1299                         goto out1;
1300                 }
1301                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1302                                 request, ep->name);
1303                 ret = -EINVAL;
1304                 goto out0;
1305         }
1306
1307 out1:
1308         /* giveback the request */
1309         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1310
1311 out0:
1312         spin_unlock_irqrestore(&dwc->lock, flags);
1313
1314         return ret;
1315 }
1316
1317 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1318 {
1319         struct dwc3_gadget_ep_cmd_params        params;
1320         struct dwc3                             *dwc = dep->dwc;
1321         int                                     ret;
1322
1323         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1324                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1325                 return -EINVAL;
1326         }
1327
1328         memset(&params, 0x00, sizeof(params));
1329
1330         if (value) {
1331                 struct dwc3_trb *trb;
1332
1333                 unsigned transfer_in_flight;
1334                 unsigned started;
1335
1336                 if (dep->number > 1)
1337                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1338                 else
1339                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1340
1341                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1342                 started = !list_empty(&dep->started_list);
1343
1344                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1345                                 (!dep->direction && started))) {
1346                         dwc3_trace(trace_dwc3_gadget,
1347                                         "%s: pending request, cannot halt",
1348                                         dep->name);
1349                         return -EAGAIN;
1350                 }
1351
1352                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1353                                 &params);
1354                 if (ret)
1355                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1356                                         dep->name);
1357                 else
1358                         dep->flags |= DWC3_EP_STALL;
1359         } else {
1360
1361                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1362                 if (ret)
1363                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1364                                         dep->name);
1365                 else
1366                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1367         }
1368
1369         return ret;
1370 }
1371
1372 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1373 {
1374         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1375         struct dwc3                     *dwc = dep->dwc;
1376
1377         unsigned long                   flags;
1378
1379         int                             ret;
1380
1381         spin_lock_irqsave(&dwc->lock, flags);
1382         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1383         spin_unlock_irqrestore(&dwc->lock, flags);
1384
1385         return ret;
1386 }
1387
1388 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1389 {
1390         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1391         struct dwc3                     *dwc = dep->dwc;
1392         unsigned long                   flags;
1393         int                             ret;
1394
1395         spin_lock_irqsave(&dwc->lock, flags);
1396         dep->flags |= DWC3_EP_WEDGE;
1397
1398         if (dep->number == 0 || dep->number == 1)
1399                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1400         else
1401                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1402         spin_unlock_irqrestore(&dwc->lock, flags);
1403
1404         return ret;
1405 }
1406
1407 /* -------------------------------------------------------------------------- */
1408
1409 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1410         .bLength        = USB_DT_ENDPOINT_SIZE,
1411         .bDescriptorType = USB_DT_ENDPOINT,
1412         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1413 };
1414
1415 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1416         .enable         = dwc3_gadget_ep0_enable,
1417         .disable        = dwc3_gadget_ep0_disable,
1418         .alloc_request  = dwc3_gadget_ep_alloc_request,
1419         .free_request   = dwc3_gadget_ep_free_request,
1420         .queue          = dwc3_gadget_ep0_queue,
1421         .dequeue        = dwc3_gadget_ep_dequeue,
1422         .set_halt       = dwc3_gadget_ep0_set_halt,
1423         .set_wedge      = dwc3_gadget_ep_set_wedge,
1424 };
1425
1426 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1427         .enable         = dwc3_gadget_ep_enable,
1428         .disable        = dwc3_gadget_ep_disable,
1429         .alloc_request  = dwc3_gadget_ep_alloc_request,
1430         .free_request   = dwc3_gadget_ep_free_request,
1431         .queue          = dwc3_gadget_ep_queue,
1432         .dequeue        = dwc3_gadget_ep_dequeue,
1433         .set_halt       = dwc3_gadget_ep_set_halt,
1434         .set_wedge      = dwc3_gadget_ep_set_wedge,
1435 };
1436
1437 /* -------------------------------------------------------------------------- */
1438
1439 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1440 {
1441         struct dwc3             *dwc = gadget_to_dwc(g);
1442
1443         return __dwc3_gadget_get_frame(dwc);
1444 }
1445
1446 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1447 {
1448         int                     retries;
1449
1450         int                     ret;
1451         u32                     reg;
1452
1453         u8                      link_state;
1454         u8                      speed;
1455
1456         /*
1457          * According to the Databook Remote wakeup request should
1458          * be issued only when the device is in early suspend state.
1459          *
1460          * We can check that via USB Link State bits in DSTS register.
1461          */
1462         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1463
1464         speed = reg & DWC3_DSTS_CONNECTSPD;
1465         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1466             (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1467                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1468                 return 0;
1469         }
1470
1471         link_state = DWC3_DSTS_USBLNKST(reg);
1472
1473         switch (link_state) {
1474         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1475         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1476                 break;
1477         default:
1478                 dwc3_trace(trace_dwc3_gadget,
1479                                 "can't wakeup from '%s'",
1480                                 dwc3_gadget_link_string(link_state));
1481                 return -EINVAL;
1482         }
1483
1484         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1485         if (ret < 0) {
1486                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1487                 return ret;
1488         }
1489
1490         /* Recent versions do this automatically */
1491         if (dwc->revision < DWC3_REVISION_194A) {
1492                 /* write zeroes to Link Change Request */
1493                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1494                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1495                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1496         }
1497
1498         /* poll until Link State changes to ON */
1499         retries = 20000;
1500
1501         while (retries--) {
1502                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1503
1504                 /* in HS, means ON */
1505                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1506                         break;
1507         }
1508
1509         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1510                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1511                 return -EINVAL;
1512         }
1513
1514         return 0;
1515 }
1516
1517 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1518 {
1519         struct dwc3             *dwc = gadget_to_dwc(g);
1520         unsigned long           flags;
1521         int                     ret;
1522
1523         spin_lock_irqsave(&dwc->lock, flags);
1524         ret = __dwc3_gadget_wakeup(dwc);
1525         spin_unlock_irqrestore(&dwc->lock, flags);
1526
1527         return ret;
1528 }
1529
1530 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1531                 int is_selfpowered)
1532 {
1533         struct dwc3             *dwc = gadget_to_dwc(g);
1534         unsigned long           flags;
1535
1536         spin_lock_irqsave(&dwc->lock, flags);
1537         g->is_selfpowered = !!is_selfpowered;
1538         spin_unlock_irqrestore(&dwc->lock, flags);
1539
1540         return 0;
1541 }
1542
1543 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1544 {
1545         u32                     reg;
1546         u32                     timeout = 500;
1547
1548         if (pm_runtime_suspended(dwc->dev))
1549                 return 0;
1550
1551         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1552         if (is_on) {
1553                 if (dwc->revision <= DWC3_REVISION_187A) {
1554                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1555                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1556                 }
1557
1558                 if (dwc->revision >= DWC3_REVISION_194A)
1559                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1560                 reg |= DWC3_DCTL_RUN_STOP;
1561
1562                 if (dwc->has_hibernation)
1563                         reg |= DWC3_DCTL_KEEP_CONNECT;
1564
1565                 dwc->pullups_connected = true;
1566         } else {
1567                 reg &= ~DWC3_DCTL_RUN_STOP;
1568
1569                 if (dwc->has_hibernation && !suspend)
1570                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1571
1572                 dwc->pullups_connected = false;
1573         }
1574
1575         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1576
1577         do {
1578                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1579                 reg &= DWC3_DSTS_DEVCTRLHLT;
1580         } while (--timeout && !(!is_on ^ !reg));
1581
1582         if (!timeout)
1583                 return -ETIMEDOUT;
1584
1585         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1586                         dwc->gadget_driver
1587                         ? dwc->gadget_driver->function : "no-function",
1588                         is_on ? "connect" : "disconnect");
1589
1590         return 0;
1591 }
1592
1593 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1594 {
1595         struct dwc3             *dwc = gadget_to_dwc(g);
1596         unsigned long           flags;
1597         int                     ret;
1598
1599         is_on = !!is_on;
1600
1601         /*
1602          * Per databook, when we want to stop the gadget, if a control transfer
1603          * is still in process, complete it and get the core into setup phase.
1604          */
1605         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1606                 reinit_completion(&dwc->ep0_in_setup);
1607
1608                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1609                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1610                 if (ret == 0) {
1611                         dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1612                         return -ETIMEDOUT;
1613                 }
1614         }
1615
1616         spin_lock_irqsave(&dwc->lock, flags);
1617         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1618         spin_unlock_irqrestore(&dwc->lock, flags);
1619
1620         return ret;
1621 }
1622
1623 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1624 {
1625         u32                     reg;
1626
1627         /* Enable all but Start and End of Frame IRQs */
1628         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1629                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1630                         DWC3_DEVTEN_CMDCMPLTEN |
1631                         DWC3_DEVTEN_ERRTICERREN |
1632                         DWC3_DEVTEN_WKUPEVTEN |
1633                         DWC3_DEVTEN_CONNECTDONEEN |
1634                         DWC3_DEVTEN_USBRSTEN |
1635                         DWC3_DEVTEN_DISCONNEVTEN);
1636
1637         if (dwc->revision < DWC3_REVISION_250A)
1638                 reg |= DWC3_DEVTEN_ULSTCNGEN;
1639
1640         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1641 }
1642
1643 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1644 {
1645         /* mask all interrupts */
1646         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1647 }
1648
1649 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1650 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1651
1652 /**
1653  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1654  * dwc: pointer to our context structure
1655  *
1656  * The following looks like complex but it's actually very simple. In order to
1657  * calculate the number of packets we can burst at once on OUT transfers, we're
1658  * gonna use RxFIFO size.
1659  *
1660  * To calculate RxFIFO size we need two numbers:
1661  * MDWIDTH = size, in bits, of the internal memory bus
1662  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1663  *
1664  * Given these two numbers, the formula is simple:
1665  *
1666  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1667  *
1668  * 24 bytes is for 3x SETUP packets
1669  * 16 bytes is a clock domain crossing tolerance
1670  *
1671  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1672  */
1673 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1674 {
1675         u32 ram2_depth;
1676         u32 mdwidth;
1677         u32 nump;
1678         u32 reg;
1679
1680         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1681         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1682
1683         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1684         nump = min_t(u32, nump, 16);
1685
1686         /* update NumP */
1687         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1688         reg &= ~DWC3_DCFG_NUMP_MASK;
1689         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1690         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1691 }
1692
1693 static int __dwc3_gadget_start(struct dwc3 *dwc)
1694 {
1695         struct dwc3_ep          *dep;
1696         int                     ret = 0;
1697         u32                     reg;
1698
1699         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1700         reg &= ~(DWC3_DCFG_SPEED_MASK);
1701
1702         /**
1703          * WORKAROUND: DWC3 revision < 2.20a have an issue
1704          * which would cause metastability state on Run/Stop
1705          * bit if we try to force the IP to USB2-only mode.
1706          *
1707          * Because of that, we cannot configure the IP to any
1708          * speed other than the SuperSpeed
1709          *
1710          * Refers to:
1711          *
1712          * STAR#9000525659: Clock Domain Crossing on DCTL in
1713          * USB 2.0 Mode
1714          */
1715         if (dwc->revision < DWC3_REVISION_220A) {
1716                 reg |= DWC3_DCFG_SUPERSPEED;
1717         } else {
1718                 switch (dwc->maximum_speed) {
1719                 case USB_SPEED_LOW:
1720                         reg |= DWC3_DCFG_LOWSPEED;
1721                         break;
1722                 case USB_SPEED_FULL:
1723                         reg |= DWC3_DCFG_FULLSPEED1;
1724                         break;
1725                 case USB_SPEED_HIGH:
1726                         reg |= DWC3_DCFG_HIGHSPEED;
1727                         break;
1728                 case USB_SPEED_SUPER_PLUS:
1729                         reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1730                         break;
1731                 default:
1732                         dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1733                                 dwc->maximum_speed);
1734                         /* fall through */
1735                 case USB_SPEED_SUPER:
1736                         reg |= DWC3_DCFG_SUPERSPEED;
1737                         break;
1738                 }
1739         }
1740         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1741
1742         /*
1743          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1744          * field instead of letting dwc3 itself calculate that automatically.
1745          *
1746          * This way, we maximize the chances that we'll be able to get several
1747          * bursts of data without going through any sort of endpoint throttling.
1748          */
1749         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1750         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1751         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1752
1753         dwc3_gadget_setup_nump(dwc);
1754
1755         /* Start with SuperSpeed Default */
1756         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1757
1758         dep = dwc->eps[0];
1759         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1760                         false);
1761         if (ret) {
1762                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1763                 goto err0;
1764         }
1765
1766         dep = dwc->eps[1];
1767         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1768                         false);
1769         if (ret) {
1770                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1771                 goto err1;
1772         }
1773
1774         /* begin to receive SETUP packets */
1775         dwc->ep0state = EP0_SETUP_PHASE;
1776         dwc3_ep0_out_start(dwc);
1777
1778         dwc3_gadget_enable_irq(dwc);
1779
1780         return 0;
1781
1782 err1:
1783         __dwc3_gadget_ep_disable(dwc->eps[0]);
1784
1785 err0:
1786         return ret;
1787 }
1788
1789 static int dwc3_gadget_start(struct usb_gadget *g,
1790                 struct usb_gadget_driver *driver)
1791 {
1792         struct dwc3             *dwc = gadget_to_dwc(g);
1793         unsigned long           flags;
1794         int                     ret = 0;
1795         int                     irq;
1796
1797         irq = dwc->irq_gadget;
1798         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1799                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1800         if (ret) {
1801                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1802                                 irq, ret);
1803                 goto err0;
1804         }
1805
1806         spin_lock_irqsave(&dwc->lock, flags);
1807         if (dwc->gadget_driver) {
1808                 dev_err(dwc->dev, "%s is already bound to %s\n",
1809                                 dwc->gadget.name,
1810                                 dwc->gadget_driver->driver.name);
1811                 ret = -EBUSY;
1812                 goto err1;
1813         }
1814
1815         dwc->gadget_driver      = driver;
1816
1817         if (pm_runtime_active(dwc->dev))
1818                 __dwc3_gadget_start(dwc);
1819
1820         spin_unlock_irqrestore(&dwc->lock, flags);
1821
1822         return 0;
1823
1824 err1:
1825         spin_unlock_irqrestore(&dwc->lock, flags);
1826         free_irq(irq, dwc);
1827
1828 err0:
1829         return ret;
1830 }
1831
1832 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1833 {
1834         dwc3_gadget_disable_irq(dwc);
1835         __dwc3_gadget_ep_disable(dwc->eps[0]);
1836         __dwc3_gadget_ep_disable(dwc->eps[1]);
1837 }
1838
1839 static int dwc3_gadget_stop(struct usb_gadget *g)
1840 {
1841         struct dwc3             *dwc = gadget_to_dwc(g);
1842         unsigned long           flags;
1843         int                     epnum;
1844
1845         spin_lock_irqsave(&dwc->lock, flags);
1846
1847         if (pm_runtime_suspended(dwc->dev))
1848                 goto out;
1849
1850         __dwc3_gadget_stop(dwc);
1851
1852         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1853                 struct dwc3_ep  *dep = dwc->eps[epnum];
1854
1855                 if (!dep)
1856                         continue;
1857
1858                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1859                         continue;
1860
1861                 wait_event_lock_irq(dep->wait_end_transfer,
1862                                     !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1863                                     dwc->lock);
1864         }
1865
1866 out:
1867         dwc->gadget_driver      = NULL;
1868         spin_unlock_irqrestore(&dwc->lock, flags);
1869
1870         free_irq(dwc->irq_gadget, dwc->ev_buf);
1871
1872         return 0;
1873 }
1874
1875 static const struct usb_gadget_ops dwc3_gadget_ops = {
1876         .get_frame              = dwc3_gadget_get_frame,
1877         .wakeup                 = dwc3_gadget_wakeup,
1878         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1879         .pullup                 = dwc3_gadget_pullup,
1880         .udc_start              = dwc3_gadget_start,
1881         .udc_stop               = dwc3_gadget_stop,
1882 };
1883
1884 /* -------------------------------------------------------------------------- */
1885
1886 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1887                 u8 num, u32 direction)
1888 {
1889         struct dwc3_ep                  *dep;
1890         u8                              i;
1891
1892         for (i = 0; i < num; i++) {
1893                 u8 epnum = (i << 1) | (direction ? 1 : 0);
1894
1895                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1896                 if (!dep)
1897                         return -ENOMEM;
1898
1899                 dep->dwc = dwc;
1900                 dep->number = epnum;
1901                 dep->direction = !!direction;
1902                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1903                 dwc->eps[epnum] = dep;
1904
1905                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1906                                 (epnum & 1) ? "in" : "out");
1907
1908                 dep->endpoint.name = dep->name;
1909                 spin_lock_init(&dep->lock);
1910
1911                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1912
1913                 if (epnum == 0 || epnum == 1) {
1914                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1915                         dep->endpoint.maxburst = 1;
1916                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1917                         if (!epnum)
1918                                 dwc->gadget.ep0 = &dep->endpoint;
1919                 } else {
1920                         int             ret;
1921
1922                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1923                         dep->endpoint.max_streams = 15;
1924                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1925                         list_add_tail(&dep->endpoint.ep_list,
1926                                         &dwc->gadget.ep_list);
1927
1928                         ret = dwc3_alloc_trb_pool(dep);
1929                         if (ret)
1930                                 return ret;
1931                 }
1932
1933                 if (epnum == 0 || epnum == 1) {
1934                         dep->endpoint.caps.type_control = true;
1935                 } else {
1936                         dep->endpoint.caps.type_iso = true;
1937                         dep->endpoint.caps.type_bulk = true;
1938                         dep->endpoint.caps.type_int = true;
1939                 }
1940
1941                 dep->endpoint.caps.dir_in = !!direction;
1942                 dep->endpoint.caps.dir_out = !direction;
1943
1944                 INIT_LIST_HEAD(&dep->pending_list);
1945                 INIT_LIST_HEAD(&dep->started_list);
1946         }
1947
1948         return 0;
1949 }
1950
1951 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1952 {
1953         int                             ret;
1954
1955         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1956
1957         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1958         if (ret < 0) {
1959                 dwc3_trace(trace_dwc3_gadget,
1960                                 "failed to allocate OUT endpoints");
1961                 return ret;
1962         }
1963
1964         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1965         if (ret < 0) {
1966                 dwc3_trace(trace_dwc3_gadget,
1967                                 "failed to allocate IN endpoints");
1968                 return ret;
1969         }
1970
1971         return 0;
1972 }
1973
1974 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1975 {
1976         struct dwc3_ep                  *dep;
1977         u8                              epnum;
1978
1979         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1980                 dep = dwc->eps[epnum];
1981                 if (!dep)
1982                         continue;
1983                 /*
1984                  * Physical endpoints 0 and 1 are special; they form the
1985                  * bi-directional USB endpoint 0.
1986                  *
1987                  * For those two physical endpoints, we don't allocate a TRB
1988                  * pool nor do we add them the endpoints list. Due to that, we
1989                  * shouldn't do these two operations otherwise we would end up
1990                  * with all sorts of bugs when removing dwc3.ko.
1991                  */
1992                 if (epnum != 0 && epnum != 1) {
1993                         dwc3_free_trb_pool(dep);
1994                         list_del(&dep->endpoint.ep_list);
1995                 }
1996
1997                 kfree(dep);
1998         }
1999 }
2000
2001 /* -------------------------------------------------------------------------- */
2002
2003 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2004                 struct dwc3_request *req, struct dwc3_trb *trb,
2005                 const struct dwc3_event_depevt *event, int status,
2006                 int chain)
2007 {
2008         unsigned int            count;
2009         unsigned int            s_pkt = 0;
2010         unsigned int            trb_status;
2011
2012         dwc3_ep_inc_deq(dep);
2013
2014         if (req->trb == trb)
2015                 dep->queued_requests--;
2016
2017         trace_dwc3_complete_trb(dep, trb);
2018
2019         /*
2020          * If we're in the middle of series of chained TRBs and we
2021          * receive a short transfer along the way, DWC3 will skip
2022          * through all TRBs including the last TRB in the chain (the
2023          * where CHN bit is zero. DWC3 will also avoid clearing HWO
2024          * bit and SW has to do it manually.
2025          *
2026          * We're going to do that here to avoid problems of HW trying
2027          * to use bogus TRBs for transfers.
2028          */
2029         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2030                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2031
2032         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2033                 return 1;
2034
2035         count = trb->size & DWC3_TRB_SIZE_MASK;
2036         req->remaining += count;
2037
2038         if (dep->direction) {
2039                 if (count) {
2040                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2041                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2042                                 dwc3_trace(trace_dwc3_gadget,
2043                                                 "%s: incomplete IN transfer",
2044                                                 dep->name);
2045                                 /*
2046                                  * If missed isoc occurred and there is
2047                                  * no request queued then issue END
2048                                  * TRANSFER, so that core generates
2049                                  * next xfernotready and we will issue
2050                                  * a fresh START TRANSFER.
2051                                  * If there are still queued request
2052                                  * then wait, do not issue either END
2053                                  * or UPDATE TRANSFER, just attach next
2054                                  * request in pending_list during
2055                                  * giveback.If any future queued request
2056                                  * is successfully transferred then we
2057                                  * will issue UPDATE TRANSFER for all
2058                                  * request in the pending_list.
2059                                  */
2060                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2061                         } else {
2062                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2063                                                 dep->name);
2064                                 status = -ECONNRESET;
2065                         }
2066                 } else {
2067                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2068                 }
2069         } else {
2070                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2071                         s_pkt = 1;
2072         }
2073
2074         if (s_pkt && !chain)
2075                 return 1;
2076
2077         if ((event->status & DEPEVT_STATUS_IOC) &&
2078                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2079                 return 1;
2080
2081         return 0;
2082 }
2083
2084 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2085                 const struct dwc3_event_depevt *event, int status)
2086 {
2087         struct dwc3_request     *req, *n;
2088         struct dwc3_trb         *trb;
2089         bool                    ioc = false;
2090         int                     ret = 0;
2091
2092         list_for_each_entry_safe(req, n, &dep->started_list, list) {
2093                 unsigned length;
2094                 int chain;
2095
2096                 length = req->request.length;
2097                 chain = req->num_pending_sgs > 0;
2098                 if (chain) {
2099                         struct scatterlist *sg = req->sg;
2100                         struct scatterlist *s;
2101                         unsigned int pending = req->num_pending_sgs;
2102                         unsigned int i;
2103
2104                         for_each_sg(sg, s, pending, i) {
2105                                 trb = &dep->trb_pool[dep->trb_dequeue];
2106
2107                                 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2108                                         break;
2109
2110                                 req->sg = sg_next(s);
2111                                 req->num_pending_sgs--;
2112
2113                                 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2114                                                 event, status, chain);
2115                                 if (ret)
2116                                         break;
2117                         }
2118                 } else {
2119                         trb = &dep->trb_pool[dep->trb_dequeue];
2120                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2121                                         event, status, chain);
2122                 }
2123
2124                 req->request.actual = length - req->remaining;
2125
2126                 if ((req->request.actual < length) && req->num_pending_sgs)
2127                         return __dwc3_gadget_kick_transfer(dep, 0);
2128
2129                 dwc3_gadget_giveback(dep, req, status);
2130
2131                 if (ret) {
2132                         if ((event->status & DEPEVT_STATUS_IOC) &&
2133                             (trb->ctrl & DWC3_TRB_CTRL_IOC))
2134                                 ioc = true;
2135                         break;
2136                 }
2137         }
2138
2139         /*
2140          * Our endpoint might get disabled by another thread during
2141          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2142          * early on so DWC3_EP_BUSY flag gets cleared
2143          */
2144         if (!dep->endpoint.desc)
2145                 return 1;
2146
2147         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2148                         list_empty(&dep->started_list)) {
2149                 if (list_empty(&dep->pending_list)) {
2150                         /*
2151                          * If there is no entry in request list then do
2152                          * not issue END TRANSFER now. Just set PENDING
2153                          * flag, so that END TRANSFER is issued when an
2154                          * entry is added into request list.
2155                          */
2156                         dep->flags = DWC3_EP_PENDING_REQUEST;
2157                 } else {
2158                         dwc3_stop_active_transfer(dwc, dep->number, true);
2159                         dep->flags = DWC3_EP_ENABLED;
2160                 }
2161                 return 1;
2162         }
2163
2164         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2165                 return 0;
2166
2167         return 1;
2168 }
2169
2170 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2171                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2172 {
2173         unsigned                status = 0;
2174         int                     clean_busy;
2175         u32                     is_xfer_complete;
2176
2177         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2178
2179         if (event->status & DEPEVT_STATUS_BUSERR)
2180                 status = -ECONNRESET;
2181
2182         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2183         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2184                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2185                 dep->flags &= ~DWC3_EP_BUSY;
2186
2187         /*
2188          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2189          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2190          */
2191         if (dwc->revision < DWC3_REVISION_183A) {
2192                 u32             reg;
2193                 int             i;
2194
2195                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2196                         dep = dwc->eps[i];
2197
2198                         if (!(dep->flags & DWC3_EP_ENABLED))
2199                                 continue;
2200
2201                         if (!list_empty(&dep->started_list))
2202                                 return;
2203                 }
2204
2205                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2206                 reg |= dwc->u1u2;
2207                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2208
2209                 dwc->u1u2 = 0;
2210         }
2211
2212         /*
2213          * Our endpoint might get disabled by another thread during
2214          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2215          * early on so DWC3_EP_BUSY flag gets cleared
2216          */
2217         if (!dep->endpoint.desc)
2218                 return;
2219
2220         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2221                 int ret;
2222
2223                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2224                 if (!ret || ret == -EBUSY)
2225                         return;
2226         }
2227 }
2228
2229 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2230                 const struct dwc3_event_depevt *event)
2231 {
2232         struct dwc3_ep          *dep;
2233         u8                      epnum = event->endpoint_number;
2234         u8                      cmd;
2235
2236         dep = dwc->eps[epnum];
2237
2238         if (!(dep->flags & DWC3_EP_ENABLED) &&
2239             !(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2240                 return;
2241
2242         if (epnum == 0 || epnum == 1) {
2243                 dwc3_ep0_interrupt(dwc, event);
2244                 return;
2245         }
2246
2247         switch (event->endpoint_event) {
2248         case DWC3_DEPEVT_XFERCOMPLETE:
2249                 dep->resource_index = 0;
2250
2251                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2252                         dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2253                         return;
2254                 }
2255
2256                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2257                 break;
2258         case DWC3_DEPEVT_XFERINPROGRESS:
2259                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2260                 break;
2261         case DWC3_DEPEVT_XFERNOTREADY:
2262                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2263                         dwc3_gadget_start_isoc(dwc, dep, event);
2264                 } else {
2265                         int ret;
2266
2267                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2268                         if (!ret || ret == -EBUSY)
2269                                 return;
2270                 }
2271
2272                 break;
2273         case DWC3_DEPEVT_STREAMEVT:
2274                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2275                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2276                                         dep->name);
2277                         return;
2278                 }
2279                 break;
2280         case DWC3_DEPEVT_EPCMDCMPLT:
2281                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2282
2283                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2284                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2285                         wake_up(&dep->wait_end_transfer);
2286                 }
2287                 break;
2288         case DWC3_DEPEVT_RXTXFIFOEVT:
2289                 break;
2290         }
2291 }
2292
2293 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2294 {
2295         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2296                 spin_unlock(&dwc->lock);
2297                 dwc->gadget_driver->disconnect(&dwc->gadget);
2298                 spin_lock(&dwc->lock);
2299         }
2300 }
2301
2302 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2303 {
2304         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2305                 spin_unlock(&dwc->lock);
2306                 dwc->gadget_driver->suspend(&dwc->gadget);
2307                 spin_lock(&dwc->lock);
2308         }
2309 }
2310
2311 static void dwc3_resume_gadget(struct dwc3 *dwc)
2312 {
2313         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2314                 spin_unlock(&dwc->lock);
2315                 dwc->gadget_driver->resume(&dwc->gadget);
2316                 spin_lock(&dwc->lock);
2317         }
2318 }
2319
2320 static void dwc3_reset_gadget(struct dwc3 *dwc)
2321 {
2322         if (!dwc->gadget_driver)
2323                 return;
2324
2325         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2326                 spin_unlock(&dwc->lock);
2327                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2328                 spin_lock(&dwc->lock);
2329         }
2330 }
2331
2332 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2333 {
2334         struct dwc3_ep *dep;
2335         struct dwc3_gadget_ep_cmd_params params;
2336         u32 cmd;
2337         int ret;
2338
2339         dep = dwc->eps[epnum];
2340
2341         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2342             !dep->resource_index)
2343                 return;
2344
2345         /*
2346          * NOTICE: We are violating what the Databook says about the
2347          * EndTransfer command. Ideally we would _always_ wait for the
2348          * EndTransfer Command Completion IRQ, but that's causing too
2349          * much trouble synchronizing between us and gadget driver.
2350          *
2351          * We have discussed this with the IP Provider and it was
2352          * suggested to giveback all requests here, but give HW some
2353          * extra time to synchronize with the interconnect. We're using
2354          * an arbitrary 100us delay for that.
2355          *
2356          * Note also that a similar handling was tested by Synopsys
2357          * (thanks a lot Paul) and nothing bad has come out of it.
2358          * In short, what we're doing is:
2359          *
2360          * - Issue EndTransfer WITH CMDIOC bit set
2361          * - Wait 100us
2362          *
2363          * As of IP version 3.10a of the DWC_usb3 IP, the controller
2364          * supports a mode to work around the above limitation. The
2365          * software can poll the CMDACT bit in the DEPCMD register
2366          * after issuing a EndTransfer command. This mode is enabled
2367          * by writing GUCTL2[14]. This polling is already done in the
2368          * dwc3_send_gadget_ep_cmd() function so if the mode is
2369          * enabled, the EndTransfer command will have completed upon
2370          * returning from this function and we don't need to delay for
2371          * 100us.
2372          *
2373          * This mode is NOT available on the DWC_usb31 IP.
2374          */
2375
2376         cmd = DWC3_DEPCMD_ENDTRANSFER;
2377         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2378         cmd |= DWC3_DEPCMD_CMDIOC;
2379         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2380         memset(&params, 0, sizeof(params));
2381         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2382         WARN_ON_ONCE(ret);
2383         dep->resource_index = 0;
2384         dep->flags &= ~DWC3_EP_BUSY;
2385
2386         if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2387                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2388                 udelay(100);
2389         }
2390 }
2391
2392 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2393 {
2394         u32 epnum;
2395
2396         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2397                 struct dwc3_ep *dep;
2398                 int ret;
2399
2400                 dep = dwc->eps[epnum];
2401                 if (!dep)
2402                         continue;
2403
2404                 if (!(dep->flags & DWC3_EP_STALL))
2405                         continue;
2406
2407                 dep->flags &= ~DWC3_EP_STALL;
2408
2409                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2410                 WARN_ON_ONCE(ret);
2411         }
2412 }
2413
2414 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2415 {
2416         int                     reg;
2417
2418         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2419         reg &= ~DWC3_DCTL_INITU1ENA;
2420         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2421
2422         reg &= ~DWC3_DCTL_INITU2ENA;
2423         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2424
2425         dwc3_disconnect_gadget(dwc);
2426
2427         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2428         dwc->setup_packet_pending = false;
2429         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2430
2431         dwc->connected = false;
2432 }
2433
2434 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2435 {
2436         u32                     reg;
2437
2438         dwc->connected = true;
2439
2440         /*
2441          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2442          * would cause a missing Disconnect Event if there's a
2443          * pending Setup Packet in the FIFO.
2444          *
2445          * There's no suggested workaround on the official Bug
2446          * report, which states that "unless the driver/application
2447          * is doing any special handling of a disconnect event,
2448          * there is no functional issue".
2449          *
2450          * Unfortunately, it turns out that we _do_ some special
2451          * handling of a disconnect event, namely complete all
2452          * pending transfers, notify gadget driver of the
2453          * disconnection, and so on.
2454          *
2455          * Our suggested workaround is to follow the Disconnect
2456          * Event steps here, instead, based on a setup_packet_pending
2457          * flag. Such flag gets set whenever we have a SETUP_PENDING
2458          * status for EP0 TRBs and gets cleared on XferComplete for the
2459          * same endpoint.
2460          *
2461          * Refers to:
2462          *
2463          * STAR#9000466709: RTL: Device : Disconnect event not
2464          * generated if setup packet pending in FIFO
2465          */
2466         if (dwc->revision < DWC3_REVISION_188A) {
2467                 if (dwc->setup_packet_pending)
2468                         dwc3_gadget_disconnect_interrupt(dwc);
2469         }
2470
2471         dwc3_reset_gadget(dwc);
2472
2473         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2474         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2475         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2476         dwc->test_mode = false;
2477         dwc3_clear_stall_all_ep(dwc);
2478
2479         /* Reset device address to zero */
2480         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2481         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2482         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2483 }
2484
2485 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2486 {
2487         u32 reg;
2488         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2489
2490         /*
2491          * We change the clock only at SS but I dunno why I would want to do
2492          * this. Maybe it becomes part of the power saving plan.
2493          */
2494
2495         if ((speed != DWC3_DSTS_SUPERSPEED) &&
2496             (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2497                 return;
2498
2499         /*
2500          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2501          * each time on Connect Done.
2502          */
2503         if (!usb30_clock)
2504                 return;
2505
2506         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2507         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2508         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2509 }
2510
2511 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2512 {
2513         struct dwc3_ep          *dep;
2514         int                     ret;
2515         u32                     reg;
2516         u8                      speed;
2517
2518         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2519         speed = reg & DWC3_DSTS_CONNECTSPD;
2520         dwc->speed = speed;
2521
2522         dwc3_update_ram_clk_sel(dwc, speed);
2523
2524         switch (speed) {
2525         case DWC3_DSTS_SUPERSPEED_PLUS:
2526                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2527                 dwc->gadget.ep0->maxpacket = 512;
2528                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2529                 break;
2530         case DWC3_DSTS_SUPERSPEED:
2531                 /*
2532                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2533                  * would cause a missing USB3 Reset event.
2534                  *
2535                  * In such situations, we should force a USB3 Reset
2536                  * event by calling our dwc3_gadget_reset_interrupt()
2537                  * routine.
2538                  *
2539                  * Refers to:
2540                  *
2541                  * STAR#9000483510: RTL: SS : USB3 reset event may
2542                  * not be generated always when the link enters poll
2543                  */
2544                 if (dwc->revision < DWC3_REVISION_190A)
2545                         dwc3_gadget_reset_interrupt(dwc);
2546
2547                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2548                 dwc->gadget.ep0->maxpacket = 512;
2549                 dwc->gadget.speed = USB_SPEED_SUPER;
2550                 break;
2551         case DWC3_DSTS_HIGHSPEED:
2552                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2553                 dwc->gadget.ep0->maxpacket = 64;
2554                 dwc->gadget.speed = USB_SPEED_HIGH;
2555                 break;
2556         case DWC3_DSTS_FULLSPEED2:
2557         case DWC3_DSTS_FULLSPEED1:
2558                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2559                 dwc->gadget.ep0->maxpacket = 64;
2560                 dwc->gadget.speed = USB_SPEED_FULL;
2561                 break;
2562         case DWC3_DSTS_LOWSPEED:
2563                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2564                 dwc->gadget.ep0->maxpacket = 8;
2565                 dwc->gadget.speed = USB_SPEED_LOW;
2566                 break;
2567         }
2568
2569         /* Enable USB2 LPM Capability */
2570
2571         if ((dwc->revision > DWC3_REVISION_194A) &&
2572             (speed != DWC3_DSTS_SUPERSPEED) &&
2573             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2574                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2575                 reg |= DWC3_DCFG_LPM_CAP;
2576                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2577
2578                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2579                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2580
2581                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2582
2583                 /*
2584                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2585                  * DCFG.LPMCap is set, core responses with an ACK and the
2586                  * BESL value in the LPM token is less than or equal to LPM
2587                  * NYET threshold.
2588                  */
2589                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2590                                 && dwc->has_lpm_erratum,
2591                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2592
2593                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2594                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2595
2596                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2597         } else {
2598                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2599                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2600                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2601         }
2602
2603         dep = dwc->eps[0];
2604         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2605                         false);
2606         if (ret) {
2607                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2608                 return;
2609         }
2610
2611         dep = dwc->eps[1];
2612         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2613                         false);
2614         if (ret) {
2615                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2616                 return;
2617         }
2618
2619         /*
2620          * Configure PHY via GUSB3PIPECTLn if required.
2621          *
2622          * Update GTXFIFOSIZn
2623          *
2624          * In both cases reset values should be sufficient.
2625          */
2626 }
2627
2628 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2629 {
2630         /*
2631          * TODO take core out of low power mode when that's
2632          * implemented.
2633          */
2634
2635         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2636                 spin_unlock(&dwc->lock);
2637                 dwc->gadget_driver->resume(&dwc->gadget);
2638                 spin_lock(&dwc->lock);
2639         }
2640 }
2641
2642 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2643                 unsigned int evtinfo)
2644 {
2645         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2646         unsigned int            pwropt;
2647
2648         /*
2649          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2650          * Hibernation mode enabled which would show up when device detects
2651          * host-initiated U3 exit.
2652          *
2653          * In that case, device will generate a Link State Change Interrupt
2654          * from U3 to RESUME which is only necessary if Hibernation is
2655          * configured in.
2656          *
2657          * There are no functional changes due to such spurious event and we
2658          * just need to ignore it.
2659          *
2660          * Refers to:
2661          *
2662          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2663          * operational mode
2664          */
2665         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2666         if ((dwc->revision < DWC3_REVISION_250A) &&
2667                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2668                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2669                                 (next == DWC3_LINK_STATE_RESUME)) {
2670                         dwc3_trace(trace_dwc3_gadget,
2671                                         "ignoring transition U3 -> Resume");
2672                         return;
2673                 }
2674         }
2675
2676         /*
2677          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2678          * on the link partner, the USB session might do multiple entry/exit
2679          * of low power states before a transfer takes place.
2680          *
2681          * Due to this problem, we might experience lower throughput. The
2682          * suggested workaround is to disable DCTL[12:9] bits if we're
2683          * transitioning from U1/U2 to U0 and enable those bits again
2684          * after a transfer completes and there are no pending transfers
2685          * on any of the enabled endpoints.
2686          *
2687          * This is the first half of that workaround.
2688          *
2689          * Refers to:
2690          *
2691          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2692          * core send LGO_Ux entering U0
2693          */
2694         if (dwc->revision < DWC3_REVISION_183A) {
2695                 if (next == DWC3_LINK_STATE_U0) {
2696                         u32     u1u2;
2697                         u32     reg;
2698
2699                         switch (dwc->link_state) {
2700                         case DWC3_LINK_STATE_U1:
2701                         case DWC3_LINK_STATE_U2:
2702                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2703                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2704                                                 | DWC3_DCTL_ACCEPTU2ENA
2705                                                 | DWC3_DCTL_INITU1ENA
2706                                                 | DWC3_DCTL_ACCEPTU1ENA);
2707
2708                                 if (!dwc->u1u2)
2709                                         dwc->u1u2 = reg & u1u2;
2710
2711                                 reg &= ~u1u2;
2712
2713                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2714                                 break;
2715                         default:
2716                                 /* do nothing */
2717                                 break;
2718                         }
2719                 }
2720         }
2721
2722         switch (next) {
2723         case DWC3_LINK_STATE_U1:
2724                 if (dwc->speed == USB_SPEED_SUPER)
2725                         dwc3_suspend_gadget(dwc);
2726                 break;
2727         case DWC3_LINK_STATE_U2:
2728         case DWC3_LINK_STATE_U3:
2729                 dwc3_suspend_gadget(dwc);
2730                 break;
2731         case DWC3_LINK_STATE_RESUME:
2732                 dwc3_resume_gadget(dwc);
2733                 break;
2734         default:
2735                 /* do nothing */
2736                 break;
2737         }
2738
2739         dwc->link_state = next;
2740 }
2741
2742 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2743                                           unsigned int evtinfo)
2744 {
2745         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2746
2747         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2748                 dwc3_suspend_gadget(dwc);
2749
2750         dwc->link_state = next;
2751 }
2752
2753 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2754                 unsigned int evtinfo)
2755 {
2756         unsigned int is_ss = evtinfo & BIT(4);
2757
2758         /**
2759          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2760          * have a known issue which can cause USB CV TD.9.23 to fail
2761          * randomly.
2762          *
2763          * Because of this issue, core could generate bogus hibernation
2764          * events which SW needs to ignore.
2765          *
2766          * Refers to:
2767          *
2768          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2769          * Device Fallback from SuperSpeed
2770          */
2771         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2772                 return;
2773
2774         /* enter hibernation here */
2775 }
2776
2777 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2778                 const struct dwc3_event_devt *event)
2779 {
2780         switch (event->type) {
2781         case DWC3_DEVICE_EVENT_DISCONNECT:
2782                 dwc3_gadget_disconnect_interrupt(dwc);
2783                 break;
2784         case DWC3_DEVICE_EVENT_RESET:
2785                 dwc3_gadget_reset_interrupt(dwc);
2786                 break;
2787         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2788                 dwc3_gadget_conndone_interrupt(dwc);
2789                 break;
2790         case DWC3_DEVICE_EVENT_WAKEUP:
2791                 dwc3_gadget_wakeup_interrupt(dwc);
2792                 break;
2793         case DWC3_DEVICE_EVENT_HIBER_REQ:
2794                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2795                                         "unexpected hibernation event\n"))
2796                         break;
2797
2798                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2799                 break;
2800         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2801                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2802                 break;
2803         case DWC3_DEVICE_EVENT_EOPF:
2804                 /* It changed to be suspend event for version 2.30a and above */
2805                 if (dwc->revision < DWC3_REVISION_230A) {
2806                         dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2807                 } else {
2808                         dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event");
2809
2810                         /*
2811                          * Ignore suspend event until the gadget enters into
2812                          * USB_STATE_CONFIGURED state.
2813                          */
2814                         if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2815                                 dwc3_gadget_suspend_interrupt(dwc,
2816                                                 event->event_info);
2817                 }
2818                 break;
2819         case DWC3_DEVICE_EVENT_SOF:
2820         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2821         case DWC3_DEVICE_EVENT_CMD_CMPL:
2822         case DWC3_DEVICE_EVENT_OVERFLOW:
2823                 break;
2824         default:
2825                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2826         }
2827 }
2828
2829 static void dwc3_process_event_entry(struct dwc3 *dwc,
2830                 const union dwc3_event *event)
2831 {
2832         trace_dwc3_event(event->raw, dwc);
2833
2834         /* Endpoint IRQ, handle it and return early */
2835         if (event->type.is_devspec == 0) {
2836                 /* depevt */
2837                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2838         }
2839
2840         switch (event->type.type) {
2841         case DWC3_EVENT_TYPE_DEV:
2842                 dwc3_gadget_interrupt(dwc, &event->devt);
2843                 break;
2844         /* REVISIT what to do with Carkit and I2C events ? */
2845         default:
2846                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2847         }
2848 }
2849
2850 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2851 {
2852         struct dwc3 *dwc = evt->dwc;
2853         irqreturn_t ret = IRQ_NONE;
2854         int left;
2855         u32 reg;
2856
2857         left = evt->count;
2858
2859         if (!(evt->flags & DWC3_EVENT_PENDING))
2860                 return IRQ_NONE;
2861
2862         while (left > 0) {
2863                 union dwc3_event event;
2864
2865                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2866
2867                 dwc3_process_event_entry(dwc, &event);
2868
2869                 /*
2870                  * FIXME we wrap around correctly to the next entry as
2871                  * almost all entries are 4 bytes in size. There is one
2872                  * entry which has 12 bytes which is a regular entry
2873                  * followed by 8 bytes data. ATM I don't know how
2874                  * things are organized if we get next to the a
2875                  * boundary so I worry about that once we try to handle
2876                  * that.
2877                  */
2878                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2879                 left -= 4;
2880
2881                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2882         }
2883
2884         evt->count = 0;
2885         evt->flags &= ~DWC3_EVENT_PENDING;
2886         ret = IRQ_HANDLED;
2887
2888         /* Unmask interrupt */
2889         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2890         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2891         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2892
2893         return ret;
2894 }
2895
2896 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2897 {
2898         struct dwc3_event_buffer *evt = _evt;
2899         struct dwc3 *dwc = evt->dwc;
2900         unsigned long flags;
2901         irqreturn_t ret = IRQ_NONE;
2902
2903         spin_lock_irqsave(&dwc->lock, flags);
2904         ret = dwc3_process_event_buf(evt);
2905         spin_unlock_irqrestore(&dwc->lock, flags);
2906
2907         return ret;
2908 }
2909
2910 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2911 {
2912         struct dwc3 *dwc = evt->dwc;
2913         u32 count;
2914         u32 reg;
2915
2916         if (pm_runtime_suspended(dwc->dev)) {
2917                 pm_runtime_get(dwc->dev);
2918                 disable_irq_nosync(dwc->irq_gadget);
2919                 dwc->pending_events = true;
2920                 return IRQ_HANDLED;
2921         }
2922
2923         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2924         count &= DWC3_GEVNTCOUNT_MASK;
2925         if (!count)
2926                 return IRQ_NONE;
2927
2928         evt->count = count;
2929         evt->flags |= DWC3_EVENT_PENDING;
2930
2931         /* Mask interrupt */
2932         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2933         reg |= DWC3_GEVNTSIZ_INTMASK;
2934         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2935
2936         return IRQ_WAKE_THREAD;
2937 }
2938
2939 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2940 {
2941         struct dwc3_event_buffer        *evt = _evt;
2942
2943         return dwc3_check_event_buf(evt);
2944 }
2945
2946 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
2947 {
2948         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2949         int irq;
2950
2951         irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2952         if (irq > 0)
2953                 goto out;
2954
2955         if (irq == -EPROBE_DEFER)
2956                 goto out;
2957
2958         irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2959         if (irq > 0)
2960                 goto out;
2961
2962         if (irq == -EPROBE_DEFER)
2963                 goto out;
2964
2965         irq = platform_get_irq(dwc3_pdev, 0);
2966         if (irq > 0)
2967                 goto out;
2968
2969         if (irq != -EPROBE_DEFER)
2970                 dev_err(dwc->dev, "missing peripheral IRQ\n");
2971
2972         if (!irq)
2973                 irq = -EINVAL;
2974
2975 out:
2976         return irq;
2977 }
2978
2979 /**
2980  * dwc3_gadget_init - Initializes gadget related registers
2981  * @dwc: pointer to our controller context structure
2982  *
2983  * Returns 0 on success otherwise negative errno.
2984  */
2985 int dwc3_gadget_init(struct dwc3 *dwc)
2986 {
2987         int ret;
2988         int irq;
2989
2990         irq = dwc3_gadget_get_irq(dwc);
2991         if (irq < 0) {
2992                 ret = irq;
2993                 goto err0;
2994         }
2995
2996         dwc->irq_gadget = irq;
2997
2998         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2999                         &dwc->ctrl_req_addr, GFP_KERNEL);
3000         if (!dwc->ctrl_req) {
3001                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
3002                 ret = -ENOMEM;
3003                 goto err0;
3004         }
3005
3006         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3007                         &dwc->ep0_trb_addr, GFP_KERNEL);
3008         if (!dwc->ep0_trb) {
3009                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3010                 ret = -ENOMEM;
3011                 goto err1;
3012         }
3013
3014         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
3015         if (!dwc->setup_buf) {
3016                 ret = -ENOMEM;
3017                 goto err2;
3018         }
3019
3020         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3021                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3022                         GFP_KERNEL);
3023         if (!dwc->ep0_bounce) {
3024                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3025                 ret = -ENOMEM;
3026                 goto err3;
3027         }
3028
3029         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3030         if (!dwc->zlp_buf) {
3031                 ret = -ENOMEM;
3032                 goto err4;
3033         }
3034
3035         init_completion(&dwc->ep0_in_setup);
3036
3037         dwc->gadget.ops                 = &dwc3_gadget_ops;
3038         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
3039         dwc->gadget.sg_supported        = true;
3040         dwc->gadget.name                = "dwc3-gadget";
3041         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
3042
3043         /*
3044          * FIXME We might be setting max_speed to <SUPER, however versions
3045          * <2.20a of dwc3 have an issue with metastability (documented
3046          * elsewhere in this driver) which tells us we can't set max speed to
3047          * anything lower than SUPER.
3048          *
3049          * Because gadget.max_speed is only used by composite.c and function
3050          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3051          * to happen so we avoid sending SuperSpeed Capability descriptor
3052          * together with our BOS descriptor as that could confuse host into
3053          * thinking we can handle super speed.
3054          *
3055          * Note that, in fact, we won't even support GetBOS requests when speed
3056          * is less than super speed because we don't have means, yet, to tell
3057          * composite.c that we are USB 2.0 + LPM ECN.
3058          */
3059         if (dwc->revision < DWC3_REVISION_220A)
3060                 dwc3_trace(trace_dwc3_gadget,
3061                                 "Changing max_speed on rev %08x",
3062                                 dwc->revision);
3063
3064         dwc->gadget.max_speed           = dwc->maximum_speed;
3065
3066         /*
3067          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3068          * on ep out.
3069          */
3070         dwc->gadget.quirk_ep_out_aligned_size = true;
3071
3072         /*
3073          * REVISIT: Here we should clear all pending IRQs to be
3074          * sure we're starting from a well known location.
3075          */
3076
3077         ret = dwc3_gadget_init_endpoints(dwc);
3078         if (ret)
3079                 goto err5;
3080
3081         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3082         if (ret) {
3083                 dev_err(dwc->dev, "failed to register udc\n");
3084                 goto err5;
3085         }
3086
3087         return 0;
3088
3089 err5:
3090         kfree(dwc->zlp_buf);
3091
3092 err4:
3093         dwc3_gadget_free_endpoints(dwc);
3094         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3095                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3096
3097 err3:
3098         kfree(dwc->setup_buf);
3099
3100 err2:
3101         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3102                         dwc->ep0_trb, dwc->ep0_trb_addr);
3103
3104 err1:
3105         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3106                         dwc->ctrl_req, dwc->ctrl_req_addr);
3107
3108 err0:
3109         return ret;
3110 }
3111
3112 /* -------------------------------------------------------------------------- */
3113
3114 void dwc3_gadget_exit(struct dwc3 *dwc)
3115 {
3116         usb_del_gadget_udc(&dwc->gadget);
3117
3118         dwc3_gadget_free_endpoints(dwc);
3119
3120         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3121                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3122
3123         kfree(dwc->setup_buf);
3124         kfree(dwc->zlp_buf);
3125
3126         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3127                         dwc->ep0_trb, dwc->ep0_trb_addr);
3128
3129         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3130                         dwc->ctrl_req, dwc->ctrl_req_addr);
3131 }
3132
3133 int dwc3_gadget_suspend(struct dwc3 *dwc)
3134 {
3135         int ret;
3136
3137         if (!dwc->gadget_driver)
3138                 return 0;
3139
3140         ret = dwc3_gadget_run_stop(dwc, false, false);
3141         if (ret < 0)
3142                 return ret;
3143
3144         dwc3_disconnect_gadget(dwc);
3145         __dwc3_gadget_stop(dwc);
3146
3147         return 0;
3148 }
3149
3150 int dwc3_gadget_resume(struct dwc3 *dwc)
3151 {
3152         int                     ret;
3153
3154         if (!dwc->gadget_driver)
3155                 return 0;
3156
3157         ret = __dwc3_gadget_start(dwc);
3158         if (ret < 0)
3159                 goto err0;
3160
3161         ret = dwc3_gadget_run_stop(dwc, true, false);
3162         if (ret < 0)
3163                 goto err1;
3164
3165         return 0;
3166
3167 err1:
3168         __dwc3_gadget_stop(dwc);
3169
3170 err0:
3171         return ret;
3172 }
3173
3174 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3175 {
3176         if (dwc->pending_events) {
3177                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3178                 dwc->pending_events = false;
3179                 enable_irq(dwc->irq_gadget);
3180         }
3181 }