drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.
  48  */
  49
  50 /**
  51  * amdgpu_fence_write - write a fence value
  52  *
  53  * @ring: ring the fence is associated with
  54  * @seq: sequence number to write
  55  *
  56  * Writes a fence value to memory (all asics).
  57  */
  58 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  59 {
  60         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  61
  62         if (drv->cpu_addr)
  63                 *drv->cpu_addr = cpu_to_le32(seq);
  64 }
  65
  66 /**
  67  * amdgpu_fence_read - read a fence value
  68  *
  69  * @ring: ring the fence is associated with
  70  *
  71  * Reads a fence value from memory (all asics).
  72  * Returns the value of the fence read from memory.
  73  */
  74 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
  75 {
  76         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  77         u32 seq = 0;
  78
  79         if (drv->cpu_addr)
  80                 seq = le32_to_cpu(*drv->cpu_addr);
  81         else
  82                 seq = lower_32_bits(atomic64_read(&drv->last_seq));
  83
  84         return seq;
  85 }
  86
  87 /**
  88  * amdgpu_fence_schedule_check - schedule lockup check
  89  *
  90  * @ring: pointer to struct amdgpu_ring
  91  *
  92  * Queues a delayed work item to check for lockups.
  93  */
  94 static void amdgpu_fence_schedule_check(struct amdgpu_ring *ring)
  95 {
  96         /*
  97          * Do not reset the timer here with mod_delayed_work,
  98          * this can livelock in an interaction with TTM delayed destroy.
  99          */
 100         queue_delayed_work(system_power_efficient_wq,
 101                 &ring->fence_drv.lockup_work,
 102                 AMDGPU_FENCE_JIFFIES_TIMEOUT);
 103 }
 104
 105 /**
 106  * amdgpu_fence_emit - emit a fence on the requested ring
 107  *
 108  * @ring: ring the fence is associated with
 109  * @owner: creator of the fence
 110  * @fence: amdgpu fence object
 111  *
 112  * Emits a fence command on the requested ring (all asics).
 113  * Returns 0 on success, -ENOMEM on failure.
 114  */
 115 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
 116                       struct amdgpu_fence **fence)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         /* we are protected by the ring emission mutex */
 121         *fence = kmalloc(sizeof(struct amdgpu_fence), GFP_KERNEL);
 122         if ((*fence) == NULL) {
 123                 return -ENOMEM;
 124         }
 125         (*fence)->seq = ++ring->fence_drv.sync_seq[ring->idx];
 126         (*fence)->ring = ring;
 127         (*fence)->owner = owner;
 128         fence_init(&(*fence)->base, &amdgpu_fence_ops,
 129                 &adev->fence_queue.lock, adev->fence_context + ring->idx,
 130                 (*fence)->seq);
 131         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 132                                (*fence)->seq,
 133                                AMDGPU_FENCE_FLAG_INT);
 134         trace_amdgpu_fence_emit(ring->adev->ddev, ring->idx, (*fence)->seq);
 135         return 0;
 136 }
 137
 138 /**
 139  * amdgpu_fence_check_signaled - callback from fence_queue
 140  *
 141  * this function is called with fence_queue lock held, which is also used
 142  * for the fence locking itself, so unlocked variants are used for
 143  * fence_signal, and remove_wait_queue.
 144  */
 145 static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
 146 {
 147         struct amdgpu_fence *fence;
 148         struct amdgpu_device *adev;
 149         u64 seq;
 150         int ret;
 151
 152         fence = container_of(wait, struct amdgpu_fence, fence_wake);
 153         adev = fence->ring->adev;
 154
 155         /*
 156          * We cannot use amdgpu_fence_process here because we're already
 157          * in the waitqueue, in a call from wake_up_all.
 158          */
 159         seq = atomic64_read(&fence->ring->fence_drv.last_seq);
 160         if (seq >= fence->seq) {
 161                 ret = fence_signal_locked(&fence->base);
 162                 if (!ret)
 163                         FENCE_TRACE(&fence->base, "signaled from irq context\n");
 164                 else
 165                         FENCE_TRACE(&fence->base, "was already signaled\n");
 166
 167                 __remove_wait_queue(&adev->fence_queue, &fence->fence_wake);
 168                 fence_put(&fence->base);
 169         } else
 170                 FENCE_TRACE(&fence->base, "pending\n");
 171         return 0;
 172 }
 173
 174 /**
 175  * amdgpu_fence_activity - check for fence activity
 176  *
 177  * @ring: pointer to struct amdgpu_ring
 178  *
 179  * Checks the current fence value and calculates the last
 180  * signalled fence value. Returns true if activity occured
 181  * on the ring, and the fence_queue should be waken up.
 182  */
 183 static bool amdgpu_fence_activity(struct amdgpu_ring *ring)
 184 {
 185         uint64_t seq, last_seq, last_emitted;
 186         unsigned count_loop = 0;
 187         bool wake = false;
 188
 189         /* Note there is a scenario here for an infinite loop but it's
 190          * very unlikely to happen. For it to happen, the current polling
 191          * process need to be interrupted by another process and another
 192          * process needs to update the last_seq btw the atomic read and
 193          * xchg of the current process.
 194          *
 195          * More over for this to go in infinite loop there need to be
 196          * continuously new fence signaled ie amdgpu_fence_read needs
 197          * to return a different value each time for both the currently
 198          * polling process and the other process that xchg the last_seq
 199          * btw atomic read and xchg of the current process. And the
 200          * value the other process set as last seq must be higher than
 201          * the seq value we just read. Which means that current process
 202          * need to be interrupted after amdgpu_fence_read and before
 203          * atomic xchg.
 204          *
 205          * To be even more safe we count the number of time we loop and
 206          * we bail after 10 loop just accepting the fact that we might
 207          * have temporarly set the last_seq not to the true real last
 208          * seq but to an older one.
 209          */
 210         last_seq = atomic64_read(&ring->fence_drv.last_seq);
 211         do {
 212                 last_emitted = ring->fence_drv.sync_seq[ring->idx];
 213                 seq = amdgpu_fence_read(ring);
 214                 seq |= last_seq & 0xffffffff00000000LL;
 215                 if (seq < last_seq) {
 216                         seq &= 0xffffffff;
 217                         seq |= last_emitted & 0xffffffff00000000LL;
 218                 }
 219
 220                 if (seq <= last_seq || seq > last_emitted) {
 221                         break;
 222                 }
 223                 /* If we loop over we don't want to return without
 224                  * checking if a fence is signaled as it means that the
 225                  * seq we just read is different from the previous on.
 226                  */
 227                 wake = true;
 228                 last_seq = seq;
 229                 if ((count_loop++) > 10) {
 230                         /* We looped over too many time leave with the
 231                          * fact that we might have set an older fence
 232                          * seq then the current real last seq as signaled
 233                          * by the hw.
 234                          */
 235                         break;
 236                 }
 237         } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
 238
 239         if (seq < last_emitted)
 240                 amdgpu_fence_schedule_check(ring);
 241
 242         return wake;
 243 }
 244
 245 /**
 246  * amdgpu_fence_check_lockup - check for hardware lockup
 247  *
 248  * @work: delayed work item
 249  *
 250  * Checks for fence activity and if there is none probe
 251  * the hardware if a lockup occured.
 252  */
 253 static void amdgpu_fence_check_lockup(struct work_struct *work)
 254 {
 255         struct amdgpu_fence_driver *fence_drv;
 256         struct amdgpu_ring *ring;
 257
 258         fence_drv = container_of(work, struct amdgpu_fence_driver,
 259                                 lockup_work.work);
 260         ring = fence_drv->ring;
 261
 262         if (!down_read_trylock(&ring->adev->exclusive_lock)) {
 263                 /* just reschedule the check if a reset is going on */
 264                 amdgpu_fence_schedule_check(ring);
 265                 return;
 266         }
 267
 268         if (amdgpu_fence_activity(ring))
 269                 wake_up_all(&ring->adev->fence_queue);
 270         else if (amdgpu_ring_is_lockup(ring)) {
 271                 /* good news we believe it's a lockup */
 272                 dev_warn(ring->adev->dev, "GPU lockup (current fence id "
 273                         "0x%016llx last fence id 0x%016llx on ring %d)\n",
 274                         (uint64_t)atomic64_read(&fence_drv->last_seq),
 275                         fence_drv->sync_seq[ring->idx], ring->idx);
 276
 277                 /* remember that we need an reset */
 278                 ring->adev->needs_reset = true;
 279                 wake_up_all(&ring->adev->fence_queue);
 280         }
 281         up_read(&ring->adev->exclusive_lock);
 282 }
 283
 284 /**
 285  * amdgpu_fence_process - process a fence
 286  *
 287  * @adev: amdgpu_device pointer
 288  * @ring: ring index the fence is associated with
 289  *
 290  * Checks the current fence value and wakes the fence queue
 291  * if the sequence number has increased (all asics).
 292  */
 293 void amdgpu_fence_process(struct amdgpu_ring *ring)
 294 {
 295         uint64_t seq, last_seq, last_emitted;
 296         unsigned count_loop = 0;
 297         bool wake = false;
 298
 299         /* Note there is a scenario here for an infinite loop but it's
 300          * very unlikely to happen. For it to happen, the current polling
 301          * process need to be interrupted by another process and another
 302          * process needs to update the last_seq btw the atomic read and
 303          * xchg of the current process.
 304          *
 305          * More over for this to go in infinite loop there need to be
 306          * continuously new fence signaled ie amdgpu_fence_read needs
 307          * to return a different value each time for both the currently
 308          * polling process and the other process that xchg the last_seq
 309          * btw atomic read and xchg of the current process. And the
 310          * value the other process set as last seq must be higher than
 311          * the seq value we just read. Which means that current process
 312          * need to be interrupted after amdgpu_fence_read and before
 313          * atomic xchg.
 314          *
 315          * To be even more safe we count the number of time we loop and
 316          * we bail after 10 loop just accepting the fact that we might
 317          * have temporarly set the last_seq not to the true real last
 318          * seq but to an older one.
 319          */
 320         last_seq = atomic64_read(&ring->fence_drv.last_seq);
 321         do {
 322                 last_emitted = ring->fence_drv.sync_seq[ring->idx];
 323                 seq = amdgpu_fence_read(ring);
 324                 seq |= last_seq & 0xffffffff00000000LL;
 325                 if (seq < last_seq) {
 326                         seq &= 0xffffffff;
 327                         seq |= last_emitted & 0xffffffff00000000LL;
 328                 }
 329
 330                 if (seq <= last_seq || seq > last_emitted) {
 331                         break;
 332                 }
 333                 /* If we loop over we don't want to return without
 334                  * checking if a fence is signaled as it means that the
 335                  * seq we just read is different from the previous on.
 336                  */
 337                 wake = true;
 338                 last_seq = seq;
 339                 if ((count_loop++) > 10) {
 340                         /* We looped over too many time leave with the
 341                          * fact that we might have set an older fence
 342                          * seq then the current real last seq as signaled
 343                          * by the hw.
 344                          */
 345                         break;
 346                 }
 347         } while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
 348
 349         if (wake)
 350                 wake_up_all(&ring->adev->fence_queue);
 351 }
 352
 353 /**
 354  * amdgpu_fence_seq_signaled - check if a fence sequence number has signaled
 355  *
 356  * @ring: ring the fence is associated with
 357  * @seq: sequence number
 358  *
 359  * Check if the last signaled fence sequnce number is >= the requested
 360  * sequence number (all asics).
 361  * Returns true if the fence has signaled (current fence value
 362  * is >= requested value) or false if it has not (current fence
 363  * value is < the requested value.  Helper function for
 364  * amdgpu_fence_signaled().
 365  */
 366 static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
 367 {
 368         if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
 369                 return true;
 370
 371         /* poll new last sequence at least once */
 372         amdgpu_fence_process(ring);
 373         if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
 374                 return true;
 375
 376         return false;
 377 }
 378
 379 static bool amdgpu_fence_is_signaled(struct fence *f)
 380 {
 381         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 382         struct amdgpu_ring *ring = fence->ring;
 383         struct amdgpu_device *adev = ring->adev;
 384
 385         if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
 386                 return true;
 387
 388         if (down_read_trylock(&adev->exclusive_lock)) {
 389                 amdgpu_fence_process(ring);
 390                 up_read(&adev->exclusive_lock);
 391
 392                 if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
 393                         return true;
 394         }
 395         return false;
 396 }
 397
 398 /**
 399  * amdgpu_fence_enable_signaling - enable signalling on fence
 400  * @fence: fence
 401  *
 402  * This function is called with fence_queue lock held, and adds a callback
 403  * to fence_queue that checks if this fence is signaled, and if so it
 404  * signals the fence and removes itself.
 405  */
 406 static bool amdgpu_fence_enable_signaling(struct fence *f)
 407 {
 408         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 409         struct amdgpu_ring *ring = fence->ring;
 410         struct amdgpu_device *adev = ring->adev;
 411
 412         if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
 413                 return false;
 414
 415         fence->fence_wake.flags = 0;
 416         fence->fence_wake.private = NULL;
 417         fence->fence_wake.func = amdgpu_fence_check_signaled;
 418         __add_wait_queue(&adev->fence_queue, &fence->fence_wake);
 419         fence_get(f);
 420         FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 421         return true;
 422 }
 423
 424 /**
 425  * amdgpu_fence_signaled - check if a fence has signaled
 426  *
 427  * @fence: amdgpu fence object
 428  *
 429  * Check if the requested fence has signaled (all asics).
 430  * Returns true if the fence has signaled or false if it has not.
 431  */
 432 bool amdgpu_fence_signaled(struct amdgpu_fence *fence)
 433 {
 434         if (!fence)
 435                 return true;
 436
 437         if (amdgpu_fence_seq_signaled(fence->ring, fence->seq)) {
 438                 if (!fence_signal(&fence->base))
 439                         FENCE_TRACE(&fence->base, "signaled from amdgpu_fence_signaled\n");
 440                 return true;
 441         }
 442
 443         return false;
 444 }
 445
 446 /**
 447  * amdgpu_fence_any_seq_signaled - check if any sequence number is signaled
 448  *
 449  * @adev: amdgpu device pointer
 450  * @seq: sequence numbers
 451  *
 452  * Check if the last signaled fence sequnce number is >= the requested
 453  * sequence number (all asics).
 454  * Returns true if any has signaled (current value is >= requested value)
 455  * or false if it has not. Helper function for amdgpu_fence_wait_seq.
 456  */
 457 static bool amdgpu_fence_any_seq_signaled(struct amdgpu_device *adev, u64 *seq)
 458 {
 459         unsigned i;
 460
 461         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 462                 if (!adev->rings[i] || !seq[i])
 463                         continue;
 464
 465                 if (amdgpu_fence_seq_signaled(adev->rings[i], seq[i]))
 466                         return true;
 467         }
 468
 469         return false;
 470 }
 471
 472 /**
 473  * amdgpu_fence_wait_seq_timeout - wait for a specific sequence numbers
 474  *
 475  * @adev: amdgpu device pointer
 476  * @target_seq: sequence number(s) we want to wait for
 477  * @intr: use interruptable sleep
 478  * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
 479  *
 480  * Wait for the requested sequence number(s) to be written by any ring
 481  * (all asics).  Sequnce number array is indexed by ring id.
 482  * @intr selects whether to use interruptable (true) or non-interruptable
 483  * (false) sleep when waiting for the sequence number.  Helper function
 484  * for amdgpu_fence_wait_*().
 485  * Returns remaining time if the sequence number has passed, 0 when
 486  * the wait timeout, or an error for all other cases.
 487  * -EDEADLK is returned when a GPU lockup has been detected.
 488  */
 489 static long amdgpu_fence_wait_seq_timeout(struct amdgpu_device *adev,
 490                                           u64 *target_seq, bool intr,
 491                                           long timeout)
 492 {
 493         uint64_t last_seq[AMDGPU_MAX_RINGS];
 494         bool signaled;
 495         int i;
 496         long r;
 497
 498         if (timeout == 0) {
 499                 return amdgpu_fence_any_seq_signaled(adev, target_seq);
 500         }
 501
 502         while (!amdgpu_fence_any_seq_signaled(adev, target_seq)) {
 503
 504                 /* Save current sequence values, used to check for GPU lockups */
 505                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 506                         struct amdgpu_ring *ring = adev->rings[i];
 507
 508                         if (!ring || !target_seq[i])
 509                                 continue;
 510
 511                         last_seq[i] = atomic64_read(&ring->fence_drv.last_seq);
 512                         trace_amdgpu_fence_wait_begin(adev->ddev, i, target_seq[i]);
 513                 }
 514
 515                 if (intr) {
 516                         r = wait_event_interruptible_timeout(adev->fence_queue, (
 517                                 (signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
 518                                  || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
 519                 } else {
 520                         r = wait_event_timeout(adev->fence_queue, (
 521                                 (signaled = amdgpu_fence_any_seq_signaled(adev, target_seq))
 522                                  || adev->needs_reset), AMDGPU_FENCE_JIFFIES_TIMEOUT);
 523                 }
 524
 525                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 526                         struct amdgpu_ring *ring = adev->rings[i];
 527
 528                         if (!ring || !target_seq[i])
 529                                 continue;
 530
 531                         trace_amdgpu_fence_wait_end(adev->ddev, i, target_seq[i]);
 532                 }
 533
 534                 if (unlikely(r < 0))
 535                         return r;
 536
 537                 if (unlikely(!signaled)) {
 538
 539                         if (adev->needs_reset)
 540                                 return -EDEADLK;
 541
 542                         /* we were interrupted for some reason and fence
 543                          * isn't signaled yet, resume waiting */
 544                         if (r)
 545                                 continue;
 546
 547                         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 548                                 struct amdgpu_ring *ring = adev->rings[i];
 549
 550                                 if (!ring || !target_seq[i])
 551                                         continue;
 552
 553                                 if (last_seq[i] != atomic64_read(&ring->fence_drv.last_seq))
 554                                         break;
 555                         }
 556
 557                         if (i != AMDGPU_MAX_RINGS)
 558                                 continue;
 559
 560                         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 561                                 if (!adev->rings[i] || !target_seq[i])
 562                                         continue;
 563
 564                                 if (amdgpu_ring_is_lockup(adev->rings[i]))
 565                                         break;
 566                         }
 567
 568                         if (i < AMDGPU_MAX_RINGS) {
 569                                 /* good news we believe it's a lockup */
 570                                 dev_warn(adev->dev, "GPU lockup (waiting for "
 571                                          "0x%016llx last fence id 0x%016llx on"
 572                                          " ring %d)\n",
 573                                          target_seq[i], last_seq[i], i);
 574
 575                                 /* remember that we need an reset */
 576                                 adev->needs_reset = true;
 577                                 wake_up_all(&adev->fence_queue);
 578                                 return -EDEADLK;
 579                         }
 580
 581                         if (timeout < MAX_SCHEDULE_TIMEOUT) {
 582                                 timeout -= AMDGPU_FENCE_JIFFIES_TIMEOUT;
 583                                 if (timeout <= 0) {
 584                                         return 0;
 585                                 }
 586                         }
 587                 }
 588         }
 589         return timeout;
 590 }
 591
 592 /**
 593  * amdgpu_fence_wait - wait for a fence to signal
 594  *
 595  * @fence: amdgpu fence object
 596  * @intr: use interruptable sleep
 597  *
 598  * Wait for the requested fence to signal (all asics).
 599  * @intr selects whether to use interruptable (true) or non-interruptable
 600  * (false) sleep when waiting for the fence.
 601  * Returns 0 if the fence has passed, error for all other cases.
 602  */
 603 int amdgpu_fence_wait(struct amdgpu_fence *fence, bool intr)
 604 {
 605         uint64_t seq[AMDGPU_MAX_RINGS] = {};
 606         long r;
 607
 608         seq[fence->ring->idx] = fence->seq;
 609         r = amdgpu_fence_wait_seq_timeout(fence->ring->adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
 610         if (r < 0) {
 611                 return r;
 612         }
 613
 614         r = fence_signal(&fence->base);
 615         if (!r)
 616                 FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
 617         return 0;
 618 }
 619
 620 /**
 621  * amdgpu_fence_wait_any - wait for a fence to signal on any ring
 622  *
 623  * @adev: amdgpu device pointer
 624  * @fences: amdgpu fence object(s)
 625  * @intr: use interruptable sleep
 626  *
 627  * Wait for any requested fence to signal (all asics).  Fence
 628  * array is indexed by ring id.  @intr selects whether to use
 629  * interruptable (true) or non-interruptable (false) sleep when
 630  * waiting for the fences. Used by the suballocator.
 631  * Returns 0 if any fence has passed, error for all other cases.
 632  */
 633 int amdgpu_fence_wait_any(struct amdgpu_device *adev,
 634                           struct amdgpu_fence **fences,
 635                           bool intr)
 636 {
 637         uint64_t seq[AMDGPU_MAX_RINGS];
 638         unsigned i, num_rings = 0;
 639         long r;
 640
 641         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 642                 seq[i] = 0;
 643
 644                 if (!fences[i]) {
 645                         continue;
 646                 }
 647
 648                 seq[i] = fences[i]->seq;
 649                 ++num_rings;
 650         }
 651
 652         /* nothing to wait for ? */
 653         if (num_rings == 0)
 654                 return -ENOENT;
 655
 656         r = amdgpu_fence_wait_seq_timeout(adev, seq, intr, MAX_SCHEDULE_TIMEOUT);
 657         if (r < 0) {
 658                 return r;
 659         }
 660         return 0;
 661 }
 662
 663 /**
 664  * amdgpu_fence_wait_next - wait for the next fence to signal
 665  *
 666  * @adev: amdgpu device pointer
 667  * @ring: ring index the fence is associated with
 668  *
 669  * Wait for the next fence on the requested ring to signal (all asics).
 670  * Returns 0 if the next fence has passed, error for all other cases.
 671  * Caller must hold ring lock.
 672  */
 673 int amdgpu_fence_wait_next(struct amdgpu_ring *ring)
 674 {
 675         uint64_t seq[AMDGPU_MAX_RINGS] = {};
 676         long r;
 677
 678         seq[ring->idx] = atomic64_read(&ring->fence_drv.last_seq) + 1ULL;
 679         if (seq[ring->idx] >= ring->fence_drv.sync_seq[ring->idx]) {
 680                 /* nothing to wait for, last_seq is
 681                    already the last emited fence */
 682                 return -ENOENT;
 683         }
 684         r = amdgpu_fence_wait_seq_timeout(ring->adev, seq, false, MAX_SCHEDULE_TIMEOUT);
 685         if (r < 0)
 686                 return r;
 687         return 0;
 688 }
 689
 690 /**
 691  * amdgpu_fence_wait_empty - wait for all fences to signal
 692  *
 693  * @adev: amdgpu device pointer
 694  * @ring: ring index the fence is associated with
 695  *
 696  * Wait for all fences on the requested ring to signal (all asics).
 697  * Returns 0 if the fences have passed, error for all other cases.
 698  * Caller must hold ring lock.
 699  */
 700 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 701 {
 702         struct amdgpu_device *adev = ring->adev;
 703         uint64_t seq[AMDGPU_MAX_RINGS] = {};
 704         long r;
 705
 706         seq[ring->idx] = ring->fence_drv.sync_seq[ring->idx];
 707         if (!seq[ring->idx])
 708                 return 0;
 709
 710         r = amdgpu_fence_wait_seq_timeout(adev, seq, false, MAX_SCHEDULE_TIMEOUT);
 711         if (r < 0) {
 712                 if (r == -EDEADLK)
 713                         return -EDEADLK;
 714
 715                 dev_err(adev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
 716                         ring->idx, r);
 717         }
 718         return 0;
 719 }
 720
 721 /**
 722  * amdgpu_fence_ref - take a ref on a fence
 723  *
 724  * @fence: amdgpu fence object
 725  *
 726  * Take a reference on a fence (all asics).
 727  * Returns the fence.
 728  */
 729 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence)
 730 {
 731         fence_get(&fence->base);
 732         return fence;
 733 }
 734
 735 /**
 736  * amdgpu_fence_unref - remove a ref on a fence
 737  *
 738  * @fence: amdgpu fence object
 739  *
 740  * Remove a reference on a fence (all asics).
 741  */
 742 void amdgpu_fence_unref(struct amdgpu_fence **fence)
 743 {
 744         struct amdgpu_fence *tmp = *fence;
 745
 746         *fence = NULL;
 747         if (tmp)
 748                 fence_put(&tmp->base);
 749 }
 750
 751 /**
 752  * amdgpu_fence_count_emitted - get the count of emitted fences
 753  *
 754  * @ring: ring the fence is associated with
 755  *
 756  * Get the number of fences emitted on the requested ring (all asics).
 757  * Returns the number of emitted fences on the ring.  Used by the
 758  * dynpm code to ring track activity.
 759  */
 760 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 761 {
 762         uint64_t emitted;
 763
 764         /* We are not protected by ring lock when reading the last sequence
 765          * but it's ok to report slightly wrong fence count here.
 766          */
 767         amdgpu_fence_process(ring);
 768         emitted = ring->fence_drv.sync_seq[ring->idx]
 769                 - atomic64_read(&ring->fence_drv.last_seq);
 770         /* to avoid 32bits warp around */
 771         if (emitted > 0x10000000)
 772                 emitted = 0x10000000;
 773
 774         return (unsigned)emitted;
 775 }
 776
 777 /**
 778  * amdgpu_fence_need_sync - do we need a semaphore
 779  *
 780  * @fence: amdgpu fence object
 781  * @dst_ring: which ring to check against
 782  *
 783  * Check if the fence needs to be synced against another ring
 784  * (all asics).  If so, we need to emit a semaphore.
 785  * Returns true if we need to sync with another ring, false if
 786  * not.
 787  */
 788 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
 789                             struct amdgpu_ring *dst_ring)
 790 {
 791         struct amdgpu_fence_driver *fdrv;
 792
 793         if (!fence)
 794                 return false;
 795
 796         if (fence->ring == dst_ring)
 797                 return false;
 798
 799         /* we are protected by the ring mutex */
 800         fdrv = &dst_ring->fence_drv;
 801         if (fence->seq <= fdrv->sync_seq[fence->ring->idx])
 802                 return false;
 803
 804         return true;
 805 }
 806
 807 /**
 808  * amdgpu_fence_note_sync - record the sync point
 809  *
 810  * @fence: amdgpu fence object
 811  * @dst_ring: which ring to check against
 812  *
 813  * Note the sequence number at which point the fence will
 814  * be synced with the requested ring (all asics).
 815  */
 816 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
 817                             struct amdgpu_ring *dst_ring)
 818 {
 819         struct amdgpu_fence_driver *dst, *src;
 820         unsigned i;
 821
 822         if (!fence)
 823                 return;
 824
 825         if (fence->ring == dst_ring)
 826                 return;
 827
 828         /* we are protected by the ring mutex */
 829         src = &fence->ring->fence_drv;
 830         dst = &dst_ring->fence_drv;
 831         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 832                 if (i == dst_ring->idx)
 833                         continue;
 834
 835                 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
 836         }
 837 }
 838
 839 /**
 840  * amdgpu_fence_driver_start_ring - make the fence driver
 841  * ready for use on the requested ring.
 842  *
 843  * @ring: ring to start the fence driver on
 844  * @irq_src: interrupt source to use for this ring
 845  * @irq_type: interrupt type to use for this ring
 846  *
 847  * Make the fence driver ready for processing (all asics).
 848  * Not all asics have all rings, so each asic will only
 849  * start the fence driver on the rings it has.
 850  * Returns 0 for success, errors for failure.
 851  */
 852 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 853                                    struct amdgpu_irq_src *irq_src,
 854                                    unsigned irq_type)
 855 {
 856         struct amdgpu_device *adev = ring->adev;
 857         uint64_t index;
 858
 859         if (ring != &adev->uvd.ring) {
 860                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 861                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 862         } else {
 863                 /* put fence directly behind firmware */
 864                 index = ALIGN(adev->uvd.fw->size, 8);
 865                 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
 866                 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
 867         }
 868         amdgpu_fence_write(ring, atomic64_read(&ring->fence_drv.last_seq));
 869         amdgpu_irq_get(adev, irq_src, irq_type);
 870
 871         ring->fence_drv.irq_src = irq_src;
 872         ring->fence_drv.irq_type = irq_type;
 873         ring->fence_drv.initialized = true;
 874
 875         dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 876                  "cpu addr 0x%p\n", ring->idx,
 877                  ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 878         return 0;
 879 }
 880
 881 /**
 882  * amdgpu_fence_driver_init_ring - init the fence driver
 883  * for the requested ring.
 884  *
 885  * @ring: ring to init the fence driver on
 886  *
 887  * Init the fence driver for the requested ring (all asics).
 888  * Helper function for amdgpu_fence_driver_init().
 889  */
 890 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
 891 {
 892         int i;
 893
 894         ring->fence_drv.cpu_addr = NULL;
 895         ring->fence_drv.gpu_addr = 0;
 896         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
 897                 ring->fence_drv.sync_seq[i] = 0;
 898
 899         atomic64_set(&ring->fence_drv.last_seq, 0);
 900         ring->fence_drv.initialized = false;
 901
 902         INIT_DELAYED_WORK(&ring->fence_drv.lockup_work,
 903                         amdgpu_fence_check_lockup);
 904         ring->fence_drv.ring = ring;
 905
 906         if (amdgpu_enable_scheduler) {
 907                 ring->scheduler = amd_sched_create((void *)ring->adev,
 908                                                    NULL, ring->idx, 5, 0);
 909                 if (!ring->scheduler)
 910                         DRM_ERROR("Failed to create scheduler on ring %d.\n",
 911                                   ring->idx);
 912         }
 913 }
 914
 915 /**
 916  * amdgpu_fence_driver_init - init the fence driver
 917  * for all possible rings.
 918  *
 919  * @adev: amdgpu device pointer
 920  *
 921  * Init the fence driver for all possible rings (all asics).
 922  * Not all asics have all rings, so each asic will only
 923  * start the fence driver on the rings it has using
 924  * amdgpu_fence_driver_start_ring().
 925  * Returns 0 for success.
 926  */
 927 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 928 {
 929         init_waitqueue_head(&adev->fence_queue);
 930         if (amdgpu_debugfs_fence_init(adev))
 931                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 932
 933         return 0;
 934 }
 935
 936 /**
 937  * amdgpu_fence_driver_fini - tear down the fence driver
 938  * for all possible rings.
 939  *
 940  * @adev: amdgpu device pointer
 941  *
 942  * Tear down the fence driver for all possible rings (all asics).
 943  */
 944 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 945 {
 946         int i, r;
 947
 948         mutex_lock(&adev->ring_lock);
 949         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 950                 struct amdgpu_ring *ring = adev->rings[i];
 951                 if (!ring || !ring->fence_drv.initialized)
 952                         continue;
 953                 r = amdgpu_fence_wait_empty(ring);
 954                 if (r) {
 955                         /* no need to trigger GPU reset as we are unloading */
 956                         amdgpu_fence_driver_force_completion(adev);
 957                 }
 958                 wake_up_all(&adev->fence_queue);
 959                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 960                                ring->fence_drv.irq_type);
 961                 if (ring->scheduler)
 962                         amd_sched_destroy(ring->scheduler);
 963                 ring->fence_drv.initialized = false;
 964         }
 965         mutex_unlock(&adev->ring_lock);
 966 }
 967
 968 /**
 969  * amdgpu_fence_driver_suspend - suspend the fence driver
 970  * for all possible rings.
 971  *
 972  * @adev: amdgpu device pointer
 973  *
 974  * Suspend the fence driver for all possible rings (all asics).
 975  */
 976 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 977 {
 978         int i, r;
 979
 980         mutex_lock(&adev->ring_lock);
 981         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 982                 struct amdgpu_ring *ring = adev->rings[i];
 983                 if (!ring || !ring->fence_drv.initialized)
 984                         continue;
 985
 986                 /* wait for gpu to finish processing current batch */
 987                 r = amdgpu_fence_wait_empty(ring);
 988                 if (r) {
 989                         /* delay GPU reset to resume */
 990                         amdgpu_fence_driver_force_completion(adev);
 991                 }
 992
 993                 /* disable the interrupt */
 994                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 995                                ring->fence_drv.irq_type);
 996         }
 997         mutex_unlock(&adev->ring_lock);
 998 }
 999
1000 /**
1001  * amdgpu_fence_driver_resume - resume the fence driver
1002  * for all possible rings.
1003  *
1004  * @adev: amdgpu device pointer
1005  *
1006  * Resume the fence driver for all possible rings (all asics).
1007  * Not all asics have all rings, so each asic will only
1008  * start the fence driver on the rings it has using
1009  * amdgpu_fence_driver_start_ring().
1010  * Returns 0 for success.
1011  */
1012 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
1013 {
1014         int i;
1015
1016         mutex_lock(&adev->ring_lock);
1017         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1018                 struct amdgpu_ring *ring = adev->rings[i];
1019                 if (!ring || !ring->fence_drv.initialized)
1020                         continue;
1021
1022                 /* enable the interrupt */
1023                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
1024                                ring->fence_drv.irq_type);
1025         }
1026         mutex_unlock(&adev->ring_lock);
1027 }
1028
1029 /**
1030  * amdgpu_fence_driver_force_completion - force all fence waiter to complete
1031  *
1032  * @adev: amdgpu device pointer
1033  *
1034  * In case of GPU reset failure make sure no process keep waiting on fence
1035  * that will never complete.
1036  */
1037 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
1038 {
1039         int i;
1040
1041         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1042                 struct amdgpu_ring *ring = adev->rings[i];
1043                 if (!ring || !ring->fence_drv.initialized)
1044                         continue;
1045
1046                 amdgpu_fence_write(ring, ring->fence_drv.sync_seq[i]);
1047         }
1048 }
1049
1050
1051 /*
1052  * Fence debugfs
1053  */
1054 #if defined(CONFIG_DEBUG_FS)
1055 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
1056 {
1057         struct drm_info_node *node = (struct drm_info_node *)m->private;
1058         struct drm_device *dev = node->minor->dev;
1059         struct amdgpu_device *adev = dev->dev_private;
1060         int i, j;
1061
1062         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1063                 struct amdgpu_ring *ring = adev->rings[i];
1064                 if (!ring || !ring->fence_drv.initialized)
1065                         continue;
1066
1067                 amdgpu_fence_process(ring);
1068
1069                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
1070                 seq_printf(m, "Last signaled fence 0x%016llx\n",
1071                            (unsigned long long)atomic64_read(&ring->fence_drv.last_seq));
1072                 seq_printf(m, "Last emitted        0x%016llx\n",
1073                            ring->fence_drv.sync_seq[i]);
1074
1075                 for (j = 0; j < AMDGPU_MAX_RINGS; ++j) {
1076                         struct amdgpu_ring *other = adev->rings[j];
1077                         if (i != j && other && other->fence_drv.initialized &&
1078                             ring->fence_drv.sync_seq[j])
1079                                 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
1080                                            j, ring->fence_drv.sync_seq[j]);
1081                 }
1082         }
1083         return 0;
1084 }
1085
1086 static struct drm_info_list amdgpu_debugfs_fence_list[] = {
1087         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
1088 };
1089 #endif
1090
1091 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
1092 {
1093 #if defined(CONFIG_DEBUG_FS)
1094         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 1);
1095 #else
1096         return 0;
1097 #endif
1098 }
1099
1100 static const char *amdgpu_fence_get_driver_name(struct fence *fence)
1101 {
1102         return "amdgpu";
1103 }
1104
1105 static const char *amdgpu_fence_get_timeline_name(struct fence *f)
1106 {
1107         struct amdgpu_fence *fence = to_amdgpu_fence(f);
1108         return (const char *)fence->ring->name;
1109 }
1110
1111 static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence)
1112 {
1113         return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
1114 }
1115
1116 struct amdgpu_wait_cb {
1117         struct fence_cb base;
1118         struct task_struct *task;
1119 };
1120
1121 static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
1122 {
1123         struct amdgpu_wait_cb *wait =
1124                 container_of(cb, struct amdgpu_wait_cb, base);
1125         wake_up_process(wait->task);
1126 }
1127
1128 static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
1129                                              signed long t)
1130 {
1131         struct amdgpu_fence *fence = to_amdgpu_fence(f);
1132         struct amdgpu_device *adev = fence->ring->adev;
1133         struct amdgpu_wait_cb cb;
1134
1135         cb.task = current;
1136
1137         if (fence_add_callback(f, &cb.base, amdgpu_fence_wait_cb))
1138                 return t;
1139
1140         while (t > 0) {
1141                 if (intr)
1142                         set_current_state(TASK_INTERRUPTIBLE);
1143                 else
1144                         set_current_state(TASK_UNINTERRUPTIBLE);
1145
1146                 /*
1147                  * amdgpu_test_signaled must be called after
1148                  * set_current_state to prevent a race with wake_up_process
1149                  */
1150                 if (amdgpu_test_signaled(fence))
1151                         break;
1152
1153                 if (adev->needs_reset) {
1154                         t = -EDEADLK;
1155                         break;
1156                 }
1157
1158                 t = schedule_timeout(t);
1159
1160                 if (t > 0 && intr && signal_pending(current))
1161                         t = -ERESTARTSYS;
1162         }
1163
1164         __set_current_state(TASK_RUNNING);
1165         fence_remove_callback(f, &cb.base);
1166
1167         return t;
1168 }
1169
1170 const struct fence_ops amdgpu_fence_ops = {
1171         .get_driver_name = amdgpu_fence_get_driver_name,
1172         .get_timeline_name = amdgpu_fence_get_timeline_name,
1173         .enable_signaling = amdgpu_fence_enable_signaling,
1174         .signaled = amdgpu_fence_is_signaled,
1175         .wait = amdgpu_fence_default_wait,
1176         .release = NULL,
1177 };