drivers/clk/meson/g12a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Amlogic Meson-G12A Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <[email protected]>
   7  *
   8  * Copyright (c) 2018 Amlogic, inc.
   9  * Author: Qiufang Dai <[email protected]>
  10  * Author: Jian Hu <[email protected]>
  11  */
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/init.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17
  18 #include "clk-input.h"
  19 #include "clk-mpll.h"
  20 #include "clk-pll.h"
  21 #include "clk-regmap.h"
  22 #include "vid-pll-div.h"
  23 #include "meson-eeclk.h"
  24 #include "g12a.h"
  25
  26 static DEFINE_SPINLOCK(meson_clk_lock);
  27
  28 static struct clk_regmap g12a_fixed_pll_dco = {
  29         .data = &(struct meson_clk_pll_data){
  30                 .en = {
  31                         .reg_off = HHI_FIX_PLL_CNTL0,
  32                         .shift   = 28,
  33                         .width   = 1,
  34                 },
  35                 .m = {
  36                         .reg_off = HHI_FIX_PLL_CNTL0,
  37                         .shift   = 0,
  38                         .width   = 8,
  39                 },
  40                 .n = {
  41                         .reg_off = HHI_FIX_PLL_CNTL0,
  42                         .shift   = 10,
  43                         .width   = 5,
  44                 },
  45                 .frac = {
  46                         .reg_off = HHI_FIX_PLL_CNTL1,
  47                         .shift   = 0,
  48                         .width   = 17,
  49                 },
  50                 .l = {
  51                         .reg_off = HHI_FIX_PLL_CNTL0,
  52                         .shift   = 31,
  53                         .width   = 1,
  54                 },
  55                 .rst = {
  56                         .reg_off = HHI_FIX_PLL_CNTL0,
  57                         .shift   = 29,
  58                         .width   = 1,
  59                 },
  60         },
  61         .hw.init = &(struct clk_init_data){
  62                 .name = "fixed_pll_dco",
  63                 .ops = &meson_clk_pll_ro_ops,
  64                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
  65                 .num_parents = 1,
  66         },
  67 };
  68
  69 static struct clk_regmap g12a_fixed_pll = {
  70         .data = &(struct clk_regmap_div_data){
  71                 .offset = HHI_FIX_PLL_CNTL0,
  72                 .shift = 16,
  73                 .width = 2,
  74                 .flags = CLK_DIVIDER_POWER_OF_TWO,
  75         },
  76         .hw.init = &(struct clk_init_data){
  77                 .name = "fixed_pll",
  78                 .ops = &clk_regmap_divider_ro_ops,
  79                 .parent_names = (const char *[]){ "fixed_pll_dco" },
  80                 .num_parents = 1,
  81                 /*
  82                  * This clock won't ever change at runtime so
  83                  * CLK_SET_RATE_PARENT is not required
  84                  */
  85         },
  86 };
  87
  88 /*
  89  * Internal sys pll emulation configuration parameters
  90  */
  91 static const struct reg_sequence g12a_sys_init_regs[] = {
  92         { .reg = HHI_SYS_PLL_CNTL1,     .def = 0x00000000 },
  93         { .reg = HHI_SYS_PLL_CNTL2,     .def = 0x00000000 },
  94         { .reg = HHI_SYS_PLL_CNTL3,     .def = 0x48681c00 },
  95         { .reg = HHI_SYS_PLL_CNTL4,     .def = 0x88770290 },
  96         { .reg = HHI_SYS_PLL_CNTL5,     .def = 0x39272000 },
  97         { .reg = HHI_SYS_PLL_CNTL6,     .def = 0x56540000 },
  98 };
  99
 100 static struct clk_regmap g12a_sys_pll_dco = {
 101         .data = &(struct meson_clk_pll_data){
 102                 .en = {
 103                         .reg_off = HHI_SYS_PLL_CNTL0,
 104                         .shift   = 28,
 105                         .width   = 1,
 106                 },
 107                 .m = {
 108                         .reg_off = HHI_SYS_PLL_CNTL0,
 109                         .shift   = 0,
 110                         .width   = 8,
 111                 },
 112                 .n = {
 113                         .reg_off = HHI_SYS_PLL_CNTL0,
 114                         .shift   = 10,
 115                         .width   = 5,
 116                 },
 117                 .l = {
 118                         .reg_off = HHI_SYS_PLL_CNTL0,
 119                         .shift   = 31,
 120                         .width   = 1,
 121                 },
 122                 .rst = {
 123                         .reg_off = HHI_SYS_PLL_CNTL0,
 124                         .shift   = 29,
 125                         .width   = 1,
 126                 },
 127                 .init_regs = g12a_sys_init_regs,
 128                 .init_count = ARRAY_SIZE(g12a_sys_init_regs),
 129         },
 130         .hw.init = &(struct clk_init_data){
 131                 .name = "sys_pll_dco",
 132                 .ops = &meson_clk_pll_ro_ops,
 133                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 134                 .num_parents = 1,
 135         },
 136 };
 137
 138 static struct clk_regmap g12a_sys_pll = {
 139         .data = &(struct clk_regmap_div_data){
 140                 .offset = HHI_SYS_PLL_CNTL0,
 141                 .shift = 16,
 142                 .width = 3,
 143                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 144         },
 145         .hw.init = &(struct clk_init_data){
 146                 .name = "sys_pll",
 147                 .ops = &clk_regmap_divider_ro_ops,
 148                 .parent_names = (const char *[]){ "sys_pll_dco" },
 149                 .num_parents = 1,
 150         },
 151 };
 152
 153 static struct clk_regmap g12b_sys1_pll_dco = {
 154         .data = &(struct meson_clk_pll_data){
 155                 .en = {
 156                         .reg_off = HHI_SYS1_PLL_CNTL0,
 157                         .shift   = 28,
 158                         .width   = 1,
 159                 },
 160                 .m = {
 161                         .reg_off = HHI_SYS1_PLL_CNTL0,
 162                         .shift   = 0,
 163                         .width   = 8,
 164                 },
 165                 .n = {
 166                         .reg_off = HHI_SYS1_PLL_CNTL0,
 167                         .shift   = 10,
 168                         .width   = 5,
 169                 },
 170                 .l = {
 171                         .reg_off = HHI_SYS1_PLL_CNTL0,
 172                         .shift   = 31,
 173                         .width   = 1,
 174                 },
 175                 .rst = {
 176                         .reg_off = HHI_SYS1_PLL_CNTL0,
 177                         .shift   = 29,
 178                         .width   = 1,
 179                 },
 180         },
 181         .hw.init = &(struct clk_init_data){
 182                 .name = "sys1_pll_dco",
 183                 .ops = &meson_clk_pll_ro_ops,
 184                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
 185                 .num_parents = 1,
 186         },
 187 };
 188
 189 static struct clk_regmap g12b_sys1_pll = {
 190         .data = &(struct clk_regmap_div_data){
 191                 .offset = HHI_SYS1_PLL_CNTL0,
 192                 .shift = 16,
 193                 .width = 3,
 194                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 195         },
 196         .hw.init = &(struct clk_init_data){
 197                 .name = "sys1_pll",
 198                 .ops = &clk_regmap_divider_ro_ops,
 199                 .parent_names = (const char *[]){ "sys1_pll_dco" },
 200                 .num_parents = 1,
 201         },
 202 };
 203
 204 static struct clk_regmap g12a_sys_pll_div16_en = {
 205         .data = &(struct clk_regmap_gate_data){
 206                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 207                 .bit_idx = 24,
 208         },
 209         .hw.init = &(struct clk_init_data) {
 210                 .name = "sys_pll_div16_en",
 211                 .ops = &clk_regmap_gate_ro_ops,
 212                 .parent_names = (const char *[]){ "sys_pll" },
 213                 .num_parents = 1,
 214                 /*
 215                  * This clock is used to debug the sys_pll range
 216                  * Linux should not change it at runtime
 217                  */
 218         },
 219 };
 220
 221 static struct clk_regmap g12b_sys1_pll_div16_en = {
 222         .data = &(struct clk_regmap_gate_data){
 223                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 224                 .bit_idx = 24,
 225         },
 226         .hw.init = &(struct clk_init_data) {
 227                 .name = "sys1_pll_div16_en",
 228                 .ops = &clk_regmap_gate_ro_ops,
 229                 .parent_names = (const char *[]){ "sys1_pll" },
 230                 .num_parents = 1,
 231                 /*
 232                  * This clock is used to debug the sys_pll range
 233                  * Linux should not change it at runtime
 234                  */
 235         },
 236 };
 237
 238 static struct clk_fixed_factor g12a_sys_pll_div16 = {
 239         .mult = 1,
 240         .div = 16,
 241         .hw.init = &(struct clk_init_data){
 242                 .name = "sys_pll_div16",
 243                 .ops = &clk_fixed_factor_ops,
 244                 .parent_names = (const char *[]){ "sys_pll_div16_en" },
 245                 .num_parents = 1,
 246         },
 247 };
 248
 249 static struct clk_fixed_factor g12b_sys1_pll_div16 = {
 250         .mult = 1,
 251         .div = 16,
 252         .hw.init = &(struct clk_init_data){
 253                 .name = "sys1_pll_div16",
 254                 .ops = &clk_fixed_factor_ops,
 255                 .parent_names = (const char *[]){ "sys1_pll_div16_en" },
 256                 .num_parents = 1,
 257         },
 258 };
 259
 260 /* Datasheet names this field as "premux0" */
 261 static struct clk_regmap g12a_cpu_clk_premux0 = {
 262         .data = &(struct clk_regmap_mux_data){
 263                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 264                 .mask = 0x3,
 265                 .shift = 0,
 266         },
 267         .hw.init = &(struct clk_init_data){
 268                 .name = "cpu_clk_dyn0_sel",
 269                 .ops = &clk_regmap_mux_ro_ops,
 270                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 271                                                   "fclk_div2",
 272                                                   "fclk_div3" },
 273                 .num_parents = 3,
 274         },
 275 };
 276
 277 /* Datasheet names this field as "mux0_divn_tcnt" */
 278 static struct clk_regmap g12a_cpu_clk_mux0_div = {
 279         .data = &(struct clk_regmap_div_data){
 280                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 281                 .shift = 4,
 282                 .width = 6,
 283         },
 284         .hw.init = &(struct clk_init_data){
 285                 .name = "cpu_clk_dyn0_div",
 286                 .ops = &clk_regmap_divider_ro_ops,
 287                 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
 288                 .num_parents = 1,
 289         },
 290 };
 291
 292 /* Datasheet names this field as "postmux0" */
 293 static struct clk_regmap g12a_cpu_clk_postmux0 = {
 294         .data = &(struct clk_regmap_mux_data){
 295                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 296                 .mask = 0x1,
 297                 .shift = 2,
 298         },
 299         .hw.init = &(struct clk_init_data){
 300                 .name = "cpu_clk_dyn0",
 301                 .ops = &clk_regmap_mux_ro_ops,
 302                 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
 303                                                   "cpu_clk_dyn0_div" },
 304                 .num_parents = 2,
 305         },
 306 };
 307
 308 /* Datasheet names this field as "premux1" */
 309 static struct clk_regmap g12a_cpu_clk_premux1 = {
 310         .data = &(struct clk_regmap_mux_data){
 311                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 312                 .mask = 0x3,
 313                 .shift = 16,
 314         },
 315         .hw.init = &(struct clk_init_data){
 316                 .name = "cpu_clk_dyn1_sel",
 317                 .ops = &clk_regmap_mux_ro_ops,
 318                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 319                                                   "fclk_div2",
 320                                                   "fclk_div3" },
 321                 .num_parents = 3,
 322         },
 323 };
 324
 325 /* Datasheet names this field as "Mux1_divn_tcnt" */
 326 static struct clk_regmap g12a_cpu_clk_mux1_div = {
 327         .data = &(struct clk_regmap_div_data){
 328                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 329                 .shift = 20,
 330                 .width = 6,
 331         },
 332         .hw.init = &(struct clk_init_data){
 333                 .name = "cpu_clk_dyn1_div",
 334                 .ops = &clk_regmap_divider_ro_ops,
 335                 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
 336                 .num_parents = 1,
 337         },
 338 };
 339
 340 /* Datasheet names this field as "postmux1" */
 341 static struct clk_regmap g12a_cpu_clk_postmux1 = {
 342         .data = &(struct clk_regmap_mux_data){
 343                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 344                 .mask = 0x1,
 345                 .shift = 18,
 346         },
 347         .hw.init = &(struct clk_init_data){
 348                 .name = "cpu_clk_dyn1",
 349                 .ops = &clk_regmap_mux_ro_ops,
 350                 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
 351                                                   "cpu_clk_dyn1_div" },
 352                 .num_parents = 2,
 353         },
 354 };
 355
 356 /* Datasheet names this field as "Final_dyn_mux_sel" */
 357 static struct clk_regmap g12a_cpu_clk_dyn = {
 358         .data = &(struct clk_regmap_mux_data){
 359                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 360                 .mask = 0x1,
 361                 .shift = 10,
 362         },
 363         .hw.init = &(struct clk_init_data){
 364                 .name = "cpu_clk_dyn",
 365                 .ops = &clk_regmap_mux_ro_ops,
 366                 .parent_names = (const char *[]){ "cpu_clk_dyn0",
 367                                                   "cpu_clk_dyn1" },
 368                 .num_parents = 2,
 369         },
 370 };
 371
 372 /* Datasheet names this field as "Final_mux_sel" */
 373 static struct clk_regmap g12a_cpu_clk = {
 374         .data = &(struct clk_regmap_mux_data){
 375                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 376                 .mask = 0x1,
 377                 .shift = 11,
 378         },
 379         .hw.init = &(struct clk_init_data){
 380                 .name = "cpu_clk",
 381                 .ops = &clk_regmap_mux_ro_ops,
 382                 .parent_names = (const char *[]){ "cpu_clk_dyn",
 383                                                   "sys_pll" },
 384                 .num_parents = 2,
 385         },
 386 };
 387
 388 /* Datasheet names this field as "Final_mux_sel" */
 389 static struct clk_regmap g12b_cpu_clk = {
 390         .data = &(struct clk_regmap_mux_data){
 391                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 392                 .mask = 0x1,
 393                 .shift = 11,
 394         },
 395         .hw.init = &(struct clk_init_data){
 396                 .name = "cpu_clk",
 397                 .ops = &clk_regmap_mux_ro_ops,
 398                 .parent_names = (const char *[]){ "cpu_clk_dyn",
 399                                                   "sys1_pll" },
 400                 .num_parents = 2,
 401         },
 402 };
 403
 404 /* Datasheet names this field as "premux0" */
 405 static struct clk_regmap g12b_cpub_clk_premux0 = {
 406         .data = &(struct clk_regmap_mux_data){
 407                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 408                 .mask = 0x3,
 409                 .shift = 0,
 410         },
 411         .hw.init = &(struct clk_init_data){
 412                 .name = "cpub_clk_dyn0_sel",
 413                 .ops = &clk_regmap_mux_ro_ops,
 414                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 415                                                   "fclk_div2",
 416                                                   "fclk_div3" },
 417                 .num_parents = 3,
 418         },
 419 };
 420
 421 /* Datasheet names this field as "mux0_divn_tcnt" */
 422 static struct clk_regmap g12b_cpub_clk_mux0_div = {
 423         .data = &(struct clk_regmap_div_data){
 424                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 425                 .shift = 4,
 426                 .width = 6,
 427         },
 428         .hw.init = &(struct clk_init_data){
 429                 .name = "cpub_clk_dyn0_div",
 430                 .ops = &clk_regmap_divider_ro_ops,
 431                 .parent_names = (const char *[]){ "cpub_clk_dyn0_sel" },
 432                 .num_parents = 1,
 433         },
 434 };
 435
 436 /* Datasheet names this field as "postmux0" */
 437 static struct clk_regmap g12b_cpub_clk_postmux0 = {
 438         .data = &(struct clk_regmap_mux_data){
 439                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 440                 .mask = 0x1,
 441                 .shift = 2,
 442         },
 443         .hw.init = &(struct clk_init_data){
 444                 .name = "cpub_clk_dyn0",
 445                 .ops = &clk_regmap_mux_ro_ops,
 446                 .parent_names = (const char *[]){ "cpub_clk_dyn0_sel",
 447                                                   "cpub_clk_dyn0_div" },
 448                 .num_parents = 2,
 449         },
 450 };
 451
 452 /* Datasheet names this field as "premux1" */
 453 static struct clk_regmap g12b_cpub_clk_premux1 = {
 454         .data = &(struct clk_regmap_mux_data){
 455                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 456                 .mask = 0x3,
 457                 .shift = 16,
 458         },
 459         .hw.init = &(struct clk_init_data){
 460                 .name = "cpub_clk_dyn1_sel",
 461                 .ops = &clk_regmap_mux_ro_ops,
 462                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
 463                                                   "fclk_div2",
 464                                                   "fclk_div3" },
 465                 .num_parents = 3,
 466         },
 467 };
 468
 469 /* Datasheet names this field as "Mux1_divn_tcnt" */
 470 static struct clk_regmap g12b_cpub_clk_mux1_div = {
 471         .data = &(struct clk_regmap_div_data){
 472                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 473                 .shift = 20,
 474                 .width = 6,
 475         },
 476         .hw.init = &(struct clk_init_data){
 477                 .name = "cpub_clk_dyn1_div",
 478                 .ops = &clk_regmap_divider_ro_ops,
 479                 .parent_names = (const char *[]){ "cpub_clk_dyn1_sel" },
 480                 .num_parents = 1,
 481         },
 482 };
 483
 484 /* Datasheet names this field as "postmux1" */
 485 static struct clk_regmap g12b_cpub_clk_postmux1 = {
 486         .data = &(struct clk_regmap_mux_data){
 487                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 488                 .mask = 0x1,
 489                 .shift = 18,
 490         },
 491         .hw.init = &(struct clk_init_data){
 492                 .name = "cpub_clk_dyn1",
 493                 .ops = &clk_regmap_mux_ro_ops,
 494                 .parent_names = (const char *[]){ "cpub_clk_dyn1_sel",
 495                                                   "cpub_clk_dyn1_div" },
 496                 .num_parents = 2,
 497         },
 498 };
 499
 500 /* Datasheet names this field as "Final_dyn_mux_sel" */
 501 static struct clk_regmap g12b_cpub_clk_dyn = {
 502         .data = &(struct clk_regmap_mux_data){
 503                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 504                 .mask = 0x1,
 505                 .shift = 10,
 506         },
 507         .hw.init = &(struct clk_init_data){
 508                 .name = "cpub_clk_dyn",
 509                 .ops = &clk_regmap_mux_ro_ops,
 510                 .parent_names = (const char *[]){ "cpub_clk_dyn0",
 511                                                   "cpub_clk_dyn1" },
 512                 .num_parents = 2,
 513         },
 514 };
 515
 516 /* Datasheet names this field as "Final_mux_sel" */
 517 static struct clk_regmap g12b_cpub_clk = {
 518         .data = &(struct clk_regmap_mux_data){
 519                 .offset = HHI_SYS_CPUB_CLK_CNTL,
 520                 .mask = 0x1,
 521                 .shift = 11,
 522         },
 523         .hw.init = &(struct clk_init_data){
 524                 .name = "cpub_clk",
 525                 .ops = &clk_regmap_mux_ro_ops,
 526                 .parent_names = (const char *[]){ "cpub_clk_dyn",
 527                                                   "sys_pll" },
 528                 .num_parents = 2,
 529         },
 530 };
 531
 532 static struct clk_regmap g12a_cpu_clk_div16_en = {
 533         .data = &(struct clk_regmap_gate_data){
 534                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 535                 .bit_idx = 1,
 536         },
 537         .hw.init = &(struct clk_init_data) {
 538                 .name = "cpu_clk_div16_en",
 539                 .ops = &clk_regmap_gate_ro_ops,
 540                 .parent_names = (const char *[]){ "cpu_clk" },
 541                 .num_parents = 1,
 542                 /*
 543                  * This clock is used to debug the cpu_clk range
 544                  * Linux should not change it at runtime
 545                  */
 546         },
 547 };
 548
 549 static struct clk_regmap g12b_cpub_clk_div16_en = {
 550         .data = &(struct clk_regmap_gate_data){
 551                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 552                 .bit_idx = 1,
 553         },
 554         .hw.init = &(struct clk_init_data) {
 555                 .name = "cpub_clk_div16_en",
 556                 .ops = &clk_regmap_gate_ro_ops,
 557                 .parent_names = (const char *[]){ "cpub_clk" },
 558                 .num_parents = 1,
 559                 /*
 560                  * This clock is used to debug the cpu_clk range
 561                  * Linux should not change it at runtime
 562                  */
 563         },
 564 };
 565
 566 static struct clk_fixed_factor g12a_cpu_clk_div16 = {
 567         .mult = 1,
 568         .div = 16,
 569         .hw.init = &(struct clk_init_data){
 570                 .name = "cpu_clk_div16",
 571                 .ops = &clk_fixed_factor_ops,
 572                 .parent_names = (const char *[]){ "cpu_clk_div16_en" },
 573                 .num_parents = 1,
 574         },
 575 };
 576
 577 static struct clk_fixed_factor g12b_cpub_clk_div16 = {
 578         .mult = 1,
 579         .div = 16,
 580         .hw.init = &(struct clk_init_data){
 581                 .name = "cpub_clk_div16",
 582                 .ops = &clk_fixed_factor_ops,
 583                 .parent_names = (const char *[]){ "cpub_clk_div16_en" },
 584                 .num_parents = 1,
 585         },
 586 };
 587
 588 static struct clk_regmap g12a_cpu_clk_apb_div = {
 589         .data = &(struct clk_regmap_div_data){
 590                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 591                 .shift = 3,
 592                 .width = 3,
 593                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 594         },
 595         .hw.init = &(struct clk_init_data){
 596                 .name = "cpu_clk_apb_div",
 597                 .ops = &clk_regmap_divider_ro_ops,
 598                 .parent_names = (const char *[]){ "cpu_clk" },
 599                 .num_parents = 1,
 600         },
 601 };
 602
 603 static struct clk_regmap g12a_cpu_clk_apb = {
 604         .data = &(struct clk_regmap_gate_data){
 605                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 606                 .bit_idx = 1,
 607         },
 608         .hw.init = &(struct clk_init_data) {
 609                 .name = "cpu_clk_apb",
 610                 .ops = &clk_regmap_gate_ro_ops,
 611                 .parent_names = (const char *[]){ "cpu_clk_apb_div" },
 612                 .num_parents = 1,
 613                 /*
 614                  * This clock is set by the ROM monitor code,
 615                  * Linux should not change it at runtime
 616                  */
 617         },
 618 };
 619
 620 static struct clk_regmap g12a_cpu_clk_atb_div = {
 621         .data = &(struct clk_regmap_div_data){
 622                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 623                 .shift = 6,
 624                 .width = 3,
 625                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 626         },
 627         .hw.init = &(struct clk_init_data){
 628                 .name = "cpu_clk_atb_div",
 629                 .ops = &clk_regmap_divider_ro_ops,
 630                 .parent_names = (const char *[]){ "cpu_clk" },
 631                 .num_parents = 1,
 632         },
 633 };
 634
 635 static struct clk_regmap g12a_cpu_clk_atb = {
 636         .data = &(struct clk_regmap_gate_data){
 637                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 638                 .bit_idx = 17,
 639         },
 640         .hw.init = &(struct clk_init_data) {
 641                 .name = "cpu_clk_atb",
 642                 .ops = &clk_regmap_gate_ro_ops,
 643                 .parent_names = (const char *[]){ "cpu_clk_atb_div" },
 644                 .num_parents = 1,
 645                 /*
 646                  * This clock is set by the ROM monitor code,
 647                  * Linux should not change it at runtime
 648                  */
 649         },
 650 };
 651
 652 static struct clk_regmap g12a_cpu_clk_axi_div = {
 653         .data = &(struct clk_regmap_div_data){
 654                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 655                 .shift = 9,
 656                 .width = 3,
 657                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 658         },
 659         .hw.init = &(struct clk_init_data){
 660                 .name = "cpu_clk_axi_div",
 661                 .ops = &clk_regmap_divider_ro_ops,
 662                 .parent_names = (const char *[]){ "cpu_clk" },
 663                 .num_parents = 1,
 664         },
 665 };
 666
 667 static struct clk_regmap g12a_cpu_clk_axi = {
 668         .data = &(struct clk_regmap_gate_data){
 669                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 670                 .bit_idx = 18,
 671         },
 672         .hw.init = &(struct clk_init_data) {
 673                 .name = "cpu_clk_axi",
 674                 .ops = &clk_regmap_gate_ro_ops,
 675                 .parent_names = (const char *[]){ "cpu_clk_axi_div" },
 676                 .num_parents = 1,
 677                 /*
 678                  * This clock is set by the ROM monitor code,
 679                  * Linux should not change it at runtime
 680                  */
 681         },
 682 };
 683
 684 static struct clk_regmap g12a_cpu_clk_trace_div = {
 685         .data = &(struct clk_regmap_div_data){
 686                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 687                 .shift = 20,
 688                 .width = 3,
 689                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 690         },
 691         .hw.init = &(struct clk_init_data){
 692                 .name = "cpu_clk_trace_div",
 693                 .ops = &clk_regmap_divider_ro_ops,
 694                 .parent_names = (const char *[]){ "cpu_clk" },
 695                 .num_parents = 1,
 696         },
 697 };
 698
 699 static struct clk_regmap g12a_cpu_clk_trace = {
 700         .data = &(struct clk_regmap_gate_data){
 701                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 702                 .bit_idx = 23,
 703         },
 704         .hw.init = &(struct clk_init_data) {
 705                 .name = "cpu_clk_trace",
 706                 .ops = &clk_regmap_gate_ro_ops,
 707                 .parent_names = (const char *[]){ "cpu_clk_trace_div" },
 708                 .num_parents = 1,
 709                 /*
 710                  * This clock is set by the ROM monitor code,
 711                  * Linux should not change it at runtime
 712                  */
 713         },
 714 };
 715
 716 static struct clk_fixed_factor g12b_cpub_clk_div2 = {
 717         .mult = 1,
 718         .div = 2,
 719         .hw.init = &(struct clk_init_data){
 720                 .name = "cpub_clk_div2",
 721                 .ops = &clk_fixed_factor_ops,
 722                 .parent_names = (const char *[]){ "cpub_clk" },
 723                 .num_parents = 1,
 724         },
 725 };
 726
 727 static struct clk_fixed_factor g12b_cpub_clk_div3 = {
 728         .mult = 1,
 729         .div = 3,
 730         .hw.init = &(struct clk_init_data){
 731                 .name = "cpub_clk_div3",
 732                 .ops = &clk_fixed_factor_ops,
 733                 .parent_names = (const char *[]){ "cpub_clk" },
 734                 .num_parents = 1,
 735         },
 736 };
 737
 738 static struct clk_fixed_factor g12b_cpub_clk_div4 = {
 739         .mult = 1,
 740         .div = 4,
 741         .hw.init = &(struct clk_init_data){
 742                 .name = "cpub_clk_div4",
 743                 .ops = &clk_fixed_factor_ops,
 744                 .parent_names = (const char *[]){ "cpub_clk" },
 745                 .num_parents = 1,
 746         },
 747 };
 748
 749 static struct clk_fixed_factor g12b_cpub_clk_div5 = {
 750         .mult = 1,
 751         .div = 5,
 752         .hw.init = &(struct clk_init_data){
 753                 .name = "cpub_clk_div5",
 754                 .ops = &clk_fixed_factor_ops,
 755                 .parent_names = (const char *[]){ "cpub_clk" },
 756                 .num_parents = 1,
 757         },
 758 };
 759
 760 static struct clk_fixed_factor g12b_cpub_clk_div6 = {
 761         .mult = 1,
 762         .div = 6,
 763         .hw.init = &(struct clk_init_data){
 764                 .name = "cpub_clk_div6",
 765                 .ops = &clk_fixed_factor_ops,
 766                 .parent_names = (const char *[]){ "cpub_clk" },
 767                 .num_parents = 1,
 768         },
 769 };
 770
 771 static struct clk_fixed_factor g12b_cpub_clk_div7 = {
 772         .mult = 1,
 773         .div = 7,
 774         .hw.init = &(struct clk_init_data){
 775                 .name = "cpub_clk_div7",
 776                 .ops = &clk_fixed_factor_ops,
 777                 .parent_names = (const char *[]){ "cpub_clk" },
 778                 .num_parents = 1,
 779         },
 780 };
 781
 782 static struct clk_fixed_factor g12b_cpub_clk_div8 = {
 783         .mult = 1,
 784         .div = 8,
 785         .hw.init = &(struct clk_init_data){
 786                 .name = "cpub_clk_div8",
 787                 .ops = &clk_fixed_factor_ops,
 788                 .parent_names = (const char *[]){ "cpub_clk" },
 789                 .num_parents = 1,
 790         },
 791 };
 792
 793 static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
 794 static struct clk_regmap g12b_cpub_clk_apb_sel = {
 795         .data = &(struct clk_regmap_mux_data){
 796                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 797                 .mask = 7,
 798                 .shift = 3,
 799                 .table = mux_table_cpub,
 800         },
 801         .hw.init = &(struct clk_init_data){
 802                 .name = "cpub_clk_apb_sel",
 803                 .ops = &clk_regmap_mux_ro_ops,
 804                 .parent_names = (const char *[]){ "cpub_clk_div2",
 805                                                   "cpub_clk_div3",
 806                                                   "cpub_clk_div4",
 807                                                   "cpub_clk_div5",
 808                                                   "cpub_clk_div6",
 809                                                   "cpub_clk_div7",
 810                                                   "cpub_clk_div8" },
 811                 .num_parents = 7,
 812         },
 813 };
 814
 815 static struct clk_regmap g12b_cpub_clk_apb = {
 816         .data = &(struct clk_regmap_gate_data){
 817                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 818                 .bit_idx = 16,
 819                 .flags = CLK_GATE_SET_TO_DISABLE,
 820         },
 821         .hw.init = &(struct clk_init_data) {
 822                 .name = "cpub_clk_apb",
 823                 .ops = &clk_regmap_gate_ro_ops,
 824                 .parent_names = (const char *[]){ "cpub_clk_apb_sel" },
 825                 .num_parents = 1,
 826                 /*
 827                  * This clock is set by the ROM monitor code,
 828                  * Linux should not change it at runtime
 829                  */
 830         },
 831 };
 832
 833 static struct clk_regmap g12b_cpub_clk_atb_sel = {
 834         .data = &(struct clk_regmap_mux_data){
 835                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 836                 .mask = 7,
 837                 .shift = 6,
 838                 .table = mux_table_cpub,
 839         },
 840         .hw.init = &(struct clk_init_data){
 841                 .name = "cpub_clk_atb_sel",
 842                 .ops = &clk_regmap_mux_ro_ops,
 843                 .parent_names = (const char *[]){ "cpub_clk_div2",
 844                                                   "cpub_clk_div3",
 845                                                   "cpub_clk_div4",
 846                                                   "cpub_clk_div5",
 847                                                   "cpub_clk_div6",
 848                                                   "cpub_clk_div7",
 849                                                   "cpub_clk_div8" },
 850                 .num_parents = 7,
 851         },
 852 };
 853
 854 static struct clk_regmap g12b_cpub_clk_atb = {
 855         .data = &(struct clk_regmap_gate_data){
 856                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 857                 .bit_idx = 17,
 858                 .flags = CLK_GATE_SET_TO_DISABLE,
 859         },
 860         .hw.init = &(struct clk_init_data) {
 861                 .name = "cpub_clk_atb",
 862                 .ops = &clk_regmap_gate_ro_ops,
 863                 .parent_names = (const char *[]){ "cpub_clk_atb_sel" },
 864                 .num_parents = 1,
 865                 /*
 866                  * This clock is set by the ROM monitor code,
 867                  * Linux should not change it at runtime
 868                  */
 869         },
 870 };
 871
 872 static struct clk_regmap g12b_cpub_clk_axi_sel = {
 873         .data = &(struct clk_regmap_mux_data){
 874                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 875                 .mask = 7,
 876                 .shift = 9,
 877                 .table = mux_table_cpub,
 878         },
 879         .hw.init = &(struct clk_init_data){
 880                 .name = "cpub_clk_axi_sel",
 881                 .ops = &clk_regmap_mux_ro_ops,
 882                 .parent_names = (const char *[]){ "cpub_clk_div2",
 883                                                   "cpub_clk_div3",
 884                                                   "cpub_clk_div4",
 885                                                   "cpub_clk_div5",
 886                                                   "cpub_clk_div6",
 887                                                   "cpub_clk_div7",
 888                                                   "cpub_clk_div8" },
 889                 .num_parents = 7,
 890         },
 891 };
 892
 893 static struct clk_regmap g12b_cpub_clk_axi = {
 894         .data = &(struct clk_regmap_gate_data){
 895                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 896                 .bit_idx = 18,
 897                 .flags = CLK_GATE_SET_TO_DISABLE,
 898         },
 899         .hw.init = &(struct clk_init_data) {
 900                 .name = "cpub_clk_axi",
 901                 .ops = &clk_regmap_gate_ro_ops,
 902                 .parent_names = (const char *[]){ "cpub_clk_axi_sel" },
 903                 .num_parents = 1,
 904                 /*
 905                  * This clock is set by the ROM monitor code,
 906                  * Linux should not change it at runtime
 907                  */
 908         },
 909 };
 910
 911 static struct clk_regmap g12b_cpub_clk_trace_sel = {
 912         .data = &(struct clk_regmap_mux_data){
 913                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 914                 .mask = 7,
 915                 .shift = 20,
 916                 .table = mux_table_cpub,
 917         },
 918         .hw.init = &(struct clk_init_data){
 919                 .name = "cpub_clk_trace_sel",
 920                 .ops = &clk_regmap_mux_ro_ops,
 921                 .parent_names = (const char *[]){ "cpub_clk_div2",
 922                                                   "cpub_clk_div3",
 923                                                   "cpub_clk_div4",
 924                                                   "cpub_clk_div5",
 925                                                   "cpub_clk_div6",
 926                                                   "cpub_clk_div7",
 927                                                   "cpub_clk_div8" },
 928                 .num_parents = 7,
 929         },
 930 };
 931
 932 static struct clk_regmap g12b_cpub_clk_trace = {
 933         .data = &(struct clk_regmap_gate_data){
 934                 .offset = HHI_SYS_CPUB_CLK_CNTL1,
 935                 .bit_idx = 23,
 936                 .flags = CLK_GATE_SET_TO_DISABLE,
 937         },
 938         .hw.init = &(struct clk_init_data) {
 939                 .name = "cpub_clk_trace",
 940                 .ops = &clk_regmap_gate_ro_ops,
 941                 .parent_names = (const char *[]){ "cpub_clk_trace_sel" },
 942                 .num_parents = 1,
 943                 /*
 944                  * This clock is set by the ROM monitor code,
 945                  * Linux should not change it at runtime
 946                  */
 947         },
 948 };
 949
 950 static const struct pll_mult_range g12a_gp0_pll_mult_range = {
 951         .min = 55,
 952         .max = 255,
 953 };
 954
 955 /*
 956  * Internal gp0 pll emulation configuration parameters
 957  */
 958 static const struct reg_sequence g12a_gp0_init_regs[] = {
 959         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0x00000000 },
 960         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x00000000 },
 961         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x48681c00 },
 962         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x33771290 },
 963         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x39272000 },
 964         { .reg = HHI_GP0_PLL_CNTL6,     .def = 0x56540000 },
 965 };
 966
 967 static struct clk_regmap g12a_gp0_pll_dco = {
 968         .data = &(struct meson_clk_pll_data){
 969                 .en = {
 970                         .reg_off = HHI_GP0_PLL_CNTL0,
 971                         .shift   = 28,
 972                         .width   = 1,
 973                 },
 974                 .m = {
 975                         .reg_off = HHI_GP0_PLL_CNTL0,
 976                         .shift   = 0,
 977                         .width   = 8,
 978                 },
 979                 .n = {
 980                         .reg_off = HHI_GP0_PLL_CNTL0,
 981                         .shift   = 10,
 982                         .width   = 5,
 983                 },
 984                 .frac = {
 985                         .reg_off = HHI_GP0_PLL_CNTL1,
 986                         .shift   = 0,
 987                         .width   = 17,
 988                 },
 989                 .l = {
 990                         .reg_off = HHI_GP0_PLL_CNTL0,
 991                         .shift   = 31,
 992                         .width   = 1,
 993                 },
 994                 .rst = {
 995                         .reg_off = HHI_GP0_PLL_CNTL0,
 996                         .shift   = 29,
 997                         .width   = 1,
 998                 },
 999                 .range = &g12a_gp0_pll_mult_range,
1000                 .init_regs = g12a_gp0_init_regs,
1001                 .init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1002         },
1003         .hw.init = &(struct clk_init_data){
1004                 .name = "gp0_pll_dco",
1005                 .ops = &meson_clk_pll_ops,
1006                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
1007                 .num_parents = 1,
1008         },
1009 };
1010
1011 static struct clk_regmap g12a_gp0_pll = {
1012         .data = &(struct clk_regmap_div_data){
1013                 .offset = HHI_GP0_PLL_CNTL0,
1014                 .shift = 16,
1015                 .width = 3,
1016                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1017                           CLK_DIVIDER_ROUND_CLOSEST),
1018         },
1019         .hw.init = &(struct clk_init_data){
1020                 .name = "gp0_pll",
1021                 .ops = &clk_regmap_divider_ops,
1022                 .parent_names = (const char *[]){ "gp0_pll_dco" },
1023                 .num_parents = 1,
1024                 .flags = CLK_SET_RATE_PARENT,
1025         },
1026 };
1027
1028 /*
1029  * Internal hifi pll emulation configuration parameters
1030  */
1031 static const struct reg_sequence g12a_hifi_init_regs[] = {
1032         { .reg = HHI_HIFI_PLL_CNTL1,    .def = 0x00000000 },
1033         { .reg = HHI_HIFI_PLL_CNTL2,    .def = 0x00000000 },
1034         { .reg = HHI_HIFI_PLL_CNTL3,    .def = 0x6a285c00 },
1035         { .reg = HHI_HIFI_PLL_CNTL4,    .def = 0x65771290 },
1036         { .reg = HHI_HIFI_PLL_CNTL5,    .def = 0x39272000 },
1037         { .reg = HHI_HIFI_PLL_CNTL6,    .def = 0x56540000 },
1038 };
1039
1040 static struct clk_regmap g12a_hifi_pll_dco = {
1041         .data = &(struct meson_clk_pll_data){
1042                 .en = {
1043                         .reg_off = HHI_HIFI_PLL_CNTL0,
1044                         .shift   = 28,
1045                         .width   = 1,
1046                 },
1047                 .m = {
1048                         .reg_off = HHI_HIFI_PLL_CNTL0,
1049                         .shift   = 0,
1050                         .width   = 8,
1051                 },
1052                 .n = {
1053                         .reg_off = HHI_HIFI_PLL_CNTL0,
1054                         .shift   = 10,
1055                         .width   = 5,
1056                 },
1057                 .frac = {
1058                         .reg_off = HHI_HIFI_PLL_CNTL1,
1059                         .shift   = 0,
1060                         .width   = 17,
1061                 },
1062                 .l = {
1063                         .reg_off = HHI_HIFI_PLL_CNTL0,
1064                         .shift   = 31,
1065                         .width   = 1,
1066                 },
1067                 .rst = {
1068                         .reg_off = HHI_HIFI_PLL_CNTL0,
1069                         .shift   = 29,
1070                         .width   = 1,
1071                 },
1072                 .range = &g12a_gp0_pll_mult_range,
1073                 .init_regs = g12a_hifi_init_regs,
1074                 .init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1075                 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
1076         },
1077         .hw.init = &(struct clk_init_data){
1078                 .name = "hifi_pll_dco",
1079                 .ops = &meson_clk_pll_ops,
1080                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
1081                 .num_parents = 1,
1082         },
1083 };
1084
1085 static struct clk_regmap g12a_hifi_pll = {
1086         .data = &(struct clk_regmap_div_data){
1087                 .offset = HHI_HIFI_PLL_CNTL0,
1088                 .shift = 16,
1089                 .width = 2,
1090                 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1091                           CLK_DIVIDER_ROUND_CLOSEST),
1092         },
1093         .hw.init = &(struct clk_init_data){
1094                 .name = "hifi_pll",
1095                 .ops = &clk_regmap_divider_ops,
1096                 .parent_names = (const char *[]){ "hifi_pll_dco" },
1097                 .num_parents = 1,
1098                 .flags = CLK_SET_RATE_PARENT,
1099         },
1100 };
1101
1102 /*
1103  * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1104  * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1105  * a strict register sequence to enable the PLL.
1106  */
1107 static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1108         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x20090496 },
1109         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x30090496 },
1110         { .reg = HHI_PCIE_PLL_CNTL1,    .def = 0x00000000 },
1111         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0x00001100 },
1112         { .reg = HHI_PCIE_PLL_CNTL3,    .def = 0x10058e00 },
1113         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0x000100c0 },
1114         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x68000048 },
1115         { .reg = HHI_PCIE_PLL_CNTL5,    .def = 0x68000068, .delay_us = 20 },
1116         { .reg = HHI_PCIE_PLL_CNTL4,    .def = 0x008100c0, .delay_us = 10 },
1117         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x34090496 },
1118         { .reg = HHI_PCIE_PLL_CNTL0,    .def = 0x14090496, .delay_us = 10 },
1119         { .reg = HHI_PCIE_PLL_CNTL2,    .def = 0x00001000 },
1120 };
1121
1122 /* Keep a single entry table for recalc/round_rate() ops */
1123 static const struct pll_params_table g12a_pcie_pll_table[] = {
1124         PLL_PARAMS(150, 1),
1125         {0, 0},
1126 };
1127
1128 static struct clk_regmap g12a_pcie_pll_dco = {
1129         .data = &(struct meson_clk_pll_data){
1130                 .en = {
1131                         .reg_off = HHI_PCIE_PLL_CNTL0,
1132                         .shift   = 28,
1133                         .width   = 1,
1134                 },
1135                 .m = {
1136                         .reg_off = HHI_PCIE_PLL_CNTL0,
1137                         .shift   = 0,
1138                         .width   = 8,
1139                 },
1140                 .n = {
1141                         .reg_off = HHI_PCIE_PLL_CNTL0,
1142                         .shift   = 10,
1143                         .width   = 5,
1144                 },
1145                 .frac = {
1146                         .reg_off = HHI_PCIE_PLL_CNTL1,
1147                         .shift   = 0,
1148                         .width   = 12,
1149                 },
1150                 .l = {
1151                         .reg_off = HHI_PCIE_PLL_CNTL0,
1152                         .shift   = 31,
1153                         .width   = 1,
1154                 },
1155                 .rst = {
1156                         .reg_off = HHI_PCIE_PLL_CNTL0,
1157                         .shift   = 29,
1158                         .width   = 1,
1159                 },
1160                 .table = g12a_pcie_pll_table,
1161                 .init_regs = g12a_pcie_pll_init_regs,
1162                 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1163         },
1164         .hw.init = &(struct clk_init_data){
1165                 .name = "pcie_pll_dco",
1166                 .ops = &meson_clk_pcie_pll_ops,
1167                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
1168                 .num_parents = 1,
1169         },
1170 };
1171
1172 static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1173         .mult = 1,
1174         .div = 2,
1175         .hw.init = &(struct clk_init_data){
1176                 .name = "pcie_pll_dco_div2",
1177                 .ops = &clk_fixed_factor_ops,
1178                 .parent_names = (const char *[]){ "pcie_pll_dco" },
1179                 .num_parents = 1,
1180                 .flags = CLK_SET_RATE_PARENT,
1181         },
1182 };
1183
1184 static struct clk_regmap g12a_pcie_pll_od = {
1185         .data = &(struct clk_regmap_div_data){
1186                 .offset = HHI_PCIE_PLL_CNTL0,
1187                 .shift = 16,
1188                 .width = 5,
1189                 .flags = CLK_DIVIDER_ROUND_CLOSEST |
1190                          CLK_DIVIDER_ONE_BASED |
1191                          CLK_DIVIDER_ALLOW_ZERO,
1192         },
1193         .hw.init = &(struct clk_init_data){
1194                 .name = "pcie_pll_od",
1195                 .ops = &clk_regmap_divider_ops,
1196                 .parent_names = (const char *[]){ "pcie_pll_dco_div2" },
1197                 .num_parents = 1,
1198                 .flags = CLK_SET_RATE_PARENT,
1199         },
1200 };
1201
1202 static struct clk_fixed_factor g12a_pcie_pll = {
1203         .mult = 1,
1204         .div = 2,
1205         .hw.init = &(struct clk_init_data){
1206                 .name = "pcie_pll_pll",
1207                 .ops = &clk_fixed_factor_ops,
1208                 .parent_names = (const char *[]){ "pcie_pll_od" },
1209                 .num_parents = 1,
1210                 .flags = CLK_SET_RATE_PARENT,
1211         },
1212 };
1213
1214 static struct clk_regmap g12a_hdmi_pll_dco = {
1215         .data = &(struct meson_clk_pll_data){
1216                 .en = {
1217                         .reg_off = HHI_HDMI_PLL_CNTL0,
1218                         .shift   = 28,
1219                         .width   = 1,
1220                 },
1221                 .m = {
1222                         .reg_off = HHI_HDMI_PLL_CNTL0,
1223                         .shift   = 0,
1224                         .width   = 8,
1225                 },
1226                 .n = {
1227                         .reg_off = HHI_HDMI_PLL_CNTL0,
1228                         .shift   = 10,
1229                         .width   = 5,
1230                 },
1231                 .frac = {
1232                         .reg_off = HHI_HDMI_PLL_CNTL1,
1233                         .shift   = 0,
1234                         .width   = 16,
1235                 },
1236                 .l = {
1237                         .reg_off = HHI_HDMI_PLL_CNTL0,
1238                         .shift   = 30,
1239                         .width   = 1,
1240                 },
1241                 .rst = {
1242                         .reg_off = HHI_HDMI_PLL_CNTL0,
1243                         .shift   = 29,
1244                         .width   = 1,
1245                 },
1246         },
1247         .hw.init = &(struct clk_init_data){
1248                 .name = "hdmi_pll_dco",
1249                 .ops = &meson_clk_pll_ro_ops,
1250                 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
1251                 .num_parents = 1,
1252                 /*
1253                  * Display directly handle hdmi pll registers ATM, we need
1254                  * NOCACHE to keep our view of the clock as accurate as possible
1255                  */
1256                 .flags = CLK_GET_RATE_NOCACHE,
1257         },
1258 };
1259
1260 static struct clk_regmap g12a_hdmi_pll_od = {
1261         .data = &(struct clk_regmap_div_data){
1262                 .offset = HHI_HDMI_PLL_CNTL0,
1263                 .shift = 16,
1264                 .width = 2,
1265                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1266         },
1267         .hw.init = &(struct clk_init_data){
1268                 .name = "hdmi_pll_od",
1269                 .ops = &clk_regmap_divider_ro_ops,
1270                 .parent_names = (const char *[]){ "hdmi_pll_dco" },
1271                 .num_parents = 1,
1272                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1273         },
1274 };
1275
1276 static struct clk_regmap g12a_hdmi_pll_od2 = {
1277         .data = &(struct clk_regmap_div_data){
1278                 .offset = HHI_HDMI_PLL_CNTL0,
1279                 .shift = 18,
1280                 .width = 2,
1281                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1282         },
1283         .hw.init = &(struct clk_init_data){
1284                 .name = "hdmi_pll_od2",
1285                 .ops = &clk_regmap_divider_ro_ops,
1286                 .parent_names = (const char *[]){ "hdmi_pll_od" },
1287                 .num_parents = 1,
1288                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1289         },
1290 };
1291
1292 static struct clk_regmap g12a_hdmi_pll = {
1293         .data = &(struct clk_regmap_div_data){
1294                 .offset = HHI_HDMI_PLL_CNTL0,
1295                 .shift = 20,
1296                 .width = 2,
1297                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1298         },
1299         .hw.init = &(struct clk_init_data){
1300                 .name = "hdmi_pll",
1301                 .ops = &clk_regmap_divider_ro_ops,
1302                 .parent_names = (const char *[]){ "hdmi_pll_od2" },
1303                 .num_parents = 1,
1304                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1305         },
1306 };
1307
1308 static struct clk_fixed_factor g12a_fclk_div2_div = {
1309         .mult = 1,
1310         .div = 2,
1311         .hw.init = &(struct clk_init_data){
1312                 .name = "fclk_div2_div",
1313                 .ops = &clk_fixed_factor_ops,
1314                 .parent_names = (const char *[]){ "fixed_pll" },
1315                 .num_parents = 1,
1316         },
1317 };
1318
1319 static struct clk_regmap g12a_fclk_div2 = {
1320         .data = &(struct clk_regmap_gate_data){
1321                 .offset = HHI_FIX_PLL_CNTL1,
1322                 .bit_idx = 24,
1323         },
1324         .hw.init = &(struct clk_init_data){
1325                 .name = "fclk_div2",
1326                 .ops = &clk_regmap_gate_ops,
1327                 .parent_names = (const char *[]){ "fclk_div2_div" },
1328                 .num_parents = 1,
1329         },
1330 };
1331
1332 static struct clk_fixed_factor g12a_fclk_div3_div = {
1333         .mult = 1,
1334         .div = 3,
1335         .hw.init = &(struct clk_init_data){
1336                 .name = "fclk_div3_div",
1337                 .ops = &clk_fixed_factor_ops,
1338                 .parent_names = (const char *[]){ "fixed_pll" },
1339                 .num_parents = 1,
1340         },
1341 };
1342
1343 static struct clk_regmap g12a_fclk_div3 = {
1344         .data = &(struct clk_regmap_gate_data){
1345                 .offset = HHI_FIX_PLL_CNTL1,
1346                 .bit_idx = 20,
1347         },
1348         .hw.init = &(struct clk_init_data){
1349                 .name = "fclk_div3",
1350                 .ops = &clk_regmap_gate_ops,
1351                 .parent_names = (const char *[]){ "fclk_div3_div" },
1352                 .num_parents = 1,
1353                 /*
1354                  * This clock is used by the resident firmware and is required
1355                  * by the platform to operate correctly.
1356                  * Until the following condition are met, we need this clock to
1357                  * be marked as critical:
1358                  * a) Mark the clock used by a firmware resource, if possible
1359                  * b) CCF has a clock hand-off mechanism to make the sure the
1360                  *    clock stays on until the proper driver comes along
1361                  */
1362                 .flags = CLK_IS_CRITICAL,
1363         },
1364 };
1365
1366 static struct clk_fixed_factor g12a_fclk_div4_div = {
1367         .mult = 1,
1368         .div = 4,
1369         .hw.init = &(struct clk_init_data){
1370                 .name = "fclk_div4_div",
1371                 .ops = &clk_fixed_factor_ops,
1372                 .parent_names = (const char *[]){ "fixed_pll" },
1373                 .num_parents = 1,
1374         },
1375 };
1376
1377 static struct clk_regmap g12a_fclk_div4 = {
1378         .data = &(struct clk_regmap_gate_data){
1379                 .offset = HHI_FIX_PLL_CNTL1,
1380                 .bit_idx = 21,
1381         },
1382         .hw.init = &(struct clk_init_data){
1383                 .name = "fclk_div4",
1384                 .ops = &clk_regmap_gate_ops,
1385                 .parent_names = (const char *[]){ "fclk_div4_div" },
1386                 .num_parents = 1,
1387         },
1388 };
1389
1390 static struct clk_fixed_factor g12a_fclk_div5_div = {
1391         .mult = 1,
1392         .div = 5,
1393         .hw.init = &(struct clk_init_data){
1394                 .name = "fclk_div5_div",
1395                 .ops = &clk_fixed_factor_ops,
1396                 .parent_names = (const char *[]){ "fixed_pll" },
1397                 .num_parents = 1,
1398         },
1399 };
1400
1401 static struct clk_regmap g12a_fclk_div5 = {
1402         .data = &(struct clk_regmap_gate_data){
1403                 .offset = HHI_FIX_PLL_CNTL1,
1404                 .bit_idx = 22,
1405         },
1406         .hw.init = &(struct clk_init_data){
1407                 .name = "fclk_div5",
1408                 .ops = &clk_regmap_gate_ops,
1409                 .parent_names = (const char *[]){ "fclk_div5_div" },
1410                 .num_parents = 1,
1411         },
1412 };
1413
1414 static struct clk_fixed_factor g12a_fclk_div7_div = {
1415         .mult = 1,
1416         .div = 7,
1417         .hw.init = &(struct clk_init_data){
1418                 .name = "fclk_div7_div",
1419                 .ops = &clk_fixed_factor_ops,
1420                 .parent_names = (const char *[]){ "fixed_pll" },
1421                 .num_parents = 1,
1422         },
1423 };
1424
1425 static struct clk_regmap g12a_fclk_div7 = {
1426         .data = &(struct clk_regmap_gate_data){
1427                 .offset = HHI_FIX_PLL_CNTL1,
1428                 .bit_idx = 23,
1429         },
1430         .hw.init = &(struct clk_init_data){
1431                 .name = "fclk_div7",
1432                 .ops = &clk_regmap_gate_ops,
1433                 .parent_names = (const char *[]){ "fclk_div7_div" },
1434                 .num_parents = 1,
1435         },
1436 };
1437
1438 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
1439         .mult = 1,
1440         .div = 5,
1441         .hw.init = &(struct clk_init_data){
1442                 .name = "fclk_div2p5_div",
1443                 .ops = &clk_fixed_factor_ops,
1444                 .parent_names = (const char *[]){ "fixed_pll_dco" },
1445                 .num_parents = 1,
1446         },
1447 };
1448
1449 static struct clk_regmap g12a_fclk_div2p5 = {
1450         .data = &(struct clk_regmap_gate_data){
1451                 .offset = HHI_FIX_PLL_CNTL1,
1452                 .bit_idx = 25,
1453         },
1454         .hw.init = &(struct clk_init_data){
1455                 .name = "fclk_div2p5",
1456                 .ops = &clk_regmap_gate_ops,
1457                 .parent_names = (const char *[]){ "fclk_div2p5_div" },
1458                 .num_parents = 1,
1459         },
1460 };
1461
1462 static struct clk_fixed_factor g12a_mpll_50m_div = {
1463         .mult = 1,
1464         .div = 80,
1465         .hw.init = &(struct clk_init_data){
1466                 .name = "mpll_50m_div",
1467                 .ops = &clk_fixed_factor_ops,
1468                 .parent_names = (const char *[]){ "fixed_pll_dco" },
1469                 .num_parents = 1,
1470         },
1471 };
1472
1473 static struct clk_regmap g12a_mpll_50m = {
1474         .data = &(struct clk_regmap_mux_data){
1475                 .offset = HHI_FIX_PLL_CNTL3,
1476                 .mask = 0x1,
1477                 .shift = 5,
1478         },
1479         .hw.init = &(struct clk_init_data){
1480                 .name = "mpll_50m",
1481                 .ops = &clk_regmap_mux_ro_ops,
1482                 .parent_names = (const char *[]){ IN_PREFIX "xtal",
1483                                                   "mpll_50m_div" },
1484                 .num_parents = 2,
1485         },
1486 };
1487
1488 static struct clk_fixed_factor g12a_mpll_prediv = {
1489         .mult = 1,
1490         .div = 2,
1491         .hw.init = &(struct clk_init_data){
1492                 .name = "mpll_prediv",
1493                 .ops = &clk_fixed_factor_ops,
1494                 .parent_names = (const char *[]){ "fixed_pll_dco" },
1495                 .num_parents = 1,
1496         },
1497 };
1498
1499 static const struct reg_sequence g12a_mpll0_init_regs[] = {
1500         { .reg = HHI_MPLL_CNTL2,        .def = 0x40000033 },
1501 };
1502
1503 static struct clk_regmap g12a_mpll0_div = {
1504         .data = &(struct meson_clk_mpll_data){
1505                 .sdm = {
1506                         .reg_off = HHI_MPLL_CNTL1,
1507                         .shift   = 0,
1508                         .width   = 14,
1509                 },
1510                 .sdm_en = {
1511                         .reg_off = HHI_MPLL_CNTL1,
1512                         .shift   = 30,
1513                         .width   = 1,
1514                 },
1515                 .n2 = {
1516                         .reg_off = HHI_MPLL_CNTL1,
1517                         .shift   = 20,
1518                         .width   = 9,
1519                 },
1520                 .ssen = {
1521                         .reg_off = HHI_MPLL_CNTL1,
1522                         .shift   = 29,
1523                         .width   = 1,
1524                 },
1525                 .lock = &meson_clk_lock,
1526                 .init_regs = g12a_mpll0_init_regs,
1527                 .init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
1528         },
1529         .hw.init = &(struct clk_init_data){
1530                 .name = "mpll0_div",
1531                 .ops = &meson_clk_mpll_ops,
1532                 .parent_names = (const char *[]){ "mpll_prediv" },
1533                 .num_parents = 1,
1534         },
1535 };
1536
1537 static struct clk_regmap g12a_mpll0 = {
1538         .data = &(struct clk_regmap_gate_data){
1539                 .offset = HHI_MPLL_CNTL1,
1540                 .bit_idx = 31,
1541         },
1542         .hw.init = &(struct clk_init_data){
1543                 .name = "mpll0",
1544                 .ops = &clk_regmap_gate_ops,
1545                 .parent_names = (const char *[]){ "mpll0_div" },
1546                 .num_parents = 1,
1547                 .flags = CLK_SET_RATE_PARENT,
1548         },
1549 };
1550
1551 static const struct reg_sequence g12a_mpll1_init_regs[] = {
1552         { .reg = HHI_MPLL_CNTL4,        .def = 0x40000033 },
1553 };
1554
1555 static struct clk_regmap g12a_mpll1_div = {
1556         .data = &(struct meson_clk_mpll_data){
1557                 .sdm = {
1558                         .reg_off = HHI_MPLL_CNTL3,
1559                         .shift   = 0,
1560                         .width   = 14,
1561                 },
1562                 .sdm_en = {
1563                         .reg_off = HHI_MPLL_CNTL3,
1564                         .shift   = 30,
1565                         .width   = 1,
1566                 },
1567                 .n2 = {
1568                         .reg_off = HHI_MPLL_CNTL3,
1569                         .shift   = 20,
1570                         .width   = 9,
1571                 },
1572                 .ssen = {
1573                         .reg_off = HHI_MPLL_CNTL3,
1574                         .shift   = 29,
1575                         .width   = 1,
1576                 },
1577                 .lock = &meson_clk_lock,
1578                 .init_regs = g12a_mpll1_init_regs,
1579                 .init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
1580         },
1581         .hw.init = &(struct clk_init_data){
1582                 .name = "mpll1_div",
1583                 .ops = &meson_clk_mpll_ops,
1584                 .parent_names = (const char *[]){ "mpll_prediv" },
1585                 .num_parents = 1,
1586         },
1587 };
1588
1589 static struct clk_regmap g12a_mpll1 = {
1590         .data = &(struct clk_regmap_gate_data){
1591                 .offset = HHI_MPLL_CNTL3,
1592                 .bit_idx = 31,
1593         },
1594         .hw.init = &(struct clk_init_data){
1595                 .name = "mpll1",
1596                 .ops = &clk_regmap_gate_ops,
1597                 .parent_names = (const char *[]){ "mpll1_div" },
1598                 .num_parents = 1,
1599                 .flags = CLK_SET_RATE_PARENT,
1600         },
1601 };
1602
1603 static const struct reg_sequence g12a_mpll2_init_regs[] = {
1604         { .reg = HHI_MPLL_CNTL6,        .def = 0x40000033 },
1605 };
1606
1607 static struct clk_regmap g12a_mpll2_div = {
1608         .data = &(struct meson_clk_mpll_data){
1609                 .sdm = {
1610                         .reg_off = HHI_MPLL_CNTL5,
1611                         .shift   = 0,
1612                         .width   = 14,
1613                 },
1614                 .sdm_en = {
1615                         .reg_off = HHI_MPLL_CNTL5,
1616                         .shift   = 30,
1617                         .width   = 1,
1618                 },
1619                 .n2 = {
1620                         .reg_off = HHI_MPLL_CNTL5,
1621                         .shift   = 20,
1622                         .width   = 9,
1623                 },
1624                 .ssen = {
1625                         .reg_off = HHI_MPLL_CNTL5,
1626                         .shift   = 29,
1627                         .width   = 1,
1628                 },
1629                 .lock = &meson_clk_lock,
1630                 .init_regs = g12a_mpll2_init_regs,
1631                 .init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
1632         },
1633         .hw.init = &(struct clk_init_data){
1634                 .name = "mpll2_div",
1635                 .ops = &meson_clk_mpll_ops,
1636                 .parent_names = (const char *[]){ "mpll_prediv" },
1637                 .num_parents = 1,
1638         },
1639 };
1640
1641 static struct clk_regmap g12a_mpll2 = {
1642         .data = &(struct clk_regmap_gate_data){
1643                 .offset = HHI_MPLL_CNTL5,
1644                 .bit_idx = 31,
1645         },
1646         .hw.init = &(struct clk_init_data){
1647                 .name = "mpll2",
1648                 .ops = &clk_regmap_gate_ops,
1649                 .parent_names = (const char *[]){ "mpll2_div" },
1650                 .num_parents = 1,
1651                 .flags = CLK_SET_RATE_PARENT,
1652         },
1653 };
1654
1655 static const struct reg_sequence g12a_mpll3_init_regs[] = {
1656         { .reg = HHI_MPLL_CNTL8,        .def = 0x40000033 },
1657 };
1658
1659 static struct clk_regmap g12a_mpll3_div = {
1660         .data = &(struct meson_clk_mpll_data){
1661                 .sdm = {
1662                         .reg_off = HHI_MPLL_CNTL7,
1663                         .shift   = 0,
1664                         .width   = 14,
1665                 },
1666                 .sdm_en = {
1667                         .reg_off = HHI_MPLL_CNTL7,
1668                         .shift   = 30,
1669                         .width   = 1,
1670                 },
1671                 .n2 = {
1672                         .reg_off = HHI_MPLL_CNTL7,
1673                         .shift   = 20,
1674                         .width   = 9,
1675                 },
1676                 .ssen = {
1677                         .reg_off = HHI_MPLL_CNTL7,
1678                         .shift   = 29,
1679                         .width   = 1,
1680                 },
1681                 .lock = &meson_clk_lock,
1682                 .init_regs = g12a_mpll3_init_regs,
1683                 .init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
1684         },
1685         .hw.init = &(struct clk_init_data){
1686                 .name = "mpll3_div",
1687                 .ops = &meson_clk_mpll_ops,
1688                 .parent_names = (const char *[]){ "mpll_prediv" },
1689                 .num_parents = 1,
1690         },
1691 };
1692
1693 static struct clk_regmap g12a_mpll3 = {
1694         .data = &(struct clk_regmap_gate_data){
1695                 .offset = HHI_MPLL_CNTL7,
1696                 .bit_idx = 31,
1697         },
1698         .hw.init = &(struct clk_init_data){
1699                 .name = "mpll3",
1700                 .ops = &clk_regmap_gate_ops,
1701                 .parent_names = (const char *[]){ "mpll3_div" },
1702                 .num_parents = 1,
1703                 .flags = CLK_SET_RATE_PARENT,
1704         },
1705 };
1706
1707 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
1708 static const char * const clk81_parent_names[] = {
1709         IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
1710         "fclk_div3", "fclk_div5"
1711 };
1712
1713 static struct clk_regmap g12a_mpeg_clk_sel = {
1714         .data = &(struct clk_regmap_mux_data){
1715                 .offset = HHI_MPEG_CLK_CNTL,
1716                 .mask = 0x7,
1717                 .shift = 12,
1718                 .table = mux_table_clk81,
1719         },
1720         .hw.init = &(struct clk_init_data){
1721                 .name = "mpeg_clk_sel",
1722                 .ops = &clk_regmap_mux_ro_ops,
1723                 .parent_names = clk81_parent_names,
1724                 .num_parents = ARRAY_SIZE(clk81_parent_names),
1725         },
1726 };
1727
1728 static struct clk_regmap g12a_mpeg_clk_div = {
1729         .data = &(struct clk_regmap_div_data){
1730                 .offset = HHI_MPEG_CLK_CNTL,
1731                 .shift = 0,
1732                 .width = 7,
1733         },
1734         .hw.init = &(struct clk_init_data){
1735                 .name = "mpeg_clk_div",
1736                 .ops = &clk_regmap_divider_ops,
1737                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
1738                 .num_parents = 1,
1739                 .flags = CLK_SET_RATE_PARENT,
1740         },
1741 };
1742
1743 static struct clk_regmap g12a_clk81 = {
1744         .data = &(struct clk_regmap_gate_data){
1745                 .offset = HHI_MPEG_CLK_CNTL,
1746                 .bit_idx = 7,
1747         },
1748         .hw.init = &(struct clk_init_data){
1749                 .name = "clk81",
1750                 .ops = &clk_regmap_gate_ops,
1751                 .parent_names = (const char *[]){ "mpeg_clk_div" },
1752                 .num_parents = 1,
1753                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
1754         },
1755 };
1756
1757 static const char * const g12a_sd_emmc_clk0_parent_names[] = {
1758         IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1759
1760         /*
1761          * Following these parent clocks, we should also have had mpll2, mpll3
1762          * and gp0_pll but these clocks are too precious to be used here. All
1763          * the necessary rates for MMC and NAND operation can be acheived using
1764          * g12a_ee_core or fclk_div clocks
1765          */
1766 };
1767
1768 /* SDIO clock */
1769 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
1770         .data = &(struct clk_regmap_mux_data){
1771                 .offset = HHI_SD_EMMC_CLK_CNTL,
1772                 .mask = 0x7,
1773                 .shift = 9,
1774         },
1775         .hw.init = &(struct clk_init_data) {
1776                 .name = "sd_emmc_a_clk0_sel",
1777                 .ops = &clk_regmap_mux_ops,
1778                 .parent_names = g12a_sd_emmc_clk0_parent_names,
1779                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1780                 .flags = CLK_SET_RATE_PARENT,
1781         },
1782 };
1783
1784 static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
1785         .data = &(struct clk_regmap_div_data){
1786                 .offset = HHI_SD_EMMC_CLK_CNTL,
1787                 .shift = 0,
1788                 .width = 7,
1789         },
1790         .hw.init = &(struct clk_init_data) {
1791                 .name = "sd_emmc_a_clk0_div",
1792                 .ops = &clk_regmap_divider_ops,
1793                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1794                 .num_parents = 1,
1795                 .flags = CLK_SET_RATE_PARENT,
1796         },
1797 };
1798
1799 static struct clk_regmap g12a_sd_emmc_a_clk0 = {
1800         .data = &(struct clk_regmap_gate_data){
1801                 .offset = HHI_SD_EMMC_CLK_CNTL,
1802                 .bit_idx = 7,
1803         },
1804         .hw.init = &(struct clk_init_data){
1805                 .name = "sd_emmc_a_clk0",
1806                 .ops = &clk_regmap_gate_ops,
1807                 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1808                 .num_parents = 1,
1809                 .flags = CLK_SET_RATE_PARENT,
1810         },
1811 };
1812
1813 /* SDcard clock */
1814 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
1815         .data = &(struct clk_regmap_mux_data){
1816                 .offset = HHI_SD_EMMC_CLK_CNTL,
1817                 .mask = 0x7,
1818                 .shift = 25,
1819         },
1820         .hw.init = &(struct clk_init_data) {
1821                 .name = "sd_emmc_b_clk0_sel",
1822                 .ops = &clk_regmap_mux_ops,
1823                 .parent_names = g12a_sd_emmc_clk0_parent_names,
1824                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1825                 .flags = CLK_SET_RATE_PARENT,
1826         },
1827 };
1828
1829 static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
1830         .data = &(struct clk_regmap_div_data){
1831                 .offset = HHI_SD_EMMC_CLK_CNTL,
1832                 .shift = 16,
1833                 .width = 7,
1834         },
1835         .hw.init = &(struct clk_init_data) {
1836                 .name = "sd_emmc_b_clk0_div",
1837                 .ops = &clk_regmap_divider_ops,
1838                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1839                 .num_parents = 1,
1840                 .flags = CLK_SET_RATE_PARENT,
1841         },
1842 };
1843
1844 static struct clk_regmap g12a_sd_emmc_b_clk0 = {
1845         .data = &(struct clk_regmap_gate_data){
1846                 .offset = HHI_SD_EMMC_CLK_CNTL,
1847                 .bit_idx = 23,
1848         },
1849         .hw.init = &(struct clk_init_data){
1850                 .name = "sd_emmc_b_clk0",
1851                 .ops = &clk_regmap_gate_ops,
1852                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1853                 .num_parents = 1,
1854                 .flags = CLK_SET_RATE_PARENT,
1855         },
1856 };
1857
1858 /* EMMC/NAND clock */
1859 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
1860         .data = &(struct clk_regmap_mux_data){
1861                 .offset = HHI_NAND_CLK_CNTL,
1862                 .mask = 0x7,
1863                 .shift = 9,
1864         },
1865         .hw.init = &(struct clk_init_data) {
1866                 .name = "sd_emmc_c_clk0_sel",
1867                 .ops = &clk_regmap_mux_ops,
1868                 .parent_names = g12a_sd_emmc_clk0_parent_names,
1869                 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
1870                 .flags = CLK_SET_RATE_PARENT,
1871         },
1872 };
1873
1874 static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
1875         .data = &(struct clk_regmap_div_data){
1876                 .offset = HHI_NAND_CLK_CNTL,
1877                 .shift = 0,
1878                 .width = 7,
1879         },
1880         .hw.init = &(struct clk_init_data) {
1881                 .name = "sd_emmc_c_clk0_div",
1882                 .ops = &clk_regmap_divider_ops,
1883                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1884                 .num_parents = 1,
1885                 .flags = CLK_SET_RATE_PARENT,
1886         },
1887 };
1888
1889 static struct clk_regmap g12a_sd_emmc_c_clk0 = {
1890         .data = &(struct clk_regmap_gate_data){
1891                 .offset = HHI_NAND_CLK_CNTL,
1892                 .bit_idx = 7,
1893         },
1894         .hw.init = &(struct clk_init_data){
1895                 .name = "sd_emmc_c_clk0",
1896                 .ops = &clk_regmap_gate_ops,
1897                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1898                 .num_parents = 1,
1899                 .flags = CLK_SET_RATE_PARENT,
1900         },
1901 };
1902
1903 /* VPU Clock */
1904
1905 static const char * const g12a_vpu_parent_names[] = {
1906         "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1907         "mpll1", "vid_pll", "hifi_pll", "gp0_pll",
1908 };
1909
1910 static struct clk_regmap g12a_vpu_0_sel = {
1911         .data = &(struct clk_regmap_mux_data){
1912                 .offset = HHI_VPU_CLK_CNTL,
1913                 .mask = 0x7,
1914                 .shift = 9,
1915         },
1916         .hw.init = &(struct clk_init_data){
1917                 .name = "vpu_0_sel",
1918                 .ops = &clk_regmap_mux_ops,
1919                 .parent_names = g12a_vpu_parent_names,
1920                 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1921                 .flags = CLK_SET_RATE_NO_REPARENT,
1922         },
1923 };
1924
1925 static struct clk_regmap g12a_vpu_0_div = {
1926         .data = &(struct clk_regmap_div_data){
1927                 .offset = HHI_VPU_CLK_CNTL,
1928                 .shift = 0,
1929                 .width = 7,
1930         },
1931         .hw.init = &(struct clk_init_data){
1932                 .name = "vpu_0_div",
1933                 .ops = &clk_regmap_divider_ops,
1934                 .parent_names = (const char *[]){ "vpu_0_sel" },
1935                 .num_parents = 1,
1936                 .flags = CLK_SET_RATE_PARENT,
1937         },
1938 };
1939
1940 static struct clk_regmap g12a_vpu_0 = {
1941         .data = &(struct clk_regmap_gate_data){
1942                 .offset = HHI_VPU_CLK_CNTL,
1943                 .bit_idx = 8,
1944         },
1945         .hw.init = &(struct clk_init_data) {
1946                 .name = "vpu_0",
1947                 .ops = &clk_regmap_gate_ops,
1948                 .parent_names = (const char *[]){ "vpu_0_div" },
1949                 .num_parents = 1,
1950                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1951         },
1952 };
1953
1954 static struct clk_regmap g12a_vpu_1_sel = {
1955         .data = &(struct clk_regmap_mux_data){
1956                 .offset = HHI_VPU_CLK_CNTL,
1957                 .mask = 0x7,
1958                 .shift = 25,
1959         },
1960         .hw.init = &(struct clk_init_data){
1961                 .name = "vpu_1_sel",
1962                 .ops = &clk_regmap_mux_ops,
1963                 .parent_names = g12a_vpu_parent_names,
1964                 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
1965                 .flags = CLK_SET_RATE_NO_REPARENT,
1966         },
1967 };
1968
1969 static struct clk_regmap g12a_vpu_1_div = {
1970         .data = &(struct clk_regmap_div_data){
1971                 .offset = HHI_VPU_CLK_CNTL,
1972                 .shift = 16,
1973                 .width = 7,
1974         },
1975         .hw.init = &(struct clk_init_data){
1976                 .name = "vpu_1_div",
1977                 .ops = &clk_regmap_divider_ops,
1978                 .parent_names = (const char *[]){ "vpu_1_sel" },
1979                 .num_parents = 1,
1980                 .flags = CLK_SET_RATE_PARENT,
1981         },
1982 };
1983
1984 static struct clk_regmap g12a_vpu_1 = {
1985         .data = &(struct clk_regmap_gate_data){
1986                 .offset = HHI_VPU_CLK_CNTL,
1987                 .bit_idx = 24,
1988         },
1989         .hw.init = &(struct clk_init_data) {
1990                 .name = "vpu_1",
1991                 .ops = &clk_regmap_gate_ops,
1992                 .parent_names = (const char *[]){ "vpu_1_div" },
1993                 .num_parents = 1,
1994                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1995         },
1996 };
1997
1998 static struct clk_regmap g12a_vpu = {
1999         .data = &(struct clk_regmap_mux_data){
2000                 .offset = HHI_VPU_CLK_CNTL,
2001                 .mask = 1,
2002                 .shift = 31,
2003         },
2004         .hw.init = &(struct clk_init_data){
2005                 .name = "vpu",
2006                 .ops = &clk_regmap_mux_ops,
2007                 /*
2008                  * bit 31 selects from 2 possible parents:
2009                  * vpu_0 or vpu_1
2010                  */
2011                 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
2012                 .num_parents = 2,
2013                 .flags = CLK_SET_RATE_NO_REPARENT,
2014         },
2015 };
2016
2017 /* VDEC clocks */
2018
2019 static const char * const g12a_vdec_parent_names[] = {
2020         "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
2021         "hifi_pll", "gp0_pll",
2022 };
2023
2024 static struct clk_regmap g12a_vdec_1_sel = {
2025         .data = &(struct clk_regmap_mux_data){
2026                 .offset = HHI_VDEC_CLK_CNTL,
2027                 .mask = 0x7,
2028                 .shift = 9,
2029                 .flags = CLK_MUX_ROUND_CLOSEST,
2030         },
2031         .hw.init = &(struct clk_init_data){
2032                 .name = "vdec_1_sel",
2033                 .ops = &clk_regmap_mux_ops,
2034                 .parent_names = g12a_vdec_parent_names,
2035                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
2036                 .flags = CLK_SET_RATE_PARENT,
2037         },
2038 };
2039
2040 static struct clk_regmap g12a_vdec_1_div = {
2041         .data = &(struct clk_regmap_div_data){
2042                 .offset = HHI_VDEC_CLK_CNTL,
2043                 .shift = 0,
2044                 .width = 7,
2045                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2046         },
2047         .hw.init = &(struct clk_init_data){
2048                 .name = "vdec_1_div",
2049                 .ops = &clk_regmap_divider_ops,
2050                 .parent_names = (const char *[]){ "vdec_1_sel" },
2051                 .num_parents = 1,
2052                 .flags = CLK_SET_RATE_PARENT,
2053         },
2054 };
2055
2056 static struct clk_regmap g12a_vdec_1 = {
2057         .data = &(struct clk_regmap_gate_data){
2058                 .offset = HHI_VDEC_CLK_CNTL,
2059                 .bit_idx = 8,
2060         },
2061         .hw.init = &(struct clk_init_data) {
2062                 .name = "vdec_1",
2063                 .ops = &clk_regmap_gate_ops,
2064                 .parent_names = (const char *[]){ "vdec_1_div" },
2065                 .num_parents = 1,
2066                 .flags = CLK_SET_RATE_PARENT,
2067         },
2068 };
2069
2070 static struct clk_regmap g12a_vdec_hevcf_sel = {
2071         .data = &(struct clk_regmap_mux_data){
2072                 .offset = HHI_VDEC2_CLK_CNTL,
2073                 .mask = 0x7,
2074                 .shift = 9,
2075                 .flags = CLK_MUX_ROUND_CLOSEST,
2076         },
2077         .hw.init = &(struct clk_init_data){
2078                 .name = "vdec_hevcf_sel",
2079                 .ops = &clk_regmap_mux_ops,
2080                 .parent_names = g12a_vdec_parent_names,
2081                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
2082                 .flags = CLK_SET_RATE_PARENT,
2083         },
2084 };
2085
2086 static struct clk_regmap g12a_vdec_hevcf_div = {
2087         .data = &(struct clk_regmap_div_data){
2088                 .offset = HHI_VDEC2_CLK_CNTL,
2089                 .shift = 0,
2090                 .width = 7,
2091                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2092         },
2093         .hw.init = &(struct clk_init_data){
2094                 .name = "vdec_hevcf_div",
2095                 .ops = &clk_regmap_divider_ops,
2096                 .parent_names = (const char *[]){ "vdec_hevcf_sel" },
2097                 .num_parents = 1,
2098                 .flags = CLK_SET_RATE_PARENT,
2099         },
2100 };
2101
2102 static struct clk_regmap g12a_vdec_hevcf = {
2103         .data = &(struct clk_regmap_gate_data){
2104                 .offset = HHI_VDEC2_CLK_CNTL,
2105                 .bit_idx = 8,
2106         },
2107         .hw.init = &(struct clk_init_data) {
2108                 .name = "vdec_hevcf",
2109                 .ops = &clk_regmap_gate_ops,
2110                 .parent_names = (const char *[]){ "vdec_hevcf_div" },
2111                 .num_parents = 1,
2112                 .flags = CLK_SET_RATE_PARENT,
2113         },
2114 };
2115
2116 static struct clk_regmap g12a_vdec_hevc_sel = {
2117         .data = &(struct clk_regmap_mux_data){
2118                 .offset = HHI_VDEC2_CLK_CNTL,
2119                 .mask = 0x7,
2120                 .shift = 25,
2121                 .flags = CLK_MUX_ROUND_CLOSEST,
2122         },
2123         .hw.init = &(struct clk_init_data){
2124                 .name = "vdec_hevc_sel",
2125                 .ops = &clk_regmap_mux_ops,
2126                 .parent_names = g12a_vdec_parent_names,
2127                 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
2128                 .flags = CLK_SET_RATE_PARENT,
2129         },
2130 };
2131
2132 static struct clk_regmap g12a_vdec_hevc_div = {
2133         .data = &(struct clk_regmap_div_data){
2134                 .offset = HHI_VDEC2_CLK_CNTL,
2135                 .shift = 16,
2136                 .width = 7,
2137                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2138         },
2139         .hw.init = &(struct clk_init_data){
2140                 .name = "vdec_hevc_div",
2141                 .ops = &clk_regmap_divider_ops,
2142                 .parent_names = (const char *[]){ "vdec_hevc_sel" },
2143                 .num_parents = 1,
2144                 .flags = CLK_SET_RATE_PARENT,
2145         },
2146 };
2147
2148 static struct clk_regmap g12a_vdec_hevc = {
2149         .data = &(struct clk_regmap_gate_data){
2150                 .offset = HHI_VDEC2_CLK_CNTL,
2151                 .bit_idx = 24,
2152         },
2153         .hw.init = &(struct clk_init_data) {
2154                 .name = "vdec_hevc",
2155                 .ops = &clk_regmap_gate_ops,
2156                 .parent_names = (const char *[]){ "vdec_hevc_div" },
2157                 .num_parents = 1,
2158                 .flags = CLK_SET_RATE_PARENT,
2159         },
2160 };
2161
2162 /* VAPB Clock */
2163
2164 static const char * const g12a_vapb_parent_names[] = {
2165         "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
2166         "mpll1", "vid_pll", "mpll2", "fclk_div2p5",
2167 };
2168
2169 static struct clk_regmap g12a_vapb_0_sel = {
2170         .data = &(struct clk_regmap_mux_data){
2171                 .offset = HHI_VAPBCLK_CNTL,
2172                 .mask = 0x3,
2173                 .shift = 9,
2174         },
2175         .hw.init = &(struct clk_init_data){
2176                 .name = "vapb_0_sel",
2177                 .ops = &clk_regmap_mux_ops,
2178                 .parent_names = g12a_vapb_parent_names,
2179                 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
2180                 .flags = CLK_SET_RATE_NO_REPARENT,
2181         },
2182 };
2183
2184 static struct clk_regmap g12a_vapb_0_div = {
2185         .data = &(struct clk_regmap_div_data){
2186                 .offset = HHI_VAPBCLK_CNTL,
2187                 .shift = 0,
2188                 .width = 7,
2189         },
2190         .hw.init = &(struct clk_init_data){
2191                 .name = "vapb_0_div",
2192                 .ops = &clk_regmap_divider_ops,
2193                 .parent_names = (const char *[]){ "vapb_0_sel" },
2194                 .num_parents = 1,
2195                 .flags = CLK_SET_RATE_PARENT,
2196         },
2197 };
2198
2199 static struct clk_regmap g12a_vapb_0 = {
2200         .data = &(struct clk_regmap_gate_data){
2201                 .offset = HHI_VAPBCLK_CNTL,
2202                 .bit_idx = 8,
2203         },
2204         .hw.init = &(struct clk_init_data) {
2205                 .name = "vapb_0",
2206                 .ops = &clk_regmap_gate_ops,
2207                 .parent_names = (const char *[]){ "vapb_0_div" },
2208                 .num_parents = 1,
2209                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2210         },
2211 };
2212
2213 static struct clk_regmap g12a_vapb_1_sel = {
2214         .data = &(struct clk_regmap_mux_data){
2215                 .offset = HHI_VAPBCLK_CNTL,
2216                 .mask = 0x3,
2217                 .shift = 25,
2218         },
2219         .hw.init = &(struct clk_init_data){
2220                 .name = "vapb_1_sel",
2221                 .ops = &clk_regmap_mux_ops,
2222                 .parent_names = g12a_vapb_parent_names,
2223                 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
2224                 .flags = CLK_SET_RATE_NO_REPARENT,
2225         },
2226 };
2227
2228 static struct clk_regmap g12a_vapb_1_div = {
2229         .data = &(struct clk_regmap_div_data){
2230                 .offset = HHI_VAPBCLK_CNTL,
2231                 .shift = 16,
2232                 .width = 7,
2233         },
2234         .hw.init = &(struct clk_init_data){
2235                 .name = "vapb_1_div",
2236                 .ops = &clk_regmap_divider_ops,
2237                 .parent_names = (const char *[]){ "vapb_1_sel" },
2238                 .num_parents = 1,
2239                 .flags = CLK_SET_RATE_PARENT,
2240         },
2241 };
2242
2243 static struct clk_regmap g12a_vapb_1 = {
2244         .data = &(struct clk_regmap_gate_data){
2245                 .offset = HHI_VAPBCLK_CNTL,
2246                 .bit_idx = 24,
2247         },
2248         .hw.init = &(struct clk_init_data) {
2249                 .name = "vapb_1",
2250                 .ops = &clk_regmap_gate_ops,
2251                 .parent_names = (const char *[]){ "vapb_1_div" },
2252                 .num_parents = 1,
2253                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2254         },
2255 };
2256
2257 static struct clk_regmap g12a_vapb_sel = {
2258         .data = &(struct clk_regmap_mux_data){
2259                 .offset = HHI_VAPBCLK_CNTL,
2260                 .mask = 1,
2261                 .shift = 31,
2262         },
2263         .hw.init = &(struct clk_init_data){
2264                 .name = "vapb_sel",
2265                 .ops = &clk_regmap_mux_ops,
2266                 /*
2267                  * bit 31 selects from 2 possible parents:
2268                  * vapb_0 or vapb_1
2269                  */
2270                 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
2271                 .num_parents = 2,
2272                 .flags = CLK_SET_RATE_NO_REPARENT,
2273         },
2274 };
2275
2276 static struct clk_regmap g12a_vapb = {
2277         .data = &(struct clk_regmap_gate_data){
2278                 .offset = HHI_VAPBCLK_CNTL,
2279                 .bit_idx = 30,
2280         },
2281         .hw.init = &(struct clk_init_data) {
2282                 .name = "vapb",
2283                 .ops = &clk_regmap_gate_ops,
2284                 .parent_names = (const char *[]){ "vapb_sel" },
2285                 .num_parents = 1,
2286                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2287         },
2288 };
2289
2290 /* Video Clocks */
2291
2292 static struct clk_regmap g12a_vid_pll_div = {
2293         .data = &(struct meson_vid_pll_div_data){
2294                 .val = {
2295                         .reg_off = HHI_VID_PLL_CLK_DIV,
2296                         .shift   = 0,
2297                         .width   = 15,
2298                 },
2299                 .sel = {
2300                         .reg_off = HHI_VID_PLL_CLK_DIV,
2301                         .shift   = 16,
2302                         .width   = 2,
2303                 },
2304         },
2305         .hw.init = &(struct clk_init_data) {
2306                 .name = "vid_pll_div",
2307                 .ops = &meson_vid_pll_div_ro_ops,
2308                 .parent_names = (const char *[]){ "hdmi_pll" },
2309                 .num_parents = 1,
2310                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2311         },
2312 };
2313
2314 static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
2315                                                           "hdmi_pll" };
2316
2317 static struct clk_regmap g12a_vid_pll_sel = {
2318         .data = &(struct clk_regmap_mux_data){
2319                 .offset = HHI_VID_PLL_CLK_DIV,
2320                 .mask = 0x1,
2321                 .shift = 18,
2322         },
2323         .hw.init = &(struct clk_init_data){
2324                 .name = "vid_pll_sel",
2325                 .ops = &clk_regmap_mux_ops,
2326                 /*
2327                  * bit 18 selects from 2 possible parents:
2328                  * vid_pll_div or hdmi_pll
2329                  */
2330                 .parent_names = g12a_vid_pll_parent_names,
2331                 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
2332                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2333         },
2334 };
2335
2336 static struct clk_regmap g12a_vid_pll = {
2337         .data = &(struct clk_regmap_gate_data){
2338                 .offset = HHI_VID_PLL_CLK_DIV,
2339                 .bit_idx = 19,
2340         },
2341         .hw.init = &(struct clk_init_data) {
2342                 .name = "vid_pll",
2343                 .ops = &clk_regmap_gate_ops,
2344                 .parent_names = (const char *[]){ "vid_pll_sel" },
2345                 .num_parents = 1,
2346                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2347         },
2348 };
2349
2350 static const char * const g12a_vclk_parent_names[] = {
2351         "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
2352         "fclk_div5", "fclk_div7"
2353 };
2354
2355 static struct clk_regmap g12a_vclk_sel = {
2356         .data = &(struct clk_regmap_mux_data){
2357                 .offset = HHI_VID_CLK_CNTL,
2358                 .mask = 0x7,
2359                 .shift = 16,
2360         },
2361         .hw.init = &(struct clk_init_data){
2362                 .name = "vclk_sel",
2363                 .ops = &clk_regmap_mux_ops,
2364                 .parent_names = g12a_vclk_parent_names,
2365                 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
2366                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2367         },
2368 };
2369
2370 static struct clk_regmap g12a_vclk2_sel = {
2371         .data = &(struct clk_regmap_mux_data){
2372                 .offset = HHI_VIID_CLK_CNTL,
2373                 .mask = 0x7,
2374                 .shift = 16,
2375         },
2376         .hw.init = &(struct clk_init_data){
2377                 .name = "vclk2_sel",
2378                 .ops = &clk_regmap_mux_ops,
2379                 .parent_names = g12a_vclk_parent_names,
2380                 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
2381                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2382         },
2383 };
2384
2385 static struct clk_regmap g12a_vclk_input = {
2386         .data = &(struct clk_regmap_gate_data){
2387                 .offset = HHI_VID_CLK_DIV,
2388                 .bit_idx = 16,
2389         },
2390         .hw.init = &(struct clk_init_data) {
2391                 .name = "vclk_input",
2392                 .ops = &clk_regmap_gate_ops,
2393                 .parent_names = (const char *[]){ "vclk_sel" },
2394                 .num_parents = 1,
2395                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2396         },
2397 };
2398
2399 static struct clk_regmap g12a_vclk2_input = {
2400         .data = &(struct clk_regmap_gate_data){
2401                 .offset = HHI_VIID_CLK_DIV,
2402                 .bit_idx = 16,
2403         },
2404         .hw.init = &(struct clk_init_data) {
2405                 .name = "vclk2_input",
2406                 .ops = &clk_regmap_gate_ops,
2407                 .parent_names = (const char *[]){ "vclk2_sel" },
2408                 .num_parents = 1,
2409                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2410         },
2411 };
2412
2413 static struct clk_regmap g12a_vclk_div = {
2414         .data = &(struct clk_regmap_div_data){
2415                 .offset = HHI_VID_CLK_DIV,
2416                 .shift = 0,
2417                 .width = 8,
2418         },
2419         .hw.init = &(struct clk_init_data){
2420                 .name = "vclk_div",
2421                 .ops = &clk_regmap_divider_ops,
2422                 .parent_names = (const char *[]){ "vclk_input" },
2423                 .num_parents = 1,
2424                 .flags = CLK_GET_RATE_NOCACHE,
2425         },
2426 };
2427
2428 static struct clk_regmap g12a_vclk2_div = {
2429         .data = &(struct clk_regmap_div_data){
2430                 .offset = HHI_VIID_CLK_DIV,
2431                 .shift = 0,
2432                 .width = 8,
2433         },
2434         .hw.init = &(struct clk_init_data){
2435                 .name = "vclk2_div",
2436                 .ops = &clk_regmap_divider_ops,
2437                 .parent_names = (const char *[]){ "vclk2_input" },
2438                 .num_parents = 1,
2439                 .flags = CLK_GET_RATE_NOCACHE,
2440         },
2441 };
2442
2443 static struct clk_regmap g12a_vclk = {
2444         .data = &(struct clk_regmap_gate_data){
2445                 .offset = HHI_VID_CLK_CNTL,
2446                 .bit_idx = 19,
2447         },
2448         .hw.init = &(struct clk_init_data) {
2449                 .name = "vclk",
2450                 .ops = &clk_regmap_gate_ops,
2451                 .parent_names = (const char *[]){ "vclk_div" },
2452                 .num_parents = 1,
2453                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2454         },
2455 };
2456
2457 static struct clk_regmap g12a_vclk2 = {
2458         .data = &(struct clk_regmap_gate_data){
2459                 .offset = HHI_VIID_CLK_CNTL,
2460                 .bit_idx = 19,
2461         },
2462         .hw.init = &(struct clk_init_data) {
2463                 .name = "vclk2",
2464                 .ops = &clk_regmap_gate_ops,
2465                 .parent_names = (const char *[]){ "vclk2_div" },
2466                 .num_parents = 1,
2467                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2468         },
2469 };
2470
2471 static struct clk_regmap g12a_vclk_div1 = {
2472         .data = &(struct clk_regmap_gate_data){
2473                 .offset = HHI_VID_CLK_CNTL,
2474                 .bit_idx = 0,
2475         },
2476         .hw.init = &(struct clk_init_data) {
2477                 .name = "vclk_div1",
2478                 .ops = &clk_regmap_gate_ops,
2479                 .parent_names = (const char *[]){ "vclk" },
2480                 .num_parents = 1,
2481                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2482         },
2483 };
2484
2485 static struct clk_regmap g12a_vclk_div2_en = {
2486         .data = &(struct clk_regmap_gate_data){
2487                 .offset = HHI_VID_CLK_CNTL,
2488                 .bit_idx = 1,
2489         },
2490         .hw.init = &(struct clk_init_data) {
2491                 .name = "vclk_div2_en",
2492                 .ops = &clk_regmap_gate_ops,
2493                 .parent_names = (const char *[]){ "vclk" },
2494                 .num_parents = 1,
2495                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2496         },
2497 };
2498
2499 static struct clk_regmap g12a_vclk_div4_en = {
2500         .data = &(struct clk_regmap_gate_data){
2501                 .offset = HHI_VID_CLK_CNTL,
2502                 .bit_idx = 2,
2503         },
2504         .hw.init = &(struct clk_init_data) {
2505                 .name = "vclk_div4_en",
2506                 .ops = &clk_regmap_gate_ops,
2507                 .parent_names = (const char *[]){ "vclk" },
2508                 .num_parents = 1,
2509                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2510         },
2511 };
2512
2513 static struct clk_regmap g12a_vclk_div6_en = {
2514         .data = &(struct clk_regmap_gate_data){
2515                 .offset = HHI_VID_CLK_CNTL,
2516                 .bit_idx = 3,
2517         },
2518         .hw.init = &(struct clk_init_data) {
2519                 .name = "vclk_div6_en",
2520                 .ops = &clk_regmap_gate_ops,
2521                 .parent_names = (const char *[]){ "vclk" },
2522                 .num_parents = 1,
2523                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2524         },
2525 };
2526
2527 static struct clk_regmap g12a_vclk_div12_en = {
2528         .data = &(struct clk_regmap_gate_data){
2529                 .offset = HHI_VID_CLK_CNTL,
2530                 .bit_idx = 4,
2531         },
2532         .hw.init = &(struct clk_init_data) {
2533                 .name = "vclk_div12_en",
2534                 .ops = &clk_regmap_gate_ops,
2535                 .parent_names = (const char *[]){ "vclk" },
2536                 .num_parents = 1,
2537                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2538         },
2539 };
2540
2541 static struct clk_regmap g12a_vclk2_div1 = {
2542         .data = &(struct clk_regmap_gate_data){
2543                 .offset = HHI_VIID_CLK_CNTL,
2544                 .bit_idx = 0,
2545         },
2546         .hw.init = &(struct clk_init_data) {
2547                 .name = "vclk2_div1",
2548                 .ops = &clk_regmap_gate_ops,
2549                 .parent_names = (const char *[]){ "vclk2" },
2550                 .num_parents = 1,
2551                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2552         },
2553 };
2554
2555 static struct clk_regmap g12a_vclk2_div2_en = {
2556         .data = &(struct clk_regmap_gate_data){
2557                 .offset = HHI_VIID_CLK_CNTL,
2558                 .bit_idx = 1,
2559         },
2560         .hw.init = &(struct clk_init_data) {
2561                 .name = "vclk2_div2_en",
2562                 .ops = &clk_regmap_gate_ops,
2563                 .parent_names = (const char *[]){ "vclk2" },
2564                 .num_parents = 1,
2565                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2566         },
2567 };
2568
2569 static struct clk_regmap g12a_vclk2_div4_en = {
2570         .data = &(struct clk_regmap_gate_data){
2571                 .offset = HHI_VIID_CLK_CNTL,
2572                 .bit_idx = 2,
2573         },
2574         .hw.init = &(struct clk_init_data) {
2575                 .name = "vclk2_div4_en",
2576                 .ops = &clk_regmap_gate_ops,
2577                 .parent_names = (const char *[]){ "vclk2" },
2578                 .num_parents = 1,
2579                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2580         },
2581 };
2582
2583 static struct clk_regmap g12a_vclk2_div6_en = {
2584         .data = &(struct clk_regmap_gate_data){
2585                 .offset = HHI_VIID_CLK_CNTL,
2586                 .bit_idx = 3,
2587         },
2588         .hw.init = &(struct clk_init_data) {
2589                 .name = "vclk2_div6_en",
2590                 .ops = &clk_regmap_gate_ops,
2591                 .parent_names = (const char *[]){ "vclk2" },
2592                 .num_parents = 1,
2593                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2594         },
2595 };
2596
2597 static struct clk_regmap g12a_vclk2_div12_en = {
2598         .data = &(struct clk_regmap_gate_data){
2599                 .offset = HHI_VIID_CLK_CNTL,
2600                 .bit_idx = 4,
2601         },
2602         .hw.init = &(struct clk_init_data) {
2603                 .name = "vclk2_div12_en",
2604                 .ops = &clk_regmap_gate_ops,
2605                 .parent_names = (const char *[]){ "vclk2" },
2606                 .num_parents = 1,
2607                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2608         },
2609 };
2610
2611 static struct clk_fixed_factor g12a_vclk_div2 = {
2612         .mult = 1,
2613         .div = 2,
2614         .hw.init = &(struct clk_init_data){
2615                 .name = "vclk_div2",
2616                 .ops = &clk_fixed_factor_ops,
2617                 .parent_names = (const char *[]){ "vclk_div2_en" },
2618                 .num_parents = 1,
2619         },
2620 };
2621
2622 static struct clk_fixed_factor g12a_vclk_div4 = {
2623         .mult = 1,
2624         .div = 4,
2625         .hw.init = &(struct clk_init_data){
2626                 .name = "vclk_div4",
2627                 .ops = &clk_fixed_factor_ops,
2628                 .parent_names = (const char *[]){ "vclk_div4_en" },
2629                 .num_parents = 1,
2630         },
2631 };
2632
2633 static struct clk_fixed_factor g12a_vclk_div6 = {
2634         .mult = 1,
2635         .div = 6,
2636         .hw.init = &(struct clk_init_data){
2637                 .name = "vclk_div6",
2638                 .ops = &clk_fixed_factor_ops,
2639                 .parent_names = (const char *[]){ "vclk_div6_en" },
2640                 .num_parents = 1,
2641         },
2642 };
2643
2644 static struct clk_fixed_factor g12a_vclk_div12 = {
2645         .mult = 1,
2646         .div = 12,
2647         .hw.init = &(struct clk_init_data){
2648                 .name = "vclk_div12",
2649                 .ops = &clk_fixed_factor_ops,
2650                 .parent_names = (const char *[]){ "vclk_div12_en" },
2651                 .num_parents = 1,
2652         },
2653 };
2654
2655 static struct clk_fixed_factor g12a_vclk2_div2 = {
2656         .mult = 1,
2657         .div = 2,
2658         .hw.init = &(struct clk_init_data){
2659                 .name = "vclk2_div2",
2660                 .ops = &clk_fixed_factor_ops,
2661                 .parent_names = (const char *[]){ "vclk2_div2_en" },
2662                 .num_parents = 1,
2663         },
2664 };
2665
2666 static struct clk_fixed_factor g12a_vclk2_div4 = {
2667         .mult = 1,
2668         .div = 4,
2669         .hw.init = &(struct clk_init_data){
2670                 .name = "vclk2_div4",
2671                 .ops = &clk_fixed_factor_ops,
2672                 .parent_names = (const char *[]){ "vclk2_div4_en" },
2673                 .num_parents = 1,
2674         },
2675 };
2676
2677 static struct clk_fixed_factor g12a_vclk2_div6 = {
2678         .mult = 1,
2679         .div = 6,
2680         .hw.init = &(struct clk_init_data){
2681                 .name = "vclk2_div6",
2682                 .ops = &clk_fixed_factor_ops,
2683                 .parent_names = (const char *[]){ "vclk2_div6_en" },
2684                 .num_parents = 1,
2685         },
2686 };
2687
2688 static struct clk_fixed_factor g12a_vclk2_div12 = {
2689         .mult = 1,
2690         .div = 12,
2691         .hw.init = &(struct clk_init_data){
2692                 .name = "vclk2_div12",
2693                 .ops = &clk_fixed_factor_ops,
2694                 .parent_names = (const char *[]){ "vclk2_div12_en" },
2695                 .num_parents = 1,
2696         },
2697 };
2698
2699 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2700 static const char * const g12a_cts_parent_names[] = {
2701         "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2702         "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2703         "vclk2_div6", "vclk2_div12"
2704 };
2705
2706 static struct clk_regmap g12a_cts_enci_sel = {
2707         .data = &(struct clk_regmap_mux_data){
2708                 .offset = HHI_VID_CLK_DIV,
2709                 .mask = 0xf,
2710                 .shift = 28,
2711                 .table = mux_table_cts_sel,
2712         },
2713         .hw.init = &(struct clk_init_data){
2714                 .name = "cts_enci_sel",
2715                 .ops = &clk_regmap_mux_ops,
2716                 .parent_names = g12a_cts_parent_names,
2717                 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2718                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2719         },
2720 };
2721
2722 static struct clk_regmap g12a_cts_encp_sel = {
2723         .data = &(struct clk_regmap_mux_data){
2724                 .offset = HHI_VID_CLK_DIV,
2725                 .mask = 0xf,
2726                 .shift = 20,
2727                 .table = mux_table_cts_sel,
2728         },
2729         .hw.init = &(struct clk_init_data){
2730                 .name = "cts_encp_sel",
2731                 .ops = &clk_regmap_mux_ops,
2732                 .parent_names = g12a_cts_parent_names,
2733                 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2734                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2735         },
2736 };
2737
2738 static struct clk_regmap g12a_cts_vdac_sel = {
2739         .data = &(struct clk_regmap_mux_data){
2740                 .offset = HHI_VIID_CLK_DIV,
2741                 .mask = 0xf,
2742                 .shift = 28,
2743                 .table = mux_table_cts_sel,
2744         },
2745         .hw.init = &(struct clk_init_data){
2746                 .name = "cts_vdac_sel",
2747                 .ops = &clk_regmap_mux_ops,
2748                 .parent_names = g12a_cts_parent_names,
2749                 .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
2750                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2751         },
2752 };
2753
2754 /* TOFIX: add support for cts_tcon */
2755 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2756 static const char * const g12a_cts_hdmi_tx_parent_names[] = {
2757         "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2758         "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2759         "vclk2_div6", "vclk2_div12"
2760 };
2761
2762 static struct clk_regmap g12a_hdmi_tx_sel = {
2763         .data = &(struct clk_regmap_mux_data){
2764                 .offset = HHI_HDMI_CLK_CNTL,
2765                 .mask = 0xf,
2766                 .shift = 16,
2767                 .table = mux_table_hdmi_tx_sel,
2768         },
2769         .hw.init = &(struct clk_init_data){
2770                 .name = "hdmi_tx_sel",
2771                 .ops = &clk_regmap_mux_ops,
2772                 .parent_names = g12a_cts_hdmi_tx_parent_names,
2773                 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names),
2774                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2775         },
2776 };
2777
2778 static struct clk_regmap g12a_cts_enci = {
2779         .data = &(struct clk_regmap_gate_data){
2780                 .offset = HHI_VID_CLK_CNTL2,
2781                 .bit_idx = 0,
2782         },
2783         .hw.init = &(struct clk_init_data) {
2784                 .name = "cts_enci",
2785                 .ops = &clk_regmap_gate_ops,
2786                 .parent_names = (const char *[]){ "cts_enci_sel" },
2787                 .num_parents = 1,
2788                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2789         },
2790 };
2791
2792 static struct clk_regmap g12a_cts_encp = {
2793         .data = &(struct clk_regmap_gate_data){
2794                 .offset = HHI_VID_CLK_CNTL2,
2795                 .bit_idx = 2,
2796         },
2797         .hw.init = &(struct clk_init_data) {
2798                 .name = "cts_encp",
2799                 .ops = &clk_regmap_gate_ops,
2800                 .parent_names = (const char *[]){ "cts_encp_sel" },
2801                 .num_parents = 1,
2802                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2803         },
2804 };
2805
2806 static struct clk_regmap g12a_cts_vdac = {
2807         .data = &(struct clk_regmap_gate_data){
2808                 .offset = HHI_VID_CLK_CNTL2,
2809                 .bit_idx = 4,
2810         },
2811         .hw.init = &(struct clk_init_data) {
2812                 .name = "cts_vdac",
2813                 .ops = &clk_regmap_gate_ops,
2814                 .parent_names = (const char *[]){ "cts_vdac_sel" },
2815                 .num_parents = 1,
2816                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2817         },
2818 };
2819
2820 static struct clk_regmap g12a_hdmi_tx = {
2821         .data = &(struct clk_regmap_gate_data){
2822                 .offset = HHI_VID_CLK_CNTL2,
2823                 .bit_idx = 5,
2824         },
2825         .hw.init = &(struct clk_init_data) {
2826                 .name = "hdmi_tx",
2827                 .ops = &clk_regmap_gate_ops,
2828                 .parent_names = (const char *[]){ "hdmi_tx_sel" },
2829                 .num_parents = 1,
2830                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2831         },
2832 };
2833
2834 /* HDMI Clocks */
2835
2836 static const char * const g12a_hdmi_parent_names[] = {
2837         IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
2838 };
2839
2840 static struct clk_regmap g12a_hdmi_sel = {
2841         .data = &(struct clk_regmap_mux_data){
2842                 .offset = HHI_HDMI_CLK_CNTL,
2843                 .mask = 0x3,
2844                 .shift = 9,
2845                 .flags = CLK_MUX_ROUND_CLOSEST,
2846         },
2847         .hw.init = &(struct clk_init_data){
2848                 .name = "hdmi_sel",
2849                 .ops = &clk_regmap_mux_ops,
2850                 .parent_names = g12a_hdmi_parent_names,
2851                 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names),
2852                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2853         },
2854 };
2855
2856 static struct clk_regmap g12a_hdmi_div = {
2857         .data = &(struct clk_regmap_div_data){
2858                 .offset = HHI_HDMI_CLK_CNTL,
2859                 .shift = 0,
2860                 .width = 7,
2861         },
2862         .hw.init = &(struct clk_init_data){
2863                 .name = "hdmi_div",
2864                 .ops = &clk_regmap_divider_ops,
2865                 .parent_names = (const char *[]){ "hdmi_sel" },
2866                 .num_parents = 1,
2867                 .flags = CLK_GET_RATE_NOCACHE,
2868         },
2869 };
2870
2871 static struct clk_regmap g12a_hdmi = {
2872         .data = &(struct clk_regmap_gate_data){
2873                 .offset = HHI_HDMI_CLK_CNTL,
2874                 .bit_idx = 8,
2875         },
2876         .hw.init = &(struct clk_init_data) {
2877                 .name = "hdmi",
2878                 .ops = &clk_regmap_gate_ops,
2879                 .parent_names = (const char *[]){ "hdmi_div" },
2880                 .num_parents = 1,
2881                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2882         },
2883 };
2884
2885 /*
2886  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
2887  * muxed by a glitch-free switch.
2888  */
2889
2890 static const char * const g12a_mali_0_1_parent_names[] = {
2891         IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",
2892         "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"
2893 };
2894
2895 static struct clk_regmap g12a_mali_0_sel = {
2896         .data = &(struct clk_regmap_mux_data){
2897                 .offset = HHI_MALI_CLK_CNTL,
2898                 .mask = 0x7,
2899                 .shift = 9,
2900         },
2901         .hw.init = &(struct clk_init_data){
2902                 .name = "mali_0_sel",
2903                 .ops = &clk_regmap_mux_ops,
2904                 .parent_names = g12a_mali_0_1_parent_names,
2905                 .num_parents = 8,
2906                 .flags = CLK_SET_RATE_NO_REPARENT,
2907         },
2908 };
2909
2910 static struct clk_regmap g12a_mali_0_div = {
2911         .data = &(struct clk_regmap_div_data){
2912                 .offset = HHI_MALI_CLK_CNTL,
2913                 .shift = 0,
2914                 .width = 7,
2915         },
2916         .hw.init = &(struct clk_init_data){
2917                 .name = "mali_0_div",
2918                 .ops = &clk_regmap_divider_ops,
2919                 .parent_names = (const char *[]){ "mali_0_sel" },
2920                 .num_parents = 1,
2921                 .flags = CLK_SET_RATE_NO_REPARENT,
2922         },
2923 };
2924
2925 static struct clk_regmap g12a_mali_0 = {
2926         .data = &(struct clk_regmap_gate_data){
2927                 .offset = HHI_MALI_CLK_CNTL,
2928                 .bit_idx = 8,
2929         },
2930         .hw.init = &(struct clk_init_data){
2931                 .name = "mali_0",
2932                 .ops = &clk_regmap_gate_ops,
2933                 .parent_names = (const char *[]){ "mali_0_div" },
2934                 .num_parents = 1,
2935                 .flags = CLK_SET_RATE_PARENT,
2936         },
2937 };
2938
2939 static struct clk_regmap g12a_mali_1_sel = {
2940         .data = &(struct clk_regmap_mux_data){
2941                 .offset = HHI_MALI_CLK_CNTL,
2942                 .mask = 0x7,
2943                 .shift = 25,
2944         },
2945         .hw.init = &(struct clk_init_data){
2946                 .name = "mali_1_sel",
2947                 .ops = &clk_regmap_mux_ops,
2948                 .parent_names = g12a_mali_0_1_parent_names,
2949                 .num_parents = 8,
2950                 .flags = CLK_SET_RATE_NO_REPARENT,
2951         },
2952 };
2953
2954 static struct clk_regmap g12a_mali_1_div = {
2955         .data = &(struct clk_regmap_div_data){
2956                 .offset = HHI_MALI_CLK_CNTL,
2957                 .shift = 16,
2958                 .width = 7,
2959         },
2960         .hw.init = &(struct clk_init_data){
2961                 .name = "mali_1_div",
2962                 .ops = &clk_regmap_divider_ops,
2963                 .parent_names = (const char *[]){ "mali_1_sel" },
2964                 .num_parents = 1,
2965                 .flags = CLK_SET_RATE_NO_REPARENT,
2966         },
2967 };
2968
2969 static struct clk_regmap g12a_mali_1 = {
2970         .data = &(struct clk_regmap_gate_data){
2971                 .offset = HHI_MALI_CLK_CNTL,
2972                 .bit_idx = 24,
2973         },
2974         .hw.init = &(struct clk_init_data){
2975                 .name = "mali_1",
2976                 .ops = &clk_regmap_gate_ops,
2977                 .parent_names = (const char *[]){ "mali_1_div" },
2978                 .num_parents = 1,
2979                 .flags = CLK_SET_RATE_PARENT,
2980         },
2981 };
2982
2983 static const char * const g12a_mali_parent_names[] = {
2984         "mali_0", "mali_1"
2985 };
2986
2987 static struct clk_regmap g12a_mali = {
2988         .data = &(struct clk_regmap_mux_data){
2989                 .offset = HHI_MALI_CLK_CNTL,
2990                 .mask = 1,
2991                 .shift = 31,
2992         },
2993         .hw.init = &(struct clk_init_data){
2994                 .name = "mali",
2995                 .ops = &clk_regmap_mux_ops,
2996                 .parent_names = g12a_mali_parent_names,
2997                 .num_parents = 2,
2998                 .flags = CLK_SET_RATE_NO_REPARENT,
2999         },
3000 };
3001
3002 static struct clk_regmap g12a_ts_div = {
3003         .data = &(struct clk_regmap_div_data){
3004                 .offset = HHI_TS_CLK_CNTL,
3005                 .shift = 0,
3006                 .width = 8,
3007         },
3008         .hw.init = &(struct clk_init_data){
3009                 .name = "ts_div",
3010                 .ops = &clk_regmap_divider_ro_ops,
3011                 .parent_names = (const char *[]){ "xtal" },
3012                 .num_parents = 1,
3013         },
3014 };
3015
3016 static struct clk_regmap g12a_ts = {
3017         .data = &(struct clk_regmap_gate_data){
3018                 .offset = HHI_TS_CLK_CNTL,
3019                 .bit_idx = 8,
3020         },
3021         .hw.init = &(struct clk_init_data){
3022                 .name = "ts",
3023                 .ops = &clk_regmap_gate_ops,
3024                 .parent_names = (const char *[]){ "ts_div" },
3025                 .num_parents = 1,
3026         },
3027 };
3028
3029 /* Everything Else (EE) domain gates */
3030 static MESON_GATE(g12a_ddr,                     HHI_GCLK_MPEG0, 0);
3031 static MESON_GATE(g12a_dos,                     HHI_GCLK_MPEG0, 1);
3032 static MESON_GATE(g12a_audio_locker,            HHI_GCLK_MPEG0, 2);
3033 static MESON_GATE(g12a_mipi_dsi_host,           HHI_GCLK_MPEG0, 3);
3034 static MESON_GATE(g12a_eth_phy,                 HHI_GCLK_MPEG0, 4);
3035 static MESON_GATE(g12a_isa,                     HHI_GCLK_MPEG0, 5);
3036 static MESON_GATE(g12a_pl301,                   HHI_GCLK_MPEG0, 6);
3037 static MESON_GATE(g12a_periphs,                 HHI_GCLK_MPEG0, 7);
3038 static MESON_GATE(g12a_spicc_0,                 HHI_GCLK_MPEG0, 8);
3039 static MESON_GATE(g12a_i2c,                     HHI_GCLK_MPEG0, 9);
3040 static MESON_GATE(g12a_sana,                    HHI_GCLK_MPEG0, 10);
3041 static MESON_GATE(g12a_sd,                      HHI_GCLK_MPEG0, 11);
3042 static MESON_GATE(g12a_rng0,                    HHI_GCLK_MPEG0, 12);
3043 static MESON_GATE(g12a_uart0,                   HHI_GCLK_MPEG0, 13);
3044 static MESON_GATE(g12a_spicc_1,                 HHI_GCLK_MPEG0, 14);
3045 static MESON_GATE(g12a_hiu_reg,                 HHI_GCLK_MPEG0, 19);
3046 static MESON_GATE(g12a_mipi_dsi_phy,            HHI_GCLK_MPEG0, 20);
3047 static MESON_GATE(g12a_assist_misc,             HHI_GCLK_MPEG0, 23);
3048 static MESON_GATE(g12a_emmc_a,                  HHI_GCLK_MPEG0, 4);
3049 static MESON_GATE(g12a_emmc_b,                  HHI_GCLK_MPEG0, 25);
3050 static MESON_GATE(g12a_emmc_c,                  HHI_GCLK_MPEG0, 26);
3051 static MESON_GATE(g12a_audio_codec,             HHI_GCLK_MPEG0, 28);
3052
3053 static MESON_GATE(g12a_audio,                   HHI_GCLK_MPEG1, 0);
3054 static MESON_GATE(g12a_eth_core,                HHI_GCLK_MPEG1, 3);
3055 static MESON_GATE(g12a_demux,                   HHI_GCLK_MPEG1, 4);
3056 static MESON_GATE(g12a_audio_ififo,             HHI_GCLK_MPEG1, 11);
3057 static MESON_GATE(g12a_adc,                     HHI_GCLK_MPEG1, 13);
3058 static MESON_GATE(g12a_uart1,                   HHI_GCLK_MPEG1, 16);
3059 static MESON_GATE(g12a_g2d,                     HHI_GCLK_MPEG1, 20);
3060 static MESON_GATE(g12a_reset,                   HHI_GCLK_MPEG1, 23);
3061 static MESON_GATE(g12a_pcie_comb,               HHI_GCLK_MPEG1, 24);
3062 static MESON_GATE(g12a_parser,                  HHI_GCLK_MPEG1, 25);
3063 static MESON_GATE(g12a_usb_general,             HHI_GCLK_MPEG1, 26);
3064 static MESON_GATE(g12a_pcie_phy,                HHI_GCLK_MPEG1, 27);
3065 static MESON_GATE(g12a_ahb_arb0,                HHI_GCLK_MPEG1, 29);
3066
3067 static MESON_GATE(g12a_ahb_data_bus,            HHI_GCLK_MPEG2, 1);
3068 static MESON_GATE(g12a_ahb_ctrl_bus,            HHI_GCLK_MPEG2, 2);
3069 static MESON_GATE(g12a_htx_hdcp22,              HHI_GCLK_MPEG2, 3);
3070 static MESON_GATE(g12a_htx_pclk,                HHI_GCLK_MPEG2, 4);
3071 static MESON_GATE(g12a_bt656,                   HHI_GCLK_MPEG2, 6);
3072 static MESON_GATE(g12a_usb1_to_ddr,             HHI_GCLK_MPEG2, 8);
3073 static MESON_GATE(g12a_mmc_pclk,                HHI_GCLK_MPEG2, 11);
3074 static MESON_GATE(g12a_uart2,                   HHI_GCLK_MPEG2, 15);
3075 static MESON_GATE(g12a_vpu_intr,                HHI_GCLK_MPEG2, 25);
3076 static MESON_GATE(g12a_gic,                     HHI_GCLK_MPEG2, 30);
3077
3078 static MESON_GATE(g12a_vclk2_venci0,            HHI_GCLK_OTHER, 1);
3079 static MESON_GATE(g12a_vclk2_venci1,            HHI_GCLK_OTHER, 2);
3080 static MESON_GATE(g12a_vclk2_vencp0,            HHI_GCLK_OTHER, 3);
3081 static MESON_GATE(g12a_vclk2_vencp1,            HHI_GCLK_OTHER, 4);
3082 static MESON_GATE(g12a_vclk2_venct0,            HHI_GCLK_OTHER, 5);
3083 static MESON_GATE(g12a_vclk2_venct1,            HHI_GCLK_OTHER, 6);
3084 static MESON_GATE(g12a_vclk2_other,             HHI_GCLK_OTHER, 7);
3085 static MESON_GATE(g12a_vclk2_enci,              HHI_GCLK_OTHER, 8);
3086 static MESON_GATE(g12a_vclk2_encp,              HHI_GCLK_OTHER, 9);
3087 static MESON_GATE(g12a_dac_clk,                 HHI_GCLK_OTHER, 10);
3088 static MESON_GATE(g12a_aoclk_gate,              HHI_GCLK_OTHER, 14);
3089 static MESON_GATE(g12a_iec958_gate,             HHI_GCLK_OTHER, 16);
3090 static MESON_GATE(g12a_enc480p,                 HHI_GCLK_OTHER, 20);
3091 static MESON_GATE(g12a_rng1,                    HHI_GCLK_OTHER, 21);
3092 static MESON_GATE(g12a_vclk2_enct,              HHI_GCLK_OTHER, 22);
3093 static MESON_GATE(g12a_vclk2_encl,              HHI_GCLK_OTHER, 23);
3094 static MESON_GATE(g12a_vclk2_venclmmc,          HHI_GCLK_OTHER, 24);
3095 static MESON_GATE(g12a_vclk2_vencl,             HHI_GCLK_OTHER, 25);
3096 static MESON_GATE(g12a_vclk2_other1,            HHI_GCLK_OTHER, 26);
3097
3098 static MESON_GATE_RO(g12a_dma,                  HHI_GCLK_OTHER2, 0);
3099 static MESON_GATE_RO(g12a_efuse,                HHI_GCLK_OTHER2, 1);
3100 static MESON_GATE_RO(g12a_rom_boot,             HHI_GCLK_OTHER2, 2);
3101 static MESON_GATE_RO(g12a_reset_sec,            HHI_GCLK_OTHER2, 3);
3102 static MESON_GATE_RO(g12a_sec_ahb_apb3,         HHI_GCLK_OTHER2, 4);
3103
3104 /* Array of all clocks provided by this provider */
3105 static struct clk_hw_onecell_data g12a_hw_onecell_data = {
3106         .hws = {
3107                 [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
3108                 [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
3109                 [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
3110                 [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
3111                 [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
3112                 [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
3113                 [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
3114                 [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
3115                 [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
3116                 [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
3117                 [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
3118                 [CLKID_CLK81]                   = &g12a_clk81.hw,
3119                 [CLKID_MPLL0]                   = &g12a_mpll0.hw,
3120                 [CLKID_MPLL1]                   = &g12a_mpll1.hw,
3121                 [CLKID_MPLL2]                   = &g12a_mpll2.hw,
3122                 [CLKID_MPLL3]                   = &g12a_mpll3.hw,
3123                 [CLKID_DDR]                     = &g12a_ddr.hw,
3124                 [CLKID_DOS]                     = &g12a_dos.hw,
3125                 [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
3126                 [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
3127                 [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
3128                 [CLKID_ISA]                     = &g12a_isa.hw,
3129                 [CLKID_PL301]                   = &g12a_pl301.hw,
3130                 [CLKID_PERIPHS]                 = &g12a_periphs.hw,
3131                 [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
3132                 [CLKID_I2C]                     = &g12a_i2c.hw,
3133                 [CLKID_SANA]                    = &g12a_sana.hw,
3134                 [CLKID_SD]                      = &g12a_sd.hw,
3135                 [CLKID_RNG0]                    = &g12a_rng0.hw,
3136                 [CLKID_UART0]                   = &g12a_uart0.hw,
3137                 [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
3138                 [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
3139                 [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
3140                 [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
3141                 [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
3142                 [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
3143                 [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
3144                 [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
3145                 [CLKID_AUDIO]                   = &g12a_audio.hw,
3146                 [CLKID_ETH]                     = &g12a_eth_core.hw,
3147                 [CLKID_DEMUX]                   = &g12a_demux.hw,
3148                 [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
3149                 [CLKID_ADC]                     = &g12a_adc.hw,
3150                 [CLKID_UART1]                   = &g12a_uart1.hw,
3151                 [CLKID_G2D]                     = &g12a_g2d.hw,
3152                 [CLKID_RESET]                   = &g12a_reset.hw,
3153                 [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
3154                 [CLKID_PARSER]                  = &g12a_parser.hw,
3155                 [CLKID_USB]                     = &g12a_usb_general.hw,
3156                 [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
3157                 [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
3158                 [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
3159                 [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
3160                 [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
3161                 [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
3162                 [CLKID_BT656]                   = &g12a_bt656.hw,
3163                 [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
3164                 [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
3165                 [CLKID_UART2]                   = &g12a_uart2.hw,
3166                 [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
3167                 [CLKID_GIC]                     = &g12a_gic.hw,
3168                 [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
3169                 [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
3170                 [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
3171                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
3172                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
3173                 [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
3174                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
3175                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
3176                 [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
3177                 [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
3178                 [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
3179                 [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
3180                 [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
3181                 [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
3182                 [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
3183                 [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
3184                 [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
3185                 [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
3186                 [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
3187                 [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
3188                 [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
3189                 [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
3190                 [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
3191                 [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
3192                 [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
3193                 [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
3194                 [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
3195                 [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
3196                 [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
3197                 [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
3198                 [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
3199                 [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
3200                 [CLKID_ENC480P]                 = &g12a_enc480p.hw,
3201                 [CLKID_RNG1]                    = &g12a_rng1.hw,
3202                 [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
3203                 [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
3204                 [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
3205                 [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
3206                 [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
3207                 [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
3208                 [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
3209                 [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
3210                 [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
3211                 [CLKID_DMA]                     = &g12a_dma.hw,
3212                 [CLKID_EFUSE]                   = &g12a_efuse.hw,
3213                 [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
3214                 [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
3215                 [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
3216                 [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
3217                 [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
3218                 [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
3219                 [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
3220                 [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
3221                 [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
3222                 [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
3223                 [CLKID_VPU]                     = &g12a_vpu.hw,
3224                 [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
3225                 [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
3226                 [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
3227                 [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
3228                 [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
3229                 [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
3230                 [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
3231                 [CLKID_VAPB]                    = &g12a_vapb.hw,
3232                 [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
3233                 [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
3234                 [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
3235                 [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
3236                 [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
3237                 [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
3238                 [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
3239                 [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
3240                 [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
3241                 [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
3242                 [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
3243                 [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
3244                 [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
3245                 [CLKID_VCLK]                    = &g12a_vclk.hw,
3246                 [CLKID_VCLK2]                   = &g12a_vclk2.hw,
3247                 [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
3248                 [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
3249                 [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
3250                 [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
3251                 [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
3252                 [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
3253                 [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
3254                 [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
3255                 [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
3256                 [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
3257                 [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
3258                 [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
3259                 [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
3260                 [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
3261                 [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
3262                 [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
3263                 [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
3264                 [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
3265                 [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
3266                 [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
3267                 [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
3268                 [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
3269                 [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
3270                 [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
3271                 [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
3272                 [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
3273                 [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
3274                 [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
3275                 [CLKID_HDMI]                    = &g12a_hdmi.hw,
3276                 [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
3277                 [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
3278                 [CLKID_MALI_0]                  = &g12a_mali_0.hw,
3279                 [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
3280                 [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
3281                 [CLKID_MALI_1]                  = &g12a_mali_1.hw,
3282                 [CLKID_MALI]                    = &g12a_mali.hw,
3283                 [CLKID_MPLL_50M_DIV]            = &g12a_mpll_50m_div.hw,
3284                 [CLKID_MPLL_50M]                = &g12a_mpll_50m.hw,
3285                 [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
3286                 [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
3287                 [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
3288                 [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
3289                 [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
3290                 [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
3291                 [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
3292                 [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
3293                 [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
3294                 [CLKID_CPU_CLK]                 = &g12a_cpu_clk.hw,
3295                 [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
3296                 [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
3297                 [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
3298                 [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
3299                 [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
3300                 [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
3301                 [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
3302                 [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
3303                 [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
3304                 [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
3305                 [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
3306                 [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
3307                 [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
3308                 [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
3309                 [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
3310                 [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
3311                 [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
3312                 [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
3313                 [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
3314                 [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
3315                 [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
3316                 [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
3317                 [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
3318                 [CLKID_TS_DIV]                  = &g12a_ts_div.hw,
3319                 [CLKID_TS]                      = &g12a_ts.hw,
3320                 [NR_CLKS]                       = NULL,
3321         },
3322         .num = NR_CLKS,
3323 };
3324
3325 static struct clk_hw_onecell_data g12b_hw_onecell_data = {
3326         .hws = {
3327                 [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
3328                 [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
3329                 [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
3330                 [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
3331                 [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
3332                 [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
3333                 [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
3334                 [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
3335                 [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
3336                 [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
3337                 [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
3338                 [CLKID_CLK81]                   = &g12a_clk81.hw,
3339                 [CLKID_MPLL0]                   = &g12a_mpll0.hw,
3340                 [CLKID_MPLL1]                   = &g12a_mpll1.hw,
3341                 [CLKID_MPLL2]                   = &g12a_mpll2.hw,
3342                 [CLKID_MPLL3]                   = &g12a_mpll3.hw,
3343                 [CLKID_DDR]                     = &g12a_ddr.hw,
3344                 [CLKID_DOS]                     = &g12a_dos.hw,
3345                 [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
3346                 [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
3347                 [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
3348                 [CLKID_ISA]                     = &g12a_isa.hw,
3349                 [CLKID_PL301]                   = &g12a_pl301.hw,
3350                 [CLKID_PERIPHS]                 = &g12a_periphs.hw,
3351                 [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
3352                 [CLKID_I2C]                     = &g12a_i2c.hw,
3353                 [CLKID_SANA]                    = &g12a_sana.hw,
3354                 [CLKID_SD]                      = &g12a_sd.hw,
3355                 [CLKID_RNG0]                    = &g12a_rng0.hw,
3356                 [CLKID_UART0]                   = &g12a_uart0.hw,
3357                 [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
3358                 [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
3359                 [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
3360                 [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
3361                 [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
3362                 [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
3363                 [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
3364                 [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
3365                 [CLKID_AUDIO]                   = &g12a_audio.hw,
3366                 [CLKID_ETH]                     = &g12a_eth_core.hw,
3367                 [CLKID_DEMUX]                   = &g12a_demux.hw,
3368                 [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
3369                 [CLKID_ADC]                     = &g12a_adc.hw,
3370                 [CLKID_UART1]                   = &g12a_uart1.hw,
3371                 [CLKID_G2D]                     = &g12a_g2d.hw,
3372                 [CLKID_RESET]                   = &g12a_reset.hw,
3373                 [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
3374                 [CLKID_PARSER]                  = &g12a_parser.hw,
3375                 [CLKID_USB]                     = &g12a_usb_general.hw,
3376                 [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
3377                 [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
3378                 [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
3379                 [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
3380                 [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
3381                 [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
3382                 [CLKID_BT656]                   = &g12a_bt656.hw,
3383                 [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
3384                 [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
3385                 [CLKID_UART2]                   = &g12a_uart2.hw,
3386                 [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
3387                 [CLKID_GIC]                     = &g12a_gic.hw,
3388                 [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
3389                 [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
3390                 [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
3391                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
3392                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
3393                 [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
3394                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
3395                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
3396                 [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
3397                 [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
3398                 [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
3399                 [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
3400                 [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
3401                 [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
3402                 [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
3403                 [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
3404                 [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
3405                 [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
3406                 [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
3407                 [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
3408                 [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
3409                 [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
3410                 [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
3411                 [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
3412                 [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
3413                 [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
3414                 [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
3415                 [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
3416                 [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
3417                 [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
3418                 [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
3419                 [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
3420                 [CLKID_ENC480P]                 = &g12a_enc480p.hw,
3421                 [CLKID_RNG1]                    = &g12a_rng1.hw,
3422                 [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
3423                 [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
3424                 [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
3425                 [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
3426                 [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
3427                 [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
3428                 [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
3429                 [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
3430                 [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
3431                 [CLKID_DMA]                     = &g12a_dma.hw,
3432                 [CLKID_EFUSE]                   = &g12a_efuse.hw,
3433                 [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
3434                 [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
3435                 [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
3436                 [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
3437                 [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
3438                 [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
3439                 [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
3440                 [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
3441                 [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
3442                 [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
3443                 [CLKID_VPU]                     = &g12a_vpu.hw,
3444                 [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
3445                 [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
3446                 [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
3447                 [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
3448                 [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
3449                 [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
3450                 [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
3451                 [CLKID_VAPB]                    = &g12a_vapb.hw,
3452                 [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
3453                 [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
3454                 [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
3455                 [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
3456                 [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
3457                 [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
3458                 [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
3459                 [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
3460                 [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
3461                 [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
3462                 [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
3463                 [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
3464                 [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
3465                 [CLKID_VCLK]                    = &g12a_vclk.hw,
3466                 [CLKID_VCLK2]                   = &g12a_vclk2.hw,
3467                 [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
3468                 [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
3469                 [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
3470                 [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
3471                 [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
3472                 [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
3473                 [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
3474                 [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
3475                 [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
3476                 [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
3477                 [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
3478                 [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
3479                 [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
3480                 [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
3481                 [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
3482                 [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
3483                 [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
3484                 [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
3485                 [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
3486                 [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
3487                 [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
3488                 [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
3489                 [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
3490                 [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
3491                 [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
3492                 [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
3493                 [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
3494                 [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
3495                 [CLKID_HDMI]                    = &g12a_hdmi.hw,
3496                 [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
3497                 [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
3498                 [CLKID_MALI_0]                  = &g12a_mali_0.hw,
3499                 [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
3500                 [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
3501                 [CLKID_MALI_1]                  = &g12a_mali_1.hw,
3502                 [CLKID_MALI]                    = &g12a_mali.hw,
3503                 [CLKID_MPLL_50M_DIV]            = &g12a_mpll_50m_div.hw,
3504                 [CLKID_MPLL_50M]                = &g12a_mpll_50m.hw,
3505                 [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
3506                 [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
3507                 [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
3508                 [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
3509                 [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
3510                 [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
3511                 [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
3512                 [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
3513                 [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
3514                 [CLKID_CPU_CLK]                 = &g12b_cpu_clk.hw,
3515                 [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
3516                 [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
3517                 [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
3518                 [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
3519                 [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
3520                 [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
3521                 [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
3522                 [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
3523                 [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
3524                 [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
3525                 [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
3526                 [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
3527                 [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
3528                 [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
3529                 [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
3530                 [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
3531                 [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
3532                 [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
3533                 [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
3534                 [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
3535                 [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
3536                 [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
3537                 [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
3538                 [CLKID_TS_DIV]                  = &g12a_ts_div.hw,
3539                 [CLKID_TS]                      = &g12a_ts.hw,
3540                 [CLKID_SYS1_PLL_DCO]            = &g12b_sys1_pll_dco.hw,
3541                 [CLKID_SYS1_PLL]                = &g12b_sys1_pll.hw,
3542                 [CLKID_SYS1_PLL_DIV16_EN]       = &g12b_sys1_pll_div16_en.hw,
3543                 [CLKID_SYS1_PLL_DIV16]          = &g12b_sys1_pll_div16.hw,
3544                 [CLKID_CPUB_CLK_DYN0_SEL]       = &g12b_cpub_clk_premux0.hw,
3545                 [CLKID_CPUB_CLK_DYN0_DIV]       = &g12b_cpub_clk_mux0_div.hw,
3546                 [CLKID_CPUB_CLK_DYN0]           = &g12b_cpub_clk_postmux0.hw,
3547                 [CLKID_CPUB_CLK_DYN1_SEL]       = &g12b_cpub_clk_premux1.hw,
3548                 [CLKID_CPUB_CLK_DYN1_DIV]       = &g12b_cpub_clk_mux1_div.hw,
3549                 [CLKID_CPUB_CLK_DYN1]           = &g12b_cpub_clk_postmux1.hw,
3550                 [CLKID_CPUB_CLK_DYN]            = &g12b_cpub_clk_dyn.hw,
3551                 [CLKID_CPUB_CLK]                = &g12b_cpub_clk.hw,
3552                 [CLKID_CPUB_CLK_DIV16_EN]       = &g12b_cpub_clk_div16_en.hw,
3553                 [CLKID_CPUB_CLK_DIV16]          = &g12b_cpub_clk_div16.hw,
3554                 [CLKID_CPUB_CLK_DIV2]           = &g12b_cpub_clk_div2.hw,
3555                 [CLKID_CPUB_CLK_DIV3]           = &g12b_cpub_clk_div3.hw,
3556                 [CLKID_CPUB_CLK_DIV4]           = &g12b_cpub_clk_div4.hw,
3557                 [CLKID_CPUB_CLK_DIV5]           = &g12b_cpub_clk_div5.hw,
3558                 [CLKID_CPUB_CLK_DIV6]           = &g12b_cpub_clk_div6.hw,
3559                 [CLKID_CPUB_CLK_DIV7]           = &g12b_cpub_clk_div7.hw,
3560                 [CLKID_CPUB_CLK_DIV8]           = &g12b_cpub_clk_div8.hw,
3561                 [CLKID_CPUB_CLK_APB_SEL]        = &g12b_cpub_clk_apb_sel.hw,
3562                 [CLKID_CPUB_CLK_APB]            = &g12b_cpub_clk_apb.hw,
3563                 [CLKID_CPUB_CLK_ATB_SEL]        = &g12b_cpub_clk_atb_sel.hw,
3564                 [CLKID_CPUB_CLK_ATB]            = &g12b_cpub_clk_atb.hw,
3565                 [CLKID_CPUB_CLK_AXI_SEL]        = &g12b_cpub_clk_axi_sel.hw,
3566                 [CLKID_CPUB_CLK_AXI]            = &g12b_cpub_clk_axi.hw,
3567                 [CLKID_CPUB_CLK_TRACE_SEL]      = &g12b_cpub_clk_trace_sel.hw,
3568                 [CLKID_CPUB_CLK_TRACE]          = &g12b_cpub_clk_trace.hw,
3569                 [NR_CLKS]                       = NULL,
3570         },
3571         .num = NR_CLKS,
3572 };
3573
3574 /* Convenience table to populate regmap in .probe */
3575 static struct clk_regmap *const g12a_clk_regmaps[] = {
3576         &g12a_clk81,
3577         &g12a_dos,
3578         &g12a_ddr,
3579         &g12a_audio_locker,
3580         &g12a_mipi_dsi_host,
3581         &g12a_eth_phy,
3582         &g12a_isa,
3583         &g12a_pl301,
3584         &g12a_periphs,
3585         &g12a_spicc_0,
3586         &g12a_i2c,
3587         &g12a_sana,
3588         &g12a_sd,
3589         &g12a_rng0,
3590         &g12a_uart0,
3591         &g12a_spicc_1,
3592         &g12a_hiu_reg,
3593         &g12a_mipi_dsi_phy,
3594         &g12a_assist_misc,
3595         &g12a_emmc_a,
3596         &g12a_emmc_b,
3597         &g12a_emmc_c,
3598         &g12a_audio_codec,
3599         &g12a_audio,
3600         &g12a_eth_core,
3601         &g12a_demux,
3602         &g12a_audio_ififo,
3603         &g12a_adc,
3604         &g12a_uart1,
3605         &g12a_g2d,
3606         &g12a_reset,
3607         &g12a_pcie_comb,
3608         &g12a_parser,
3609         &g12a_usb_general,
3610         &g12a_pcie_phy,
3611         &g12a_ahb_arb0,
3612         &g12a_ahb_data_bus,
3613         &g12a_ahb_ctrl_bus,
3614         &g12a_htx_hdcp22,
3615         &g12a_htx_pclk,
3616         &g12a_bt656,
3617         &g12a_usb1_to_ddr,
3618         &g12a_mmc_pclk,
3619         &g12a_vpu_intr,
3620         &g12a_gic,
3621         &g12a_sd_emmc_a_clk0,
3622         &g12a_sd_emmc_b_clk0,
3623         &g12a_sd_emmc_c_clk0,
3624         &g12a_mpeg_clk_div,
3625         &g12a_sd_emmc_a_clk0_div,
3626         &g12a_sd_emmc_b_clk0_div,
3627         &g12a_sd_emmc_c_clk0_div,
3628         &g12a_mpeg_clk_sel,
3629         &g12a_sd_emmc_a_clk0_sel,
3630         &g12a_sd_emmc_b_clk0_sel,
3631         &g12a_sd_emmc_c_clk0_sel,
3632         &g12a_mpll0,
3633         &g12a_mpll1,
3634         &g12a_mpll2,
3635         &g12a_mpll3,
3636         &g12a_mpll0_div,
3637         &g12a_mpll1_div,
3638         &g12a_mpll2_div,
3639         &g12a_mpll3_div,
3640         &g12a_fixed_pll,
3641         &g12a_sys_pll,
3642         &g12a_gp0_pll,
3643         &g12a_hifi_pll,
3644         &g12a_vclk2_venci0,
3645         &g12a_vclk2_venci1,
3646         &g12a_vclk2_vencp0,
3647         &g12a_vclk2_vencp1,
3648         &g12a_vclk2_venct0,
3649         &g12a_vclk2_venct1,
3650         &g12a_vclk2_other,
3651         &g12a_vclk2_enci,
3652         &g12a_vclk2_encp,
3653         &g12a_dac_clk,
3654         &g12a_aoclk_gate,
3655         &g12a_iec958_gate,
3656         &g12a_enc480p,
3657         &g12a_rng1,
3658         &g12a_vclk2_enct,
3659         &g12a_vclk2_encl,
3660         &g12a_vclk2_venclmmc,
3661         &g12a_vclk2_vencl,
3662         &g12a_vclk2_other1,
3663         &g12a_fixed_pll_dco,
3664         &g12a_sys_pll_dco,
3665         &g12a_gp0_pll_dco,
3666         &g12a_hifi_pll_dco,
3667         &g12a_fclk_div2,
3668         &g12a_fclk_div3,
3669         &g12a_fclk_div4,
3670         &g12a_fclk_div5,
3671         &g12a_fclk_div7,
3672         &g12a_fclk_div2p5,
3673         &g12a_dma,
3674         &g12a_efuse,
3675         &g12a_rom_boot,
3676         &g12a_reset_sec,
3677         &g12a_sec_ahb_apb3,
3678         &g12a_vpu_0_sel,
3679         &g12a_vpu_0_div,
3680         &g12a_vpu_0,
3681         &g12a_vpu_1_sel,
3682         &g12a_vpu_1_div,
3683         &g12a_vpu_1,
3684         &g12a_vpu,
3685         &g12a_vapb_0_sel,
3686         &g12a_vapb_0_div,
3687         &g12a_vapb_0,
3688         &g12a_vapb_1_sel,
3689         &g12a_vapb_1_div,
3690         &g12a_vapb_1,
3691         &g12a_vapb_sel,
3692         &g12a_vapb,
3693         &g12a_hdmi_pll_dco,
3694         &g12a_hdmi_pll_od,
3695         &g12a_hdmi_pll_od2,
3696         &g12a_hdmi_pll,
3697         &g12a_vid_pll_div,
3698         &g12a_vid_pll_sel,
3699         &g12a_vid_pll,
3700         &g12a_vclk_sel,
3701         &g12a_vclk2_sel,
3702         &g12a_vclk_input,
3703         &g12a_vclk2_input,
3704         &g12a_vclk_div,
3705         &g12a_vclk2_div,
3706         &g12a_vclk,
3707         &g12a_vclk2,
3708         &g12a_vclk_div1,
3709         &g12a_vclk_div2_en,
3710         &g12a_vclk_div4_en,
3711         &g12a_vclk_div6_en,
3712         &g12a_vclk_div12_en,
3713         &g12a_vclk2_div1,
3714         &g12a_vclk2_div2_en,
3715         &g12a_vclk2_div4_en,
3716         &g12a_vclk2_div6_en,
3717         &g12a_vclk2_div12_en,
3718         &g12a_cts_enci_sel,
3719         &g12a_cts_encp_sel,
3720         &g12a_cts_vdac_sel,
3721         &g12a_hdmi_tx_sel,
3722         &g12a_cts_enci,
3723         &g12a_cts_encp,
3724         &g12a_cts_vdac,
3725         &g12a_hdmi_tx,
3726         &g12a_hdmi_sel,
3727         &g12a_hdmi_div,
3728         &g12a_hdmi,
3729         &g12a_mali_0_sel,
3730         &g12a_mali_0_div,
3731         &g12a_mali_0,
3732         &g12a_mali_1_sel,
3733         &g12a_mali_1_div,
3734         &g12a_mali_1,
3735         &g12a_mali,
3736         &g12a_mpll_50m,
3737         &g12a_sys_pll_div16_en,
3738         &g12a_cpu_clk_premux0,
3739         &g12a_cpu_clk_mux0_div,
3740         &g12a_cpu_clk_postmux0,
3741         &g12a_cpu_clk_premux1,
3742         &g12a_cpu_clk_mux1_div,
3743         &g12a_cpu_clk_postmux1,
3744         &g12a_cpu_clk_dyn,
3745         &g12a_cpu_clk,
3746         &g12a_cpu_clk_div16_en,
3747         &g12a_cpu_clk_apb_div,
3748         &g12a_cpu_clk_apb,
3749         &g12a_cpu_clk_atb_div,
3750         &g12a_cpu_clk_atb,
3751         &g12a_cpu_clk_axi_div,
3752         &g12a_cpu_clk_axi,
3753         &g12a_cpu_clk_trace_div,
3754         &g12a_cpu_clk_trace,
3755         &g12a_pcie_pll_od,
3756         &g12a_pcie_pll_dco,
3757         &g12a_vdec_1_sel,
3758         &g12a_vdec_1_div,
3759         &g12a_vdec_1,
3760         &g12a_vdec_hevc_sel,
3761         &g12a_vdec_hevc_div,
3762         &g12a_vdec_hevc,
3763         &g12a_vdec_hevcf_sel,
3764         &g12a_vdec_hevcf_div,
3765         &g12a_vdec_hevcf,
3766         &g12a_ts_div,
3767         &g12a_ts,
3768         &g12b_cpu_clk,
3769         &g12b_sys1_pll_dco,
3770         &g12b_sys1_pll,
3771         &g12b_sys1_pll_div16_en,
3772         &g12b_cpub_clk_premux0,
3773         &g12b_cpub_clk_mux0_div,
3774         &g12b_cpub_clk_postmux0,
3775         &g12b_cpub_clk_premux1,
3776         &g12b_cpub_clk_mux1_div,
3777         &g12b_cpub_clk_postmux1,
3778         &g12b_cpub_clk_dyn,
3779         &g12b_cpub_clk,
3780         &g12b_cpub_clk_div16_en,
3781         &g12b_cpub_clk_apb_sel,
3782         &g12b_cpub_clk_apb,
3783         &g12b_cpub_clk_atb_sel,
3784         &g12b_cpub_clk_atb,
3785         &g12b_cpub_clk_axi_sel,
3786         &g12b_cpub_clk_axi,
3787         &g12b_cpub_clk_trace_sel,
3788         &g12b_cpub_clk_trace,
3789 };
3790
3791 static const struct reg_sequence g12a_init_regs[] = {
3792         { .reg = HHI_MPLL_CNTL0,        .def = 0x00000543 },
3793 };
3794
3795 static const struct meson_eeclkc_data g12a_clkc_data = {
3796         .regmap_clks = g12a_clk_regmaps,
3797         .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
3798         .hw_onecell_data = &g12a_hw_onecell_data,
3799         .init_regs = g12a_init_regs,
3800         .init_count = ARRAY_SIZE(g12a_init_regs),
3801 };
3802
3803 static const struct meson_eeclkc_data g12b_clkc_data = {
3804         .regmap_clks = g12a_clk_regmaps,
3805         .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
3806         .hw_onecell_data = &g12b_hw_onecell_data
3807 };
3808
3809 static const struct of_device_id clkc_match_table[] = {
3810         { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data },
3811         { .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data },
3812         {}
3813 };
3814
3815 static struct platform_driver g12a_driver = {
3816         .probe          = meson_eeclkc_probe,
3817         .driver         = {
3818                 .name   = "g12a-clkc",
3819                 .of_match_table = clkc_match_table,
3820         },
3821 };
3822
3823 builtin_platform_driver(g12a_driver);