drivers/gpu/drm/msm/msm_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include "msm_gpu.h"
   8 #include "msm_gem.h"
   9 #include "msm_mmu.h"
  10 #include "msm_fence.h"
  11 #include "msm_gpu_trace.h"
  12 #include "adreno/adreno_gpu.h"
  13
  14 #include <generated/utsrelease.h>
  15 #include <linux/string_helpers.h>
  16 #include <linux/pm_opp.h>
  17 #include <linux/devfreq.h>
  18 #include <linux/devcoredump.h>
  19 #include <linux/sched/task.h>
  20
  21 /*
  22  * Power Management:
  23  */
  24
  25 static int msm_devfreq_target(struct device *dev, unsigned long *freq,
  26                 u32 flags)
  27 {
  28         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  29         struct dev_pm_opp *opp;
  30
  31         opp = devfreq_recommended_opp(dev, freq, flags);
  32
  33         if (IS_ERR(opp))
  34                 return PTR_ERR(opp);
  35
  36         if (gpu->funcs->gpu_set_freq)
  37                 gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
  38         else
  39                 clk_set_rate(gpu->core_clk, *freq);
  40
  41         dev_pm_opp_put(opp);
  42
  43         return 0;
  44 }
  45
  46 static int msm_devfreq_get_dev_status(struct device *dev,
  47                 struct devfreq_dev_status *status)
  48 {
  49         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  50         ktime_t time;
  51
  52         if (gpu->funcs->gpu_get_freq)
  53                 status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
  54         else
  55                 status->current_frequency = clk_get_rate(gpu->core_clk);
  56
  57         status->busy_time = gpu->funcs->gpu_busy(gpu);
  58
  59         time = ktime_get();
  60         status->total_time = ktime_us_delta(time, gpu->devfreq.time);
  61         gpu->devfreq.time = time;
  62
  63         return 0;
  64 }
  65
  66 static int msm_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
  67 {
  68         struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
  69
  70         if (gpu->funcs->gpu_get_freq)
  71                 *freq = gpu->funcs->gpu_get_freq(gpu);
  72         else
  73                 *freq = clk_get_rate(gpu->core_clk);
  74
  75         return 0;
  76 }
  77
  78 static struct devfreq_dev_profile msm_devfreq_profile = {
  79         .polling_ms = 10,
  80         .target = msm_devfreq_target,
  81         .get_dev_status = msm_devfreq_get_dev_status,
  82         .get_cur_freq = msm_devfreq_get_cur_freq,
  83 };
  84
  85 static void msm_devfreq_init(struct msm_gpu *gpu)
  86 {
  87         /* We need target support to do devfreq */
  88         if (!gpu->funcs->gpu_busy)
  89                 return;
  90
  91         msm_devfreq_profile.initial_freq = gpu->fast_rate;
  92
  93         /*
  94          * Don't set the freq_table or max_state and let devfreq build the table
  95          * from OPP
  96          */
  97
  98         gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
  99                         &msm_devfreq_profile, DEVFREQ_GOV_SIMPLE_ONDEMAND,
 100                         NULL);
 101
 102         if (IS_ERR(gpu->devfreq.devfreq)) {
 103                 DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
 104                 gpu->devfreq.devfreq = NULL;
 105         }
 106
 107         devfreq_suspend_device(gpu->devfreq.devfreq);
 108 }
 109
 110 static int enable_pwrrail(struct msm_gpu *gpu)
 111 {
 112         struct drm_device *dev = gpu->dev;
 113         int ret = 0;
 114
 115         if (gpu->gpu_reg) {
 116                 ret = regulator_enable(gpu->gpu_reg);
 117                 if (ret) {
 118                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
 119                         return ret;
 120                 }
 121         }
 122
 123         if (gpu->gpu_cx) {
 124                 ret = regulator_enable(gpu->gpu_cx);
 125                 if (ret) {
 126                         DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
 127                         return ret;
 128                 }
 129         }
 130
 131         return 0;
 132 }
 133
 134 static int disable_pwrrail(struct msm_gpu *gpu)
 135 {
 136         if (gpu->gpu_cx)
 137                 regulator_disable(gpu->gpu_cx);
 138         if (gpu->gpu_reg)
 139                 regulator_disable(gpu->gpu_reg);
 140         return 0;
 141 }
 142
 143 static int enable_clk(struct msm_gpu *gpu)
 144 {
 145         if (gpu->core_clk && gpu->fast_rate)
 146                 clk_set_rate(gpu->core_clk, gpu->fast_rate);
 147
 148         /* Set the RBBM timer rate to 19.2Mhz */
 149         if (gpu->rbbmtimer_clk)
 150                 clk_set_rate(gpu->rbbmtimer_clk, 19200000);
 151
 152         return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
 153 }
 154
 155 static int disable_clk(struct msm_gpu *gpu)
 156 {
 157         clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
 158
 159         /*
 160          * Set the clock to a deliberately low rate. On older targets the clock
 161          * speed had to be non zero to avoid problems. On newer targets this
 162          * will be rounded down to zero anyway so it all works out.
 163          */
 164         if (gpu->core_clk)
 165                 clk_set_rate(gpu->core_clk, 27000000);
 166
 167         if (gpu->rbbmtimer_clk)
 168                 clk_set_rate(gpu->rbbmtimer_clk, 0);
 169
 170         return 0;
 171 }
 172
 173 static int enable_axi(struct msm_gpu *gpu)
 174 {
 175         if (gpu->ebi1_clk)
 176                 clk_prepare_enable(gpu->ebi1_clk);
 177         return 0;
 178 }
 179
 180 static int disable_axi(struct msm_gpu *gpu)
 181 {
 182         if (gpu->ebi1_clk)
 183                 clk_disable_unprepare(gpu->ebi1_clk);
 184         return 0;
 185 }
 186
 187 void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
 188 {
 189         gpu->devfreq.busy_cycles = 0;
 190         gpu->devfreq.time = ktime_get();
 191
 192         devfreq_resume_device(gpu->devfreq.devfreq);
 193 }
 194
 195 int msm_gpu_pm_resume(struct msm_gpu *gpu)
 196 {
 197         int ret;
 198
 199         DBG("%s", gpu->name);
 200
 201         ret = enable_pwrrail(gpu);
 202         if (ret)
 203                 return ret;
 204
 205         ret = enable_clk(gpu);
 206         if (ret)
 207                 return ret;
 208
 209         ret = enable_axi(gpu);
 210         if (ret)
 211                 return ret;
 212
 213         msm_gpu_resume_devfreq(gpu);
 214
 215         gpu->needs_hw_init = true;
 216
 217         return 0;
 218 }
 219
 220 int msm_gpu_pm_suspend(struct msm_gpu *gpu)
 221 {
 222         int ret;
 223
 224         DBG("%s", gpu->name);
 225
 226         devfreq_suspend_device(gpu->devfreq.devfreq);
 227
 228         ret = disable_axi(gpu);
 229         if (ret)
 230                 return ret;
 231
 232         ret = disable_clk(gpu);
 233         if (ret)
 234                 return ret;
 235
 236         ret = disable_pwrrail(gpu);
 237         if (ret)
 238                 return ret;
 239
 240         return 0;
 241 }
 242
 243 int msm_gpu_hw_init(struct msm_gpu *gpu)
 244 {
 245         int ret;
 246
 247         WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
 248
 249         if (!gpu->needs_hw_init)
 250                 return 0;
 251
 252         disable_irq(gpu->irq);
 253         ret = gpu->funcs->hw_init(gpu);
 254         if (!ret)
 255                 gpu->needs_hw_init = false;
 256         enable_irq(gpu->irq);
 257
 258         return ret;
 259 }
 260
 261 #ifdef CONFIG_DEV_COREDUMP
 262 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset,
 263                 size_t count, void *data, size_t datalen)
 264 {
 265         struct msm_gpu *gpu = data;
 266         struct drm_print_iterator iter;
 267         struct drm_printer p;
 268         struct msm_gpu_state *state;
 269
 270         state = msm_gpu_crashstate_get(gpu);
 271         if (!state)
 272                 return 0;
 273
 274         iter.data = buffer;
 275         iter.offset = 0;
 276         iter.start = offset;
 277         iter.remain = count;
 278
 279         p = drm_coredump_printer(&iter);
 280
 281         drm_printf(&p, "---\n");
 282         drm_printf(&p, "kernel: " UTS_RELEASE "\n");
 283         drm_printf(&p, "module: " KBUILD_MODNAME "\n");
 284         drm_printf(&p, "time: %lld.%09ld\n",
 285                 state->time.tv_sec, state->time.tv_nsec);
 286         if (state->comm)
 287                 drm_printf(&p, "comm: %s\n", state->comm);
 288         if (state->cmd)
 289                 drm_printf(&p, "cmdline: %s\n", state->cmd);
 290
 291         gpu->funcs->show(gpu, state, &p);
 292
 293         msm_gpu_crashstate_put(gpu);
 294
 295         return count - iter.remain;
 296 }
 297
 298 static void msm_gpu_devcoredump_free(void *data)
 299 {
 300         struct msm_gpu *gpu = data;
 301
 302         msm_gpu_crashstate_put(gpu);
 303 }
 304
 305 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state,
 306                 struct msm_gem_object *obj, u64 iova, u32 flags)
 307 {
 308         struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos];
 309
 310         /* Don't record write only objects */
 311         state_bo->size = obj->base.size;
 312         state_bo->iova = iova;
 313
 314         /* Only store data for non imported buffer objects marked for read */
 315         if ((flags & MSM_SUBMIT_BO_READ) && !obj->base.import_attach) {
 316                 void *ptr;
 317
 318                 state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL);
 319                 if (!state_bo->data)
 320                         goto out;
 321
 322                 ptr = msm_gem_get_vaddr_active(&obj->base);
 323                 if (IS_ERR(ptr)) {
 324                         kvfree(state_bo->data);
 325                         state_bo->data = NULL;
 326                         goto out;
 327                 }
 328
 329                 memcpy(state_bo->data, ptr, obj->base.size);
 330                 msm_gem_put_vaddr(&obj->base);
 331         }
 332 out:
 333         state->nr_bos++;
 334 }
 335
 336 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 337                 struct msm_gem_submit *submit, char *comm, char *cmd)
 338 {
 339         struct msm_gpu_state *state;
 340
 341         /* Check if the target supports capturing crash state */
 342         if (!gpu->funcs->gpu_state_get)
 343                 return;
 344
 345         /* Only save one crash state at a time */
 346         if (gpu->crashstate)
 347                 return;
 348
 349         state = gpu->funcs->gpu_state_get(gpu);
 350         if (IS_ERR_OR_NULL(state))
 351                 return;
 352
 353         /* Fill in the additional crash state information */
 354         state->comm = kstrdup(comm, GFP_KERNEL);
 355         state->cmd = kstrdup(cmd, GFP_KERNEL);
 356
 357         if (submit) {
 358                 int i, nr = 0;
 359
 360                 /* count # of buffers to dump: */
 361                 for (i = 0; i < submit->nr_bos; i++)
 362                         if (should_dump(submit, i))
 363                                 nr++;
 364                 /* always dump cmd bo's, but don't double count them: */
 365                 for (i = 0; i < submit->nr_cmds; i++)
 366                         if (!should_dump(submit, submit->cmd[i].idx))
 367                                 nr++;
 368
 369                 state->bos = kcalloc(nr,
 370                         sizeof(struct msm_gpu_state_bo), GFP_KERNEL);
 371
 372                 for (i = 0; i < submit->nr_bos; i++) {
 373                         if (should_dump(submit, i)) {
 374                                 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj,
 375                                         submit->bos[i].iova, submit->bos[i].flags);
 376                         }
 377                 }
 378
 379                 for (i = 0; state->bos && i < submit->nr_cmds; i++) {
 380                         int idx = submit->cmd[i].idx;
 381
 382                         if (!should_dump(submit, submit->cmd[i].idx)) {
 383                                 msm_gpu_crashstate_get_bo(state, submit->bos[idx].obj,
 384                                         submit->bos[idx].iova, submit->bos[idx].flags);
 385                         }
 386                 }
 387         }
 388
 389         /* Set the active crash state to be dumped on failure */
 390         gpu->crashstate = state;
 391
 392         /* FIXME: Release the crashstate if this errors out? */
 393         dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
 394                 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free);
 395 }
 396 #else
 397 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
 398                 struct msm_gem_submit *submit, char *comm, char *cmd)
 399 {
 400 }
 401 #endif
 402
 403 /*
 404  * Hangcheck detection for locked gpu:
 405  */
 406
 407 static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 408                 uint32_t fence)
 409 {
 410         struct msm_gem_submit *submit;
 411
 412         list_for_each_entry(submit, &ring->submits, node) {
 413                 if (submit->seqno > fence)
 414                         break;
 415
 416                 msm_update_fence(submit->ring->fctx,
 417                         submit->fence->seqno);
 418         }
 419 }
 420
 421 static struct msm_gem_submit *
 422 find_submit(struct msm_ringbuffer *ring, uint32_t fence)
 423 {
 424         struct msm_gem_submit *submit;
 425
 426         WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
 427
 428         list_for_each_entry(submit, &ring->submits, node)
 429                 if (submit->seqno == fence)
 430                         return submit;
 431
 432         return NULL;
 433 }
 434
 435 static void retire_submits(struct msm_gpu *gpu);
 436
 437 static void recover_worker(struct work_struct *work)
 438 {
 439         struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
 440         struct drm_device *dev = gpu->dev;
 441         struct msm_drm_private *priv = dev->dev_private;
 442         struct msm_gem_submit *submit;
 443         struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
 444         char *comm = NULL, *cmd = NULL;
 445         int i;
 446
 447         mutex_lock(&dev->struct_mutex);
 448
 449         DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 450
 451         submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1);
 452         if (submit) {
 453                 struct task_struct *task;
 454
 455                 /* Increment the fault counts */
 456                 gpu->global_faults++;
 457                 submit->queue->faults++;
 458
 459                 task = get_pid_task(submit->pid, PIDTYPE_PID);
 460                 if (task) {
 461                         comm = kstrdup(task->comm, GFP_KERNEL);
 462                         cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL);
 463                         put_task_struct(task);
 464                 }
 465
 466                 if (comm && cmd) {
 467                         DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n",
 468                                 gpu->name, comm, cmd);
 469
 470                         msm_rd_dump_submit(priv->hangrd, submit,
 471                                 "offending task: %s (%s)", comm, cmd);
 472                 } else
 473                         msm_rd_dump_submit(priv->hangrd, submit, NULL);
 474         }
 475
 476         /* Record the crash state */
 477         pm_runtime_get_sync(&gpu->pdev->dev);
 478         msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
 479         pm_runtime_put_sync(&gpu->pdev->dev);
 480
 481         kfree(cmd);
 482         kfree(comm);
 483
 484         /*
 485          * Update all the rings with the latest and greatest fence.. this
 486          * needs to happen after msm_rd_dump_submit() to ensure that the
 487          * bo's referenced by the offending submit are still around.
 488          */
 489         for (i = 0; i < gpu->nr_rings; i++) {
 490                 struct msm_ringbuffer *ring = gpu->rb[i];
 491
 492                 uint32_t fence = ring->memptrs->fence;
 493
 494                 /*
 495                  * For the current (faulting?) ring/submit advance the fence by
 496                  * one more to clear the faulting submit
 497                  */
 498                 if (ring == cur_ring)
 499                         fence++;
 500
 501                 update_fences(gpu, ring, fence);
 502         }
 503
 504         if (msm_gpu_active(gpu)) {
 505                 /* retire completed submits, plus the one that hung: */
 506                 retire_submits(gpu);
 507
 508                 pm_runtime_get_sync(&gpu->pdev->dev);
 509                 gpu->funcs->recover(gpu);
 510                 pm_runtime_put_sync(&gpu->pdev->dev);
 511
 512                 /*
 513                  * Replay all remaining submits starting with highest priority
 514                  * ring
 515                  */
 516                 for (i = 0; i < gpu->nr_rings; i++) {
 517                         struct msm_ringbuffer *ring = gpu->rb[i];
 518
 519                         list_for_each_entry(submit, &ring->submits, node)
 520                                 gpu->funcs->submit(gpu, submit, NULL);
 521                 }
 522         }
 523
 524         mutex_unlock(&dev->struct_mutex);
 525
 526         msm_gpu_retire(gpu);
 527 }
 528
 529 static void hangcheck_timer_reset(struct msm_gpu *gpu)
 530 {
 531         DBG("%s", gpu->name);
 532         mod_timer(&gpu->hangcheck_timer,
 533                         round_jiffies_up(jiffies + DRM_MSM_HANGCHECK_JIFFIES));
 534 }
 535
 536 static void hangcheck_handler(struct timer_list *t)
 537 {
 538         struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
 539         struct drm_device *dev = gpu->dev;
 540         struct msm_drm_private *priv = dev->dev_private;
 541         struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
 542         uint32_t fence = ring->memptrs->fence;
 543
 544         if (fence != ring->hangcheck_fence) {
 545                 /* some progress has been made.. ya! */
 546                 ring->hangcheck_fence = fence;
 547         } else if (fence < ring->seqno) {
 548                 /* no progress and not done.. hung! */
 549                 ring->hangcheck_fence = fence;
 550                 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n",
 551                                 gpu->name, ring->id);
 552                 DRM_DEV_ERROR(dev->dev, "%s:     completed fence: %u\n",
 553                                 gpu->name, fence);
 554                 DRM_DEV_ERROR(dev->dev, "%s:     submitted fence: %u\n",
 555                                 gpu->name, ring->seqno);
 556
 557                 queue_work(priv->wq, &gpu->recover_work);
 558         }
 559
 560         /* if still more pending work, reset the hangcheck timer: */
 561         if (ring->seqno > ring->hangcheck_fence)
 562                 hangcheck_timer_reset(gpu);
 563
 564         /* workaround for missing irq: */
 565         queue_work(priv->wq, &gpu->retire_work);
 566 }
 567
 568 /*
 569  * Performance Counters:
 570  */
 571
 572 /* called under perf_lock */
 573 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
 574 {
 575         uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
 576         int i, n = min(ncntrs, gpu->num_perfcntrs);
 577
 578         /* read current values: */
 579         for (i = 0; i < gpu->num_perfcntrs; i++)
 580                 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
 581
 582         /* update cntrs: */
 583         for (i = 0; i < n; i++)
 584                 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
 585
 586         /* save current values: */
 587         for (i = 0; i < gpu->num_perfcntrs; i++)
 588                 gpu->last_cntrs[i] = current_cntrs[i];
 589
 590         return n;
 591 }
 592
 593 static void update_sw_cntrs(struct msm_gpu *gpu)
 594 {
 595         ktime_t time;
 596         uint32_t elapsed;
 597         unsigned long flags;
 598
 599         spin_lock_irqsave(&gpu->perf_lock, flags);
 600         if (!gpu->perfcntr_active)
 601                 goto out;
 602
 603         time = ktime_get();
 604         elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
 605
 606         gpu->totaltime += elapsed;
 607         if (gpu->last_sample.active)
 608                 gpu->activetime += elapsed;
 609
 610         gpu->last_sample.active = msm_gpu_active(gpu);
 611         gpu->last_sample.time = time;
 612
 613 out:
 614         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 615 }
 616
 617 void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
 618 {
 619         unsigned long flags;
 620
 621         pm_runtime_get_sync(&gpu->pdev->dev);
 622
 623         spin_lock_irqsave(&gpu->perf_lock, flags);
 624         /* we could dynamically enable/disable perfcntr registers too.. */
 625         gpu->last_sample.active = msm_gpu_active(gpu);
 626         gpu->last_sample.time = ktime_get();
 627         gpu->activetime = gpu->totaltime = 0;
 628         gpu->perfcntr_active = true;
 629         update_hw_cntrs(gpu, 0, NULL);
 630         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 631 }
 632
 633 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
 634 {
 635         gpu->perfcntr_active = false;
 636         pm_runtime_put_sync(&gpu->pdev->dev);
 637 }
 638
 639 /* returns -errno or # of cntrs sampled */
 640 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
 641                 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs)
 642 {
 643         unsigned long flags;
 644         int ret;
 645
 646         spin_lock_irqsave(&gpu->perf_lock, flags);
 647
 648         if (!gpu->perfcntr_active) {
 649                 ret = -EINVAL;
 650                 goto out;
 651         }
 652
 653         *activetime = gpu->activetime;
 654         *totaltime = gpu->totaltime;
 655
 656         gpu->activetime = gpu->totaltime = 0;
 657
 658         ret = update_hw_cntrs(gpu, ncntrs, cntrs);
 659
 660 out:
 661         spin_unlock_irqrestore(&gpu->perf_lock, flags);
 662
 663         return ret;
 664 }
 665
 666 /*
 667  * Cmdstream submission/retirement:
 668  */
 669
 670 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
 671                 struct msm_gem_submit *submit)
 672 {
 673         int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
 674         volatile struct msm_gpu_submit_stats *stats;
 675         u64 elapsed, clock = 0;
 676         int i;
 677
 678         stats = &ring->memptrs->stats[index];
 679         /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */
 680         elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000;
 681         do_div(elapsed, 192);
 682
 683         /* Calculate the clock frequency from the number of CP cycles */
 684         if (elapsed) {
 685                 clock = (stats->cpcycles_end - stats->cpcycles_start) * 1000;
 686                 do_div(clock, elapsed);
 687         }
 688
 689         trace_msm_gpu_submit_retired(submit, elapsed, clock,
 690                 stats->alwayson_start, stats->alwayson_end);
 691
 692         for (i = 0; i < submit->nr_bos; i++) {
 693                 struct msm_gem_object *msm_obj = submit->bos[i].obj;
 694                 /* move to inactive: */
 695                 msm_gem_move_to_inactive(&msm_obj->base);
 696                 msm_gem_unpin_iova(&msm_obj->base, submit->aspace);
 697                 drm_gem_object_put(&msm_obj->base);
 698         }
 699
 700         pm_runtime_mark_last_busy(&gpu->pdev->dev);
 701         pm_runtime_put_autosuspend(&gpu->pdev->dev);
 702         msm_gem_submit_free(submit);
 703 }
 704
 705 static void retire_submits(struct msm_gpu *gpu)
 706 {
 707         struct drm_device *dev = gpu->dev;
 708         struct msm_gem_submit *submit, *tmp;
 709         int i;
 710
 711         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 712
 713         /* Retire the commits starting with highest priority */
 714         for (i = 0; i < gpu->nr_rings; i++) {
 715                 struct msm_ringbuffer *ring = gpu->rb[i];
 716
 717                 list_for_each_entry_safe(submit, tmp, &ring->submits, node) {
 718                         if (dma_fence_is_signaled(submit->fence))
 719                                 retire_submit(gpu, ring, submit);
 720                 }
 721         }
 722 }
 723
 724 static void retire_worker(struct work_struct *work)
 725 {
 726         struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 727         struct drm_device *dev = gpu->dev;
 728         int i;
 729
 730         for (i = 0; i < gpu->nr_rings; i++)
 731                 update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
 732
 733         mutex_lock(&dev->struct_mutex);
 734         retire_submits(gpu);
 735         mutex_unlock(&dev->struct_mutex);
 736 }
 737
 738 /* call from irq handler to schedule work to retire bo's */
 739 void msm_gpu_retire(struct msm_gpu *gpu)
 740 {
 741         struct msm_drm_private *priv = gpu->dev->dev_private;
 742         queue_work(priv->wq, &gpu->retire_work);
 743         update_sw_cntrs(gpu);
 744 }
 745
 746 /* add bo's to gpu's ring, and kick gpu: */
 747 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 748                 struct msm_file_private *ctx)
 749 {
 750         struct drm_device *dev = gpu->dev;
 751         struct msm_drm_private *priv = dev->dev_private;
 752         struct msm_ringbuffer *ring = submit->ring;
 753         int i;
 754
 755         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 756
 757         pm_runtime_get_sync(&gpu->pdev->dev);
 758
 759         msm_gpu_hw_init(gpu);
 760
 761         submit->seqno = ++ring->seqno;
 762
 763         list_add_tail(&submit->node, &ring->submits);
 764
 765         msm_rd_dump_submit(priv->rd, submit, NULL);
 766
 767         update_sw_cntrs(gpu);
 768
 769         for (i = 0; i < submit->nr_bos; i++) {
 770                 struct msm_gem_object *msm_obj = submit->bos[i].obj;
 771                 uint64_t iova;
 772
 773                 /* can't happen yet.. but when we add 2d support we'll have
 774                  * to deal w/ cross-ring synchronization:
 775                  */
 776                 WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
 777
 778                 /* submit takes a reference to the bo and iova until retired: */
 779                 drm_gem_object_get(&msm_obj->base);
 780                 msm_gem_get_and_pin_iova(&msm_obj->base, submit->aspace, &iova);
 781
 782                 if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE)
 783                         msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
 784                 else if (submit->bos[i].flags & MSM_SUBMIT_BO_READ)
 785                         msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
 786         }
 787
 788         gpu->funcs->submit(gpu, submit, ctx);
 789         priv->lastctx = ctx;
 790
 791         hangcheck_timer_reset(gpu);
 792 }
 793
 794 /*
 795  * Init/Cleanup:
 796  */
 797
 798 static irqreturn_t irq_handler(int irq, void *data)
 799 {
 800         struct msm_gpu *gpu = data;
 801         return gpu->funcs->irq(gpu);
 802 }
 803
 804 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
 805 {
 806         int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
 807
 808         if (ret < 1) {
 809                 gpu->nr_clocks = 0;
 810                 return ret;
 811         }
 812
 813         gpu->nr_clocks = ret;
 814
 815         gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 816                 gpu->nr_clocks, "core");
 817
 818         gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
 819                 gpu->nr_clocks, "rbbmtimer");
 820
 821         return 0;
 822 }
 823
 824 static struct msm_gem_address_space *
 825 msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
 826                 uint64_t va_start, uint64_t va_end)
 827 {
 828         struct msm_gem_address_space *aspace;
 829         int ret;
 830
 831         /*
 832          * Setup IOMMU.. eventually we will (I think) do this once per context
 833          * and have separate page tables per context.  For now, to keep things
 834          * simple and to get something working, just use a single address space:
 835          */
 836         if (!adreno_is_a2xx(to_adreno_gpu(gpu))) {
 837                 struct iommu_domain *iommu = iommu_domain_alloc(&platform_bus_type);
 838                 if (!iommu)
 839                         return NULL;
 840
 841                 iommu->geometry.aperture_start = va_start;
 842                 iommu->geometry.aperture_end = va_end;
 843
 844                 DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
 845
 846                 aspace = msm_gem_address_space_create(&pdev->dev, iommu, "gpu");
 847                 if (IS_ERR(aspace))
 848                         iommu_domain_free(iommu);
 849         } else {
 850                 aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu",
 851                         va_start, va_end);
 852         }
 853
 854         if (IS_ERR(aspace)) {
 855                 DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n",
 856                         PTR_ERR(aspace));
 857                 return ERR_CAST(aspace);
 858         }
 859
 860         ret = aspace->mmu->funcs->attach(aspace->mmu);
 861         if (ret) {
 862                 msm_gem_address_space_put(aspace);
 863                 return ERR_PTR(ret);
 864         }
 865
 866         return aspace;
 867 }
 868
 869 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 870                 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
 871                 const char *name, struct msm_gpu_config *config)
 872 {
 873         int i, ret, nr_rings = config->nr_rings;
 874         void *memptrs;
 875         uint64_t memptrs_iova;
 876
 877         if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
 878                 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
 879
 880         gpu->dev = drm;
 881         gpu->funcs = funcs;
 882         gpu->name = name;
 883
 884         INIT_LIST_HEAD(&gpu->active_list);
 885         INIT_WORK(&gpu->retire_work, retire_worker);
 886         INIT_WORK(&gpu->recover_work, recover_worker);
 887
 888
 889         timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
 890
 891         spin_lock_init(&gpu->perf_lock);
 892
 893
 894         /* Map registers: */
 895         gpu->mmio = msm_ioremap(pdev, config->ioname, name);
 896         if (IS_ERR(gpu->mmio)) {
 897                 ret = PTR_ERR(gpu->mmio);
 898                 goto fail;
 899         }
 900
 901         /* Get Interrupt: */
 902         gpu->irq = platform_get_irq(pdev, 0);
 903         if (gpu->irq < 0) {
 904                 ret = gpu->irq;
 905                 DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret);
 906                 goto fail;
 907         }
 908
 909         ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
 910                         IRQF_TRIGGER_HIGH, gpu->name, gpu);
 911         if (ret) {
 912                 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
 913                 goto fail;
 914         }
 915
 916         ret = get_clocks(pdev, gpu);
 917         if (ret)
 918                 goto fail;
 919
 920         gpu->ebi1_clk = msm_clk_get(pdev, "bus");
 921         DBG("ebi1_clk: %p", gpu->ebi1_clk);
 922         if (IS_ERR(gpu->ebi1_clk))
 923                 gpu->ebi1_clk = NULL;
 924
 925         /* Acquire regulators: */
 926         gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
 927         DBG("gpu_reg: %p", gpu->gpu_reg);
 928         if (IS_ERR(gpu->gpu_reg))
 929                 gpu->gpu_reg = NULL;
 930
 931         gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
 932         DBG("gpu_cx: %p", gpu->gpu_cx);
 933         if (IS_ERR(gpu->gpu_cx))
 934                 gpu->gpu_cx = NULL;
 935
 936         gpu->pdev = pdev;
 937         platform_set_drvdata(pdev, gpu);
 938
 939         msm_devfreq_init(gpu);
 940
 941         gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
 942                 config->va_start, config->va_end);
 943
 944         if (gpu->aspace == NULL)
 945                 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
 946         else if (IS_ERR(gpu->aspace)) {
 947                 ret = PTR_ERR(gpu->aspace);
 948                 goto fail;
 949         }
 950
 951         memptrs = msm_gem_kernel_new(drm,
 952                 sizeof(struct msm_rbmemptrs) * nr_rings,
 953                 MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
 954                 &memptrs_iova);
 955
 956         if (IS_ERR(memptrs)) {
 957                 ret = PTR_ERR(memptrs);
 958                 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret);
 959                 goto fail;
 960         }
 961
 962         msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
 963
 964         if (nr_rings > ARRAY_SIZE(gpu->rb)) {
 965                 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n",
 966                         ARRAY_SIZE(gpu->rb));
 967                 nr_rings = ARRAY_SIZE(gpu->rb);
 968         }
 969
 970         /* Create ringbuffer(s): */
 971         for (i = 0; i < nr_rings; i++) {
 972                 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
 973
 974                 if (IS_ERR(gpu->rb[i])) {
 975                         ret = PTR_ERR(gpu->rb[i]);
 976                         DRM_DEV_ERROR(drm->dev,
 977                                 "could not create ringbuffer %d: %d\n", i, ret);
 978                         goto fail;
 979                 }
 980
 981                 memptrs += sizeof(struct msm_rbmemptrs);
 982                 memptrs_iova += sizeof(struct msm_rbmemptrs);
 983         }
 984
 985         gpu->nr_rings = nr_rings;
 986
 987         return 0;
 988
 989 fail:
 990         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
 991                 msm_ringbuffer_destroy(gpu->rb[i]);
 992                 gpu->rb[i] = NULL;
 993         }
 994
 995         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
 996
 997         platform_set_drvdata(pdev, NULL);
 998         return ret;
 999 }
1000
1001 void msm_gpu_cleanup(struct msm_gpu *gpu)
1002 {
1003         int i;
1004
1005         DBG("%s", gpu->name);
1006
1007         WARN_ON(!list_empty(&gpu->active_list));
1008
1009         for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
1010                 msm_ringbuffer_destroy(gpu->rb[i]);
1011                 gpu->rb[i] = NULL;
1012         }
1013
1014         msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
1015
1016         if (!IS_ERR_OR_NULL(gpu->aspace)) {
1017                 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu);
1018                 msm_gem_address_space_put(gpu->aspace);
1019         }
1020 }