2 * Copyright 2011, Netlogic Microsystems Inc.
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
10 #include <linux/err.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/ioport.h>
15 #include <linux/delay.h>
16 #include <linux/errno.h>
17 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/of_device.h>
21 #include <linux/clk.h>
22 #include <linux/interrupt.h>
23 #include <linux/wait.h>
25 /* XLR I2C REGISTERS */
26 #define XLR_I2C_CFG 0x00
27 #define XLR_I2C_CLKDIV 0x01
28 #define XLR_I2C_DEVADDR 0x02
29 #define XLR_I2C_ADDR 0x03
30 #define XLR_I2C_DATAOUT 0x04
31 #define XLR_I2C_DATAIN 0x05
32 #define XLR_I2C_STATUS 0x06
33 #define XLR_I2C_STARTXFR 0x07
34 #define XLR_I2C_BYTECNT 0x08
35 #define XLR_I2C_HDSTATIM 0x09
37 /* Sigma Designs additional registers */
38 #define XLR_I2C_INT_EN 0x09
39 #define XLR_I2C_INT_STAT 0x0a
41 /* XLR I2C REGISTERS FLAGS */
42 #define XLR_I2C_BUS_BUSY 0x01
43 #define XLR_I2C_SDOEMPTY 0x02
44 #define XLR_I2C_RXRDY 0x04
45 #define XLR_I2C_ACK_ERR 0x08
46 #define XLR_I2C_ARB_STARTERR 0x30
49 #define XLR_I2C_CFG_ADDR 0xF8
50 #define XLR_I2C_CFG_NOADDR 0xFA
51 #define XLR_I2C_STARTXFR_ND 0x02 /* No Data */
52 #define XLR_I2C_STARTXFR_RD 0x01 /* Read */
53 #define XLR_I2C_STARTXFR_WR 0x00 /* Write */
55 #define XLR_I2C_TIMEOUT 10 /* timeout per byte in msec */
58 * On XLR/XLS, we need to use __raw_ IO to read the I2C registers
59 * because they are in the big-endian MMIO area on the SoC.
61 * The readl/writel implementation on XLR/XLS byteswaps, because
62 * those are for its little-endian PCI space (see arch/mips/Kconfig).
64 static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val)
66 __raw_writel(val, base + reg);
69 static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg)
71 return __raw_readl(base + reg);
74 #define XLR_I2C_FLAG_IRQ 1
76 struct xlr_i2c_config {
77 u32 flags; /* optional feature support */
78 u32 status_busy; /* value of STATUS[0] when busy */
79 u32 cfg_extra; /* extra CFG bits to set */
82 struct xlr_i2c_private {
83 struct i2c_adapter adap;
88 const struct xlr_i2c_config *cfg;
89 wait_queue_head_t wait;
93 static int xlr_i2c_busy(struct xlr_i2c_private *priv, u32 status)
95 return (status & XLR_I2C_BUS_BUSY) == priv->cfg->status_busy;
98 static int xlr_i2c_idle(struct xlr_i2c_private *priv)
100 return !xlr_i2c_busy(priv, xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS));
103 static int xlr_i2c_wait(struct xlr_i2c_private *priv, unsigned long timeout)
108 t = wait_event_timeout(priv->wait, xlr_i2c_idle(priv),
109 msecs_to_jiffies(timeout));
113 status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
115 return status & XLR_I2C_ACK_ERR ? -EIO : 0;
118 static void xlr_i2c_tx_irq(struct xlr_i2c_private *priv, u32 status)
120 struct i2c_msg *msg = priv->msg;
122 if (status & XLR_I2C_SDOEMPTY)
123 xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT,
124 msg->buf[priv->pos++]);
127 static void xlr_i2c_rx_irq(struct xlr_i2c_private *priv, u32 status)
129 struct i2c_msg *msg = priv->msg;
131 if (status & XLR_I2C_RXRDY)
132 msg->buf[priv->pos++] =
133 xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
136 static irqreturn_t xlr_i2c_irq(int irq, void *dev_id)
138 struct xlr_i2c_private *priv = dev_id;
139 struct i2c_msg *msg = priv->msg;
140 u32 int_stat, status;
142 int_stat = xlr_i2c_rdreg(priv->iobase, XLR_I2C_INT_STAT);
146 xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, int_stat);
151 status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
153 if (priv->pos < msg->len) {
154 if (msg->flags & I2C_M_RD)
155 xlr_i2c_rx_irq(priv, status);
157 xlr_i2c_tx_irq(priv, status);
160 if (!xlr_i2c_busy(priv, status))
161 wake_up(&priv->wait);
166 static int xlr_i2c_tx(struct xlr_i2c_private *priv, u16 len,
169 struct i2c_adapter *adap = &priv->adap;
170 unsigned long timeout, stoptime, checktime;
177 xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset);
178 xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
179 xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG,
180 XLR_I2C_CFG_ADDR | priv->cfg->cfg_extra);
182 timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
183 stoptime = jiffies + timeout;
187 xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
188 xfer = XLR_I2C_STARTXFR_ND;
191 xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 2);
192 xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[1]);
193 xfer = XLR_I2C_STARTXFR_WR;
200 /* retry can only happen on the first byte */
201 xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, xfer);
204 return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len);
208 i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
210 if ((i2c_status & XLR_I2C_SDOEMPTY) && pos < len) {
211 xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos++]);
213 /* reset timeout on successful xmit */
214 stoptime = jiffies + timeout;
216 timedout = time_after(checktime, stoptime);
218 if (i2c_status & XLR_I2C_ARB_STARTERR) {
224 if (i2c_status & XLR_I2C_ACK_ERR)
227 if (!xlr_i2c_busy(priv, i2c_status) && pos >= len)
230 dev_err(&adap->dev, "I2C transmit timeout\n");
234 static int xlr_i2c_rx(struct xlr_i2c_private *priv, u16 len, u8 *buf, u16 addr)
236 struct i2c_adapter *adap = &priv->adap;
238 unsigned long timeout, stoptime, checktime;
239 int nbytes, timedout;
241 xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG,
242 XLR_I2C_CFG_NOADDR | priv->cfg->cfg_extra);
243 xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
244 xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
248 timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
249 stoptime = jiffies + timeout;
253 xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD);
256 return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len);
260 i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
261 if (i2c_status & XLR_I2C_RXRDY) {
263 return -EIO; /* should not happen */
266 xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
268 /* reset timeout on successful read */
269 stoptime = jiffies + timeout;
272 timedout = time_after(checktime, stoptime);
273 if (i2c_status & XLR_I2C_ARB_STARTERR) {
279 if (i2c_status & XLR_I2C_ACK_ERR)
282 if (!xlr_i2c_busy(priv, i2c_status))
286 dev_err(&adap->dev, "I2C receive timeout\n");
290 static int xlr_i2c_xfer(struct i2c_adapter *adap,
291 struct i2c_msg *msgs, int num)
296 struct xlr_i2c_private *priv = i2c_get_adapdata(adap);
298 ret = clk_enable(priv->clk);
303 xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0xf);
306 for (i = 0; ret == 0 && i < num; i++) {
309 if (msg->flags & I2C_M_RD)
310 ret = xlr_i2c_rx(priv, msg->len, &msg->buf[0],
313 ret = xlr_i2c_tx(priv, msg->len, &msg->buf[0],
318 xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0);
320 clk_disable(priv->clk);
323 return (ret != 0) ? ret : num;
326 static u32 xlr_func(struct i2c_adapter *adap)
328 /* Emulate SMBUS over I2C */
329 return (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | I2C_FUNC_I2C;
332 static const struct i2c_algorithm xlr_i2c_algo = {
333 .master_xfer = xlr_i2c_xfer,
334 .functionality = xlr_func,
337 static const struct i2c_adapter_quirks xlr_i2c_quirks = {
338 .flags = I2C_AQ_NO_ZERO_LEN,
341 static const struct xlr_i2c_config xlr_i2c_config_default = {
342 .status_busy = XLR_I2C_BUS_BUSY,
346 static const struct xlr_i2c_config xlr_i2c_config_tangox = {
347 .flags = XLR_I2C_FLAG_IRQ,
352 static const struct of_device_id xlr_i2c_dt_ids[] = {
354 .compatible = "sigma,smp8642-i2c",
355 .data = &xlr_i2c_config_tangox,
359 MODULE_DEVICE_TABLE(of, xlr_i2c_dt_ids);
361 static int xlr_i2c_probe(struct platform_device *pdev)
363 const struct of_device_id *match;
364 struct xlr_i2c_private *priv;
366 unsigned long clk_rate;
367 unsigned long clk_div;
372 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
376 match = of_match_device(xlr_i2c_dt_ids, &pdev->dev);
378 priv->cfg = match->data;
380 priv->cfg = &xlr_i2c_config_default;
382 priv->iobase = devm_platform_ioremap_resource(pdev, 0);
383 if (IS_ERR(priv->iobase))
384 return PTR_ERR(priv->iobase);
386 irq = platform_get_irq(pdev, 0);
388 if (irq > 0 && (priv->cfg->flags & XLR_I2C_FLAG_IRQ)) {
391 xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0);
392 xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, 0xf);
394 ret = devm_request_irq(&pdev->dev, priv->irq, xlr_i2c_irq,
395 IRQF_SHARED, dev_name(&pdev->dev),
400 init_waitqueue_head(&priv->wait);
403 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
405 busfreq = I2C_MAX_STANDARD_MODE_FREQ;
407 clk = devm_clk_get(&pdev->dev, NULL);
409 ret = clk_prepare_enable(clk);
413 clk_rate = clk_get_rate(clk);
414 clk_div = DIV_ROUND_UP(clk_rate, 2 * busfreq);
415 xlr_i2c_wreg(priv->iobase, XLR_I2C_CLKDIV, clk_div);
421 priv->adap.dev.parent = &pdev->dev;
422 priv->adap.dev.of_node = pdev->dev.of_node;
423 priv->adap.owner = THIS_MODULE;
424 priv->adap.algo_data = priv;
425 priv->adap.algo = &xlr_i2c_algo;
426 priv->adap.quirks = &xlr_i2c_quirks;
427 priv->adap.nr = pdev->id;
428 priv->adap.class = I2C_CLASS_HWMON;
429 snprintf(priv->adap.name, sizeof(priv->adap.name), "xlr-i2c");
431 i2c_set_adapdata(&priv->adap, priv);
432 ret = i2c_add_numbered_adapter(&priv->adap);
436 platform_set_drvdata(pdev, priv);
437 dev_info(&priv->adap.dev, "Added I2C Bus.\n");
441 static int xlr_i2c_remove(struct platform_device *pdev)
443 struct xlr_i2c_private *priv;
445 priv = platform_get_drvdata(pdev);
446 i2c_del_adapter(&priv->adap);
447 clk_unprepare(priv->clk);
452 static struct platform_driver xlr_i2c_driver = {
453 .probe = xlr_i2c_probe,
454 .remove = xlr_i2c_remove,
456 .name = "xlr-i2cbus",
457 .of_match_table = xlr_i2c_dt_ids,
461 module_platform_driver(xlr_i2c_driver);
464 MODULE_DESCRIPTION("XLR/XLS SoC I2C Controller driver");
465 MODULE_LICENSE("GPL v2");
466 MODULE_ALIAS("platform:xlr-i2cbus");