drivers/dma/ste_dma40.c

   1 /*
   2  * Copyright (C) Ericsson AB 2007-2008
   3  * Copyright (C) ST-Ericsson SA 2008-2010
   4  * Author: Per Forlin <[email protected]> for ST-Ericsson
   5  * Author: Jonas Aaberg <[email protected]> for ST-Ericsson
   6  * License terms: GNU General Public License (GPL) version 2
   7  */
   8
   9 #include <linux/dma-mapping.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/export.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/log2.h>
  18 #include <linux/pm.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/err.h>
  21 #include <linux/of.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/amba/bus.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/platform_data/dma-ste-dma40.h>
  26
  27 #include "dmaengine.h"
  28 #include "ste_dma40_ll.h"
  29
  30 #define D40_NAME "dma40"
  31
  32 #define D40_PHY_CHAN -1
  33
  34 /* For masking out/in 2 bit channel positions */
  35 #define D40_CHAN_POS(chan)  (2 * (chan / 2))
  36 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
  37
  38 /* Maximum iterations taken before giving up suspending a channel */
  39 #define D40_SUSPEND_MAX_IT 500
  40
  41 /* Milliseconds */
  42 #define DMA40_AUTOSUSPEND_DELAY 100
  43
  44 /* Hardware requirement on LCLA alignment */
  45 #define LCLA_ALIGNMENT 0x40000
  46
  47 /* Max number of links per event group */
  48 #define D40_LCLA_LINK_PER_EVENT_GRP 128
  49 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
  50
  51 /* Max number of logical channels per physical channel */
  52 #define D40_MAX_LOG_CHAN_PER_PHY 32
  53
  54 /* Attempts before giving up to trying to get pages that are aligned */
  55 #define MAX_LCLA_ALLOC_ATTEMPTS 256
  56
  57 /* Bit markings for allocation map */
  58 #define D40_ALLOC_FREE          BIT(31)
  59 #define D40_ALLOC_PHY           BIT(30)
  60 #define D40_ALLOC_LOG_FREE      0
  61
  62 #define D40_MEMCPY_MAX_CHANS    8
  63
  64 /* Reserved event lines for memcpy only. */
  65 #define DB8500_DMA_MEMCPY_EV_0  51
  66 #define DB8500_DMA_MEMCPY_EV_1  56
  67 #define DB8500_DMA_MEMCPY_EV_2  57
  68 #define DB8500_DMA_MEMCPY_EV_3  58
  69 #define DB8500_DMA_MEMCPY_EV_4  59
  70 #define DB8500_DMA_MEMCPY_EV_5  60
  71
  72 static int dma40_memcpy_channels[] = {
  73         DB8500_DMA_MEMCPY_EV_0,
  74         DB8500_DMA_MEMCPY_EV_1,
  75         DB8500_DMA_MEMCPY_EV_2,
  76         DB8500_DMA_MEMCPY_EV_3,
  77         DB8500_DMA_MEMCPY_EV_4,
  78         DB8500_DMA_MEMCPY_EV_5,
  79 };
  80
  81 /* Default configuration for physcial memcpy */
  82 static const struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  83         .mode = STEDMA40_MODE_PHYSICAL,
  84         .dir = DMA_MEM_TO_MEM,
  85
  86         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  87         .src_info.psize = STEDMA40_PSIZE_PHY_1,
  88         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  89
  90         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
  91         .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  92         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  93 };
  94
  95 /* Default configuration for logical memcpy */
  96 static const struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  97         .mode = STEDMA40_MODE_LOGICAL,
  98         .dir = DMA_MEM_TO_MEM,
  99
 100         .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 101         .src_info.psize = STEDMA40_PSIZE_LOG_1,
 102         .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 103
 104         .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
 105         .dst_info.psize = STEDMA40_PSIZE_LOG_1,
 106         .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
 107 };
 108
 109 /**
 110  * enum 40_command - The different commands and/or statuses.
 111  *
 112  * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
 113  * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
 114  * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
 115  * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
 116  */
 117 enum d40_command {
 118         D40_DMA_STOP            = 0,
 119         D40_DMA_RUN             = 1,
 120         D40_DMA_SUSPEND_REQ     = 2,
 121         D40_DMA_SUSPENDED       = 3
 122 };
 123
 124 /*
 125  * enum d40_events - The different Event Enables for the event lines.
 126  *
 127  * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
 128  * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
 129  * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
 130  * @D40_ROUND_EVENTLINE: Status check for event line.
 131  */
 132
 133 enum d40_events {
 134         D40_DEACTIVATE_EVENTLINE        = 0,
 135         D40_ACTIVATE_EVENTLINE          = 1,
 136         D40_SUSPEND_REQ_EVENTLINE       = 2,
 137         D40_ROUND_EVENTLINE             = 3
 138 };
 139
 140 /*
 141  * These are the registers that has to be saved and later restored
 142  * when the DMA hw is powered off.
 143  * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
 144  */
 145 static u32 d40_backup_regs[] = {
 146         D40_DREG_LCPA,
 147         D40_DREG_LCLA,
 148         D40_DREG_PRMSE,
 149         D40_DREG_PRMSO,
 150         D40_DREG_PRMOE,
 151         D40_DREG_PRMOO,
 152 };
 153
 154 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
 155
 156 /*
 157  * since 9540 and 8540 has the same HW revision
 158  * use v4a for 9540 or ealier
 159  * use v4b for 8540 or later
 160  * HW revision:
 161  * DB8500ed has revision 0
 162  * DB8500v1 has revision 2
 163  * DB8500v2 has revision 3
 164  * AP9540v1 has revision 4
 165  * DB8540v1 has revision 4
 166  * TODO: Check if all these registers have to be saved/restored on dma40 v4a
 167  */
 168 static u32 d40_backup_regs_v4a[] = {
 169         D40_DREG_PSEG1,
 170         D40_DREG_PSEG2,
 171         D40_DREG_PSEG3,
 172         D40_DREG_PSEG4,
 173         D40_DREG_PCEG1,
 174         D40_DREG_PCEG2,
 175         D40_DREG_PCEG3,
 176         D40_DREG_PCEG4,
 177         D40_DREG_RSEG1,
 178         D40_DREG_RSEG2,
 179         D40_DREG_RSEG3,
 180         D40_DREG_RSEG4,
 181         D40_DREG_RCEG1,
 182         D40_DREG_RCEG2,
 183         D40_DREG_RCEG3,
 184         D40_DREG_RCEG4,
 185 };
 186
 187 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
 188
 189 static u32 d40_backup_regs_v4b[] = {
 190         D40_DREG_CPSEG1,
 191         D40_DREG_CPSEG2,
 192         D40_DREG_CPSEG3,
 193         D40_DREG_CPSEG4,
 194         D40_DREG_CPSEG5,
 195         D40_DREG_CPCEG1,
 196         D40_DREG_CPCEG2,
 197         D40_DREG_CPCEG3,
 198         D40_DREG_CPCEG4,
 199         D40_DREG_CPCEG5,
 200         D40_DREG_CRSEG1,
 201         D40_DREG_CRSEG2,
 202         D40_DREG_CRSEG3,
 203         D40_DREG_CRSEG4,
 204         D40_DREG_CRSEG5,
 205         D40_DREG_CRCEG1,
 206         D40_DREG_CRCEG2,
 207         D40_DREG_CRCEG3,
 208         D40_DREG_CRCEG4,
 209         D40_DREG_CRCEG5,
 210 };
 211
 212 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
 213
 214 static u32 d40_backup_regs_chan[] = {
 215         D40_CHAN_REG_SSCFG,
 216         D40_CHAN_REG_SSELT,
 217         D40_CHAN_REG_SSPTR,
 218         D40_CHAN_REG_SSLNK,
 219         D40_CHAN_REG_SDCFG,
 220         D40_CHAN_REG_SDELT,
 221         D40_CHAN_REG_SDPTR,
 222         D40_CHAN_REG_SDLNK,
 223 };
 224
 225 #define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
 226                              BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
 227
 228 /**
 229  * struct d40_interrupt_lookup - lookup table for interrupt handler
 230  *
 231  * @src: Interrupt mask register.
 232  * @clr: Interrupt clear register.
 233  * @is_error: true if this is an error interrupt.
 234  * @offset: start delta in the lookup_log_chans in d40_base. If equals to
 235  * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
 236  */
 237 struct d40_interrupt_lookup {
 238         u32 src;
 239         u32 clr;
 240         bool is_error;
 241         int offset;
 242 };
 243
 244
 245 static struct d40_interrupt_lookup il_v4a[] = {
 246         {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
 247         {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
 248         {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
 249         {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
 250         {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
 251         {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
 252         {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
 253         {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
 254         {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
 255         {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
 256 };
 257
 258 static struct d40_interrupt_lookup il_v4b[] = {
 259         {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false,  0},
 260         {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
 261         {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
 262         {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
 263         {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
 264         {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true,   0},
 265         {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true,  32},
 266         {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true,  64},
 267         {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true,  96},
 268         {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true,  128},
 269         {D40_DREG_CPCTIS,  D40_DREG_CPCICR,  false, D40_PHY_CHAN},
 270         {D40_DREG_CPCEIS,  D40_DREG_CPCICR,  true,  D40_PHY_CHAN},
 271 };
 272
 273 /**
 274  * struct d40_reg_val - simple lookup struct
 275  *
 276  * @reg: The register.
 277  * @val: The value that belongs to the register in reg.
 278  */
 279 struct d40_reg_val {
 280         unsigned int reg;
 281         unsigned int val;
 282 };
 283
 284 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
 285         /* Clock every part of the DMA block from start */
 286         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
 287
 288         /* Interrupts on all logical channels */
 289         { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
 290         { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
 291         { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
 292         { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
 293         { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
 294         { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
 295         { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
 296         { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
 297         { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
 298         { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
 299         { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
 300         { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
 301 };
 302 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
 303         /* Clock every part of the DMA block from start */
 304         { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
 305
 306         /* Interrupts on all logical channels */
 307         { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
 308         { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
 309         { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
 310         { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
 311         { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
 312         { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
 313         { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
 314         { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
 315         { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
 316         { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
 317         { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
 318         { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
 319         { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
 320         { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
 321         { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
 322 };
 323
 324 /**
 325  * struct d40_lli_pool - Structure for keeping LLIs in memory
 326  *
 327  * @base: Pointer to memory area when the pre_alloc_lli's are not large
 328  * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
 329  * pre_alloc_lli is used.
 330  * @dma_addr: DMA address, if mapped
 331  * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
 332  * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
 333  * one buffer to one buffer.
 334  */
 335 struct d40_lli_pool {
 336         void    *base;
 337         int      size;
 338         dma_addr_t      dma_addr;
 339         /* Space for dst and src, plus an extra for padding */
 340         u8       pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
 341 };
 342
 343 /**
 344  * struct d40_desc - A descriptor is one DMA job.
 345  *
 346  * @lli_phy: LLI settings for physical channel. Both src and dst=
 347  * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
 348  * lli_len equals one.
 349  * @lli_log: Same as above but for logical channels.
 350  * @lli_pool: The pool with two entries pre-allocated.
 351  * @lli_len: Number of llis of current descriptor.
 352  * @lli_current: Number of transferred llis.
 353  * @lcla_alloc: Number of LCLA entries allocated.
 354  * @txd: DMA engine struct. Used for among other things for communication
 355  * during a transfer.
 356  * @node: List entry.
 357  * @is_in_client_list: true if the client owns this descriptor.
 358  * @cyclic: true if this is a cyclic job
 359  *
 360  * This descriptor is used for both logical and physical transfers.
 361  */
 362 struct d40_desc {
 363         /* LLI physical */
 364         struct d40_phy_lli_bidir         lli_phy;
 365         /* LLI logical */
 366         struct d40_log_lli_bidir         lli_log;
 367
 368         struct d40_lli_pool              lli_pool;
 369         int                              lli_len;
 370         int                              lli_current;
 371         int                              lcla_alloc;
 372
 373         struct dma_async_tx_descriptor   txd;
 374         struct list_head                 node;
 375
 376         bool                             is_in_client_list;
 377         bool                             cyclic;
 378 };
 379
 380 /**
 381  * struct d40_lcla_pool - LCLA pool settings and data.
 382  *
 383  * @base: The virtual address of LCLA. 18 bit aligned.
 384  * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
 385  * This pointer is only there for clean-up on error.
 386  * @pages: The number of pages needed for all physical channels.
 387  * Only used later for clean-up on error
 388  * @lock: Lock to protect the content in this struct.
 389  * @alloc_map: big map over which LCLA entry is own by which job.
 390  */
 391 struct d40_lcla_pool {
 392         void            *base;
 393         dma_addr_t      dma_addr;
 394         void            *base_unaligned;
 395         int              pages;
 396         spinlock_t       lock;
 397         struct d40_desc **alloc_map;
 398 };
 399
 400 /**
 401  * struct d40_phy_res - struct for handling eventlines mapped to physical
 402  * channels.
 403  *
 404  * @lock: A lock protection this entity.
 405  * @reserved: True if used by secure world or otherwise.
 406  * @num: The physical channel number of this entity.
 407  * @allocated_src: Bit mapped to show which src event line's are mapped to
 408  * this physical channel. Can also be free or physically allocated.
 409  * @allocated_dst: Same as for src but is dst.
 410  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
 411  * event line number.
 412  * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
 413  */
 414 struct d40_phy_res {
 415         spinlock_t lock;
 416         bool       reserved;
 417         int        num;
 418         u32        allocated_src;
 419         u32        allocated_dst;
 420         bool       use_soft_lli;
 421 };
 422
 423 struct d40_base;
 424
 425 /**
 426  * struct d40_chan - Struct that describes a channel.
 427  *
 428  * @lock: A spinlock to protect this struct.
 429  * @log_num: The logical number, if any of this channel.
 430  * @pending_tx: The number of pending transfers. Used between interrupt handler
 431  * and tasklet.
 432  * @busy: Set to true when transfer is ongoing on this channel.
 433  * @phy_chan: Pointer to physical channel which this instance runs on. If this
 434  * point is NULL, then the channel is not allocated.
 435  * @chan: DMA engine handle.
 436  * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
 437  * transfer and call client callback.
 438  * @client: Cliented owned descriptor list.
 439  * @pending_queue: Submitted jobs, to be issued by issue_pending()
 440  * @active: Active descriptor.
 441  * @done: Completed jobs
 442  * @queue: Queued jobs.
 443  * @prepare_queue: Prepared jobs.
 444  * @dma_cfg: The client configuration of this dma channel.
 445  * @configured: whether the dma_cfg configuration is valid
 446  * @base: Pointer to the device instance struct.
 447  * @src_def_cfg: Default cfg register setting for src.
 448  * @dst_def_cfg: Default cfg register setting for dst.
 449  * @log_def: Default logical channel settings.
 450  * @lcpa: Pointer to dst and src lcpa settings.
 451  * @runtime_addr: runtime configured address.
 452  * @runtime_direction: runtime configured direction.
 453  *
 454  * This struct can either "be" a logical or a physical channel.
 455  */
 456 struct d40_chan {
 457         spinlock_t                       lock;
 458         int                              log_num;
 459         int                              pending_tx;
 460         bool                             busy;
 461         struct d40_phy_res              *phy_chan;
 462         struct dma_chan                  chan;
 463         struct tasklet_struct            tasklet;
 464         struct list_head                 client;
 465         struct list_head                 pending_queue;
 466         struct list_head                 active;
 467         struct list_head                 done;
 468         struct list_head                 queue;
 469         struct list_head                 prepare_queue;
 470         struct stedma40_chan_cfg         dma_cfg;
 471         bool                             configured;
 472         struct d40_base                 *base;
 473         /* Default register configurations */
 474         u32                              src_def_cfg;
 475         u32                              dst_def_cfg;
 476         struct d40_def_lcsp              log_def;
 477         struct d40_log_lli_full         *lcpa;
 478         /* Runtime reconfiguration */
 479         dma_addr_t                      runtime_addr;
 480         enum dma_transfer_direction     runtime_direction;
 481 };
 482
 483 /**
 484  * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
 485  * controller
 486  *
 487  * @backup: the pointer to the registers address array for backup
 488  * @backup_size: the size of the registers address array for backup
 489  * @realtime_en: the realtime enable register
 490  * @realtime_clear: the realtime clear register
 491  * @high_prio_en: the high priority enable register
 492  * @high_prio_clear: the high priority clear register
 493  * @interrupt_en: the interrupt enable register
 494  * @interrupt_clear: the interrupt clear register
 495  * @il: the pointer to struct d40_interrupt_lookup
 496  * @il_size: the size of d40_interrupt_lookup array
 497  * @init_reg: the pointer to the struct d40_reg_val
 498  * @init_reg_size: the size of d40_reg_val array
 499  */
 500 struct d40_gen_dmac {
 501         u32                             *backup;
 502         u32                              backup_size;
 503         u32                              realtime_en;
 504         u32                              realtime_clear;
 505         u32                              high_prio_en;
 506         u32                              high_prio_clear;
 507         u32                              interrupt_en;
 508         u32                              interrupt_clear;
 509         struct d40_interrupt_lookup     *il;
 510         u32                              il_size;
 511         struct d40_reg_val              *init_reg;
 512         u32                              init_reg_size;
 513 };
 514
 515 /**
 516  * struct d40_base - The big global struct, one for each probe'd instance.
 517  *
 518  * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
 519  * @execmd_lock: Lock for execute command usage since several channels share
 520  * the same physical register.
 521  * @dev: The device structure.
 522  * @virtbase: The virtual base address of the DMA's register.
 523  * @rev: silicon revision detected.
 524  * @clk: Pointer to the DMA clock structure.
 525  * @phy_start: Physical memory start of the DMA registers.
 526  * @phy_size: Size of the DMA register map.
 527  * @irq: The IRQ number.
 528  * @num_memcpy_chans: The number of channels used for memcpy (mem-to-mem
 529  * transfers).
 530  * @num_phy_chans: The number of physical channels. Read from HW. This
 531  * is the number of available channels for this driver, not counting "Secure
 532  * mode" allocated physical channels.
 533  * @num_log_chans: The number of logical channels. Calculated from
 534  * num_phy_chans.
 535  * @dma_both: dma_device channels that can do both memcpy and slave transfers.
 536  * @dma_slave: dma_device channels that can do only do slave transfers.
 537  * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
 538  * @phy_chans: Room for all possible physical channels in system.
 539  * @log_chans: Room for all possible logical channels in system.
 540  * @lookup_log_chans: Used to map interrupt number to logical channel. Points
 541  * to log_chans entries.
 542  * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
 543  * to phy_chans entries.
 544  * @plat_data: Pointer to provided platform_data which is the driver
 545  * configuration.
 546  * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
 547  * @phy_res: Vector containing all physical channels.
 548  * @lcla_pool: lcla pool settings and data.
 549  * @lcpa_base: The virtual mapped address of LCPA.
 550  * @phy_lcpa: The physical address of the LCPA.
 551  * @lcpa_size: The size of the LCPA area.
 552  * @desc_slab: cache for descriptors.
 553  * @reg_val_backup: Here the values of some hardware registers are stored
 554  * before the DMA is powered off. They are restored when the power is back on.
 555  * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
 556  * later
 557  * @reg_val_backup_chan: Backup data for standard channel parameter registers.
 558  * @regs_interrupt: Scratch space for registers during interrupt.
 559  * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
 560  * @gen_dmac: the struct for generic registers values to represent u8500/8540
 561  * DMA controller
 562  */
 563 struct d40_base {
 564         spinlock_t                       interrupt_lock;
 565         spinlock_t                       execmd_lock;
 566         struct device                    *dev;
 567         void __iomem                     *virtbase;
 568         u8                                rev:4;
 569         struct clk                       *clk;
 570         phys_addr_t                       phy_start;
 571         resource_size_t                   phy_size;
 572         int                               irq;
 573         int                               num_memcpy_chans;
 574         int                               num_phy_chans;
 575         int                               num_log_chans;
 576         struct device_dma_parameters      dma_parms;
 577         struct dma_device                 dma_both;
 578         struct dma_device                 dma_slave;
 579         struct dma_device                 dma_memcpy;
 580         struct d40_chan                  *phy_chans;
 581         struct d40_chan                  *log_chans;
 582         struct d40_chan                 **lookup_log_chans;
 583         struct d40_chan                 **lookup_phy_chans;
 584         struct stedma40_platform_data    *plat_data;
 585         struct regulator                 *lcpa_regulator;
 586         /* Physical half channels */
 587         struct d40_phy_res               *phy_res;
 588         struct d40_lcla_pool              lcla_pool;
 589         void                             *lcpa_base;
 590         dma_addr_t                        phy_lcpa;
 591         resource_size_t                   lcpa_size;
 592         struct kmem_cache                *desc_slab;
 593         u32                               reg_val_backup[BACKUP_REGS_SZ];
 594         u32                               reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
 595         u32                              *reg_val_backup_chan;
 596         u32                              *regs_interrupt;
 597         u16                               gcc_pwr_off_mask;
 598         struct d40_gen_dmac               gen_dmac;
 599 };
 600
 601 static struct device *chan2dev(struct d40_chan *d40c)
 602 {
 603         return &d40c->chan.dev->device;
 604 }
 605
 606 static bool chan_is_physical(struct d40_chan *chan)
 607 {
 608         return chan->log_num == D40_PHY_CHAN;
 609 }
 610
 611 static bool chan_is_logical(struct d40_chan *chan)
 612 {
 613         return !chan_is_physical(chan);
 614 }
 615
 616 static void __iomem *chan_base(struct d40_chan *chan)
 617 {
 618         return chan->base->virtbase + D40_DREG_PCBASE +
 619                chan->phy_chan->num * D40_DREG_PCDELTA;
 620 }
 621
 622 #define d40_err(dev, format, arg...)            \
 623         dev_err(dev, "[%s] " format, __func__, ## arg)
 624
 625 #define chan_err(d40c, format, arg...)          \
 626         d40_err(chan2dev(d40c), format, ## arg)
 627
 628 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
 629                               int lli_len)
 630 {
 631         bool is_log = chan_is_logical(d40c);
 632         u32 align;
 633         void *base;
 634
 635         if (is_log)
 636                 align = sizeof(struct d40_log_lli);
 637         else
 638                 align = sizeof(struct d40_phy_lli);
 639
 640         if (lli_len == 1) {
 641                 base = d40d->lli_pool.pre_alloc_lli;
 642                 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
 643                 d40d->lli_pool.base = NULL;
 644         } else {
 645                 d40d->lli_pool.size = lli_len * 2 * align;
 646
 647                 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
 648                 d40d->lli_pool.base = base;
 649
 650                 if (d40d->lli_pool.base == NULL)
 651                         return -ENOMEM;
 652         }
 653
 654         if (is_log) {
 655                 d40d->lli_log.src = PTR_ALIGN(base, align);
 656                 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
 657
 658                 d40d->lli_pool.dma_addr = 0;
 659         } else {
 660                 d40d->lli_phy.src = PTR_ALIGN(base, align);
 661                 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
 662
 663                 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
 664                                                          d40d->lli_phy.src,
 665                                                          d40d->lli_pool.size,
 666                                                          DMA_TO_DEVICE);
 667
 668                 if (dma_mapping_error(d40c->base->dev,
 669                                       d40d->lli_pool.dma_addr)) {
 670                         kfree(d40d->lli_pool.base);
 671                         d40d->lli_pool.base = NULL;
 672                         d40d->lli_pool.dma_addr = 0;
 673                         return -ENOMEM;
 674                 }
 675         }
 676
 677         return 0;
 678 }
 679
 680 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
 681 {
 682         if (d40d->lli_pool.dma_addr)
 683                 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
 684                                  d40d->lli_pool.size, DMA_TO_DEVICE);
 685
 686         kfree(d40d->lli_pool.base);
 687         d40d->lli_pool.base = NULL;
 688         d40d->lli_pool.size = 0;
 689         d40d->lli_log.src = NULL;
 690         d40d->lli_log.dst = NULL;
 691         d40d->lli_phy.src = NULL;
 692         d40d->lli_phy.dst = NULL;
 693 }
 694
 695 static int d40_lcla_alloc_one(struct d40_chan *d40c,
 696                               struct d40_desc *d40d)
 697 {
 698         unsigned long flags;
 699         int i;
 700         int ret = -EINVAL;
 701
 702         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 703
 704         /*
 705          * Allocate both src and dst at the same time, therefore the half
 706          * start on 1 since 0 can't be used since zero is used as end marker.
 707          */
 708         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 709                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
 710
 711                 if (!d40c->base->lcla_pool.alloc_map[idx]) {
 712                         d40c->base->lcla_pool.alloc_map[idx] = d40d;
 713                         d40d->lcla_alloc++;
 714                         ret = i;
 715                         break;
 716                 }
 717         }
 718
 719         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 720
 721         return ret;
 722 }
 723
 724 static int d40_lcla_free_all(struct d40_chan *d40c,
 725                              struct d40_desc *d40d)
 726 {
 727         unsigned long flags;
 728         int i;
 729         int ret = -EINVAL;
 730
 731         if (chan_is_physical(d40c))
 732                 return 0;
 733
 734         spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
 735
 736         for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
 737                 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
 738
 739                 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
 740                         d40c->base->lcla_pool.alloc_map[idx] = NULL;
 741                         d40d->lcla_alloc--;
 742                         if (d40d->lcla_alloc == 0) {
 743                                 ret = 0;
 744                                 break;
 745                         }
 746                 }
 747         }
 748
 749         spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
 750
 751         return ret;
 752
 753 }
 754
 755 static void d40_desc_remove(struct d40_desc *d40d)
 756 {
 757         list_del(&d40d->node);
 758 }
 759
 760 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
 761 {
 762         struct d40_desc *desc = NULL;
 763
 764         if (!list_empty(&d40c->client)) {
 765                 struct d40_desc *d;
 766                 struct d40_desc *_d;
 767
 768                 list_for_each_entry_safe(d, _d, &d40c->client, node) {
 769                         if (async_tx_test_ack(&d->txd)) {
 770                                 d40_desc_remove(d);
 771                                 desc = d;
 772                                 memset(desc, 0, sizeof(*desc));
 773                                 break;
 774                         }
 775                 }
 776         }
 777
 778         if (!desc)
 779                 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
 780
 781         if (desc)
 782                 INIT_LIST_HEAD(&desc->node);
 783
 784         return desc;
 785 }
 786
 787 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
 788 {
 789
 790         d40_pool_lli_free(d40c, d40d);
 791         d40_lcla_free_all(d40c, d40d);
 792         kmem_cache_free(d40c->base->desc_slab, d40d);
 793 }
 794
 795 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
 796 {
 797         list_add_tail(&desc->node, &d40c->active);
 798 }
 799
 800 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
 801 {
 802         struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
 803         struct d40_phy_lli *lli_src = desc->lli_phy.src;
 804         void __iomem *base = chan_base(chan);
 805
 806         writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
 807         writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
 808         writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
 809         writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
 810
 811         writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
 812         writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
 813         writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
 814         writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
 815 }
 816
 817 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
 818 {
 819         list_add_tail(&desc->node, &d40c->done);
 820 }
 821
 822 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
 823 {
 824         struct d40_lcla_pool *pool = &chan->base->lcla_pool;
 825         struct d40_log_lli_bidir *lli = &desc->lli_log;
 826         int lli_current = desc->lli_current;
 827         int lli_len = desc->lli_len;
 828         bool cyclic = desc->cyclic;
 829         int curr_lcla = -EINVAL;
 830         int first_lcla = 0;
 831         bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
 832         bool linkback;
 833
 834         /*
 835          * We may have partially running cyclic transfers, in case we did't get
 836          * enough LCLA entries.
 837          */
 838         linkback = cyclic && lli_current == 0;
 839
 840         /*
 841          * For linkback, we need one LCLA even with only one link, because we
 842          * can't link back to the one in LCPA space
 843          */
 844         if (linkback || (lli_len - lli_current > 1)) {
 845                 /*
 846                  * If the channel is expected to use only soft_lli don't
 847                  * allocate a lcla. This is to avoid a HW issue that exists
 848                  * in some controller during a peripheral to memory transfer
 849                  * that uses linked lists.
 850                  */
 851                 if (!(chan->phy_chan->use_soft_lli &&
 852                         chan->dma_cfg.dir == DMA_DEV_TO_MEM))
 853                         curr_lcla = d40_lcla_alloc_one(chan, desc);
 854
 855                 first_lcla = curr_lcla;
 856         }
 857
 858         /*
 859          * For linkback, we normally load the LCPA in the loop since we need to
 860          * link it to the second LCLA and not the first.  However, if we
 861          * couldn't even get a first LCLA, then we have to run in LCPA and
 862          * reload manually.
 863          */
 864         if (!linkback || curr_lcla == -EINVAL) {
 865                 unsigned int flags = 0;
 866
 867                 if (curr_lcla == -EINVAL)
 868                         flags |= LLI_TERM_INT;
 869
 870                 d40_log_lli_lcpa_write(chan->lcpa,
 871                                        &lli->dst[lli_current],
 872                                        &lli->src[lli_current],
 873                                        curr_lcla,
 874                                        flags);
 875                 lli_current++;
 876         }
 877
 878         if (curr_lcla < 0)
 879                 goto set_current;
 880
 881         for (; lli_current < lli_len; lli_current++) {
 882                 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
 883                                            8 * curr_lcla * 2;
 884                 struct d40_log_lli *lcla = pool->base + lcla_offset;
 885                 unsigned int flags = 0;
 886                 int next_lcla;
 887
 888                 if (lli_current + 1 < lli_len)
 889                         next_lcla = d40_lcla_alloc_one(chan, desc);
 890                 else
 891                         next_lcla = linkback ? first_lcla : -EINVAL;
 892
 893                 if (cyclic || next_lcla == -EINVAL)
 894                         flags |= LLI_TERM_INT;
 895
 896                 if (linkback && curr_lcla == first_lcla) {
 897                         /* First link goes in both LCPA and LCLA */
 898                         d40_log_lli_lcpa_write(chan->lcpa,
 899                                                &lli->dst[lli_current],
 900                                                &lli->src[lli_current],
 901                                                next_lcla, flags);
 902                 }
 903
 904                 /*
 905                  * One unused LCLA in the cyclic case if the very first
 906                  * next_lcla fails...
 907                  */
 908                 d40_log_lli_lcla_write(lcla,
 909                                        &lli->dst[lli_current],
 910                                        &lli->src[lli_current],
 911                                        next_lcla, flags);
 912
 913                 /*
 914                  * Cache maintenance is not needed if lcla is
 915                  * mapped in esram
 916                  */
 917                 if (!use_esram_lcla) {
 918                         dma_sync_single_range_for_device(chan->base->dev,
 919                                                 pool->dma_addr, lcla_offset,
 920                                                 2 * sizeof(struct d40_log_lli),
 921                                                 DMA_TO_DEVICE);
 922                 }
 923                 curr_lcla = next_lcla;
 924
 925                 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
 926                         lli_current++;
 927                         break;
 928                 }
 929         }
 930  set_current:
 931         desc->lli_current = lli_current;
 932 }
 933
 934 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
 935 {
 936         if (chan_is_physical(d40c)) {
 937                 d40_phy_lli_load(d40c, d40d);
 938                 d40d->lli_current = d40d->lli_len;
 939         } else
 940                 d40_log_lli_to_lcxa(d40c, d40d);
 941 }
 942
 943 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
 944 {
 945         return list_first_entry_or_null(&d40c->active, struct d40_desc, node);
 946 }
 947
 948 /* remove desc from current queue and add it to the pending_queue */
 949 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
 950 {
 951         d40_desc_remove(desc);
 952         desc->is_in_client_list = false;
 953         list_add_tail(&desc->node, &d40c->pending_queue);
 954 }
 955
 956 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
 957 {
 958         return list_first_entry_or_null(&d40c->pending_queue, struct d40_desc,
 959                                         node);
 960 }
 961
 962 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
 963 {
 964         return list_first_entry_or_null(&d40c->queue, struct d40_desc, node);
 965 }
 966
 967 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
 968 {
 969         return list_first_entry_or_null(&d40c->done, struct d40_desc, node);
 970 }
 971
 972 static int d40_psize_2_burst_size(bool is_log, int psize)
 973 {
 974         if (is_log) {
 975                 if (psize == STEDMA40_PSIZE_LOG_1)
 976                         return 1;
 977         } else {
 978                 if (psize == STEDMA40_PSIZE_PHY_1)
 979                         return 1;
 980         }
 981
 982         return 2 << psize;
 983 }
 984
 985 /*
 986  * The dma only supports transmitting packages up to
 987  * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
 988  *
 989  * Calculate the total number of dma elements required to send the entire sg list.
 990  */
 991 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
 992 {
 993         int dmalen;
 994         u32 max_w = max(data_width1, data_width2);
 995         u32 min_w = min(data_width1, data_width2);
 996         u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
 997
 998         if (seg_max > STEDMA40_MAX_SEG_SIZE)
 999                 seg_max -= max_w;
1000
1001         if (!IS_ALIGNED(size, max_w))
1002                 return -EINVAL;
1003
1004         if (size <= seg_max)
1005                 dmalen = 1;
1006         else {
1007                 dmalen = size / seg_max;
1008                 if (dmalen * seg_max < size)
1009                         dmalen++;
1010         }
1011         return dmalen;
1012 }
1013
1014 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1015                            u32 data_width1, u32 data_width2)
1016 {
1017         struct scatterlist *sg;
1018         int i;
1019         int len = 0;
1020         int ret;
1021
1022         for_each_sg(sgl, sg, sg_len, i) {
1023                 ret = d40_size_2_dmalen(sg_dma_len(sg),
1024                                         data_width1, data_width2);
1025                 if (ret < 0)
1026                         return ret;
1027                 len += ret;
1028         }
1029         return len;
1030 }
1031
1032 static int __d40_execute_command_phy(struct d40_chan *d40c,
1033                                      enum d40_command command)
1034 {
1035         u32 status;
1036         int i;
1037         void __iomem *active_reg;
1038         int ret = 0;
1039         unsigned long flags;
1040         u32 wmask;
1041
1042         if (command == D40_DMA_STOP) {
1043                 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1044                 if (ret)
1045                         return ret;
1046         }
1047
1048         spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1049
1050         if (d40c->phy_chan->num % 2 == 0)
1051                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1052         else
1053                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1054
1055         if (command == D40_DMA_SUSPEND_REQ) {
1056                 status = (readl(active_reg) &
1057                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1058                         D40_CHAN_POS(d40c->phy_chan->num);
1059
1060                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1061                         goto unlock;
1062         }
1063
1064         wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1065         writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1066                active_reg);
1067
1068         if (command == D40_DMA_SUSPEND_REQ) {
1069
1070                 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1071                         status = (readl(active_reg) &
1072                                   D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1073                                 D40_CHAN_POS(d40c->phy_chan->num);
1074
1075                         cpu_relax();
1076                         /*
1077                          * Reduce the number of bus accesses while
1078                          * waiting for the DMA to suspend.
1079                          */
1080                         udelay(3);
1081
1082                         if (status == D40_DMA_STOP ||
1083                             status == D40_DMA_SUSPENDED)
1084                                 break;
1085                 }
1086
1087                 if (i == D40_SUSPEND_MAX_IT) {
1088                         chan_err(d40c,
1089                                 "unable to suspend the chl %d (log: %d) status %x\n",
1090                                 d40c->phy_chan->num, d40c->log_num,
1091                                 status);
1092                         dump_stack();
1093                         ret = -EBUSY;
1094                 }
1095
1096         }
1097  unlock:
1098         spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1099         return ret;
1100 }
1101
1102 static void d40_term_all(struct d40_chan *d40c)
1103 {
1104         struct d40_desc *d40d;
1105         struct d40_desc *_d;
1106
1107         /* Release completed descriptors */
1108         while ((d40d = d40_first_done(d40c))) {
1109                 d40_desc_remove(d40d);
1110                 d40_desc_free(d40c, d40d);
1111         }
1112
1113         /* Release active descriptors */
1114         while ((d40d = d40_first_active_get(d40c))) {
1115                 d40_desc_remove(d40d);
1116                 d40_desc_free(d40c, d40d);
1117         }
1118
1119         /* Release queued descriptors waiting for transfer */
1120         while ((d40d = d40_first_queued(d40c))) {
1121                 d40_desc_remove(d40d);
1122                 d40_desc_free(d40c, d40d);
1123         }
1124
1125         /* Release pending descriptors */
1126         while ((d40d = d40_first_pending(d40c))) {
1127                 d40_desc_remove(d40d);
1128                 d40_desc_free(d40c, d40d);
1129         }
1130
1131         /* Release client owned descriptors */
1132         if (!list_empty(&d40c->client))
1133                 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1134                         d40_desc_remove(d40d);
1135                         d40_desc_free(d40c, d40d);
1136                 }
1137
1138         /* Release descriptors in prepare queue */
1139         if (!list_empty(&d40c->prepare_queue))
1140                 list_for_each_entry_safe(d40d, _d,
1141                                          &d40c->prepare_queue, node) {
1142                         d40_desc_remove(d40d);
1143                         d40_desc_free(d40c, d40d);
1144                 }
1145
1146         d40c->pending_tx = 0;
1147 }
1148
1149 static void __d40_config_set_event(struct d40_chan *d40c,
1150                                    enum d40_events event_type, u32 event,
1151                                    int reg)
1152 {
1153         void __iomem *addr = chan_base(d40c) + reg;
1154         int tries;
1155         u32 status;
1156
1157         switch (event_type) {
1158
1159         case D40_DEACTIVATE_EVENTLINE:
1160
1161                 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1162                        | ~D40_EVENTLINE_MASK(event), addr);
1163                 break;
1164
1165         case D40_SUSPEND_REQ_EVENTLINE:
1166                 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1167                           D40_EVENTLINE_POS(event);
1168
1169                 if (status == D40_DEACTIVATE_EVENTLINE ||
1170                     status == D40_SUSPEND_REQ_EVENTLINE)
1171                         break;
1172
1173                 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1174                        | ~D40_EVENTLINE_MASK(event), addr);
1175
1176                 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1177
1178                         status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1179                                   D40_EVENTLINE_POS(event);
1180
1181                         cpu_relax();
1182                         /*
1183                          * Reduce the number of bus accesses while
1184                          * waiting for the DMA to suspend.
1185                          */
1186                         udelay(3);
1187
1188                         if (status == D40_DEACTIVATE_EVENTLINE)
1189                                 break;
1190                 }
1191
1192                 if (tries == D40_SUSPEND_MAX_IT) {
1193                         chan_err(d40c,
1194                                 "unable to stop the event_line chl %d (log: %d)"
1195                                 "status %x\n", d40c->phy_chan->num,
1196                                  d40c->log_num, status);
1197                 }
1198                 break;
1199
1200         case D40_ACTIVATE_EVENTLINE:
1201         /*
1202          * The hardware sometimes doesn't register the enable when src and dst
1203          * event lines are active on the same logical channel.  Retry to ensure
1204          * it does.  Usually only one retry is sufficient.
1205          */
1206                 tries = 100;
1207                 while (--tries) {
1208                         writel((D40_ACTIVATE_EVENTLINE <<
1209                                 D40_EVENTLINE_POS(event)) |
1210                                 ~D40_EVENTLINE_MASK(event), addr);
1211
1212                         if (readl(addr) & D40_EVENTLINE_MASK(event))
1213                                 break;
1214                 }
1215
1216                 if (tries != 99)
1217                         dev_dbg(chan2dev(d40c),
1218                                 "[%s] workaround enable S%cLNK (%d tries)\n",
1219                                 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1220                                 100 - tries);
1221
1222                 WARN_ON(!tries);
1223                 break;
1224
1225         case D40_ROUND_EVENTLINE:
1226                 BUG();
1227                 break;
1228
1229         }
1230 }
1231
1232 static void d40_config_set_event(struct d40_chan *d40c,
1233                                  enum d40_events event_type)
1234 {
1235         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1236
1237         /* Enable event line connected to device (or memcpy) */
1238         if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1239             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1240                 __d40_config_set_event(d40c, event_type, event,
1241                                        D40_CHAN_REG_SSLNK);
1242
1243         if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
1244                 __d40_config_set_event(d40c, event_type, event,
1245                                        D40_CHAN_REG_SDLNK);
1246 }
1247
1248 static u32 d40_chan_has_events(struct d40_chan *d40c)
1249 {
1250         void __iomem *chanbase = chan_base(d40c);
1251         u32 val;
1252
1253         val = readl(chanbase + D40_CHAN_REG_SSLNK);
1254         val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1255
1256         return val;
1257 }
1258
1259 static int
1260 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1261 {
1262         unsigned long flags;
1263         int ret = 0;
1264         u32 active_status;
1265         void __iomem *active_reg;
1266
1267         if (d40c->phy_chan->num % 2 == 0)
1268                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1269         else
1270                 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1271
1272
1273         spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1274
1275         switch (command) {
1276         case D40_DMA_STOP:
1277         case D40_DMA_SUSPEND_REQ:
1278
1279                 active_status = (readl(active_reg) &
1280                                  D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1281                                  D40_CHAN_POS(d40c->phy_chan->num);
1282
1283                 if (active_status == D40_DMA_RUN)
1284                         d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1285                 else
1286                         d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1287
1288                 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1289                         ret = __d40_execute_command_phy(d40c, command);
1290
1291                 break;
1292
1293         case D40_DMA_RUN:
1294
1295                 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1296                 ret = __d40_execute_command_phy(d40c, command);
1297                 break;
1298
1299         case D40_DMA_SUSPENDED:
1300                 BUG();
1301                 break;
1302         }
1303
1304         spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1305         return ret;
1306 }
1307
1308 static int d40_channel_execute_command(struct d40_chan *d40c,
1309                                        enum d40_command command)
1310 {
1311         if (chan_is_logical(d40c))
1312                 return __d40_execute_command_log(d40c, command);
1313         else
1314                 return __d40_execute_command_phy(d40c, command);
1315 }
1316
1317 static u32 d40_get_prmo(struct d40_chan *d40c)
1318 {
1319         static const unsigned int phy_map[] = {
1320                 [STEDMA40_PCHAN_BASIC_MODE]
1321                         = D40_DREG_PRMO_PCHAN_BASIC,
1322                 [STEDMA40_PCHAN_MODULO_MODE]
1323                         = D40_DREG_PRMO_PCHAN_MODULO,
1324                 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1325                         = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1326         };
1327         static const unsigned int log_map[] = {
1328                 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1329                         = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1330                 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1331                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1332                 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1333                         = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1334         };
1335
1336         if (chan_is_physical(d40c))
1337                 return phy_map[d40c->dma_cfg.mode_opt];
1338         else
1339                 return log_map[d40c->dma_cfg.mode_opt];
1340 }
1341
1342 static void d40_config_write(struct d40_chan *d40c)
1343 {
1344         u32 addr_base;
1345         u32 var;
1346
1347         /* Odd addresses are even addresses + 4 */
1348         addr_base = (d40c->phy_chan->num % 2) * 4;
1349         /* Setup channel mode to logical or physical */
1350         var = ((u32)(chan_is_logical(d40c)) + 1) <<
1351                 D40_CHAN_POS(d40c->phy_chan->num);
1352         writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1353
1354         /* Setup operational mode option register */
1355         var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1356
1357         writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1358
1359         if (chan_is_logical(d40c)) {
1360                 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1361                            & D40_SREG_ELEM_LOG_LIDX_MASK;
1362                 void __iomem *chanbase = chan_base(d40c);
1363
1364                 /* Set default config for CFG reg */
1365                 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1366                 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1367
1368                 /* Set LIDX for lcla */
1369                 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1370                 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1371
1372                 /* Clear LNK which will be used by d40_chan_has_events() */
1373                 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1374                 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1375         }
1376 }
1377
1378 static u32 d40_residue(struct d40_chan *d40c)
1379 {
1380         u32 num_elt;
1381
1382         if (chan_is_logical(d40c))
1383                 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1384                         >> D40_MEM_LCSP2_ECNT_POS;
1385         else {
1386                 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1387                 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1388                           >> D40_SREG_ELEM_PHY_ECNT_POS;
1389         }
1390
1391         return num_elt * d40c->dma_cfg.dst_info.data_width;
1392 }
1393
1394 static bool d40_tx_is_linked(struct d40_chan *d40c)
1395 {
1396         bool is_link;
1397
1398         if (chan_is_logical(d40c))
1399                 is_link = readl(&d40c->lcpa->lcsp3) &  D40_MEM_LCSP3_DLOS_MASK;
1400         else
1401                 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1402                           & D40_SREG_LNK_PHYS_LNK_MASK;
1403
1404         return is_link;
1405 }
1406
1407 static int d40_pause(struct dma_chan *chan)
1408 {
1409         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1410         int res = 0;
1411         unsigned long flags;
1412
1413         if (d40c->phy_chan == NULL) {
1414                 chan_err(d40c, "Channel is not allocated!\n");
1415                 return -EINVAL;
1416         }
1417
1418         if (!d40c->busy)
1419                 return 0;
1420
1421         spin_lock_irqsave(&d40c->lock, flags);
1422         pm_runtime_get_sync(d40c->base->dev);
1423
1424         res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1425
1426         pm_runtime_mark_last_busy(d40c->base->dev);
1427         pm_runtime_put_autosuspend(d40c->base->dev);
1428         spin_unlock_irqrestore(&d40c->lock, flags);
1429         return res;
1430 }
1431
1432 static int d40_resume(struct dma_chan *chan)
1433 {
1434         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
1435         int res = 0;
1436         unsigned long flags;
1437
1438         if (d40c->phy_chan == NULL) {
1439                 chan_err(d40c, "Channel is not allocated!\n");
1440                 return -EINVAL;
1441         }
1442
1443         if (!d40c->busy)
1444                 return 0;
1445
1446         spin_lock_irqsave(&d40c->lock, flags);
1447         pm_runtime_get_sync(d40c->base->dev);
1448
1449         /* If bytes left to transfer or linked tx resume job */
1450         if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1451                 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1452
1453         pm_runtime_mark_last_busy(d40c->base->dev);
1454         pm_runtime_put_autosuspend(d40c->base->dev);
1455         spin_unlock_irqrestore(&d40c->lock, flags);
1456         return res;
1457 }
1458
1459 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1460 {
1461         struct d40_chan *d40c = container_of(tx->chan,
1462                                              struct d40_chan,
1463                                              chan);
1464         struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1465         unsigned long flags;
1466         dma_cookie_t cookie;
1467
1468         spin_lock_irqsave(&d40c->lock, flags);
1469         cookie = dma_cookie_assign(tx);
1470         d40_desc_queue(d40c, d40d);
1471         spin_unlock_irqrestore(&d40c->lock, flags);
1472
1473         return cookie;
1474 }
1475
1476 static int d40_start(struct d40_chan *d40c)
1477 {
1478         return d40_channel_execute_command(d40c, D40_DMA_RUN);
1479 }
1480
1481 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1482 {
1483         struct d40_desc *d40d;
1484         int err;
1485
1486         /* Start queued jobs, if any */
1487         d40d = d40_first_queued(d40c);
1488
1489         if (d40d != NULL) {
1490                 if (!d40c->busy) {
1491                         d40c->busy = true;
1492                         pm_runtime_get_sync(d40c->base->dev);
1493                 }
1494
1495                 /* Remove from queue */
1496                 d40_desc_remove(d40d);
1497
1498                 /* Add to active queue */
1499                 d40_desc_submit(d40c, d40d);
1500
1501                 /* Initiate DMA job */
1502                 d40_desc_load(d40c, d40d);
1503
1504                 /* Start dma job */
1505                 err = d40_start(d40c);
1506
1507                 if (err)
1508                         return NULL;
1509         }
1510
1511         return d40d;
1512 }
1513
1514 /* called from interrupt context */
1515 static void dma_tc_handle(struct d40_chan *d40c)
1516 {
1517         struct d40_desc *d40d;
1518
1519         /* Get first active entry from list */
1520         d40d = d40_first_active_get(d40c);
1521
1522         if (d40d == NULL)
1523                 return;
1524
1525         if (d40d->cyclic) {
1526                 /*
1527                  * If this was a paritially loaded list, we need to reloaded
1528                  * it, and only when the list is completed.  We need to check
1529                  * for done because the interrupt will hit for every link, and
1530                  * not just the last one.
1531                  */
1532                 if (d40d->lli_current < d40d->lli_len
1533                     && !d40_tx_is_linked(d40c)
1534                     && !d40_residue(d40c)) {
1535                         d40_lcla_free_all(d40c, d40d);
1536                         d40_desc_load(d40c, d40d);
1537                         (void) d40_start(d40c);
1538
1539                         if (d40d->lli_current == d40d->lli_len)
1540                                 d40d->lli_current = 0;
1541                 }
1542         } else {
1543                 d40_lcla_free_all(d40c, d40d);
1544
1545                 if (d40d->lli_current < d40d->lli_len) {
1546                         d40_desc_load(d40c, d40d);
1547                         /* Start dma job */
1548                         (void) d40_start(d40c);
1549                         return;
1550                 }
1551
1552                 if (d40_queue_start(d40c) == NULL) {
1553                         d40c->busy = false;
1554
1555                         pm_runtime_mark_last_busy(d40c->base->dev);
1556                         pm_runtime_put_autosuspend(d40c->base->dev);
1557                 }
1558
1559                 d40_desc_remove(d40d);
1560                 d40_desc_done(d40c, d40d);
1561         }
1562
1563         d40c->pending_tx++;
1564         tasklet_schedule(&d40c->tasklet);
1565
1566 }
1567
1568 static void dma_tasklet(unsigned long data)
1569 {
1570         struct d40_chan *d40c = (struct d40_chan *) data;
1571         struct d40_desc *d40d;
1572         unsigned long flags;
1573         bool callback_active;
1574         struct dmaengine_desc_callback cb;
1575
1576         spin_lock_irqsave(&d40c->lock, flags);
1577
1578         /* Get first entry from the done list */
1579         d40d = d40_first_done(d40c);
1580         if (d40d == NULL) {
1581                 /* Check if we have reached here for cyclic job */
1582                 d40d = d40_first_active_get(d40c);
1583                 if (d40d == NULL || !d40d->cyclic)
1584                         goto check_pending_tx;
1585         }
1586
1587         if (!d40d->cyclic)
1588                 dma_cookie_complete(&d40d->txd);
1589
1590         /*
1591          * If terminating a channel pending_tx is set to zero.
1592          * This prevents any finished active jobs to return to the client.
1593          */
1594         if (d40c->pending_tx == 0) {
1595                 spin_unlock_irqrestore(&d40c->lock, flags);
1596                 return;
1597         }
1598
1599         /* Callback to client */
1600         callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
1601         dmaengine_desc_get_callback(&d40d->txd, &cb);
1602
1603         if (!d40d->cyclic) {
1604                 if (async_tx_test_ack(&d40d->txd)) {
1605                         d40_desc_remove(d40d);
1606                         d40_desc_free(d40c, d40d);
1607                 } else if (!d40d->is_in_client_list) {
1608                         d40_desc_remove(d40d);
1609                         d40_lcla_free_all(d40c, d40d);
1610                         list_add_tail(&d40d->node, &d40c->client);
1611                         d40d->is_in_client_list = true;
1612                 }
1613         }
1614
1615         d40c->pending_tx--;
1616
1617         if (d40c->pending_tx)
1618                 tasklet_schedule(&d40c->tasklet);
1619
1620         spin_unlock_irqrestore(&d40c->lock, flags);
1621
1622         if (callback_active)
1623                 dmaengine_desc_callback_invoke(&cb, NULL);
1624
1625         return;
1626  check_pending_tx:
1627         /* Rescue manouver if receiving double interrupts */
1628         if (d40c->pending_tx > 0)
1629                 d40c->pending_tx--;
1630         spin_unlock_irqrestore(&d40c->lock, flags);
1631 }
1632
1633 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1634 {
1635         int i;
1636         u32 idx;
1637         u32 row;
1638         long chan = -1;
1639         struct d40_chan *d40c;
1640         unsigned long flags;
1641         struct d40_base *base = data;
1642         u32 *regs = base->regs_interrupt;
1643         struct d40_interrupt_lookup *il = base->gen_dmac.il;
1644         u32 il_size = base->gen_dmac.il_size;
1645
1646         spin_lock_irqsave(&base->interrupt_lock, flags);
1647
1648         /* Read interrupt status of both logical and physical channels */
1649         for (i = 0; i < il_size; i++)
1650                 regs[i] = readl(base->virtbase + il[i].src);
1651
1652         for (;;) {
1653
1654                 chan = find_next_bit((unsigned long *)regs,
1655                                      BITS_PER_LONG * il_size, chan + 1);
1656
1657                 /* No more set bits found? */
1658                 if (chan == BITS_PER_LONG * il_size)
1659                         break;
1660
1661                 row = chan / BITS_PER_LONG;
1662                 idx = chan & (BITS_PER_LONG - 1);
1663
1664                 if (il[row].offset == D40_PHY_CHAN)
1665                         d40c = base->lookup_phy_chans[idx];
1666                 else
1667                         d40c = base->lookup_log_chans[il[row].offset + idx];
1668
1669                 if (!d40c) {
1670                         /*
1671                          * No error because this can happen if something else
1672                          * in the system is using the channel.
1673                          */
1674                         continue;
1675                 }
1676
1677                 /* ACK interrupt */
1678                 writel(BIT(idx), base->virtbase + il[row].clr);
1679
1680                 spin_lock(&d40c->lock);
1681
1682                 if (!il[row].is_error)
1683                         dma_tc_handle(d40c);
1684                 else
1685                         d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1686                                 chan, il[row].offset, idx);
1687
1688                 spin_unlock(&d40c->lock);
1689         }
1690
1691         spin_unlock_irqrestore(&base->interrupt_lock, flags);
1692
1693         return IRQ_HANDLED;
1694 }
1695
1696 static int d40_validate_conf(struct d40_chan *d40c,
1697                              struct stedma40_chan_cfg *conf)
1698 {
1699         int res = 0;
1700         bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1701
1702         if (!conf->dir) {
1703                 chan_err(d40c, "Invalid direction.\n");
1704                 res = -EINVAL;
1705         }
1706
1707         if ((is_log && conf->dev_type > d40c->base->num_log_chans)  ||
1708             (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1709             (conf->dev_type < 0)) {
1710                 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
1711                 res = -EINVAL;
1712         }
1713
1714         if (conf->dir == DMA_DEV_TO_DEV) {
1715                 /*
1716                  * DMAC HW supports it. Will be added to this driver,
1717                  * in case any dma client requires it.
1718                  */
1719                 chan_err(d40c, "periph to periph not supported\n");
1720                 res = -EINVAL;
1721         }
1722
1723         if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1724             conf->src_info.data_width !=
1725             d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1726             conf->dst_info.data_width) {
1727                 /*
1728                  * The DMAC hardware only supports
1729                  * src (burst x width) == dst (burst x width)
1730                  */
1731
1732                 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1733                 res = -EINVAL;
1734         }
1735
1736         return res;
1737 }
1738
1739 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1740                                bool is_src, int log_event_line, bool is_log,
1741                                bool *first_user)
1742 {
1743         unsigned long flags;
1744         spin_lock_irqsave(&phy->lock, flags);
1745
1746         *first_user = ((phy->allocated_src | phy->allocated_dst)
1747                         == D40_ALLOC_FREE);
1748
1749         if (!is_log) {
1750                 /* Physical interrupts are masked per physical full channel */
1751                 if (phy->allocated_src == D40_ALLOC_FREE &&
1752                     phy->allocated_dst == D40_ALLOC_FREE) {
1753                         phy->allocated_dst = D40_ALLOC_PHY;
1754                         phy->allocated_src = D40_ALLOC_PHY;
1755                         goto found_unlock;
1756                 } else
1757                         goto not_found_unlock;
1758         }
1759
1760         /* Logical channel */
1761         if (is_src) {
1762                 if (phy->allocated_src == D40_ALLOC_PHY)
1763                         goto not_found_unlock;
1764
1765                 if (phy->allocated_src == D40_ALLOC_FREE)
1766                         phy->allocated_src = D40_ALLOC_LOG_FREE;
1767
1768                 if (!(phy->allocated_src & BIT(log_event_line))) {
1769                         phy->allocated_src |= BIT(log_event_line);
1770                         goto found_unlock;
1771                 } else
1772                         goto not_found_unlock;
1773         } else {
1774                 if (phy->allocated_dst == D40_ALLOC_PHY)
1775                         goto not_found_unlock;
1776
1777                 if (phy->allocated_dst == D40_ALLOC_FREE)
1778                         phy->allocated_dst = D40_ALLOC_LOG_FREE;
1779
1780                 if (!(phy->allocated_dst & BIT(log_event_line))) {
1781                         phy->allocated_dst |= BIT(log_event_line);
1782                         goto found_unlock;
1783                 }
1784         }
1785  not_found_unlock:
1786         spin_unlock_irqrestore(&phy->lock, flags);
1787         return false;
1788  found_unlock:
1789         spin_unlock_irqrestore(&phy->lock, flags);
1790         return true;
1791 }
1792
1793 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1794                                int log_event_line)
1795 {
1796         unsigned long flags;
1797         bool is_free = false;
1798
1799         spin_lock_irqsave(&phy->lock, flags);
1800         if (!log_event_line) {
1801                 phy->allocated_dst = D40_ALLOC_FREE;
1802                 phy->allocated_src = D40_ALLOC_FREE;
1803                 is_free = true;
1804                 goto unlock;
1805         }
1806
1807         /* Logical channel */
1808         if (is_src) {
1809                 phy->allocated_src &= ~BIT(log_event_line);
1810                 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1811                         phy->allocated_src = D40_ALLOC_FREE;
1812         } else {
1813                 phy->allocated_dst &= ~BIT(log_event_line);
1814                 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1815                         phy->allocated_dst = D40_ALLOC_FREE;
1816         }
1817
1818         is_free = ((phy->allocated_src | phy->allocated_dst) ==
1819                    D40_ALLOC_FREE);
1820  unlock:
1821         spin_unlock_irqrestore(&phy->lock, flags);
1822
1823         return is_free;
1824 }
1825
1826 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1827 {
1828         int dev_type = d40c->dma_cfg.dev_type;
1829         int event_group;
1830         int event_line;
1831         struct d40_phy_res *phys;
1832         int i;
1833         int j;
1834         int log_num;
1835         int num_phy_chans;
1836         bool is_src;
1837         bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1838
1839         phys = d40c->base->phy_res;
1840         num_phy_chans = d40c->base->num_phy_chans;
1841
1842         if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
1843                 log_num = 2 * dev_type;
1844                 is_src = true;
1845         } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1846                    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1847                 /* dst event lines are used for logical memcpy */
1848                 log_num = 2 * dev_type + 1;
1849                 is_src = false;
1850         } else
1851                 return -EINVAL;
1852
1853         event_group = D40_TYPE_TO_GROUP(dev_type);
1854         event_line = D40_TYPE_TO_EVENT(dev_type);
1855
1856         if (!is_log) {
1857                 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1858                         /* Find physical half channel */
1859                         if (d40c->dma_cfg.use_fixed_channel) {
1860                                 i = d40c->dma_cfg.phy_channel;
1861                                 if (d40_alloc_mask_set(&phys[i], is_src,
1862                                                        0, is_log,
1863                                                        first_phy_user))
1864                                         goto found_phy;
1865                         } else {
1866                                 for (i = 0; i < num_phy_chans; i++) {
1867                                         if (d40_alloc_mask_set(&phys[i], is_src,
1868                                                        0, is_log,
1869                                                        first_phy_user))
1870                                                 goto found_phy;
1871                                 }
1872                         }
1873                 } else
1874                         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1875                                 int phy_num = j  + event_group * 2;
1876                                 for (i = phy_num; i < phy_num + 2; i++) {
1877                                         if (d40_alloc_mask_set(&phys[i],
1878                                                                is_src,
1879                                                                0,
1880                                                                is_log,
1881                                                                first_phy_user))
1882                                                 goto found_phy;
1883                                 }
1884                         }
1885                 return -EINVAL;
1886 found_phy:
1887                 d40c->phy_chan = &phys[i];
1888                 d40c->log_num = D40_PHY_CHAN;
1889                 goto out;
1890         }
1891         if (dev_type == -1)
1892                 return -EINVAL;
1893
1894         /* Find logical channel */
1895         for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1896                 int phy_num = j + event_group * 2;
1897
1898                 if (d40c->dma_cfg.use_fixed_channel) {
1899                         i = d40c->dma_cfg.phy_channel;
1900
1901                         if ((i != phy_num) && (i != phy_num + 1)) {
1902                                 dev_err(chan2dev(d40c),
1903                                         "invalid fixed phy channel %d\n", i);
1904                                 return -EINVAL;
1905                         }
1906
1907                         if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1908                                                is_log, first_phy_user))
1909                                 goto found_log;
1910
1911                         dev_err(chan2dev(d40c),
1912                                 "could not allocate fixed phy channel %d\n", i);
1913                         return -EINVAL;
1914                 }
1915
1916                 /*
1917                  * Spread logical channels across all available physical rather
1918                  * than pack every logical channel at the first available phy
1919                  * channels.
1920                  */
1921                 if (is_src) {
1922                         for (i = phy_num; i < phy_num + 2; i++) {
1923                                 if (d40_alloc_mask_set(&phys[i], is_src,
1924                                                        event_line, is_log,
1925                                                        first_phy_user))
1926                                         goto found_log;
1927                         }
1928                 } else {
1929                         for (i = phy_num + 1; i >= phy_num; i--) {
1930                                 if (d40_alloc_mask_set(&phys[i], is_src,
1931                                                        event_line, is_log,
1932                                                        first_phy_user))
1933                                         goto found_log;
1934                         }
1935                 }
1936         }
1937         return -EINVAL;
1938
1939 found_log:
1940         d40c->phy_chan = &phys[i];
1941         d40c->log_num = log_num;
1942 out:
1943
1944         if (is_log)
1945                 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1946         else
1947                 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1948
1949         return 0;
1950
1951 }
1952
1953 static int d40_config_memcpy(struct d40_chan *d40c)
1954 {
1955         dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1956
1957         if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1958                 d40c->dma_cfg = dma40_memcpy_conf_log;
1959                 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
1960
1961                 d40_log_cfg(&d40c->dma_cfg,
1962                             &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1963
1964         } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1965                    dma_has_cap(DMA_SLAVE, cap)) {
1966                 d40c->dma_cfg = dma40_memcpy_conf_phy;
1967
1968                 /* Generate interrrupt at end of transfer or relink. */
1969                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
1970
1971                 /* Generate interrupt on error. */
1972                 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
1973                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
1974
1975         } else {
1976                 chan_err(d40c, "No memcpy\n");
1977                 return -EINVAL;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static int d40_free_dma(struct d40_chan *d40c)
1984 {
1985
1986         int res = 0;
1987         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1988         struct d40_phy_res *phy = d40c->phy_chan;
1989         bool is_src;
1990
1991         /* Terminate all queued and active transfers */
1992         d40_term_all(d40c);
1993
1994         if (phy == NULL) {
1995                 chan_err(d40c, "phy == null\n");
1996                 return -EINVAL;
1997         }
1998
1999         if (phy->allocated_src == D40_ALLOC_FREE &&
2000             phy->allocated_dst == D40_ALLOC_FREE) {
2001                 chan_err(d40c, "channel already free\n");
2002                 return -EINVAL;
2003         }
2004
2005         if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2006             d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
2007                 is_src = false;
2008         else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2009                 is_src = true;
2010         else {
2011                 chan_err(d40c, "Unknown direction\n");
2012                 return -EINVAL;
2013         }
2014
2015         pm_runtime_get_sync(d40c->base->dev);
2016         res = d40_channel_execute_command(d40c, D40_DMA_STOP);
2017         if (res) {
2018                 chan_err(d40c, "stop failed\n");
2019                 goto mark_last_busy;
2020         }
2021
2022         d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
2023
2024         if (chan_is_logical(d40c))
2025                 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
2026         else
2027                 d40c->base->lookup_phy_chans[phy->num] = NULL;
2028
2029         if (d40c->busy) {
2030                 pm_runtime_mark_last_busy(d40c->base->dev);
2031                 pm_runtime_put_autosuspend(d40c->base->dev);
2032         }
2033
2034         d40c->busy = false;
2035         d40c->phy_chan = NULL;
2036         d40c->configured = false;
2037  mark_last_busy:
2038         pm_runtime_mark_last_busy(d40c->base->dev);
2039         pm_runtime_put_autosuspend(d40c->base->dev);
2040         return res;
2041 }
2042
2043 static bool d40_is_paused(struct d40_chan *d40c)
2044 {
2045         void __iomem *chanbase = chan_base(d40c);
2046         bool is_paused = false;
2047         unsigned long flags;
2048         void __iomem *active_reg;
2049         u32 status;
2050         u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2051
2052         spin_lock_irqsave(&d40c->lock, flags);
2053
2054         if (chan_is_physical(d40c)) {
2055                 if (d40c->phy_chan->num % 2 == 0)
2056                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2057                 else
2058                         active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2059
2060                 status = (readl(active_reg) &
2061                           D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2062                         D40_CHAN_POS(d40c->phy_chan->num);
2063                 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2064                         is_paused = true;
2065                 goto unlock;
2066         }
2067
2068         if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2069             d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
2070                 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2071         } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
2072                 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2073         } else {
2074                 chan_err(d40c, "Unknown direction\n");
2075                 goto unlock;
2076         }
2077
2078         status = (status & D40_EVENTLINE_MASK(event)) >>
2079                 D40_EVENTLINE_POS(event);
2080
2081         if (status != D40_DMA_RUN)
2082                 is_paused = true;
2083  unlock:
2084         spin_unlock_irqrestore(&d40c->lock, flags);
2085         return is_paused;
2086
2087 }
2088
2089 static u32 stedma40_residue(struct dma_chan *chan)
2090 {
2091         struct d40_chan *d40c =
2092                 container_of(chan, struct d40_chan, chan);
2093         u32 bytes_left;
2094         unsigned long flags;
2095
2096         spin_lock_irqsave(&d40c->lock, flags);
2097         bytes_left = d40_residue(d40c);
2098         spin_unlock_irqrestore(&d40c->lock, flags);
2099
2100         return bytes_left;
2101 }
2102
2103 static int
2104 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2105                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2106                 unsigned int sg_len, dma_addr_t src_dev_addr,
2107                 dma_addr_t dst_dev_addr)
2108 {
2109         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2110         struct stedma40_half_channel_info *src_info = &cfg->src_info;
2111         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2112         int ret;
2113
2114         ret = d40_log_sg_to_lli(sg_src, sg_len,
2115                                 src_dev_addr,
2116                                 desc->lli_log.src,
2117                                 chan->log_def.lcsp1,
2118                                 src_info->data_width,
2119                                 dst_info->data_width);
2120
2121         ret = d40_log_sg_to_lli(sg_dst, sg_len,
2122                                 dst_dev_addr,
2123                                 desc->lli_log.dst,
2124                                 chan->log_def.lcsp3,
2125                                 dst_info->data_width,
2126                                 src_info->data_width);
2127
2128         return ret < 0 ? ret : 0;
2129 }
2130
2131 static int
2132 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2133                 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2134                 unsigned int sg_len, dma_addr_t src_dev_addr,
2135                 dma_addr_t dst_dev_addr)
2136 {
2137         struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2138         struct stedma40_half_channel_info *src_info = &cfg->src_info;
2139         struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2140         unsigned long flags = 0;
2141         int ret;
2142
2143         if (desc->cyclic)
2144                 flags |= LLI_CYCLIC | LLI_TERM_INT;
2145
2146         ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2147                                 desc->lli_phy.src,
2148                                 virt_to_phys(desc->lli_phy.src),
2149                                 chan->src_def_cfg,
2150                                 src_info, dst_info, flags);
2151
2152         ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2153                                 desc->lli_phy.dst,
2154                                 virt_to_phys(desc->lli_phy.dst),
2155                                 chan->dst_def_cfg,
2156                                 dst_info, src_info, flags);
2157
2158         dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2159                                    desc->lli_pool.size, DMA_TO_DEVICE);
2160
2161         return ret < 0 ? ret : 0;
2162 }
2163
2164 static struct d40_desc *
2165 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2166               unsigned int sg_len, unsigned long dma_flags)
2167 {
2168         struct stedma40_chan_cfg *cfg;
2169         struct d40_desc *desc;
2170         int ret;
2171
2172         desc = d40_desc_get(chan);
2173         if (!desc)
2174                 return NULL;
2175
2176         cfg = &chan->dma_cfg;
2177         desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2178                                         cfg->dst_info.data_width);
2179         if (desc->lli_len < 0) {
2180                 chan_err(chan, "Unaligned size\n");
2181                 goto free_desc;
2182         }
2183
2184         ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2185         if (ret < 0) {
2186                 chan_err(chan, "Could not allocate lli\n");
2187                 goto free_desc;
2188         }
2189
2190         desc->lli_current = 0;
2191         desc->txd.flags = dma_flags;
2192         desc->txd.tx_submit = d40_tx_submit;
2193
2194         dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2195
2196         return desc;
2197  free_desc:
2198         d40_desc_free(chan, desc);
2199         return NULL;
2200 }
2201
2202 static struct dma_async_tx_descriptor *
2203 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2204             struct scatterlist *sg_dst, unsigned int sg_len,
2205             enum dma_transfer_direction direction, unsigned long dma_flags)
2206 {
2207         struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2208         dma_addr_t src_dev_addr;
2209         dma_addr_t dst_dev_addr;
2210         struct d40_desc *desc;
2211         unsigned long flags;
2212         int ret;
2213
2214         if (!chan->phy_chan) {
2215                 chan_err(chan, "Cannot prepare unallocated channel\n");
2216                 return NULL;
2217         }
2218
2219         spin_lock_irqsave(&chan->lock, flags);
2220
2221         desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2222         if (desc == NULL)
2223                 goto unlock;
2224
2225         if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2226                 desc->cyclic = true;
2227
2228         src_dev_addr = 0;
2229         dst_dev_addr = 0;
2230         if (direction == DMA_DEV_TO_MEM)
2231                 src_dev_addr = chan->runtime_addr;
2232         else if (direction == DMA_MEM_TO_DEV)
2233                 dst_dev_addr = chan->runtime_addr;
2234
2235         if (chan_is_logical(chan))
2236                 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2237                                       sg_len, src_dev_addr, dst_dev_addr);
2238         else
2239                 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2240                                       sg_len, src_dev_addr, dst_dev_addr);
2241
2242         if (ret) {
2243                 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2244                          chan_is_logical(chan) ? "log" : "phy", ret);
2245                 goto free_desc;
2246         }
2247
2248         /*
2249          * add descriptor to the prepare queue in order to be able
2250          * to free them later in terminate_all
2251          */
2252         list_add_tail(&desc->node, &chan->prepare_queue);
2253
2254         spin_unlock_irqrestore(&chan->lock, flags);
2255
2256         return &desc->txd;
2257  free_desc:
2258         d40_desc_free(chan, desc);
2259  unlock:
2260         spin_unlock_irqrestore(&chan->lock, flags);
2261         return NULL;
2262 }
2263
2264 bool stedma40_filter(struct dma_chan *chan, void *data)
2265 {
2266         struct stedma40_chan_cfg *info = data;
2267         struct d40_chan *d40c =
2268                 container_of(chan, struct d40_chan, chan);
2269         int err;
2270
2271         if (data) {
2272                 err = d40_validate_conf(d40c, info);
2273                 if (!err)
2274                         d40c->dma_cfg = *info;
2275         } else
2276                 err = d40_config_memcpy(d40c);
2277
2278         if (!err)
2279                 d40c->configured = true;
2280
2281         return err == 0;
2282 }
2283 EXPORT_SYMBOL(stedma40_filter);
2284
2285 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2286 {
2287         bool realtime = d40c->dma_cfg.realtime;
2288         bool highprio = d40c->dma_cfg.high_priority;
2289         u32 rtreg;
2290         u32 event = D40_TYPE_TO_EVENT(dev_type);
2291         u32 group = D40_TYPE_TO_GROUP(dev_type);
2292         u32 bit = BIT(event);
2293         u32 prioreg;
2294         struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2295
2296         rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
2297         /*
2298          * Due to a hardware bug, in some cases a logical channel triggered by
2299          * a high priority destination event line can generate extra packet
2300          * transactions.
2301          *
2302          * The workaround is to not set the high priority level for the
2303          * destination event lines that trigger logical channels.
2304          */
2305         if (!src && chan_is_logical(d40c))
2306                 highprio = false;
2307
2308         prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
2309
2310         /* Destination event lines are stored in the upper halfword */
2311         if (!src)
2312                 bit <<= 16;
2313
2314         writel(bit, d40c->base->virtbase + prioreg + group * 4);
2315         writel(bit, d40c->base->virtbase + rtreg + group * 4);
2316 }
2317
2318 static void d40_set_prio_realtime(struct d40_chan *d40c)
2319 {
2320         if (d40c->base->rev < 3)
2321                 return;
2322
2323         if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
2324             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2325                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2326
2327         if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
2328             (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2329                 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2330 }
2331
2332 #define D40_DT_FLAGS_MODE(flags)       ((flags >> 0) & 0x1)
2333 #define D40_DT_FLAGS_DIR(flags)        ((flags >> 1) & 0x1)
2334 #define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2335 #define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2336 #define D40_DT_FLAGS_HIGH_PRIO(flags)  ((flags >> 4) & 0x1)
2337
2338 static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2339                                   struct of_dma *ofdma)
2340 {
2341         struct stedma40_chan_cfg cfg;
2342         dma_cap_mask_t cap;
2343         u32 flags;
2344
2345         memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2346
2347         dma_cap_zero(cap);
2348         dma_cap_set(DMA_SLAVE, cap);
2349
2350         cfg.dev_type = dma_spec->args[0];
2351         flags = dma_spec->args[2];
2352
2353         switch (D40_DT_FLAGS_MODE(flags)) {
2354         case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2355         case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2356         }
2357
2358         switch (D40_DT_FLAGS_DIR(flags)) {
2359         case 0:
2360                 cfg.dir = DMA_MEM_TO_DEV;
2361                 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2362                 break;
2363         case 1:
2364                 cfg.dir = DMA_DEV_TO_MEM;
2365                 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2366                 break;
2367         }
2368
2369         if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2370                 cfg.phy_channel = dma_spec->args[1];
2371                 cfg.use_fixed_channel = true;
2372         }
2373
2374         if (D40_DT_FLAGS_HIGH_PRIO(flags))
2375                 cfg.high_priority = true;
2376
2377         return dma_request_channel(cap, stedma40_filter, &cfg);
2378 }
2379
2380 /* DMA ENGINE functions */
2381 static int d40_alloc_chan_resources(struct dma_chan *chan)
2382 {
2383         int err;
2384         unsigned long flags;
2385         struct d40_chan *d40c =
2386                 container_of(chan, struct d40_chan, chan);
2387         bool is_free_phy;
2388         spin_lock_irqsave(&d40c->lock, flags);
2389
2390         dma_cookie_init(chan);
2391
2392         /* If no dma configuration is set use default configuration (memcpy) */
2393         if (!d40c->configured) {
2394                 err = d40_config_memcpy(d40c);
2395                 if (err) {
2396                         chan_err(d40c, "Failed to configure memcpy channel\n");
2397                         goto mark_last_busy;
2398                 }
2399         }
2400
2401         err = d40_allocate_channel(d40c, &is_free_phy);
2402         if (err) {
2403                 chan_err(d40c, "Failed to allocate channel\n");
2404                 d40c->configured = false;
2405                 goto mark_last_busy;
2406         }
2407
2408         pm_runtime_get_sync(d40c->base->dev);
2409
2410         d40_set_prio_realtime(d40c);
2411
2412         if (chan_is_logical(d40c)) {
2413                 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2414                         d40c->lcpa = d40c->base->lcpa_base +
2415                                 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2416                 else
2417                         d40c->lcpa = d40c->base->lcpa_base +
2418                                 d40c->dma_cfg.dev_type *
2419                                 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2420
2421                 /* Unmask the Global Interrupt Mask. */
2422                 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2423                 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2424         }
2425
2426         dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2427                  chan_is_logical(d40c) ? "logical" : "physical",
2428                  d40c->phy_chan->num,
2429                  d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2430
2431
2432         /*
2433          * Only write channel configuration to the DMA if the physical
2434          * resource is free. In case of multiple logical channels
2435          * on the same physical resource, only the first write is necessary.
2436          */
2437         if (is_free_phy)
2438                 d40_config_write(d40c);
2439  mark_last_busy:
2440         pm_runtime_mark_last_busy(d40c->base->dev);
2441         pm_runtime_put_autosuspend(d40c->base->dev);
2442         spin_unlock_irqrestore(&d40c->lock, flags);
2443         return err;
2444 }
2445
2446 static void d40_free_chan_resources(struct dma_chan *chan)
2447 {
2448         struct d40_chan *d40c =
2449                 container_of(chan, struct d40_chan, chan);
2450         int err;
2451         unsigned long flags;
2452
2453         if (d40c->phy_chan == NULL) {
2454                 chan_err(d40c, "Cannot free unallocated channel\n");
2455                 return;
2456         }
2457
2458         spin_lock_irqsave(&d40c->lock, flags);
2459
2460         err = d40_free_dma(d40c);
2461
2462         if (err)
2463                 chan_err(d40c, "Failed to free channel\n");
2464         spin_unlock_irqrestore(&d40c->lock, flags);
2465 }
2466
2467 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2468                                                        dma_addr_t dst,
2469                                                        dma_addr_t src,
2470                                                        size_t size,
2471                                                        unsigned long dma_flags)
2472 {
2473         struct scatterlist dst_sg;
2474         struct scatterlist src_sg;
2475
2476         sg_init_table(&dst_sg, 1);
2477         sg_init_table(&src_sg, 1);
2478
2479         sg_dma_address(&dst_sg) = dst;
2480         sg_dma_address(&src_sg) = src;
2481
2482         sg_dma_len(&dst_sg) = size;
2483         sg_dma_len(&src_sg) = size;
2484
2485         return d40_prep_sg(chan, &src_sg, &dst_sg, 1,
2486                            DMA_MEM_TO_MEM, dma_flags);
2487 }
2488
2489 static struct dma_async_tx_descriptor *
2490 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2491                   unsigned int sg_len, enum dma_transfer_direction direction,
2492                   unsigned long dma_flags, void *context)
2493 {
2494         if (!is_slave_direction(direction))
2495                 return NULL;
2496
2497         return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2498 }
2499
2500 static struct dma_async_tx_descriptor *
2501 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2502                      size_t buf_len, size_t period_len,
2503                      enum dma_transfer_direction direction, unsigned long flags)
2504 {
2505         unsigned int periods = buf_len / period_len;
2506         struct dma_async_tx_descriptor *txd;
2507         struct scatterlist *sg;
2508         int i;
2509
2510         sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2511         if (!sg)
2512                 return NULL;
2513
2514         for (i = 0; i < periods; i++) {
2515                 sg_dma_address(&sg[i]) = dma_addr;
2516                 sg_dma_len(&sg[i]) = period_len;
2517                 dma_addr += period_len;
2518         }
2519
2520         sg_chain(sg, periods + 1, sg);
2521
2522         txd = d40_prep_sg(chan, sg, sg, periods, direction,
2523                           DMA_PREP_INTERRUPT);
2524
2525         kfree(sg);
2526
2527         return txd;
2528 }
2529
2530 static enum dma_status d40_tx_status(struct dma_chan *chan,
2531                                      dma_cookie_t cookie,
2532                                      struct dma_tx_state *txstate)
2533 {
2534         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2535         enum dma_status ret;
2536
2537         if (d40c->phy_chan == NULL) {
2538                 chan_err(d40c, "Cannot read status of unallocated channel\n");
2539                 return -EINVAL;
2540         }
2541
2542         ret = dma_cookie_status(chan, cookie, txstate);
2543         if (ret != DMA_COMPLETE && txstate)
2544                 dma_set_residue(txstate, stedma40_residue(chan));
2545
2546         if (d40_is_paused(d40c))
2547                 ret = DMA_PAUSED;
2548
2549         return ret;
2550 }
2551
2552 static void d40_issue_pending(struct dma_chan *chan)
2553 {
2554         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2555         unsigned long flags;
2556
2557         if (d40c->phy_chan == NULL) {
2558                 chan_err(d40c, "Channel is not allocated!\n");
2559                 return;
2560         }
2561
2562         spin_lock_irqsave(&d40c->lock, flags);
2563
2564         list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2565
2566         /* Busy means that queued jobs are already being processed */
2567         if (!d40c->busy)
2568                 (void) d40_queue_start(d40c);
2569
2570         spin_unlock_irqrestore(&d40c->lock, flags);
2571 }
2572
2573 static int d40_terminate_all(struct dma_chan *chan)
2574 {
2575         unsigned long flags;
2576         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2577         int ret;
2578
2579         if (d40c->phy_chan == NULL) {
2580                 chan_err(d40c, "Channel is not allocated!\n");
2581                 return -EINVAL;
2582         }
2583
2584         spin_lock_irqsave(&d40c->lock, flags);
2585
2586         pm_runtime_get_sync(d40c->base->dev);
2587         ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2588         if (ret)
2589                 chan_err(d40c, "Failed to stop channel\n");
2590
2591         d40_term_all(d40c);
2592         pm_runtime_mark_last_busy(d40c->base->dev);
2593         pm_runtime_put_autosuspend(d40c->base->dev);
2594         if (d40c->busy) {
2595                 pm_runtime_mark_last_busy(d40c->base->dev);
2596                 pm_runtime_put_autosuspend(d40c->base->dev);
2597         }
2598         d40c->busy = false;
2599
2600         spin_unlock_irqrestore(&d40c->lock, flags);
2601         return 0;
2602 }
2603
2604 static int
2605 dma40_config_to_halfchannel(struct d40_chan *d40c,
2606                             struct stedma40_half_channel_info *info,
2607                             u32 maxburst)
2608 {
2609         int psize;
2610
2611         if (chan_is_logical(d40c)) {
2612                 if (maxburst >= 16)
2613                         psize = STEDMA40_PSIZE_LOG_16;
2614                 else if (maxburst >= 8)
2615                         psize = STEDMA40_PSIZE_LOG_8;
2616                 else if (maxburst >= 4)
2617                         psize = STEDMA40_PSIZE_LOG_4;
2618                 else
2619                         psize = STEDMA40_PSIZE_LOG_1;
2620         } else {
2621                 if (maxburst >= 16)
2622                         psize = STEDMA40_PSIZE_PHY_16;
2623                 else if (maxburst >= 8)
2624                         psize = STEDMA40_PSIZE_PHY_8;
2625                 else if (maxburst >= 4)
2626                         psize = STEDMA40_PSIZE_PHY_4;
2627                 else
2628                         psize = STEDMA40_PSIZE_PHY_1;
2629         }
2630
2631         info->psize = psize;
2632         info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2633
2634         return 0;
2635 }
2636
2637 /* Runtime reconfiguration extension */
2638 static int d40_set_runtime_config(struct dma_chan *chan,
2639                                   struct dma_slave_config *config)
2640 {
2641         struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2642         struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2643         enum dma_slave_buswidth src_addr_width, dst_addr_width;
2644         dma_addr_t config_addr;
2645         u32 src_maxburst, dst_maxburst;
2646         int ret;
2647
2648         if (d40c->phy_chan == NULL) {
2649                 chan_err(d40c, "Channel is not allocated!\n");
2650                 return -EINVAL;
2651         }
2652
2653         src_addr_width = config->src_addr_width;
2654         src_maxburst = config->src_maxburst;
2655         dst_addr_width = config->dst_addr_width;
2656         dst_maxburst = config->dst_maxburst;
2657
2658         if (config->direction == DMA_DEV_TO_MEM) {
2659                 config_addr = config->src_addr;
2660
2661                 if (cfg->dir != DMA_DEV_TO_MEM)
2662                         dev_dbg(d40c->base->dev,
2663                                 "channel was not configured for peripheral "
2664                                 "to memory transfer (%d) overriding\n",
2665                                 cfg->dir);
2666                 cfg->dir = DMA_DEV_TO_MEM;
2667
2668                 /* Configure the memory side */
2669                 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2670                         dst_addr_width = src_addr_width;
2671                 if (dst_maxburst == 0)
2672                         dst_maxburst = src_maxburst;
2673
2674         } else if (config->direction == DMA_MEM_TO_DEV) {
2675                 config_addr = config->dst_addr;
2676
2677                 if (cfg->dir != DMA_MEM_TO_DEV)
2678                         dev_dbg(d40c->base->dev,
2679                                 "channel was not configured for memory "
2680                                 "to peripheral transfer (%d) overriding\n",
2681                                 cfg->dir);
2682                 cfg->dir = DMA_MEM_TO_DEV;
2683
2684                 /* Configure the memory side */
2685                 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2686                         src_addr_width = dst_addr_width;
2687                 if (src_maxburst == 0)
2688                         src_maxburst = dst_maxburst;
2689         } else {
2690                 dev_err(d40c->base->dev,
2691                         "unrecognized channel direction %d\n",
2692                         config->direction);
2693                 return -EINVAL;
2694         }
2695
2696         if (config_addr <= 0) {
2697                 dev_err(d40c->base->dev, "no address supplied\n");
2698                 return -EINVAL;
2699         }
2700
2701         if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2702                 dev_err(d40c->base->dev,
2703                         "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2704                         src_maxburst,
2705                         src_addr_width,
2706                         dst_maxburst,
2707                         dst_addr_width);
2708                 return -EINVAL;
2709         }
2710
2711         if (src_maxburst > 16) {
2712                 src_maxburst = 16;
2713                 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2714         } else if (dst_maxburst > 16) {
2715                 dst_maxburst = 16;
2716                 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2717         }
2718
2719         /* Only valid widths are; 1, 2, 4 and 8. */
2720         if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2721             src_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
2722             dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2723             dst_addr_width >  DMA_SLAVE_BUSWIDTH_8_BYTES   ||
2724             !is_power_of_2(src_addr_width) ||
2725             !is_power_of_2(dst_addr_width))
2726                 return -EINVAL;
2727
2728         cfg->src_info.data_width = src_addr_width;
2729         cfg->dst_info.data_width = dst_addr_width;
2730
2731         ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2732                                           src_maxburst);
2733         if (ret)
2734                 return ret;
2735
2736         ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2737                                           dst_maxburst);
2738         if (ret)
2739                 return ret;
2740
2741         /* Fill in register values */
2742         if (chan_is_logical(d40c))
2743                 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2744         else
2745                 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
2746
2747         /* These settings will take precedence later */
2748         d40c->runtime_addr = config_addr;
2749         d40c->runtime_direction = config->direction;
2750         dev_dbg(d40c->base->dev,
2751                 "configured channel %s for %s, data width %d/%d, "
2752                 "maxburst %d/%d elements, LE, no flow control\n",
2753                 dma_chan_name(chan),
2754                 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2755                 src_addr_width, dst_addr_width,
2756                 src_maxburst, dst_maxburst);
2757
2758         return 0;
2759 }
2760
2761 /* Initialization functions */
2762
2763 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2764                                  struct d40_chan *chans, int offset,
2765                                  int num_chans)
2766 {
2767         int i = 0;
2768         struct d40_chan *d40c;
2769
2770         INIT_LIST_HEAD(&dma->channels);
2771
2772         for (i = offset; i < offset + num_chans; i++) {
2773                 d40c = &chans[i];
2774                 d40c->base = base;
2775                 d40c->chan.device = dma;
2776
2777                 spin_lock_init(&d40c->lock);
2778
2779                 d40c->log_num = D40_PHY_CHAN;
2780
2781                 INIT_LIST_HEAD(&d40c->done);
2782                 INIT_LIST_HEAD(&d40c->active);
2783                 INIT_LIST_HEAD(&d40c->queue);
2784                 INIT_LIST_HEAD(&d40c->pending_queue);
2785                 INIT_LIST_HEAD(&d40c->client);
2786                 INIT_LIST_HEAD(&d40c->prepare_queue);
2787
2788                 tasklet_init(&d40c->tasklet, dma_tasklet,
2789                              (unsigned long) d40c);
2790
2791                 list_add_tail(&d40c->chan.device_node,
2792                               &dma->channels);
2793         }
2794 }
2795
2796 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2797 {
2798         if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) {
2799                 dev->device_prep_slave_sg = d40_prep_slave_sg;
2800                 dev->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2801         }
2802
2803         if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2804                 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2805                 dev->directions = BIT(DMA_MEM_TO_MEM);
2806                 /*
2807                  * This controller can only access address at even
2808                  * 32bit boundaries, i.e. 2^2
2809                  */
2810                 dev->copy_align = DMAENGINE_ALIGN_4_BYTES;
2811         }
2812
2813         if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2814                 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2815
2816         dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2817         dev->device_free_chan_resources = d40_free_chan_resources;
2818         dev->device_issue_pending = d40_issue_pending;
2819         dev->device_tx_status = d40_tx_status;
2820         dev->device_config = d40_set_runtime_config;
2821         dev->device_pause = d40_pause;
2822         dev->device_resume = d40_resume;
2823         dev->device_terminate_all = d40_terminate_all;
2824         dev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2825         dev->dev = base->dev;
2826 }
2827
2828 static int __init d40_dmaengine_init(struct d40_base *base,
2829                                      int num_reserved_chans)
2830 {
2831         int err ;
2832
2833         d40_chan_init(base, &base->dma_slave, base->log_chans,
2834                       0, base->num_log_chans);
2835
2836         dma_cap_zero(base->dma_slave.cap_mask);
2837         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2838         dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2839
2840         d40_ops_init(base, &base->dma_slave);
2841
2842         err = dmaenginem_async_device_register(&base->dma_slave);
2843
2844         if (err) {
2845                 d40_err(base->dev, "Failed to register slave channels\n");
2846                 goto exit;
2847         }
2848
2849         d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2850                       base->num_log_chans, base->num_memcpy_chans);
2851
2852         dma_cap_zero(base->dma_memcpy.cap_mask);
2853         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2854
2855         d40_ops_init(base, &base->dma_memcpy);
2856
2857         err = dmaenginem_async_device_register(&base->dma_memcpy);
2858
2859         if (err) {
2860                 d40_err(base->dev,
2861                         "Failed to register memcpy only channels\n");
2862                 goto exit;
2863         }
2864
2865         d40_chan_init(base, &base->dma_both, base->phy_chans,
2866                       0, num_reserved_chans);
2867
2868         dma_cap_zero(base->dma_both.cap_mask);
2869         dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2870         dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2871         dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2872
2873         d40_ops_init(base, &base->dma_both);
2874         err = dmaenginem_async_device_register(&base->dma_both);
2875
2876         if (err) {
2877                 d40_err(base->dev,
2878                         "Failed to register logical and physical capable channels\n");
2879                 goto exit;
2880         }
2881         return 0;
2882  exit:
2883         return err;
2884 }
2885
2886 /* Suspend resume functionality */
2887 #ifdef CONFIG_PM_SLEEP
2888 static int dma40_suspend(struct device *dev)
2889 {
2890         struct d40_base *base = dev_get_drvdata(dev);
2891         int ret;
2892
2893         ret = pm_runtime_force_suspend(dev);
2894         if (ret)
2895                 return ret;
2896
2897         if (base->lcpa_regulator)
2898                 ret = regulator_disable(base->lcpa_regulator);
2899         return ret;
2900 }
2901
2902 static int dma40_resume(struct device *dev)
2903 {
2904         struct d40_base *base = dev_get_drvdata(dev);
2905         int ret = 0;
2906
2907         if (base->lcpa_regulator) {
2908                 ret = regulator_enable(base->lcpa_regulator);
2909                 if (ret)
2910                         return ret;
2911         }
2912
2913         return pm_runtime_force_resume(dev);
2914 }
2915 #endif
2916
2917 #ifdef CONFIG_PM
2918 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
2919                          u32 *regaddr, int num, bool save)
2920 {
2921         int i;
2922
2923         for (i = 0; i < num; i++) {
2924                 void __iomem *addr = baseaddr + regaddr[i];
2925
2926                 if (save)
2927                         backup[i] = readl_relaxed(addr);
2928                 else
2929                         writel_relaxed(backup[i], addr);
2930         }
2931 }
2932
2933 static void d40_save_restore_registers(struct d40_base *base, bool save)
2934 {
2935         int i;
2936
2937         /* Save/Restore channel specific registers */
2938         for (i = 0; i < base->num_phy_chans; i++) {
2939                 void __iomem *addr;
2940                 int idx;
2941
2942                 if (base->phy_res[i].reserved)
2943                         continue;
2944
2945                 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
2946                 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
2947
2948                 dma40_backup(addr, &base->reg_val_backup_chan[idx],
2949                              d40_backup_regs_chan,
2950                              ARRAY_SIZE(d40_backup_regs_chan),
2951                              save);
2952         }
2953
2954         /* Save/Restore global registers */
2955         dma40_backup(base->virtbase, base->reg_val_backup,
2956                      d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
2957                      save);
2958
2959         /* Save/Restore registers only existing on dma40 v3 and later */
2960         if (base->gen_dmac.backup)
2961                 dma40_backup(base->virtbase, base->reg_val_backup_v4,
2962                              base->gen_dmac.backup,
2963                         base->gen_dmac.backup_size,
2964                         save);
2965 }
2966
2967 static int dma40_runtime_suspend(struct device *dev)
2968 {
2969         struct d40_base *base = dev_get_drvdata(dev);
2970
2971         d40_save_restore_registers(base, true);
2972
2973         /* Don't disable/enable clocks for v1 due to HW bugs */
2974         if (base->rev != 1)
2975                 writel_relaxed(base->gcc_pwr_off_mask,
2976                                base->virtbase + D40_DREG_GCC);
2977
2978         return 0;
2979 }
2980
2981 static int dma40_runtime_resume(struct device *dev)
2982 {
2983         struct d40_base *base = dev_get_drvdata(dev);
2984
2985         d40_save_restore_registers(base, false);
2986
2987         writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
2988                        base->virtbase + D40_DREG_GCC);
2989         return 0;
2990 }
2991 #endif
2992
2993 static const struct dev_pm_ops dma40_pm_ops = {
2994         SET_LATE_SYSTEM_SLEEP_PM_OPS(dma40_suspend, dma40_resume)
2995         SET_RUNTIME_PM_OPS(dma40_runtime_suspend,
2996                                 dma40_runtime_resume,
2997                                 NULL)
2998 };
2999
3000 /* Initialization functions. */
3001
3002 static int __init d40_phy_res_init(struct d40_base *base)
3003 {
3004         int i;
3005         int num_phy_chans_avail = 0;
3006         u32 val[2];
3007         int odd_even_bit = -2;
3008         int gcc = D40_DREG_GCC_ENA;
3009
3010         val[0] = readl(base->virtbase + D40_DREG_PRSME);
3011         val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3012
3013         for (i = 0; i < base->num_phy_chans; i++) {
3014                 base->phy_res[i].num = i;
3015                 odd_even_bit += 2 * ((i % 2) == 0);
3016                 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3017                         /* Mark security only channels as occupied */
3018                         base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3019                         base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
3020                         base->phy_res[i].reserved = true;
3021                         gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3022                                                        D40_DREG_GCC_SRC);
3023                         gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3024                                                        D40_DREG_GCC_DST);
3025
3026
3027                 } else {
3028                         base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3029                         base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
3030                         base->phy_res[i].reserved = false;
3031                         num_phy_chans_avail++;
3032                 }
3033                 spin_lock_init(&base->phy_res[i].lock);
3034         }
3035
3036         /* Mark disabled channels as occupied */
3037         for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
3038                 int chan = base->plat_data->disabled_channels[i];
3039
3040                 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3041                 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
3042                 base->phy_res[chan].reserved = true;
3043                 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3044                                                D40_DREG_GCC_SRC);
3045                 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3046                                                D40_DREG_GCC_DST);
3047                 num_phy_chans_avail--;
3048         }
3049
3050         /* Mark soft_lli channels */
3051         for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3052                 int chan = base->plat_data->soft_lli_chans[i];
3053
3054                 base->phy_res[chan].use_soft_lli = true;
3055         }
3056
3057         dev_info(base->dev, "%d of %d physical DMA channels available\n",
3058                  num_phy_chans_avail, base->num_phy_chans);
3059
3060         /* Verify settings extended vs standard */
3061         val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3062
3063         for (i = 0; i < base->num_phy_chans; i++) {
3064
3065                 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3066                     (val[0] & 0x3) != 1)
3067                         dev_info(base->dev,
3068                                  "[%s] INFO: channel %d is misconfigured (%d)\n",
3069                                  __func__, i, val[0] & 0x3);
3070
3071                 val[0] = val[0] >> 2;
3072         }
3073
3074         /*
3075          * To keep things simple, Enable all clocks initially.
3076          * The clocks will get managed later post channel allocation.
3077          * The clocks for the event lines on which reserved channels exists
3078          * are not managed here.
3079          */
3080         writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3081         base->gcc_pwr_off_mask = gcc;
3082
3083         return num_phy_chans_avail;
3084 }
3085
3086 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3087 {
3088         struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3089         struct clk *clk;
3090         void __iomem *virtbase;
3091         struct resource *res;
3092         struct d40_base *base;
3093         int num_log_chans;
3094         int num_phy_chans;
3095         int num_memcpy_chans;
3096         int clk_ret = -EINVAL;
3097         int i;
3098         u32 pid;
3099         u32 cid;
3100         u8 rev;
3101
3102         clk = clk_get(&pdev->dev, NULL);
3103         if (IS_ERR(clk)) {
3104                 d40_err(&pdev->dev, "No matching clock found\n");
3105                 goto check_prepare_enabled;
3106         }
3107
3108         clk_ret = clk_prepare_enable(clk);
3109         if (clk_ret) {
3110                 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3111                 goto disable_unprepare;
3112         }
3113
3114         /* Get IO for DMAC base address */
3115         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3116         if (!res)
3117                 goto disable_unprepare;
3118
3119         if (request_mem_region(res->start, resource_size(res),
3120                                D40_NAME " I/O base") == NULL)
3121                 goto release_region;
3122
3123         virtbase = ioremap(res->start, resource_size(res));
3124         if (!virtbase)
3125                 goto release_region;
3126
3127         /* This is just a regular AMBA PrimeCell ID actually */
3128         for (pid = 0, i = 0; i < 4; i++)
3129                 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3130                         & 255) << (i * 8);
3131         for (cid = 0, i = 0; i < 4; i++)
3132                 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3133                         & 255) << (i * 8);
3134
3135         if (cid != AMBA_CID) {
3136                 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3137                 goto unmap_io;
3138         }
3139         if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
3140                 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
3141                         AMBA_MANF_BITS(pid),
3142                         AMBA_VENDOR_ST);
3143                 goto unmap_io;
3144         }
3145         /*
3146          * HW revision:
3147          * DB8500ed has revision 0
3148          * ? has revision 1
3149          * DB8500v1 has revision 2
3150          * DB8500v2 has revision 3
3151          * AP9540v1 has revision 4
3152          * DB8540v1 has revision 4
3153          */
3154         rev = AMBA_REV_BITS(pid);
3155         if (rev < 2) {
3156                 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3157                 goto unmap_io;
3158         }
3159
3160         /* The number of physical channels on this HW */
3161         if (plat_data->num_of_phy_chans)
3162                 num_phy_chans = plat_data->num_of_phy_chans;
3163         else
3164                 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3165
3166         /* The number of channels used for memcpy */
3167         if (plat_data->num_of_memcpy_chans)
3168                 num_memcpy_chans = plat_data->num_of_memcpy_chans;
3169         else
3170                 num_memcpy_chans = ARRAY_SIZE(dma40_memcpy_channels);
3171
3172         num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3173
3174         dev_info(&pdev->dev,
3175                  "hardware rev: %d @ %pa with %d physical and %d logical channels\n",
3176                  rev, &res->start, num_phy_chans, num_log_chans);
3177
3178         base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3179                        (num_phy_chans + num_log_chans + num_memcpy_chans) *
3180                        sizeof(struct d40_chan), GFP_KERNEL);
3181
3182         if (base == NULL)
3183                 goto unmap_io;
3184
3185         base->rev = rev;
3186         base->clk = clk;
3187         base->num_memcpy_chans = num_memcpy_chans;
3188         base->num_phy_chans = num_phy_chans;
3189         base->num_log_chans = num_log_chans;
3190         base->phy_start = res->start;
3191         base->phy_size = resource_size(res);
3192         base->virtbase = virtbase;
3193         base->plat_data = plat_data;
3194         base->dev = &pdev->dev;
3195         base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3196         base->log_chans = &base->phy_chans[num_phy_chans];
3197
3198         if (base->plat_data->num_of_phy_chans == 14) {
3199                 base->gen_dmac.backup = d40_backup_regs_v4b;
3200                 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3201                 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3202                 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3203                 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3204                 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3205                 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3206                 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3207                 base->gen_dmac.il = il_v4b;
3208                 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3209                 base->gen_dmac.init_reg = dma_init_reg_v4b;
3210                 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3211         } else {
3212                 if (base->rev >= 3) {
3213                         base->gen_dmac.backup = d40_backup_regs_v4a;
3214                         base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3215                 }
3216                 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3217                 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3218                 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3219                 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3220                 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3221                 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3222                 base->gen_dmac.il = il_v4a;
3223                 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3224                 base->gen_dmac.init_reg = dma_init_reg_v4a;
3225                 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3226         }
3227
3228         base->phy_res = kcalloc(num_phy_chans,
3229                                 sizeof(*base->phy_res),
3230                                 GFP_KERNEL);
3231         if (!base->phy_res)
3232                 goto free_base;
3233
3234         base->lookup_phy_chans = kcalloc(num_phy_chans,
3235                                          sizeof(*base->lookup_phy_chans),
3236                                          GFP_KERNEL);
3237         if (!base->lookup_phy_chans)
3238                 goto free_phy_res;
3239
3240         base->lookup_log_chans = kcalloc(num_log_chans,
3241                                          sizeof(*base->lookup_log_chans),
3242                                          GFP_KERNEL);
3243         if (!base->lookup_log_chans)
3244                 goto free_phy_chans;
3245
3246         base->reg_val_backup_chan = kmalloc_array(base->num_phy_chans,
3247                                                   sizeof(d40_backup_regs_chan),
3248                                                   GFP_KERNEL);
3249         if (!base->reg_val_backup_chan)
3250                 goto free_log_chans;
3251
3252         base->lcla_pool.alloc_map = kcalloc(num_phy_chans
3253                                             * D40_LCLA_LINK_PER_EVENT_GRP,
3254                                             sizeof(*base->lcla_pool.alloc_map),
3255                                             GFP_KERNEL);
3256         if (!base->lcla_pool.alloc_map)
3257                 goto free_backup_chan;
3258
3259         base->regs_interrupt = kmalloc_array(base->gen_dmac.il_size,
3260                                              sizeof(*base->regs_interrupt),
3261                                              GFP_KERNEL);
3262         if (!base->regs_interrupt)
3263                 goto free_map;
3264
3265         base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3266                                             0, SLAB_HWCACHE_ALIGN,
3267                                             NULL);
3268         if (base->desc_slab == NULL)
3269                 goto free_regs;
3270
3271
3272         return base;
3273  free_regs:
3274         kfree(base->regs_interrupt);
3275  free_map:
3276         kfree(base->lcla_pool.alloc_map);
3277  free_backup_chan:
3278         kfree(base->reg_val_backup_chan);
3279  free_log_chans:
3280         kfree(base->lookup_log_chans);
3281  free_phy_chans:
3282         kfree(base->lookup_phy_chans);
3283  free_phy_res:
3284         kfree(base->phy_res);
3285  free_base:
3286         kfree(base);
3287  unmap_io:
3288         iounmap(virtbase);
3289  release_region:
3290         release_mem_region(res->start, resource_size(res));
3291  check_prepare_enabled:
3292         if (!clk_ret)
3293  disable_unprepare:
3294                 clk_disable_unprepare(clk);
3295         if (!IS_ERR(clk))
3296                 clk_put(clk);
3297         return NULL;
3298 }
3299
3300 static void __init d40_hw_init(struct d40_base *base)
3301 {
3302
3303         int i;
3304         u32 prmseo[2] = {0, 0};
3305         u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3306         u32 pcmis = 0;
3307         u32 pcicr = 0;
3308         struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3309         u32 reg_size = base->gen_dmac.init_reg_size;
3310
3311         for (i = 0; i < reg_size; i++)
3312                 writel(dma_init_reg[i].val,
3313                        base->virtbase + dma_init_reg[i].reg);
3314
3315         /* Configure all our dma channels to default settings */
3316         for (i = 0; i < base->num_phy_chans; i++) {
3317
3318                 activeo[i % 2] = activeo[i % 2] << 2;
3319
3320                 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3321                     == D40_ALLOC_PHY) {
3322                         activeo[i % 2] |= 3;
3323                         continue;
3324                 }
3325
3326                 /* Enable interrupt # */
3327                 pcmis = (pcmis << 1) | 1;
3328
3329                 /* Clear interrupt # */
3330                 pcicr = (pcicr << 1) | 1;
3331
3332                 /* Set channel to physical mode */
3333                 prmseo[i % 2] = prmseo[i % 2] << 2;
3334                 prmseo[i % 2] |= 1;
3335
3336         }
3337
3338         writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3339         writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3340         writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3341         writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3342
3343         /* Write which interrupt to enable */
3344         writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3345
3346         /* Write which interrupt to clear */
3347         writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3348
3349         /* These are __initdata and cannot be accessed after init */
3350         base->gen_dmac.init_reg = NULL;
3351         base->gen_dmac.init_reg_size = 0;
3352 }
3353
3354 static int __init d40_lcla_allocate(struct d40_base *base)
3355 {
3356         struct d40_lcla_pool *pool = &base->lcla_pool;
3357         unsigned long *page_list;
3358         int i, j;
3359         int ret;
3360
3361         /*
3362          * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3363          * To full fill this hardware requirement without wasting 256 kb
3364          * we allocate pages until we get an aligned one.
3365          */
3366         page_list = kmalloc_array(MAX_LCLA_ALLOC_ATTEMPTS,
3367                                   sizeof(*page_list),
3368                                   GFP_KERNEL);
3369         if (!page_list)
3370                 return -ENOMEM;
3371
3372         /* Calculating how many pages that are required */
3373         base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3374
3375         for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3376                 page_list[i] = __get_free_pages(GFP_KERNEL,
3377                                                 base->lcla_pool.pages);
3378                 if (!page_list[i]) {
3379
3380                         d40_err(base->dev, "Failed to allocate %d pages.\n",
3381                                 base->lcla_pool.pages);
3382                         ret = -ENOMEM;
3383
3384                         for (j = 0; j < i; j++)
3385                                 free_pages(page_list[j], base->lcla_pool.pages);
3386                         goto free_page_list;
3387                 }
3388
3389                 if ((virt_to_phys((void *)page_list[i]) &
3390                      (LCLA_ALIGNMENT - 1)) == 0)
3391                         break;
3392         }
3393
3394         for (j = 0; j < i; j++)
3395                 free_pages(page_list[j], base->lcla_pool.pages);
3396
3397         if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3398                 base->lcla_pool.base = (void *)page_list[i];
3399         } else {
3400                 /*
3401                  * After many attempts and no succees with finding the correct
3402                  * alignment, try with allocating a big buffer.
3403                  */
3404                 dev_warn(base->dev,
3405                          "[%s] Failed to get %d pages @ 18 bit align.\n",
3406                          __func__, base->lcla_pool.pages);
3407                 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3408                                                          base->num_phy_chans +
3409                                                          LCLA_ALIGNMENT,
3410                                                          GFP_KERNEL);
3411                 if (!base->lcla_pool.base_unaligned) {
3412                         ret = -ENOMEM;
3413                         goto free_page_list;
3414                 }
3415
3416                 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3417                                                  LCLA_ALIGNMENT);
3418         }
3419
3420         pool->dma_addr = dma_map_single(base->dev, pool->base,
3421                                         SZ_1K * base->num_phy_chans,
3422                                         DMA_TO_DEVICE);
3423         if (dma_mapping_error(base->dev, pool->dma_addr)) {
3424                 pool->dma_addr = 0;
3425                 ret = -ENOMEM;
3426                 goto free_page_list;
3427         }
3428
3429         writel(virt_to_phys(base->lcla_pool.base),
3430                base->virtbase + D40_DREG_LCLA);
3431         ret = 0;
3432  free_page_list:
3433         kfree(page_list);
3434         return ret;
3435 }
3436
3437 static int __init d40_of_probe(struct platform_device *pdev,
3438                                struct device_node *np)
3439 {
3440         struct stedma40_platform_data *pdata;
3441         int num_phy = 0, num_memcpy = 0, num_disabled = 0;
3442         const __be32 *list;
3443
3444         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
3445         if (!pdata)
3446                 return -ENOMEM;
3447
3448         /* If absent this value will be obtained from h/w. */
3449         of_property_read_u32(np, "dma-channels", &num_phy);
3450         if (num_phy > 0)
3451                 pdata->num_of_phy_chans = num_phy;
3452
3453         list = of_get_property(np, "memcpy-channels", &num_memcpy);
3454         num_memcpy /= sizeof(*list);
3455
3456         if (num_memcpy > D40_MEMCPY_MAX_CHANS || num_memcpy <= 0) {
3457                 d40_err(&pdev->dev,
3458                         "Invalid number of memcpy channels specified (%d)\n",
3459                         num_memcpy);
3460                 return -EINVAL;
3461         }
3462         pdata->num_of_memcpy_chans = num_memcpy;
3463
3464         of_property_read_u32_array(np, "memcpy-channels",
3465                                    dma40_memcpy_channels,
3466                                    num_memcpy);
3467
3468         list = of_get_property(np, "disabled-channels", &num_disabled);
3469         num_disabled /= sizeof(*list);
3470
3471         if (num_disabled >= STEDMA40_MAX_PHYS || num_disabled < 0) {
3472                 d40_err(&pdev->dev,
3473                         "Invalid number of disabled channels specified (%d)\n",
3474                         num_disabled);
3475                 return -EINVAL;
3476         }
3477
3478         of_property_read_u32_array(np, "disabled-channels",
3479                                    pdata->disabled_channels,
3480                                    num_disabled);
3481         pdata->disabled_channels[num_disabled] = -1;
3482
3483         pdev->dev.platform_data = pdata;
3484
3485         return 0;
3486 }
3487
3488 static int __init d40_probe(struct platform_device *pdev)
3489 {
3490         struct stedma40_platform_data *plat_data = dev_get_platdata(&pdev->dev);
3491         struct device_node *np = pdev->dev.of_node;
3492         int ret = -ENOENT;
3493         struct d40_base *base;
3494         struct resource *res;
3495         int num_reserved_chans;
3496         u32 val;
3497
3498         if (!plat_data) {
3499                 if (np) {
3500                         if (d40_of_probe(pdev, np)) {
3501                                 ret = -ENOMEM;
3502                                 goto report_failure;
3503                         }
3504                 } else {
3505                         d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3506                         goto report_failure;
3507                 }
3508         }
3509
3510         base = d40_hw_detect_init(pdev);
3511         if (!base)
3512                 goto report_failure;
3513
3514         num_reserved_chans = d40_phy_res_init(base);
3515
3516         platform_set_drvdata(pdev, base);
3517
3518         spin_lock_init(&base->interrupt_lock);
3519         spin_lock_init(&base->execmd_lock);
3520
3521         /* Get IO for logical channel parameter address */
3522         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3523         if (!res) {
3524                 ret = -ENOENT;
3525                 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3526                 goto destroy_cache;
3527         }
3528         base->lcpa_size = resource_size(res);
3529         base->phy_lcpa = res->start;
3530
3531         if (request_mem_region(res->start, resource_size(res),
3532                                D40_NAME " I/O lcpa") == NULL) {
3533                 ret = -EBUSY;
3534                 d40_err(&pdev->dev, "Failed to request LCPA region %pR\n", res);
3535                 goto destroy_cache;
3536         }
3537
3538         /* We make use of ESRAM memory for this. */
3539         val = readl(base->virtbase + D40_DREG_LCPA);
3540         if (res->start != val && val != 0) {
3541                 dev_warn(&pdev->dev,
3542                          "[%s] Mismatch LCPA dma 0x%x, def %pa\n",
3543                          __func__, val, &res->start);
3544         } else
3545                 writel(res->start, base->virtbase + D40_DREG_LCPA);
3546
3547         base->lcpa_base = ioremap(res->start, resource_size(res));
3548         if (!base->lcpa_base) {
3549                 ret = -ENOMEM;
3550                 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3551                 goto destroy_cache;
3552         }
3553         /* If lcla has to be located in ESRAM we don't need to allocate */
3554         if (base->plat_data->use_esram_lcla) {
3555                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3556                                                         "lcla_esram");
3557                 if (!res) {
3558                         ret = -ENOENT;
3559                         d40_err(&pdev->dev,
3560                                 "No \"lcla_esram\" memory resource\n");
3561                         goto destroy_cache;
3562                 }
3563                 base->lcla_pool.base = ioremap(res->start,
3564                                                 resource_size(res));
3565                 if (!base->lcla_pool.base) {
3566                         ret = -ENOMEM;
3567                         d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3568                         goto destroy_cache;
3569                 }
3570                 writel(res->start, base->virtbase + D40_DREG_LCLA);
3571
3572         } else {
3573                 ret = d40_lcla_allocate(base);
3574                 if (ret) {
3575                         d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3576                         goto destroy_cache;
3577                 }
3578         }
3579
3580         spin_lock_init(&base->lcla_pool.lock);
3581
3582         base->irq = platform_get_irq(pdev, 0);
3583
3584         ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3585         if (ret) {
3586                 d40_err(&pdev->dev, "No IRQ defined\n");
3587                 goto destroy_cache;
3588         }
3589
3590         if (base->plat_data->use_esram_lcla) {
3591
3592                 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3593                 if (IS_ERR(base->lcpa_regulator)) {
3594                         d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3595                         ret = PTR_ERR(base->lcpa_regulator);
3596                         base->lcpa_regulator = NULL;
3597                         goto destroy_cache;
3598                 }
3599
3600                 ret = regulator_enable(base->lcpa_regulator);
3601                 if (ret) {
3602                         d40_err(&pdev->dev,
3603                                 "Failed to enable lcpa_regulator\n");
3604                         regulator_put(base->lcpa_regulator);
3605                         base->lcpa_regulator = NULL;
3606                         goto destroy_cache;
3607                 }
3608         }
3609
3610         writel_relaxed(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3611
3612         pm_runtime_irq_safe(base->dev);
3613         pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3614         pm_runtime_use_autosuspend(base->dev);
3615         pm_runtime_mark_last_busy(base->dev);
3616         pm_runtime_set_active(base->dev);
3617         pm_runtime_enable(base->dev);
3618
3619         ret = d40_dmaengine_init(base, num_reserved_chans);
3620         if (ret)
3621                 goto destroy_cache;
3622
3623         base->dev->dma_parms = &base->dma_parms;
3624         ret = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3625         if (ret) {
3626                 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3627                 goto destroy_cache;
3628         }
3629
3630         d40_hw_init(base);
3631
3632         if (np) {
3633                 ret = of_dma_controller_register(np, d40_xlate, NULL);
3634                 if (ret)
3635                         dev_err(&pdev->dev,
3636                                 "could not register of_dma_controller\n");
3637         }
3638
3639         dev_info(base->dev, "initialized\n");
3640         return 0;
3641  destroy_cache:
3642         kmem_cache_destroy(base->desc_slab);
3643         if (base->virtbase)
3644                 iounmap(base->virtbase);
3645
3646         if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3647                 iounmap(base->lcla_pool.base);
3648                 base->lcla_pool.base = NULL;
3649         }
3650
3651         if (base->lcla_pool.dma_addr)
3652                 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3653                                  SZ_1K * base->num_phy_chans,
3654                                  DMA_TO_DEVICE);
3655
3656         if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3657                 free_pages((unsigned long)base->lcla_pool.base,
3658                            base->lcla_pool.pages);
3659
3660         kfree(base->lcla_pool.base_unaligned);
3661
3662         if (base->phy_lcpa)
3663                 release_mem_region(base->phy_lcpa,
3664                                    base->lcpa_size);
3665         if (base->phy_start)
3666                 release_mem_region(base->phy_start,
3667                                    base->phy_size);
3668         if (base->clk) {
3669                 clk_disable_unprepare(base->clk);
3670                 clk_put(base->clk);
3671         }
3672
3673         if (base->lcpa_regulator) {
3674                 regulator_disable(base->lcpa_regulator);
3675                 regulator_put(base->lcpa_regulator);
3676         }
3677
3678         kfree(base->lcla_pool.alloc_map);
3679         kfree(base->lookup_log_chans);
3680         kfree(base->lookup_phy_chans);
3681         kfree(base->phy_res);
3682         kfree(base);
3683  report_failure:
3684         d40_err(&pdev->dev, "probe failed\n");
3685         return ret;
3686 }
3687
3688 static const struct of_device_id d40_match[] = {
3689         { .compatible = "stericsson,dma40", },
3690         {}
3691 };
3692
3693 static struct platform_driver d40_driver = {
3694         .driver = {
3695                 .name  = D40_NAME,
3696                 .pm = &dma40_pm_ops,
3697                 .of_match_table = d40_match,
3698         },
3699 };
3700
3701 static int __init stedma40_init(void)
3702 {
3703         return platform_driver_probe(&d40_driver, d40_probe);
3704 }
3705 subsys_initcall(stedma40_init);