drivers/gpu/drm/i915/display/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <[email protected]>
  25  *   Jani Nikula <[email protected]>
  26  */
  27
  28 #include <drm/display/drm_dsc_helper.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_fixed.h>
  31 #include <drm/drm_mipi_dsi.h>
  32
  33 #include "i915_reg.h"
  34 #include "icl_dsi.h"
  35 #include "icl_dsi_regs.h"
  36 #include "intel_atomic.h"
  37 #include "intel_backlight.h"
  38 #include "intel_backlight_regs.h"
  39 #include "intel_combo_phy.h"
  40 #include "intel_combo_phy_regs.h"
  41 #include "intel_connector.h"
  42 #include "intel_crtc.h"
  43 #include "intel_ddi.h"
  44 #include "intel_de.h"
  45 #include "intel_dsi.h"
  46 #include "intel_dsi_vbt.h"
  47 #include "intel_panel.h"
  48 #include "intel_vdsc.h"
  49 #include "intel_vdsc_regs.h"
  50 #include "skl_scaler.h"
  51 #include "skl_universal_plane.h"
  52
  53 static int header_credits_available(struct drm_i915_private *dev_priv,
  54                                     enum transcoder dsi_trans)
  55 {
  56         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  57                 >> FREE_HEADER_CREDIT_SHIFT;
  58 }
  59
  60 static int payload_credits_available(struct drm_i915_private *dev_priv,
  61                                      enum transcoder dsi_trans)
  62 {
  63         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  64                 >> FREE_PLOAD_CREDIT_SHIFT;
  65 }
  66
  67 static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
  68                                     enum transcoder dsi_trans, int hdr_credit)
  69 {
  70         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  71                         hdr_credit, 100)) {
  72                 drm_err(&dev_priv->drm, "DSI header credits not released\n");
  73                 return false;
  74         }
  75
  76         return true;
  77 }
  78
  79 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
  80                                      enum transcoder dsi_trans, int payld_credit)
  81 {
  82         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  83                         payld_credit, 100)) {
  84                 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
  85                 return false;
  86         }
  87
  88         return true;
  89 }
  90
  91 static enum transcoder dsi_port_to_transcoder(enum port port)
  92 {
  93         if (port == PORT_A)
  94                 return TRANSCODER_DSI_0;
  95         else
  96                 return TRANSCODER_DSI_1;
  97 }
  98
  99 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
 100 {
 101         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 102         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 103         struct mipi_dsi_device *dsi;
 104         enum port port;
 105         enum transcoder dsi_trans;
 106         int ret;
 107
 108         /* wait for header/payload credits to be released */
 109         for_each_dsi_port(port, intel_dsi->ports) {
 110                 dsi_trans = dsi_port_to_transcoder(port);
 111                 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
 112                 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
 113         }
 114
 115         /* send nop DCS command */
 116         for_each_dsi_port(port, intel_dsi->ports) {
 117                 dsi = intel_dsi->dsi_hosts[port]->device;
 118                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
 119                 dsi->channel = 0;
 120                 ret = mipi_dsi_dcs_nop(dsi);
 121                 if (ret < 0)
 122                         drm_err(&dev_priv->drm,
 123                                 "error sending DCS NOP command\n");
 124         }
 125
 126         /* wait for header credits to be released */
 127         for_each_dsi_port(port, intel_dsi->ports) {
 128                 dsi_trans = dsi_port_to_transcoder(port);
 129                 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
 130         }
 131
 132         /* wait for LP TX in progress bit to be cleared */
 133         for_each_dsi_port(port, intel_dsi->ports) {
 134                 dsi_trans = dsi_port_to_transcoder(port);
 135                 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
 136                                   LPTX_IN_PROGRESS), 20))
 137                         drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
 138         }
 139 }
 140
 141 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 142                               const struct mipi_dsi_packet *packet)
 143 {
 144         struct intel_dsi *intel_dsi = host->intel_dsi;
 145         struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 146         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 147         const u8 *data = packet->payload;
 148         u32 len = packet->payload_length;
 149         int i, j;
 150
 151         /* payload queue can accept *256 bytes*, check limit */
 152         if (len > MAX_PLOAD_CREDIT * 4) {
 153                 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
 154                 return -EINVAL;
 155         }
 156
 157         for (i = 0; i < len; i += 4) {
 158                 u32 tmp = 0;
 159
 160                 if (!wait_for_payload_credits(i915, dsi_trans, 1))
 161                         return -EBUSY;
 162
 163                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 164                         tmp |= *data++ << 8 * j;
 165
 166                 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
 167         }
 168
 169         return 0;
 170 }
 171
 172 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 173                             const struct mipi_dsi_packet *packet,
 174                             bool enable_lpdt)
 175 {
 176         struct intel_dsi *intel_dsi = host->intel_dsi;
 177         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 178         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 179         u32 tmp;
 180
 181         if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
 182                 return -EBUSY;
 183
 184         tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
 185
 186         if (packet->payload)
 187                 tmp |= PAYLOAD_PRESENT;
 188         else
 189                 tmp &= ~PAYLOAD_PRESENT;
 190
 191         tmp &= ~VBLANK_FENCE;
 192
 193         if (enable_lpdt)
 194                 tmp |= LP_DATA_TRANSFER;
 195         else
 196                 tmp &= ~LP_DATA_TRANSFER;
 197
 198         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 199         tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
 200         tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
 201         tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
 202         tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
 203         intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
 204
 205         return 0;
 206 }
 207
 208 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
 209 {
 210         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 211         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 212         u32 mode_flags;
 213         enum port port;
 214
 215         mode_flags = crtc_state->mode_flags;
 216
 217         /*
 218          * case 1 also covers dual link
 219          * In case of dual link, frame update should be set on
 220          * DSI_0
 221          */
 222         if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
 223                 port = PORT_A;
 224         else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
 225                 port = PORT_B;
 226         else
 227                 return;
 228
 229         intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
 230 }
 231
 232 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 233 {
 234         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 235         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 236         enum phy phy;
 237         u32 tmp, mask, val;
 238         int lane;
 239
 240         for_each_dsi_phy(phy, intel_dsi->phys) {
 241                 /*
 242                  * Program voltage swing and pre-emphasis level values as per
 243                  * table in BSPEC under DDI buffer programing
 244                  */
 245                 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
 246                 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
 247                       RTERM_SELECT(0x6);
 248                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 249                 tmp &= ~mask;
 250                 tmp |= val;
 251                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 252                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
 253
 254                 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 255                        RCOMP_SCALAR_MASK;
 256                 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
 257                       RCOMP_SCALAR(0x98);
 258                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 259                 tmp &= ~mask;
 260                 tmp |= val;
 261                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 262                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
 263
 264                 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 265                        CURSOR_COEFF_MASK;
 266                 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
 267                       CURSOR_COEFF(0x3f);
 268                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
 269
 270                 /* Bspec: must not use GRP register for write */
 271                 for (lane = 0; lane <= 3; lane++)
 272                         intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
 273                                      mask, val);
 274         }
 275 }
 276
 277 static void configure_dual_link_mode(struct intel_encoder *encoder,
 278                                      const struct intel_crtc_state *pipe_config)
 279 {
 280         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 281         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 282         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 283         u32 dss_ctl1;
 284
 285         /* FIXME: Move all DSS handling to intel_vdsc.c */
 286         if (DISPLAY_VER(dev_priv) >= 12) {
 287                 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 288
 289                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
 290                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
 291         } else {
 292                 dss_ctl1_reg = DSS_CTL1;
 293                 dss_ctl2_reg = DSS_CTL2;
 294         }
 295
 296         dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
 297         dss_ctl1 |= SPLITTER_ENABLE;
 298         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 299         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 300
 301         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 302                 const struct drm_display_mode *adjusted_mode =
 303                                         &pipe_config->hw.adjusted_mode;
 304                 u16 hactive = adjusted_mode->crtc_hdisplay;
 305                 u16 dl_buffer_depth;
 306
 307                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 308                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 309
 310                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 311                         drm_err(&dev_priv->drm,
 312                                 "DL buffer depth exceed max value\n");
 313
 314                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 315                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 316                 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
 317                              RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
 318         } else {
 319                 /* Interleave */
 320                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 321         }
 322
 323         intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
 324 }
 325
 326 /* aka DSI 8X clock */
 327 static int afe_clk(struct intel_encoder *encoder,
 328                    const struct intel_crtc_state *crtc_state)
 329 {
 330         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 331         int bpp;
 332
 333         if (crtc_state->dsc.compression_enable)
 334                 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
 335         else
 336                 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 337
 338         return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 339 }
 340
 341 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 342                                           const struct intel_crtc_state *crtc_state)
 343 {
 344         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 345         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 346         enum port port;
 347         int afe_clk_khz;
 348         int theo_word_clk, act_word_clk;
 349         u32 esc_clk_div_m, esc_clk_div_m_phy;
 350
 351         afe_clk_khz = afe_clk(encoder, crtc_state);
 352
 353         if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
 354                 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
 355                 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
 356                 esc_clk_div_m = act_word_clk * 8;
 357                 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
 358         } else {
 359                 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 360         }
 361
 362         for_each_dsi_port(port, intel_dsi->ports) {
 363                 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
 364                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 365                 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
 366         }
 367
 368         for_each_dsi_port(port, intel_dsi->ports) {
 369                 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
 370                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 371                 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
 372         }
 373
 374         if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
 375                 for_each_dsi_port(port, intel_dsi->ports) {
 376                         intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
 377                                        esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
 378                         intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
 379                 }
 380         }
 381 }
 382
 383 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
 384                                      struct intel_dsi *intel_dsi)
 385 {
 386         enum port port;
 387
 388         for_each_dsi_port(port, intel_dsi->ports) {
 389                 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
 390                 intel_dsi->io_wakeref[port] =
 391                         intel_display_power_get(dev_priv,
 392                                                 port == PORT_A ?
 393                                                 POWER_DOMAIN_PORT_DDI_IO_A :
 394                                                 POWER_DOMAIN_PORT_DDI_IO_B);
 395         }
 396 }
 397
 398 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 399 {
 400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 401         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 402         enum port port;
 403
 404         for_each_dsi_port(port, intel_dsi->ports)
 405                 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
 406                              0, COMBO_PHY_MODE_DSI);
 407
 408         get_dsi_io_power_domains(dev_priv, intel_dsi);
 409 }
 410
 411 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 412 {
 413         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 414         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 415         enum phy phy;
 416
 417         for_each_dsi_phy(phy, intel_dsi->phys)
 418                 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 419                                                intel_dsi->lane_count, false);
 420 }
 421
 422 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 423 {
 424         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 425         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 426         enum phy phy;
 427         u32 tmp;
 428         int lane;
 429
 430         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 431         for_each_dsi_phy(phy, intel_dsi->phys) {
 432                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
 433                 for (lane = 0; lane <= 3; lane++)
 434                         intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
 435                                      LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
 436         }
 437
 438         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 439         for_each_dsi_phy(phy, intel_dsi->phys) {
 440                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
 441                              FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
 442                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 443                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 444                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 445                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 446
 447                 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
 448                 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
 449                     (DISPLAY_VER(dev_priv) >= 12)) {
 450                         intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 451                                      LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 452
 453                         tmp = intel_de_read(dev_priv,
 454                                             ICL_PORT_PCS_DW1_LN(0, phy));
 455                         tmp &= ~LATENCY_OPTIM_MASK;
 456                         tmp |= LATENCY_OPTIM_VAL(0x1);
 457                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
 458                                        tmp);
 459                 }
 460         }
 461
 462 }
 463
 464 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 465 {
 466         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 467         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 468         u32 tmp;
 469         enum phy phy;
 470
 471         /* clear common keeper enable bit */
 472         for_each_dsi_phy(phy, intel_dsi->phys) {
 473                 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
 474                 tmp &= ~COMMON_KEEPER_EN;
 475                 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
 476                 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
 477         }
 478
 479         /*
 480          * Set SUS Clock Config bitfield to 11b
 481          * Note: loadgen select program is done
 482          * as part of lane phy sequence configuration
 483          */
 484         for_each_dsi_phy(phy, intel_dsi->phys)
 485                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
 486
 487         /* Clear training enable to change swing values */
 488         for_each_dsi_phy(phy, intel_dsi->phys) {
 489                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 490                 tmp &= ~TX_TRAINING_EN;
 491                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 492                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
 493         }
 494
 495         /* Program swing and de-emphasis */
 496         dsi_program_swing_and_deemphasis(encoder);
 497
 498         /* Set training enable to trigger update */
 499         for_each_dsi_phy(phy, intel_dsi->phys) {
 500                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 501                 tmp |= TX_TRAINING_EN;
 502                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 503                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
 504         }
 505 }
 506
 507 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 508 {
 509         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 510         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 511         enum port port;
 512
 513         for_each_dsi_port(port, intel_dsi->ports) {
 514                 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
 515
 516                 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 517                                   DDI_BUF_IS_IDLE),
 518                                   500))
 519                         drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
 520                                 port_name(port));
 521         }
 522 }
 523
 524 static void
 525 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 526                              const struct intel_crtc_state *crtc_state)
 527 {
 528         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 529         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 530         enum port port;
 531         enum phy phy;
 532
 533         /* Program DPHY clock lanes timings */
 534         for_each_dsi_port(port, intel_dsi->ports)
 535                 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
 536                                intel_dsi->dphy_reg);
 537
 538         /* Program DPHY data lanes timings */
 539         for_each_dsi_port(port, intel_dsi->ports)
 540                 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
 541                                intel_dsi->dphy_data_lane_reg);
 542
 543         /*
 544          * If DSI link operating at or below an 800 MHz,
 545          * TA_SURE should be override and programmed to
 546          * a value '0' inside TA_PARAM_REGISTERS otherwise
 547          * leave all fields at HW default values.
 548          */
 549         if (DISPLAY_VER(dev_priv) == 11) {
 550                 if (afe_clk(encoder, crtc_state) <= 800000) {
 551                         for_each_dsi_port(port, intel_dsi->ports)
 552                                 intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
 553                                              TA_SURE_MASK,
 554                                              TA_SURE_OVERRIDE | TA_SURE(0));
 555                 }
 556         }
 557
 558         if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
 559                 for_each_dsi_phy(phy, intel_dsi->phys)
 560                         intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 561                                      0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
 562         }
 563 }
 564
 565 static void
 566 gen11_dsi_setup_timings(struct intel_encoder *encoder,
 567                         const struct intel_crtc_state *crtc_state)
 568 {
 569         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 570         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 571         enum port port;
 572
 573         /* Program T-INIT master registers */
 574         for_each_dsi_port(port, intel_dsi->ports)
 575                 intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
 576                              DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
 577
 578         /* shadow register inside display core */
 579         for_each_dsi_port(port, intel_dsi->ports)
 580                 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
 581                                intel_dsi->dphy_reg);
 582
 583         /* shadow register inside display core */
 584         for_each_dsi_port(port, intel_dsi->ports)
 585                 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
 586                                intel_dsi->dphy_data_lane_reg);
 587
 588         /* shadow register inside display core */
 589         if (DISPLAY_VER(dev_priv) == 11) {
 590                 if (afe_clk(encoder, crtc_state) <= 800000) {
 591                         for_each_dsi_port(port, intel_dsi->ports) {
 592                                 intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
 593                                              TA_SURE_MASK,
 594                                              TA_SURE_OVERRIDE | TA_SURE(0));
 595                         }
 596                 }
 597         }
 598 }
 599
 600 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 601 {
 602         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 603         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 604         u32 tmp;
 605         enum phy phy;
 606
 607         mutex_lock(&dev_priv->display.dpll.lock);
 608         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 609         for_each_dsi_phy(phy, intel_dsi->phys)
 610                 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 611
 612         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 613         mutex_unlock(&dev_priv->display.dpll.lock);
 614 }
 615
 616 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 619         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 620         u32 tmp;
 621         enum phy phy;
 622
 623         mutex_lock(&dev_priv->display.dpll.lock);
 624         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 625         for_each_dsi_phy(phy, intel_dsi->phys)
 626                 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 627
 628         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 629         mutex_unlock(&dev_priv->display.dpll.lock);
 630 }
 631
 632 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
 633 {
 634         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 635         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 636         bool clock_enabled = false;
 637         enum phy phy;
 638         u32 tmp;
 639
 640         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 641
 642         for_each_dsi_phy(phy, intel_dsi->phys) {
 643                 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
 644                         clock_enabled = true;
 645         }
 646
 647         return clock_enabled;
 648 }
 649
 650 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 651                               const struct intel_crtc_state *crtc_state)
 652 {
 653         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 654         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 655         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 656         enum phy phy;
 657         u32 val;
 658
 659         mutex_lock(&dev_priv->display.dpll.lock);
 660
 661         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 662         for_each_dsi_phy(phy, intel_dsi->phys) {
 663                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 664                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 665         }
 666         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 667
 668         for_each_dsi_phy(phy, intel_dsi->phys) {
 669                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 670         }
 671         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 672
 673         intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
 674
 675         mutex_unlock(&dev_priv->display.dpll.lock);
 676 }
 677
 678 static void
 679 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 680                                const struct intel_crtc_state *pipe_config)
 681 {
 682         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 683         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 684         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 685         enum pipe pipe = crtc->pipe;
 686         u32 tmp;
 687         enum port port;
 688         enum transcoder dsi_trans;
 689
 690         for_each_dsi_port(port, intel_dsi->ports) {
 691                 dsi_trans = dsi_port_to_transcoder(port);
 692                 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
 693
 694                 if (intel_dsi->eotp_pkt)
 695                         tmp &= ~EOTP_DISABLED;
 696                 else
 697                         tmp |= EOTP_DISABLED;
 698
 699                 /* enable link calibration if freq > 1.5Gbps */
 700                 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 701                         tmp &= ~LINK_CALIBRATION_MASK;
 702                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 703                 }
 704
 705                 /* configure continuous clock */
 706                 tmp &= ~CONTINUOUS_CLK_MASK;
 707                 if (intel_dsi->clock_stop)
 708                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 709                 else
 710                         tmp |= CLK_HS_CONTINUOUS;
 711
 712                 /* configure buffer threshold limit to minimum */
 713                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 714                 tmp |= PIX_BUF_THRESHOLD_1_4;
 715
 716                 /* set virtual channel to '0' */
 717                 tmp &= ~PIX_VIRT_CHAN_MASK;
 718                 tmp |= PIX_VIRT_CHAN(0);
 719
 720                 /* program BGR transmission */
 721                 if (intel_dsi->bgr_enabled)
 722                         tmp |= BGR_TRANSMISSION;
 723
 724                 /* select pixel format */
 725                 tmp &= ~PIX_FMT_MASK;
 726                 if (pipe_config->dsc.compression_enable) {
 727                         tmp |= PIX_FMT_COMPRESSED;
 728                 } else {
 729                         switch (intel_dsi->pixel_format) {
 730                         default:
 731                                 MISSING_CASE(intel_dsi->pixel_format);
 732                                 fallthrough;
 733                         case MIPI_DSI_FMT_RGB565:
 734                                 tmp |= PIX_FMT_RGB565;
 735                                 break;
 736                         case MIPI_DSI_FMT_RGB666_PACKED:
 737                                 tmp |= PIX_FMT_RGB666_PACKED;
 738                                 break;
 739                         case MIPI_DSI_FMT_RGB666:
 740                                 tmp |= PIX_FMT_RGB666_LOOSE;
 741                                 break;
 742                         case MIPI_DSI_FMT_RGB888:
 743                                 tmp |= PIX_FMT_RGB888;
 744                                 break;
 745                         }
 746                 }
 747
 748                 if (DISPLAY_VER(dev_priv) >= 12) {
 749                         if (is_vid_mode(intel_dsi))
 750                                 tmp |= BLANKING_PACKET_ENABLE;
 751                 }
 752
 753                 /* program DSI operation mode */
 754                 if (is_vid_mode(intel_dsi)) {
 755                         tmp &= ~OP_MODE_MASK;
 756                         switch (intel_dsi->video_mode) {
 757                         default:
 758                                 MISSING_CASE(intel_dsi->video_mode);
 759                                 fallthrough;
 760                         case NON_BURST_SYNC_EVENTS:
 761                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 762                                 break;
 763                         case NON_BURST_SYNC_PULSE:
 764                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 765                                 break;
 766                         }
 767                 } else {
 768                         /*
 769                          * FIXME: Retrieve this info from VBT.
 770                          * As per the spec when dsi transcoder is operating
 771                          * in TE GATE mode, TE comes from GPIO
 772                          * which is UTIL PIN for DSI 0.
 773                          * Also this GPIO would not be used for other
 774                          * purposes is an assumption.
 775                          */
 776                         tmp &= ~OP_MODE_MASK;
 777                         tmp |= CMD_MODE_TE_GATE;
 778                         tmp |= TE_SOURCE_GPIO;
 779                 }
 780
 781                 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 782         }
 783
 784         /* enable port sync mode if dual link */
 785         if (intel_dsi->dual_link) {
 786                 for_each_dsi_port(port, intel_dsi->ports) {
 787                         dsi_trans = dsi_port_to_transcoder(port);
 788                         intel_de_rmw(dev_priv,
 789                                      TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
 790                                      0, PORT_SYNC_MODE_ENABLE);
 791                 }
 792
 793                 /* configure stream splitting */
 794                 configure_dual_link_mode(encoder, pipe_config);
 795         }
 796
 797         for_each_dsi_port(port, intel_dsi->ports) {
 798                 dsi_trans = dsi_port_to_transcoder(port);
 799
 800                 /* select data lane width */
 801                 tmp = intel_de_read(dev_priv,
 802                                     TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
 803                 tmp &= ~DDI_PORT_WIDTH_MASK;
 804                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 805
 806                 /* select input pipe */
 807                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 808                 switch (pipe) {
 809                 default:
 810                         MISSING_CASE(pipe);
 811                         fallthrough;
 812                 case PIPE_A:
 813                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 814                         break;
 815                 case PIPE_B:
 816                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 817                         break;
 818                 case PIPE_C:
 819                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 820                         break;
 821                 case PIPE_D:
 822                         tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
 823                         break;
 824                 }
 825
 826                 /* enable DDI buffer */
 827                 tmp |= TRANS_DDI_FUNC_ENABLE;
 828                 intel_de_write(dev_priv,
 829                                TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
 830         }
 831
 832         /* wait for link ready */
 833         for_each_dsi_port(port, intel_dsi->ports) {
 834                 dsi_trans = dsi_port_to_transcoder(port);
 835                 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
 836                                  LINK_READY), 2500))
 837                         drm_err(&dev_priv->drm, "DSI link not ready\n");
 838         }
 839 }
 840
 841 static void
 842 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 843                                  const struct intel_crtc_state *crtc_state)
 844 {
 845         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 846         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 847         const struct drm_display_mode *adjusted_mode =
 848                 &crtc_state->hw.adjusted_mode;
 849         enum port port;
 850         enum transcoder dsi_trans;
 851         /* horizontal timings */
 852         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 853         u16 hback_porch;
 854         /* vertical timings */
 855         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 856         int mul = 1, div = 1;
 857
 858         /*
 859          * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
 860          * for slower link speed if DSC is enabled.
 861          *
 862          * The compression frequency ratio is the ratio between compressed and
 863          * non-compressed link speeds, and simplifies down to the ratio between
 864          * compressed and non-compressed bpp.
 865          */
 866         if (crtc_state->dsc.compression_enable) {
 867                 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
 868                 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 869         }
 870
 871         hactive = adjusted_mode->crtc_hdisplay;
 872
 873         if (is_vid_mode(intel_dsi))
 874                 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
 875         else
 876                 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
 877
 878         hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
 879         hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
 880         hsync_size  = hsync_end - hsync_start;
 881         hback_porch = (adjusted_mode->crtc_htotal -
 882                        adjusted_mode->crtc_hsync_end);
 883         vactive = adjusted_mode->crtc_vdisplay;
 884
 885         if (is_vid_mode(intel_dsi)) {
 886                 vtotal = adjusted_mode->crtc_vtotal;
 887         } else {
 888                 int bpp, line_time_us, byte_clk_period_ns;
 889
 890                 if (crtc_state->dsc.compression_enable)
 891                         bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16);
 892                 else
 893                         bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 894
 895                 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
 896                 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
 897                 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
 898         }
 899         vsync_start = adjusted_mode->crtc_vsync_start;
 900         vsync_end = adjusted_mode->crtc_vsync_end;
 901         vsync_shift = hsync_start - htotal / 2;
 902
 903         if (intel_dsi->dual_link) {
 904                 hactive /= 2;
 905                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 906                         hactive += intel_dsi->pixel_overlap;
 907                 htotal /= 2;
 908         }
 909
 910         /* minimum hactive as per bspec: 256 pixels */
 911         if (adjusted_mode->crtc_hdisplay < 256)
 912                 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
 913
 914         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 915         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 916                 drm_err(&dev_priv->drm,
 917                         "hactive pixels are not multiple of 4\n");
 918
 919         /* program TRANS_HTOTAL register */
 920         for_each_dsi_port(port, intel_dsi->ports) {
 921                 dsi_trans = dsi_port_to_transcoder(port);
 922                 intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
 923                                HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
 924         }
 925
 926         /* TRANS_HSYNC register to be programmed only for video mode */
 927         if (is_vid_mode(intel_dsi)) {
 928                 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
 929                         /* BSPEC: hsync size should be atleast 16 pixels */
 930                         if (hsync_size < 16)
 931                                 drm_err(&dev_priv->drm,
 932                                         "hsync size < 16 pixels\n");
 933                 }
 934
 935                 if (hback_porch < 16)
 936                         drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
 937
 938                 if (intel_dsi->dual_link) {
 939                         hsync_start /= 2;
 940                         hsync_end /= 2;
 941                 }
 942
 943                 for_each_dsi_port(port, intel_dsi->ports) {
 944                         dsi_trans = dsi_port_to_transcoder(port);
 945                         intel_de_write(dev_priv,
 946                                        TRANS_HSYNC(dev_priv, dsi_trans),
 947                                        HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
 948                 }
 949         }
 950
 951         /* program TRANS_VTOTAL register */
 952         for_each_dsi_port(port, intel_dsi->ports) {
 953                 dsi_trans = dsi_port_to_transcoder(port);
 954                 /*
 955                  * FIXME: Programing this by assuming progressive mode, since
 956                  * non-interlaced info from VBT is not saved inside
 957                  * struct drm_display_mode.
 958                  * For interlace mode: program required pixel minus 2
 959                  */
 960                 intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
 961                                VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
 962         }
 963
 964         if (vsync_end < vsync_start || vsync_end > vtotal)
 965                 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
 966
 967         if (vsync_start < vactive)
 968                 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
 969
 970         /* program TRANS_VSYNC register for video mode only */
 971         if (is_vid_mode(intel_dsi)) {
 972                 for_each_dsi_port(port, intel_dsi->ports) {
 973                         dsi_trans = dsi_port_to_transcoder(port);
 974                         intel_de_write(dev_priv,
 975                                        TRANS_VSYNC(dev_priv, dsi_trans),
 976                                        VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
 977                 }
 978         }
 979
 980         /*
 981          * FIXME: It has to be programmed only for video modes and interlaced
 982          * modes. Put the check condition here once interlaced
 983          * info available as described above.
 984          * program TRANS_VSYNCSHIFT register
 985          */
 986         if (is_vid_mode(intel_dsi)) {
 987                 for_each_dsi_port(port, intel_dsi->ports) {
 988                         dsi_trans = dsi_port_to_transcoder(port);
 989                         intel_de_write(dev_priv,
 990                                        TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
 991                                        vsync_shift);
 992                 }
 993         }
 994
 995         /*
 996          * program TRANS_VBLANK register, should be same as vtotal programmed
 997          *
 998          * FIXME get rid of these local hacks and do it right,
 999          * this will not handle eg. delayed vblank correctly.
1000          */
1001         if (DISPLAY_VER(dev_priv) >= 12) {
1002                 for_each_dsi_port(port, intel_dsi->ports) {
1003                         dsi_trans = dsi_port_to_transcoder(port);
1004                         intel_de_write(dev_priv,
1005                                        TRANS_VBLANK(dev_priv, dsi_trans),
1006                                        VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1007                 }
1008         }
1009 }
1010
1011 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1012 {
1013         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1014         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1015         enum port port;
1016         enum transcoder dsi_trans;
1017
1018         for_each_dsi_port(port, intel_dsi->ports) {
1019                 dsi_trans = dsi_port_to_transcoder(port);
1020                 intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
1021                              TRANSCONF_ENABLE);
1022
1023                 /* wait for transcoder to be enabled */
1024                 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
1025                                           TRANSCONF_STATE_ENABLE, 10))
1026                         drm_err(&dev_priv->drm,
1027                                 "DSI transcoder not enabled\n");
1028         }
1029 }
1030
1031 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1032                                      const struct intel_crtc_state *crtc_state)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1035         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1036         enum port port;
1037         enum transcoder dsi_trans;
1038         u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1039
1040         /*
1041          * escape clock count calculation:
1042          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1043          * UI (nsec) = (10^6)/Bitrate
1044          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1045          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
1046          */
1047         divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1048         mul = 8 * 1000000;
1049         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1050                                      divisor);
1051         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1052         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1053
1054         for_each_dsi_port(port, intel_dsi->ports) {
1055                 dsi_trans = dsi_port_to_transcoder(port);
1056
1057                 /* program hst_tx_timeout */
1058                 intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
1059                              HSTX_TIMEOUT_VALUE_MASK,
1060                              HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1061
1062                 /* FIXME: DSI_CALIB_TO */
1063
1064                 /* program lp_rx_host timeout */
1065                 intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
1066                              LPRX_TIMEOUT_VALUE_MASK,
1067                              LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1068
1069                 /* FIXME: DSI_PWAIT_TO */
1070
1071                 /* program turn around timeout */
1072                 intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
1073                              TA_TIMEOUT_VALUE_MASK,
1074                              TA_TIMEOUT_VALUE(ta_timeout));
1075         }
1076 }
1077
1078 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1079                                       bool enable)
1080 {
1081         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1082         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1083         u32 tmp;
1084
1085         /*
1086          * used as TE i/p for DSI0,
1087          * for dual link/DSI1 TE is from slave DSI1
1088          * through GPIO.
1089          */
1090         if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1091                 return;
1092
1093         tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1094
1095         if (enable) {
1096                 tmp |= UTIL_PIN_DIRECTION_INPUT;
1097                 tmp |= UTIL_PIN_ENABLE;
1098         } else {
1099                 tmp &= ~UTIL_PIN_ENABLE;
1100         }
1101         intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1102 }
1103
1104 static void
1105 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1106                               const struct intel_crtc_state *crtc_state)
1107 {
1108         /* step 4a: power up all lanes of the DDI used by DSI */
1109         gen11_dsi_power_up_lanes(encoder);
1110
1111         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1112         gen11_dsi_config_phy_lanes_sequence(encoder);
1113
1114         /* step 4c: configure voltage swing and skew */
1115         gen11_dsi_voltage_swing_program_seq(encoder);
1116
1117         /* setup D-PHY timings */
1118         gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1119
1120         /* enable DDI buffer */
1121         gen11_dsi_enable_ddi_buffer(encoder);
1122
1123         gen11_dsi_gate_clocks(encoder);
1124
1125         gen11_dsi_setup_timings(encoder, crtc_state);
1126
1127         /* Since transcoder is configured to take events from GPIO */
1128         gen11_dsi_config_util_pin(encoder, true);
1129
1130         /* step 4h: setup DSI protocol timeouts */
1131         gen11_dsi_setup_timeouts(encoder, crtc_state);
1132
1133         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1134         gen11_dsi_configure_transcoder(encoder, crtc_state);
1135 }
1136
1137 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1138 {
1139         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1140         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1141         struct mipi_dsi_device *dsi;
1142         enum port port;
1143         enum transcoder dsi_trans;
1144         u32 tmp;
1145         int ret;
1146
1147         /* set maximum return packet size */
1148         for_each_dsi_port(port, intel_dsi->ports) {
1149                 dsi_trans = dsi_port_to_transcoder(port);
1150
1151                 /*
1152                  * FIXME: This uses the number of DW's currently in the payload
1153                  * receive queue. This is probably not what we want here.
1154                  */
1155                 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1156                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1157                 /* multiply "Number Rx Payload DW" by 4 to get max value */
1158                 tmp = tmp * 4;
1159                 dsi = intel_dsi->dsi_hosts[port]->device;
1160                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1161                 if (ret < 0)
1162                         drm_err(&dev_priv->drm,
1163                                 "error setting max return pkt size%d\n", tmp);
1164         }
1165
1166         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1167
1168         /* ensure all panel commands dispatched before enabling transcoder */
1169         wait_for_cmds_dispatched_to_panel(encoder);
1170 }
1171
1172 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1173                                      struct intel_encoder *encoder,
1174                                      const struct intel_crtc_state *crtc_state,
1175                                      const struct drm_connector_state *conn_state)
1176 {
1177         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1178
1179         intel_dsi_wait_panel_power_cycle(intel_dsi);
1180
1181         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1182         msleep(intel_dsi->panel_on_delay);
1183         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1184
1185         /* step2: enable IO power */
1186         gen11_dsi_enable_io_power(encoder);
1187
1188         /* step3: enable DSI PLL */
1189         gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1190 }
1191
1192 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1193                                  struct intel_encoder *encoder,
1194                                  const struct intel_crtc_state *pipe_config,
1195                                  const struct drm_connector_state *conn_state)
1196 {
1197         /* step3b */
1198         gen11_dsi_map_pll(encoder, pipe_config);
1199
1200         /* step4: enable DSI port and DPHY */
1201         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1202
1203         /* step5: program and powerup panel */
1204         gen11_dsi_powerup_panel(encoder);
1205
1206         intel_dsc_dsi_pps_write(encoder, pipe_config);
1207
1208         /* step6c: configure transcoder timings */
1209         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1210 }
1211
1212 /*
1213  * Wa_1409054076:icl,jsl,ehl
1214  * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1215  * the AMT KVMR feature will incorrectly see pipe A as enabled.
1216  * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1217  * it set while DSI is enabled on pipe B
1218  */
1219 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1220                                      enum pipe pipe, bool enable)
1221 {
1222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1223
1224         if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
1225                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1226                              IGNORE_KVMR_PIPE_A,
1227                              enable ? IGNORE_KVMR_PIPE_A : 0);
1228 }
1229
1230 /*
1231  * Wa_16012360555:adl-p
1232  * SW will have to program the "LP to HS Wakeup Guardband"
1233  * to account for the repeaters on the HS Request/Ready
1234  * PPI signaling between the Display engine and the DPHY.
1235  */
1236 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1237 {
1238         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1239         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1240         enum port port;
1241
1242         if (DISPLAY_VER(i915) == 13) {
1243                 for_each_dsi_port(port, intel_dsi->ports)
1244                         intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
1245                                      TGL_DSI_CHKN_LSHS_GB_MASK,
1246                                      TGL_DSI_CHKN_LSHS_GB(4));
1247         }
1248 }
1249
1250 static void gen11_dsi_enable(struct intel_atomic_state *state,
1251                              struct intel_encoder *encoder,
1252                              const struct intel_crtc_state *crtc_state,
1253                              const struct drm_connector_state *conn_state)
1254 {
1255         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1256         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1257
1258         /* Wa_1409054076:icl,jsl,ehl */
1259         icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1260
1261         /* Wa_16012360555:adl-p */
1262         adlp_set_lp_hs_wakeup_gb(encoder);
1263
1264         /* step6d: enable dsi transcoder */
1265         gen11_dsi_enable_transcoder(encoder);
1266
1267         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1268
1269         /* step7: enable backlight */
1270         intel_backlight_enable(crtc_state, conn_state);
1271         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1272
1273         intel_crtc_vblank_on(crtc_state);
1274 }
1275
1276 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1277 {
1278         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1279         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1280         enum port port;
1281         enum transcoder dsi_trans;
1282
1283         for_each_dsi_port(port, intel_dsi->ports) {
1284                 dsi_trans = dsi_port_to_transcoder(port);
1285
1286                 /* disable transcoder */
1287                 intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
1288                              TRANSCONF_ENABLE, 0);
1289
1290                 /* wait for transcoder to be disabled */
1291                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
1292                                             TRANSCONF_STATE_ENABLE, 50))
1293                         drm_err(&dev_priv->drm,
1294                                 "DSI trancoder not disabled\n");
1295         }
1296 }
1297
1298 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1299 {
1300         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1301
1302         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1303
1304         /* ensure cmds dispatched to panel */
1305         wait_for_cmds_dispatched_to_panel(encoder);
1306 }
1307
1308 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1309 {
1310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1311         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1312         enum port port;
1313         enum transcoder dsi_trans;
1314         u32 tmp;
1315
1316         /* disable periodic update mode */
1317         if (is_cmd_mode(intel_dsi)) {
1318                 for_each_dsi_port(port, intel_dsi->ports)
1319                         intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
1320                                      DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
1321         }
1322
1323         /* put dsi link in ULPS */
1324         for_each_dsi_port(port, intel_dsi->ports) {
1325                 dsi_trans = dsi_port_to_transcoder(port);
1326                 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1327                 tmp |= LINK_ENTER_ULPS;
1328                 tmp &= ~LINK_ULPS_TYPE_LP11;
1329                 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1330
1331                 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1332                                  LINK_IN_ULPS),
1333                                 10))
1334                         drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1335         }
1336
1337         /* disable ddi function */
1338         for_each_dsi_port(port, intel_dsi->ports) {
1339                 dsi_trans = dsi_port_to_transcoder(port);
1340                 intel_de_rmw(dev_priv,
1341                              TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
1342                              TRANS_DDI_FUNC_ENABLE, 0);
1343         }
1344
1345         /* disable port sync mode if dual link */
1346         if (intel_dsi->dual_link) {
1347                 for_each_dsi_port(port, intel_dsi->ports) {
1348                         dsi_trans = dsi_port_to_transcoder(port);
1349                         intel_de_rmw(dev_priv,
1350                                      TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
1351                                      PORT_SYNC_MODE_ENABLE, 0);
1352                 }
1353         }
1354 }
1355
1356 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1357 {
1358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1359         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1360         enum port port;
1361
1362         gen11_dsi_ungate_clocks(encoder);
1363         for_each_dsi_port(port, intel_dsi->ports) {
1364                 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1365
1366                 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1367                                  DDI_BUF_IS_IDLE),
1368                                  8))
1369                         drm_err(&dev_priv->drm,
1370                                 "DDI port:%c buffer not idle\n",
1371                                 port_name(port));
1372         }
1373         gen11_dsi_gate_clocks(encoder);
1374 }
1375
1376 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1377 {
1378         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1379         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1380         enum port port;
1381
1382         for_each_dsi_port(port, intel_dsi->ports) {
1383                 intel_wakeref_t wakeref;
1384
1385                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1386                 intel_display_power_put(dev_priv,
1387                                         port == PORT_A ?
1388                                         POWER_DOMAIN_PORT_DDI_IO_A :
1389                                         POWER_DOMAIN_PORT_DDI_IO_B,
1390                                         wakeref);
1391         }
1392
1393         /* set mode to DDI */
1394         for_each_dsi_port(port, intel_dsi->ports)
1395                 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
1396                              COMBO_PHY_MODE_DSI, 0);
1397 }
1398
1399 static void gen11_dsi_disable(struct intel_atomic_state *state,
1400                               struct intel_encoder *encoder,
1401                               const struct intel_crtc_state *old_crtc_state,
1402                               const struct drm_connector_state *old_conn_state)
1403 {
1404         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1405
1406         /* step1: turn off backlight */
1407         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1408         intel_backlight_disable(old_conn_state);
1409 }
1410
1411 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1412                                    struct intel_encoder *encoder,
1413                                    const struct intel_crtc_state *old_crtc_state,
1414                                    const struct drm_connector_state *old_conn_state)
1415 {
1416         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1417         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1418
1419         intel_crtc_vblank_off(old_crtc_state);
1420
1421         /* step2d,e: disable transcoder and wait */
1422         gen11_dsi_disable_transcoder(encoder);
1423
1424         /* Wa_1409054076:icl,jsl,ehl */
1425         icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1426
1427         /* step2f,g: powerdown panel */
1428         gen11_dsi_powerdown_panel(encoder);
1429
1430         /* step2h,i,j: deconfig trancoder */
1431         gen11_dsi_deconfigure_trancoder(encoder);
1432
1433         intel_dsc_disable(old_crtc_state);
1434         skl_scaler_disable(old_crtc_state);
1435
1436         /* step3: disable port */
1437         gen11_dsi_disable_port(encoder);
1438
1439         gen11_dsi_config_util_pin(encoder, false);
1440
1441         /* step4: disable IO power */
1442         gen11_dsi_disable_io_power(encoder);
1443
1444         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1445
1446         msleep(intel_dsi->panel_off_delay);
1447         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1448
1449         intel_dsi->panel_power_off_time = ktime_get_boottime();
1450 }
1451
1452 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1453                                                  struct drm_display_mode *mode)
1454 {
1455         struct drm_i915_private *i915 = to_i915(connector->dev);
1456         enum drm_mode_status status;
1457
1458         status = intel_cpu_transcoder_mode_valid(i915, mode);
1459         if (status != MODE_OK)
1460                 return status;
1461
1462         /* FIXME: DSC? */
1463         return intel_dsi_mode_valid(connector, mode);
1464 }
1465
1466 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1467                                   struct intel_crtc_state *pipe_config)
1468 {
1469         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1470         struct drm_display_mode *adjusted_mode =
1471                                         &pipe_config->hw.adjusted_mode;
1472
1473         if (pipe_config->dsc.compressed_bpp_x16) {
1474                 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
1475                 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1476
1477                 adjusted_mode->crtc_htotal =
1478                         DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1479                 adjusted_mode->crtc_hsync_start =
1480                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1481                 adjusted_mode->crtc_hsync_end =
1482                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1483         }
1484
1485         if (intel_dsi->dual_link) {
1486                 adjusted_mode->crtc_hdisplay *= 2;
1487                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1488                         adjusted_mode->crtc_hdisplay -=
1489                                                 intel_dsi->pixel_overlap;
1490                 adjusted_mode->crtc_htotal *= 2;
1491         }
1492         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1493         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1494
1495         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1496                 if (intel_dsi->dual_link) {
1497                         adjusted_mode->crtc_hsync_start *= 2;
1498                         adjusted_mode->crtc_hsync_end *= 2;
1499                 }
1500         }
1501         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1502         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1503 }
1504
1505 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1506 {
1507         struct drm_device *dev = intel_dsi->base.base.dev;
1508         struct drm_i915_private *dev_priv = to_i915(dev);
1509         enum transcoder dsi_trans;
1510         u32 val;
1511
1512         if (intel_dsi->ports == BIT(PORT_B))
1513                 dsi_trans = TRANSCODER_DSI_1;
1514         else
1515                 dsi_trans = TRANSCODER_DSI_0;
1516
1517         val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1518         return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1519 }
1520
1521 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1522                                           struct intel_crtc_state *pipe_config)
1523 {
1524         if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1525                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1526                                             I915_MODE_FLAG_DSI_USE_TE0;
1527         else if (intel_dsi->ports == BIT(PORT_B))
1528                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1529         else
1530                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1531 }
1532
1533 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1534                                  struct intel_crtc_state *pipe_config)
1535 {
1536         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1537         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1538
1539         intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1540
1541         pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1542         if (intel_dsi->dual_link)
1543                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1544
1545         gen11_dsi_get_timings(encoder, pipe_config);
1546         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1547         pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1548
1549         /* Get the details on which TE should be enabled */
1550         if (is_cmd_mode(intel_dsi))
1551                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1552
1553         if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1554                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1555 }
1556
1557 static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1558                                  const struct intel_crtc_state *crtc_state)
1559 {
1560         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1561         struct intel_crtc *intel_crtc;
1562         enum pipe pipe;
1563
1564         if (!crtc_state)
1565                 return;
1566
1567         intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1568         pipe = intel_crtc->pipe;
1569
1570         /* wa verify 1409054076:icl,jsl,ehl */
1571         if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
1572             !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1573                 drm_dbg_kms(&dev_priv->drm,
1574                             "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1575                             encoder->base.base.id,
1576                             encoder->base.name);
1577 }
1578
1579 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1580                                         struct intel_crtc_state *crtc_state)
1581 {
1582         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1583         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1584         int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
1585         bool use_dsc;
1586         int ret;
1587
1588         use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1589         if (!use_dsc)
1590                 return 0;
1591
1592         if (crtc_state->pipe_bpp < 8 * 3)
1593                 return -EINVAL;
1594
1595         /* FIXME: split only when necessary */
1596         if (crtc_state->dsc.slice_count > 1)
1597                 crtc_state->dsc.dsc_split = true;
1598
1599         /* FIXME: initialize from VBT */
1600         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1601
1602         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1603
1604         ret = intel_dsc_compute_params(crtc_state);
1605         if (ret)
1606                 return ret;
1607
1608         /* DSI specific sanity checks on the common code */
1609         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1610         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1611         drm_WARN_ON(&dev_priv->drm,
1612                     vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1613         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1614         drm_WARN_ON(&dev_priv->drm,
1615                     vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1616
1617         ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1618         if (ret)
1619                 return ret;
1620
1621         crtc_state->dsc.compression_enable = true;
1622
1623         return 0;
1624 }
1625
1626 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1627                                     struct intel_crtc_state *pipe_config,
1628                                     struct drm_connector_state *conn_state)
1629 {
1630         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1631         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1632         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1633         struct drm_display_mode *adjusted_mode =
1634                 &pipe_config->hw.adjusted_mode;
1635         int ret;
1636
1637         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1638         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1639
1640         ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1641         if (ret)
1642                 return ret;
1643
1644         ret = intel_panel_fitting(pipe_config, conn_state);
1645         if (ret)
1646                 return ret;
1647
1648         adjusted_mode->flags = 0;
1649
1650         /* Dual link goes to trancoder DSI'0' */
1651         if (intel_dsi->ports == BIT(PORT_B))
1652                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1653         else
1654                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1655
1656         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1657                 pipe_config->pipe_bpp = 24;
1658         else
1659                 pipe_config->pipe_bpp = 18;
1660
1661         pipe_config->clock_set = true;
1662
1663         if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1664                 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1665
1666         pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1667
1668         /*
1669          * In case of TE GATE cmd mode, we
1670          * receive TE from the slave if
1671          * dual link is enabled
1672          */
1673         if (is_cmd_mode(intel_dsi))
1674                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1675
1676         return 0;
1677 }
1678
1679 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1680                                         struct intel_crtc_state *crtc_state)
1681 {
1682         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1683
1684         get_dsi_io_power_domains(i915,
1685                                  enc_to_intel_dsi(encoder));
1686 }
1687
1688 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1689                                    enum pipe *pipe)
1690 {
1691         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1692         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1693         enum transcoder dsi_trans;
1694         intel_wakeref_t wakeref;
1695         enum port port;
1696         bool ret = false;
1697         u32 tmp;
1698
1699         wakeref = intel_display_power_get_if_enabled(dev_priv,
1700                                                      encoder->power_domain);
1701         if (!wakeref)
1702                 return false;
1703
1704         for_each_dsi_port(port, intel_dsi->ports) {
1705                 dsi_trans = dsi_port_to_transcoder(port);
1706                 tmp = intel_de_read(dev_priv,
1707                                     TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
1708                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1709                 case TRANS_DDI_EDP_INPUT_A_ON:
1710                         *pipe = PIPE_A;
1711                         break;
1712                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1713                         *pipe = PIPE_B;
1714                         break;
1715                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1716                         *pipe = PIPE_C;
1717                         break;
1718                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1719                         *pipe = PIPE_D;
1720                         break;
1721                 default:
1722                         drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1723                         goto out;
1724                 }
1725
1726                 tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
1727                 ret = tmp & TRANSCONF_ENABLE;
1728         }
1729 out:
1730         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1731         return ret;
1732 }
1733
1734 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1735                                             struct intel_crtc_state *crtc_state)
1736 {
1737         if (crtc_state->dsc.compression_enable) {
1738                 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1739                 crtc_state->uapi.mode_changed = true;
1740
1741                 return false;
1742         }
1743
1744         return true;
1745 }
1746
1747 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1748 {
1749         intel_encoder_destroy(encoder);
1750 }
1751
1752 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1753         .destroy = gen11_dsi_encoder_destroy,
1754 };
1755
1756 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1757         .detect = intel_panel_detect,
1758         .late_register = intel_connector_register,
1759         .early_unregister = intel_connector_unregister,
1760         .destroy = intel_connector_destroy,
1761         .fill_modes = drm_helper_probe_single_connector_modes,
1762         .atomic_get_property = intel_digital_connector_atomic_get_property,
1763         .atomic_set_property = intel_digital_connector_atomic_set_property,
1764         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1765         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1766 };
1767
1768 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1769         .get_modes = intel_dsi_get_modes,
1770         .mode_valid = gen11_dsi_mode_valid,
1771         .atomic_check = intel_digital_connector_atomic_check,
1772 };
1773
1774 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1775                                  struct mipi_dsi_device *dsi)
1776 {
1777         return 0;
1778 }
1779
1780 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1781                                  struct mipi_dsi_device *dsi)
1782 {
1783         return 0;
1784 }
1785
1786 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1787                                        const struct mipi_dsi_msg *msg)
1788 {
1789         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1790         struct mipi_dsi_packet dsi_pkt;
1791         ssize_t ret;
1792         bool enable_lpdt = false;
1793
1794         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1795         if (ret < 0)
1796                 return ret;
1797
1798         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1799                 enable_lpdt = true;
1800
1801         /* only long packet contains payload */
1802         if (mipi_dsi_packet_format_is_long(msg->type)) {
1803                 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt);
1804                 if (ret < 0)
1805                         return ret;
1806         }
1807
1808         /* send packet header */
1809         ret  = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt);
1810         if (ret < 0)
1811                 return ret;
1812
1813         //TODO: add payload receive code if needed
1814
1815         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1816
1817         return ret;
1818 }
1819
1820 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1821         .attach = gen11_dsi_host_attach,
1822         .detach = gen11_dsi_host_detach,
1823         .transfer = gen11_dsi_host_transfer,
1824 };
1825
1826 #define ICL_PREPARE_CNT_MAX     0x7
1827 #define ICL_CLK_ZERO_CNT_MAX    0xf
1828 #define ICL_TRAIL_CNT_MAX       0x7
1829 #define ICL_TCLK_PRE_CNT_MAX    0x3
1830 #define ICL_TCLK_POST_CNT_MAX   0x7
1831 #define ICL_HS_ZERO_CNT_MAX     0xf
1832 #define ICL_EXIT_ZERO_CNT_MAX   0x7
1833
1834 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1835 {
1836         struct drm_device *dev = intel_dsi->base.base.dev;
1837         struct drm_i915_private *dev_priv = to_i915(dev);
1838         struct intel_connector *connector = intel_dsi->attached_connector;
1839         struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1840         u32 tlpx_ns;
1841         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1842         u32 ths_prepare_ns, tclk_trail_ns;
1843         u32 hs_zero_cnt;
1844         u32 tclk_pre_cnt;
1845
1846         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1847
1848         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1849         ths_prepare_ns = max(mipi_config->ths_prepare,
1850                              mipi_config->tclk_prepare);
1851
1852         /*
1853          * prepare cnt in escape clocks
1854          * this field represents a hexadecimal value with a precision
1855          * of 1.2 – i.e. the most significant bit is the integer
1856          * and the least significant 2 bits are fraction bits.
1857          * so, the field can represent a range of 0.25 to 1.75
1858          */
1859         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1860         if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1861                 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1862                             prepare_cnt);
1863                 prepare_cnt = ICL_PREPARE_CNT_MAX;
1864         }
1865
1866         /* clk zero count in escape clocks */
1867         clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1868                                     ths_prepare_ns, tlpx_ns);
1869         if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1870                 drm_dbg_kms(&dev_priv->drm,
1871                             "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1872                 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1873         }
1874
1875         /* trail cnt in escape clocks*/
1876         trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1877         if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1878                 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1879                             trail_cnt);
1880                 trail_cnt = ICL_TRAIL_CNT_MAX;
1881         }
1882
1883         /* tclk pre count in escape clocks */
1884         tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1885         if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1886                 drm_dbg_kms(&dev_priv->drm,
1887                             "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1888                 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1889         }
1890
1891         /* hs zero cnt in escape clocks */
1892         hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1893                                    ths_prepare_ns, tlpx_ns);
1894         if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1895                 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1896                             hs_zero_cnt);
1897                 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1898         }
1899
1900         /* hs exit zero cnt in escape clocks */
1901         exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1902         if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1903                 drm_dbg_kms(&dev_priv->drm,
1904                             "exit_zero_cnt out of range (%d)\n",
1905                             exit_zero_cnt);
1906                 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1907         }
1908
1909         /* clock lane dphy timings */
1910         intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1911                                CLK_PREPARE(prepare_cnt) |
1912                                CLK_ZERO_OVERRIDE |
1913                                CLK_ZERO(clk_zero_cnt) |
1914                                CLK_PRE_OVERRIDE |
1915                                CLK_PRE(tclk_pre_cnt) |
1916                                CLK_TRAIL_OVERRIDE |
1917                                CLK_TRAIL(trail_cnt));
1918
1919         /* data lanes dphy timings */
1920         intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1921                                          HS_PREPARE(prepare_cnt) |
1922                                          HS_ZERO_OVERRIDE |
1923                                          HS_ZERO(hs_zero_cnt) |
1924                                          HS_TRAIL_OVERRIDE |
1925                                          HS_TRAIL(trail_cnt) |
1926                                          HS_EXIT_OVERRIDE |
1927                                          HS_EXIT(exit_zero_cnt));
1928
1929         intel_dsi_log_params(intel_dsi);
1930 }
1931
1932 static void icl_dsi_add_properties(struct intel_connector *connector)
1933 {
1934         const struct drm_display_mode *fixed_mode =
1935                 intel_panel_preferred_fixed_mode(connector);
1936
1937         intel_attach_scaling_mode_property(&connector->base);
1938
1939         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1940                                                        intel_dsi_get_panel_orientation(connector),
1941                                                        fixed_mode->hdisplay,
1942                                                        fixed_mode->vdisplay);
1943 }
1944
1945 void icl_dsi_init(struct drm_i915_private *dev_priv,
1946                   const struct intel_bios_encoder_data *devdata)
1947 {
1948         struct intel_display *display = &dev_priv->display;
1949         struct intel_dsi *intel_dsi;
1950         struct intel_encoder *encoder;
1951         struct intel_connector *intel_connector;
1952         struct drm_connector *connector;
1953         enum port port;
1954
1955         port = intel_bios_encoder_port(devdata);
1956         if (port == PORT_NONE)
1957                 return;
1958
1959         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1960         if (!intel_dsi)
1961                 return;
1962
1963         intel_connector = intel_connector_alloc();
1964         if (!intel_connector) {
1965                 kfree(intel_dsi);
1966                 return;
1967         }
1968
1969         encoder = &intel_dsi->base;
1970         intel_dsi->attached_connector = intel_connector;
1971         connector = &intel_connector->base;
1972
1973         encoder->devdata = devdata;
1974
1975         /* register DSI encoder with DRM subsystem */
1976         drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
1977                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1978
1979         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1980         encoder->pre_enable = gen11_dsi_pre_enable;
1981         encoder->enable = gen11_dsi_enable;
1982         encoder->disable = gen11_dsi_disable;
1983         encoder->post_disable = gen11_dsi_post_disable;
1984         encoder->port = port;
1985         encoder->get_config = gen11_dsi_get_config;
1986         encoder->sync_state = gen11_dsi_sync_state;
1987         encoder->update_pipe = intel_backlight_update;
1988         encoder->compute_config = gen11_dsi_compute_config;
1989         encoder->get_hw_state = gen11_dsi_get_hw_state;
1990         encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1991         encoder->type = INTEL_OUTPUT_DSI;
1992         encoder->cloneable = 0;
1993         encoder->pipe_mask = ~0;
1994         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1995         encoder->get_power_domains = gen11_dsi_get_power_domains;
1996         encoder->disable_clock = gen11_dsi_gate_clocks;
1997         encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
1998         encoder->shutdown = intel_dsi_shutdown;
1999
2000         /* register DSI connector with DRM subsystem */
2001         drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
2002                            DRM_MODE_CONNECTOR_DSI);
2003         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
2004         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2005         intel_connector->get_hw_state = intel_connector_get_hw_state;
2006
2007         /* attach connector to encoder */
2008         intel_connector_attach_encoder(intel_connector, encoder);
2009
2010         intel_dsi->panel_power_off_time = ktime_get_boottime();
2011
2012         intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
2013
2014         mutex_lock(&dev_priv->drm.mode_config.mutex);
2015         intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
2016         mutex_unlock(&dev_priv->drm.mode_config.mutex);
2017
2018         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2019                 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
2020                 goto err;
2021         }
2022
2023         intel_panel_init(intel_connector, NULL);
2024
2025         intel_backlight_setup(intel_connector, INVALID_PIPE);
2026
2027         if (intel_connector->panel.vbt.dsi.config->dual_link)
2028                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
2029         else
2030                 intel_dsi->ports = BIT(port);
2031
2032         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
2033                 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
2034
2035         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
2036                 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
2037
2038         for_each_dsi_port(port, intel_dsi->ports) {
2039                 struct intel_dsi_host *host;
2040
2041                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2042                 if (!host)
2043                         goto err;
2044
2045                 intel_dsi->dsi_hosts[port] = host;
2046         }
2047
2048         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2049                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
2050                 goto err;
2051         }
2052
2053         icl_dphy_param_init(intel_dsi);
2054
2055         icl_dsi_add_properties(intel_connector);
2056         return;
2057
2058 err:
2059         drm_connector_cleanup(connector);
2060         drm_encoder_cleanup(&encoder->base);
2061         kfree(intel_dsi);
2062         kfree(intel_connector);
2063 }