drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static int
 135 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 136 {
 137         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 138
 139         switch (max_link_bw) {
 140         case DP_LINK_BW_1_62:
 141         case DP_LINK_BW_2_7:
 142         case DP_LINK_BW_5_4:
 143                 break;
 144         default:
 145                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 146                      max_link_bw);
 147                 max_link_bw = DP_LINK_BW_1_62;
 148                 break;
 149         }
 150         return max_link_bw;
 151 }
 152
 153 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 154 {
 155         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 156         u8 source_max, sink_max;
 157
 158         source_max = intel_dig_port->max_lanes;
 159         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 160
 161         return min(source_max, sink_max);
 162 }
 163
 164 /*
 165  * The units on the numbers in the next two are... bizarre.  Examples will
 166  * make it clearer; this one parallels an example in the eDP spec.
 167  *
 168  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 169  *
 170  *     270000 * 1 * 8 / 10 == 216000
 171  *
 172  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 173  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 174  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 175  * 119000.  At 18bpp that's 2142000 kilobits per second.
 176  *
 177  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 178  * get the result in decakilobits instead of kilobits.
 179  */
 180
 181 static int
 182 intel_dp_link_required(int pixel_clock, int bpp)
 183 {
 184         return (pixel_clock * bpp + 9) / 10;
 185 }
 186
 187 static int
 188 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 189 {
 190         return (max_link_clock * max_lanes * 8) / 10;
 191 }
 192
 193 static enum drm_mode_status
 194 intel_dp_mode_valid(struct drm_connector *connector,
 195                     struct drm_display_mode *mode)
 196 {
 197         struct intel_dp *intel_dp = intel_attached_dp(connector);
 198         struct intel_connector *intel_connector = to_intel_connector(connector);
 199         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 200         int target_clock = mode->clock;
 201         int max_rate, mode_rate, max_lanes, max_link_clock;
 202         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 203
 204         if (is_edp(intel_dp) && fixed_mode) {
 205                 if (mode->hdisplay > fixed_mode->hdisplay)
 206                         return MODE_PANEL;
 207
 208                 if (mode->vdisplay > fixed_mode->vdisplay)
 209                         return MODE_PANEL;
 210
 211                 target_clock = fixed_mode->clock;
 212         }
 213
 214         max_link_clock = intel_dp_max_link_rate(intel_dp);
 215         max_lanes = intel_dp_max_lane_count(intel_dp);
 216
 217         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 218         mode_rate = intel_dp_link_required(target_clock, 18);
 219
 220         if (mode_rate > max_rate || target_clock > max_dotclk)
 221                 return MODE_CLOCK_HIGH;
 222
 223         if (mode->clock < 10000)
 224                 return MODE_CLOCK_LOW;
 225
 226         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 227                 return MODE_H_ILLEGAL;
 228
 229         return MODE_OK;
 230 }
 231
 232 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 233 {
 234         int     i;
 235         uint32_t v = 0;
 236
 237         if (src_bytes > 4)
 238                 src_bytes = 4;
 239         for (i = 0; i < src_bytes; i++)
 240                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 241         return v;
 242 }
 243
 244 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 245 {
 246         int i;
 247         if (dst_bytes > 4)
 248                 dst_bytes = 4;
 249         for (i = 0; i < dst_bytes; i++)
 250                 dst[i] = src >> ((3-i) * 8);
 251 }
 252
 253 static void
 254 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 255                                     struct intel_dp *intel_dp);
 256 static void
 257 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 258                                               struct intel_dp *intel_dp);
 259
 260 static void pps_lock(struct intel_dp *intel_dp)
 261 {
 262         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 263         struct intel_encoder *encoder = &intel_dig_port->base;
 264         struct drm_device *dev = encoder->base.dev;
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         enum intel_display_power_domain power_domain;
 267
 268         /*
 269          * See vlv_power_sequencer_reset() why we need
 270          * a power domain reference here.
 271          */
 272         power_domain = intel_display_port_aux_power_domain(encoder);
 273         intel_display_power_get(dev_priv, power_domain);
 274
 275         mutex_lock(&dev_priv->pps_mutex);
 276 }
 277
 278 static void pps_unlock(struct intel_dp *intel_dp)
 279 {
 280         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 281         struct intel_encoder *encoder = &intel_dig_port->base;
 282         struct drm_device *dev = encoder->base.dev;
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         enum intel_display_power_domain power_domain;
 285
 286         mutex_unlock(&dev_priv->pps_mutex);
 287
 288         power_domain = intel_display_port_aux_power_domain(encoder);
 289         intel_display_power_put(dev_priv, power_domain);
 290 }
 291
 292 static void
 293 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 294 {
 295         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 296         struct drm_device *dev = intel_dig_port->base.base.dev;
 297         struct drm_i915_private *dev_priv = dev->dev_private;
 298         enum pipe pipe = intel_dp->pps_pipe;
 299         bool pll_enabled, release_cl_override = false;
 300         enum dpio_phy phy = DPIO_PHY(pipe);
 301         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 302         uint32_t DP;
 303
 304         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 305                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 306                  pipe_name(pipe), port_name(intel_dig_port->port)))
 307                 return;
 308
 309         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 310                       pipe_name(pipe), port_name(intel_dig_port->port));
 311
 312         /* Preserve the BIOS-computed detected bit. This is
 313          * supposed to be read-only.
 314          */
 315         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 316         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 317         DP |= DP_PORT_WIDTH(1);
 318         DP |= DP_LINK_TRAIN_PAT_1;
 319
 320         if (IS_CHERRYVIEW(dev))
 321                 DP |= DP_PIPE_SELECT_CHV(pipe);
 322         else if (pipe == PIPE_B)
 323                 DP |= DP_PIPEB_SELECT;
 324
 325         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 326
 327         /*
 328          * The DPLL for the pipe must be enabled for this to work.
 329          * So enable temporarily it if it's not already enabled.
 330          */
 331         if (!pll_enabled) {
 332                 release_cl_override = IS_CHERRYVIEW(dev) &&
 333                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 334
 335                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 336                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 337                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 338                                   pipe_name(pipe));
 339                         return;
 340                 }
 341         }
 342
 343         /*
 344          * Similar magic as in intel_dp_enable_port().
 345          * We _must_ do this port enable + disable trick
 346          * to make this power seqeuencer lock onto the port.
 347          * Otherwise even VDD force bit won't work.
 348          */
 349         I915_WRITE(intel_dp->output_reg, DP);
 350         POSTING_READ(intel_dp->output_reg);
 351
 352         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 353         POSTING_READ(intel_dp->output_reg);
 354
 355         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 356         POSTING_READ(intel_dp->output_reg);
 357
 358         if (!pll_enabled) {
 359                 vlv_force_pll_off(dev, pipe);
 360
 361                 if (release_cl_override)
 362                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 363         }
 364 }
 365
 366 static enum pipe
 367 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 368 {
 369         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 370         struct drm_device *dev = intel_dig_port->base.base.dev;
 371         struct drm_i915_private *dev_priv = dev->dev_private;
 372         struct intel_encoder *encoder;
 373         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 374         enum pipe pipe;
 375
 376         lockdep_assert_held(&dev_priv->pps_mutex);
 377
 378         /* We should never land here with regular DP ports */
 379         WARN_ON(!is_edp(intel_dp));
 380
 381         if (intel_dp->pps_pipe != INVALID_PIPE)
 382                 return intel_dp->pps_pipe;
 383
 384         /*
 385          * We don't have power sequencer currently.
 386          * Pick one that's not used by other ports.
 387          */
 388         for_each_intel_encoder(dev, encoder) {
 389                 struct intel_dp *tmp;
 390
 391                 if (encoder->type != INTEL_OUTPUT_EDP)
 392                         continue;
 393
 394                 tmp = enc_to_intel_dp(&encoder->base);
 395
 396                 if (tmp->pps_pipe != INVALID_PIPE)
 397                         pipes &= ~(1 << tmp->pps_pipe);
 398         }
 399
 400         /*
 401          * Didn't find one. This should not happen since there
 402          * are two power sequencers and up to two eDP ports.
 403          */
 404         if (WARN_ON(pipes == 0))
 405                 pipe = PIPE_A;
 406         else
 407                 pipe = ffs(pipes) - 1;
 408
 409         vlv_steal_power_sequencer(dev, pipe);
 410         intel_dp->pps_pipe = pipe;
 411
 412         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 413                       pipe_name(intel_dp->pps_pipe),
 414                       port_name(intel_dig_port->port));
 415
 416         /* init power sequencer on this pipe and port */
 417         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 418         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 419
 420         /*
 421          * Even vdd force doesn't work until we've made
 422          * the power sequencer lock in on the port.
 423          */
 424         vlv_power_sequencer_kick(intel_dp);
 425
 426         return intel_dp->pps_pipe;
 427 }
 428
 429 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 430                                enum pipe pipe);
 431
 432 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 433                                enum pipe pipe)
 434 {
 435         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 436 }
 437
 438 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 439                                 enum pipe pipe)
 440 {
 441         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 442 }
 443
 444 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 445                          enum pipe pipe)
 446 {
 447         return true;
 448 }
 449
 450 static enum pipe
 451 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 452                      enum port port,
 453                      vlv_pipe_check pipe_check)
 454 {
 455         enum pipe pipe;
 456
 457         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 458                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 459                         PANEL_PORT_SELECT_MASK;
 460
 461                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 462                         continue;
 463
 464                 if (!pipe_check(dev_priv, pipe))
 465                         continue;
 466
 467                 return pipe;
 468         }
 469
 470         return INVALID_PIPE;
 471 }
 472
 473 static void
 474 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 475 {
 476         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 477         struct drm_device *dev = intel_dig_port->base.base.dev;
 478         struct drm_i915_private *dev_priv = dev->dev_private;
 479         enum port port = intel_dig_port->port;
 480
 481         lockdep_assert_held(&dev_priv->pps_mutex);
 482
 483         /* try to find a pipe with this port selected */
 484         /* first pick one where the panel is on */
 485         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 486                                                   vlv_pipe_has_pp_on);
 487         /* didn't find one? pick one where vdd is on */
 488         if (intel_dp->pps_pipe == INVALID_PIPE)
 489                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 490                                                           vlv_pipe_has_vdd_on);
 491         /* didn't find one? pick one with just the correct port */
 492         if (intel_dp->pps_pipe == INVALID_PIPE)
 493                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 494                                                           vlv_pipe_any);
 495
 496         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 497         if (intel_dp->pps_pipe == INVALID_PIPE) {
 498                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 499                               port_name(port));
 500                 return;
 501         }
 502
 503         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 504                       port_name(port), pipe_name(intel_dp->pps_pipe));
 505
 506         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 507         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 508 }
 509
 510 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 511 {
 512         struct drm_device *dev = dev_priv->dev;
 513         struct intel_encoder *encoder;
 514
 515         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
 516                 return;
 517
 518         /*
 519          * We can't grab pps_mutex here due to deadlock with power_domain
 520          * mutex when power_domain functions are called while holding pps_mutex.
 521          * That also means that in order to use pps_pipe the code needs to
 522          * hold both a power domain reference and pps_mutex, and the power domain
 523          * reference get/put must be done while _not_ holding pps_mutex.
 524          * pps_{lock,unlock}() do these steps in the correct order, so one
 525          * should use them always.
 526          */
 527
 528         for_each_intel_encoder(dev, encoder) {
 529                 struct intel_dp *intel_dp;
 530
 531                 if (encoder->type != INTEL_OUTPUT_EDP)
 532                         continue;
 533
 534                 intel_dp = enc_to_intel_dp(&encoder->base);
 535                 intel_dp->pps_pipe = INVALID_PIPE;
 536         }
 537 }
 538
 539 static i915_reg_t
 540 _pp_ctrl_reg(struct intel_dp *intel_dp)
 541 {
 542         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 543
 544         if (IS_BROXTON(dev))
 545                 return BXT_PP_CONTROL(0);
 546         else if (HAS_PCH_SPLIT(dev))
 547                 return PCH_PP_CONTROL;
 548         else
 549                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 550 }
 551
 552 static i915_reg_t
 553 _pp_stat_reg(struct intel_dp *intel_dp)
 554 {
 555         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 556
 557         if (IS_BROXTON(dev))
 558                 return BXT_PP_STATUS(0);
 559         else if (HAS_PCH_SPLIT(dev))
 560                 return PCH_PP_STATUS;
 561         else
 562                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 563 }
 564
 565 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 566    This function only applicable when panel PM state is not to be tracked */
 567 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 568                               void *unused)
 569 {
 570         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 571                                                  edp_notifier);
 572         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 573         struct drm_i915_private *dev_priv = dev->dev_private;
 574
 575         if (!is_edp(intel_dp) || code != SYS_RESTART)
 576                 return 0;
 577
 578         pps_lock(intel_dp);
 579
 580         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 581                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 582                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 583                 u32 pp_div;
 584
 585                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 586                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 587                 pp_div = I915_READ(pp_div_reg);
 588                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 589
 590                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 591                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 592                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 593                 msleep(intel_dp->panel_power_cycle_delay);
 594         }
 595
 596         pps_unlock(intel_dp);
 597
 598         return 0;
 599 }
 600
 601 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 602 {
 603         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 604         struct drm_i915_private *dev_priv = dev->dev_private;
 605
 606         lockdep_assert_held(&dev_priv->pps_mutex);
 607
 608         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 609             intel_dp->pps_pipe == INVALID_PIPE)
 610                 return false;
 611
 612         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 613 }
 614
 615 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 616 {
 617         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 618         struct drm_i915_private *dev_priv = dev->dev_private;
 619
 620         lockdep_assert_held(&dev_priv->pps_mutex);
 621
 622         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 623             intel_dp->pps_pipe == INVALID_PIPE)
 624                 return false;
 625
 626         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 627 }
 628
 629 static void
 630 intel_dp_check_edp(struct intel_dp *intel_dp)
 631 {
 632         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 633         struct drm_i915_private *dev_priv = dev->dev_private;
 634
 635         if (!is_edp(intel_dp))
 636                 return;
 637
 638         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 639                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 640                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 641                               I915_READ(_pp_stat_reg(intel_dp)),
 642                               I915_READ(_pp_ctrl_reg(intel_dp)));
 643         }
 644 }
 645
 646 static uint32_t
 647 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 648 {
 649         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 650         struct drm_device *dev = intel_dig_port->base.base.dev;
 651         struct drm_i915_private *dev_priv = dev->dev_private;
 652         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 653         uint32_t status;
 654         bool done;
 655
 656 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 657         if (has_aux_irq)
 658                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 659                                           msecs_to_jiffies_timeout(10));
 660         else
 661                 done = wait_for_atomic(C, 10) == 0;
 662         if (!done)
 663                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 664                           has_aux_irq);
 665 #undef C
 666
 667         return status;
 668 }
 669
 670 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 671 {
 672         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 673         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 674
 675         if (index)
 676                 return 0;
 677
 678         /*
 679          * The clock divider is based off the hrawclk, and would like to run at
 680          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 681          */
 682         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 683 }
 684
 685 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 686 {
 687         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 688         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 689
 690         if (index)
 691                 return 0;
 692
 693         /*
 694          * The clock divider is based off the cdclk or PCH rawclk, and would
 695          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 696          * divide by 2000 and use that
 697          */
 698         if (intel_dig_port->port == PORT_A)
 699                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 700         else
 701                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 702 }
 703
 704 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 705 {
 706         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 707         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 708
 709         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 710                 /* Workaround for non-ULT HSW */
 711                 switch (index) {
 712                 case 0: return 63;
 713                 case 1: return 72;
 714                 default: return 0;
 715                 }
 716         }
 717
 718         return ilk_get_aux_clock_divider(intel_dp, index);
 719 }
 720
 721 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 722 {
 723         /*
 724          * SKL doesn't need us to program the AUX clock divider (Hardware will
 725          * derive the clock from CDCLK automatically). We still implement the
 726          * get_aux_clock_divider vfunc to plug-in into the existing code.
 727          */
 728         return index ? 0 : 1;
 729 }
 730
 731 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 732                                      bool has_aux_irq,
 733                                      int send_bytes,
 734                                      uint32_t aux_clock_divider)
 735 {
 736         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 737         struct drm_device *dev = intel_dig_port->base.base.dev;
 738         uint32_t precharge, timeout;
 739
 740         if (IS_GEN6(dev))
 741                 precharge = 3;
 742         else
 743                 precharge = 5;
 744
 745         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 746                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 747         else
 748                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 749
 750         return DP_AUX_CH_CTL_SEND_BUSY |
 751                DP_AUX_CH_CTL_DONE |
 752                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 753                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 754                timeout |
 755                DP_AUX_CH_CTL_RECEIVE_ERROR |
 756                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 757                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 758                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 759 }
 760
 761 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 762                                       bool has_aux_irq,
 763                                       int send_bytes,
 764                                       uint32_t unused)
 765 {
 766         return DP_AUX_CH_CTL_SEND_BUSY |
 767                DP_AUX_CH_CTL_DONE |
 768                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 769                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 770                DP_AUX_CH_CTL_TIME_OUT_1600us |
 771                DP_AUX_CH_CTL_RECEIVE_ERROR |
 772                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 773                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 774 }
 775
 776 static int
 777 intel_dp_aux_ch(struct intel_dp *intel_dp,
 778                 const uint8_t *send, int send_bytes,
 779                 uint8_t *recv, int recv_size)
 780 {
 781         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 782         struct drm_device *dev = intel_dig_port->base.base.dev;
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 785         uint32_t aux_clock_divider;
 786         int i, ret, recv_bytes;
 787         uint32_t status;
 788         int try, clock = 0;
 789         bool has_aux_irq = HAS_AUX_IRQ(dev);
 790         bool vdd;
 791
 792         pps_lock(intel_dp);
 793
 794         /*
 795          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 796          * In such cases we want to leave VDD enabled and it's up to upper layers
 797          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 798          * ourselves.
 799          */
 800         vdd = edp_panel_vdd_on(intel_dp);
 801
 802         /* dp aux is extremely sensitive to irq latency, hence request the
 803          * lowest possible wakeup latency and so prevent the cpu from going into
 804          * deep sleep states.
 805          */
 806         pm_qos_update_request(&dev_priv->pm_qos, 0);
 807
 808         intel_dp_check_edp(intel_dp);
 809
 810         /* Try to wait for any previous AUX channel activity */
 811         for (try = 0; try < 3; try++) {
 812                 status = I915_READ_NOTRACE(ch_ctl);
 813                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 814                         break;
 815                 msleep(1);
 816         }
 817
 818         if (try == 3) {
 819                 static u32 last_status = -1;
 820                 const u32 status = I915_READ(ch_ctl);
 821
 822                 if (status != last_status) {
 823                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 824                              status);
 825                         last_status = status;
 826                 }
 827
 828                 ret = -EBUSY;
 829                 goto out;
 830         }
 831
 832         /* Only 5 data registers! */
 833         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 834                 ret = -E2BIG;
 835                 goto out;
 836         }
 837
 838         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 839                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 840                                                           has_aux_irq,
 841                                                           send_bytes,
 842                                                           aux_clock_divider);
 843
 844                 /* Must try at least 3 times according to DP spec */
 845                 for (try = 0; try < 5; try++) {
 846                         /* Load the send data into the aux channel data registers */
 847                         for (i = 0; i < send_bytes; i += 4)
 848                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 849                                            intel_dp_pack_aux(send + i,
 850                                                              send_bytes - i));
 851
 852                         /* Send the command and wait for it to complete */
 853                         I915_WRITE(ch_ctl, send_ctl);
 854
 855                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 856
 857                         /* Clear done status and any errors */
 858                         I915_WRITE(ch_ctl,
 859                                    status |
 860                                    DP_AUX_CH_CTL_DONE |
 861                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 862                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 863
 864                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 865                                 continue;
 866
 867                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 868                          *   400us delay required for errors and timeouts
 869                          *   Timeout errors from the HW already meet this
 870                          *   requirement so skip to next iteration
 871                          */
 872                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 873                                 usleep_range(400, 500);
 874                                 continue;
 875                         }
 876                         if (status & DP_AUX_CH_CTL_DONE)
 877                                 goto done;
 878                 }
 879         }
 880
 881         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 882                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 883                 ret = -EBUSY;
 884                 goto out;
 885         }
 886
 887 done:
 888         /* Check for timeout or receive error.
 889          * Timeouts occur when the sink is not connected
 890          */
 891         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 892                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 893                 ret = -EIO;
 894                 goto out;
 895         }
 896
 897         /* Timeouts occur when the device isn't connected, so they're
 898          * "normal" -- don't fill the kernel log with these */
 899         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 900                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 901                 ret = -ETIMEDOUT;
 902                 goto out;
 903         }
 904
 905         /* Unload any bytes sent back from the other side */
 906         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 907                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 908
 909         /*
 910          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 911          * We have no idea of what happened so we return -EBUSY so
 912          * drm layer takes care for the necessary retries.
 913          */
 914         if (recv_bytes == 0 || recv_bytes > 20) {
 915                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 916                               recv_bytes);
 917                 /*
 918                  * FIXME: This patch was created on top of a series that
 919                  * organize the retries at drm level. There EBUSY should
 920                  * also take care for 1ms wait before retrying.
 921                  * That aux retries re-org is still needed and after that is
 922                  * merged we remove this sleep from here.
 923                  */
 924                 usleep_range(1000, 1500);
 925                 ret = -EBUSY;
 926                 goto out;
 927         }
 928
 929         if (recv_bytes > recv_size)
 930                 recv_bytes = recv_size;
 931
 932         for (i = 0; i < recv_bytes; i += 4)
 933                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 934                                     recv + i, recv_bytes - i);
 935
 936         ret = recv_bytes;
 937 out:
 938         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 939
 940         if (vdd)
 941                 edp_panel_vdd_off(intel_dp, false);
 942
 943         pps_unlock(intel_dp);
 944
 945         return ret;
 946 }
 947
 948 #define BARE_ADDRESS_SIZE       3
 949 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 950 static ssize_t
 951 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 952 {
 953         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 954         uint8_t txbuf[20], rxbuf[20];
 955         size_t txsize, rxsize;
 956         int ret;
 957
 958         txbuf[0] = (msg->request << 4) |
 959                 ((msg->address >> 16) & 0xf);
 960         txbuf[1] = (msg->address >> 8) & 0xff;
 961         txbuf[2] = msg->address & 0xff;
 962         txbuf[3] = msg->size - 1;
 963
 964         switch (msg->request & ~DP_AUX_I2C_MOT) {
 965         case DP_AUX_NATIVE_WRITE:
 966         case DP_AUX_I2C_WRITE:
 967         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 968                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 969                 rxsize = 2; /* 0 or 1 data bytes */
 970
 971                 if (WARN_ON(txsize > 20))
 972                         return -E2BIG;
 973
 974                 if (msg->buffer)
 975                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 976                 else
 977                         WARN_ON(msg->size);
 978
 979                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 980                 if (ret > 0) {
 981                         msg->reply = rxbuf[0] >> 4;
 982
 983                         if (ret > 1) {
 984                                 /* Number of bytes written in a short write. */
 985                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 986                         } else {
 987                                 /* Return payload size. */
 988                                 ret = msg->size;
 989                         }
 990                 }
 991                 break;
 992
 993         case DP_AUX_NATIVE_READ:
 994         case DP_AUX_I2C_READ:
 995                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 996                 rxsize = msg->size + 1;
 997
 998                 if (WARN_ON(rxsize > 20))
 999                         return -E2BIG;
1000
1001                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1002                 if (ret > 0) {
1003                         msg->reply = rxbuf[0] >> 4;
1004                         /*
1005                          * Assume happy day, and copy the data. The caller is
1006                          * expected to check msg->reply before touching it.
1007                          *
1008                          * Return payload size.
1009                          */
1010                         ret--;
1011                         memcpy(msg->buffer, rxbuf + 1, ret);
1012                 }
1013                 break;
1014
1015         default:
1016                 ret = -EINVAL;
1017                 break;
1018         }
1019
1020         return ret;
1021 }
1022
1023 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1024                                        enum port port)
1025 {
1026         switch (port) {
1027         case PORT_B:
1028         case PORT_C:
1029         case PORT_D:
1030                 return DP_AUX_CH_CTL(port);
1031         default:
1032                 MISSING_CASE(port);
1033                 return DP_AUX_CH_CTL(PORT_B);
1034         }
1035 }
1036
1037 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1038                                         enum port port, int index)
1039 {
1040         switch (port) {
1041         case PORT_B:
1042         case PORT_C:
1043         case PORT_D:
1044                 return DP_AUX_CH_DATA(port, index);
1045         default:
1046                 MISSING_CASE(port);
1047                 return DP_AUX_CH_DATA(PORT_B, index);
1048         }
1049 }
1050
1051 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1052                                        enum port port)
1053 {
1054         switch (port) {
1055         case PORT_A:
1056                 return DP_AUX_CH_CTL(port);
1057         case PORT_B:
1058         case PORT_C:
1059         case PORT_D:
1060                 return PCH_DP_AUX_CH_CTL(port);
1061         default:
1062                 MISSING_CASE(port);
1063                 return DP_AUX_CH_CTL(PORT_A);
1064         }
1065 }
1066
1067 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1068                                         enum port port, int index)
1069 {
1070         switch (port) {
1071         case PORT_A:
1072                 return DP_AUX_CH_DATA(port, index);
1073         case PORT_B:
1074         case PORT_C:
1075         case PORT_D:
1076                 return PCH_DP_AUX_CH_DATA(port, index);
1077         default:
1078                 MISSING_CASE(port);
1079                 return DP_AUX_CH_DATA(PORT_A, index);
1080         }
1081 }
1082
1083 /*
1084  * On SKL we don't have Aux for port E so we rely
1085  * on VBT to set a proper alternate aux channel.
1086  */
1087 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1088 {
1089         const struct ddi_vbt_port_info *info =
1090                 &dev_priv->vbt.ddi_port_info[PORT_E];
1091
1092         switch (info->alternate_aux_channel) {
1093         case DP_AUX_A:
1094                 return PORT_A;
1095         case DP_AUX_B:
1096                 return PORT_B;
1097         case DP_AUX_C:
1098                 return PORT_C;
1099         case DP_AUX_D:
1100                 return PORT_D;
1101         default:
1102                 MISSING_CASE(info->alternate_aux_channel);
1103                 return PORT_A;
1104         }
1105 }
1106
1107 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1108                                        enum port port)
1109 {
1110         if (port == PORT_E)
1111                 port = skl_porte_aux_port(dev_priv);
1112
1113         switch (port) {
1114         case PORT_A:
1115         case PORT_B:
1116         case PORT_C:
1117         case PORT_D:
1118                 return DP_AUX_CH_CTL(port);
1119         default:
1120                 MISSING_CASE(port);
1121                 return DP_AUX_CH_CTL(PORT_A);
1122         }
1123 }
1124
1125 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1126                                         enum port port, int index)
1127 {
1128         if (port == PORT_E)
1129                 port = skl_porte_aux_port(dev_priv);
1130
1131         switch (port) {
1132         case PORT_A:
1133         case PORT_B:
1134         case PORT_C:
1135         case PORT_D:
1136                 return DP_AUX_CH_DATA(port, index);
1137         default:
1138                 MISSING_CASE(port);
1139                 return DP_AUX_CH_DATA(PORT_A, index);
1140         }
1141 }
1142
1143 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1144                                          enum port port)
1145 {
1146         if (INTEL_INFO(dev_priv)->gen >= 9)
1147                 return skl_aux_ctl_reg(dev_priv, port);
1148         else if (HAS_PCH_SPLIT(dev_priv))
1149                 return ilk_aux_ctl_reg(dev_priv, port);
1150         else
1151                 return g4x_aux_ctl_reg(dev_priv, port);
1152 }
1153
1154 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1155                                           enum port port, int index)
1156 {
1157         if (INTEL_INFO(dev_priv)->gen >= 9)
1158                 return skl_aux_data_reg(dev_priv, port, index);
1159         else if (HAS_PCH_SPLIT(dev_priv))
1160                 return ilk_aux_data_reg(dev_priv, port, index);
1161         else
1162                 return g4x_aux_data_reg(dev_priv, port, index);
1163 }
1164
1165 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1166 {
1167         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1168         enum port port = dp_to_dig_port(intel_dp)->port;
1169         int i;
1170
1171         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1172         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1173                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1174 }
1175
1176 static void
1177 intel_dp_aux_fini(struct intel_dp *intel_dp)
1178 {
1179         drm_dp_aux_unregister(&intel_dp->aux);
1180         kfree(intel_dp->aux.name);
1181 }
1182
1183 static int
1184 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1185 {
1186         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1187         enum port port = intel_dig_port->port;
1188         int ret;
1189
1190         intel_aux_reg_init(intel_dp);
1191
1192         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1193         if (!intel_dp->aux.name)
1194                 return -ENOMEM;
1195
1196         intel_dp->aux.dev = connector->base.kdev;
1197         intel_dp->aux.transfer = intel_dp_aux_transfer;
1198
1199         DRM_DEBUG_KMS("registering %s bus for %s\n",
1200                       intel_dp->aux.name,
1201                       connector->base.kdev->kobj.name);
1202
1203         ret = drm_dp_aux_register(&intel_dp->aux);
1204         if (ret < 0) {
1205                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1206                           intel_dp->aux.name, ret);
1207                 kfree(intel_dp->aux.name);
1208                 return ret;
1209         }
1210
1211         return 0;
1212 }
1213
1214 static void
1215 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1216 {
1217         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1218
1219         intel_dp_aux_fini(intel_dp);
1220         intel_connector_unregister(intel_connector);
1221 }
1222
1223 static int
1224 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1225 {
1226         if (intel_dp->num_sink_rates) {
1227                 *sink_rates = intel_dp->sink_rates;
1228                 return intel_dp->num_sink_rates;
1229         }
1230
1231         *sink_rates = default_rates;
1232
1233         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1234 }
1235
1236 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1237 {
1238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1239         struct drm_device *dev = dig_port->base.base.dev;
1240
1241         /* WaDisableHBR2:skl */
1242         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1243                 return false;
1244
1245         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1246             (INTEL_INFO(dev)->gen >= 9))
1247                 return true;
1248         else
1249                 return false;
1250 }
1251
1252 static int
1253 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1254 {
1255         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1256         struct drm_device *dev = dig_port->base.base.dev;
1257         int size;
1258
1259         if (IS_BROXTON(dev)) {
1260                 *source_rates = bxt_rates;
1261                 size = ARRAY_SIZE(bxt_rates);
1262         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1263                 *source_rates = skl_rates;
1264                 size = ARRAY_SIZE(skl_rates);
1265         } else {
1266                 *source_rates = default_rates;
1267                 size = ARRAY_SIZE(default_rates);
1268         }
1269
1270         /* This depends on the fact that 5.4 is last value in the array */
1271         if (!intel_dp_source_supports_hbr2(intel_dp))
1272                 size--;
1273
1274         return size;
1275 }
1276
1277 static void
1278 intel_dp_set_clock(struct intel_encoder *encoder,
1279                    struct intel_crtc_state *pipe_config)
1280 {
1281         struct drm_device *dev = encoder->base.dev;
1282         const struct dp_link_dpll *divisor = NULL;
1283         int i, count = 0;
1284
1285         if (IS_G4X(dev)) {
1286                 divisor = gen4_dpll;
1287                 count = ARRAY_SIZE(gen4_dpll);
1288         } else if (HAS_PCH_SPLIT(dev)) {
1289                 divisor = pch_dpll;
1290                 count = ARRAY_SIZE(pch_dpll);
1291         } else if (IS_CHERRYVIEW(dev)) {
1292                 divisor = chv_dpll;
1293                 count = ARRAY_SIZE(chv_dpll);
1294         } else if (IS_VALLEYVIEW(dev)) {
1295                 divisor = vlv_dpll;
1296                 count = ARRAY_SIZE(vlv_dpll);
1297         }
1298
1299         if (divisor && count) {
1300                 for (i = 0; i < count; i++) {
1301                         if (pipe_config->port_clock == divisor[i].clock) {
1302                                 pipe_config->dpll = divisor[i].dpll;
1303                                 pipe_config->clock_set = true;
1304                                 break;
1305                         }
1306                 }
1307         }
1308 }
1309
1310 static int intersect_rates(const int *source_rates, int source_len,
1311                            const int *sink_rates, int sink_len,
1312                            int *common_rates)
1313 {
1314         int i = 0, j = 0, k = 0;
1315
1316         while (i < source_len && j < sink_len) {
1317                 if (source_rates[i] == sink_rates[j]) {
1318                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1319                                 return k;
1320                         common_rates[k] = source_rates[i];
1321                         ++k;
1322                         ++i;
1323                         ++j;
1324                 } else if (source_rates[i] < sink_rates[j]) {
1325                         ++i;
1326                 } else {
1327                         ++j;
1328                 }
1329         }
1330         return k;
1331 }
1332
1333 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1334                                  int *common_rates)
1335 {
1336         const int *source_rates, *sink_rates;
1337         int source_len, sink_len;
1338
1339         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1340         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1341
1342         return intersect_rates(source_rates, source_len,
1343                                sink_rates, sink_len,
1344                                common_rates);
1345 }
1346
1347 static void snprintf_int_array(char *str, size_t len,
1348                                const int *array, int nelem)
1349 {
1350         int i;
1351
1352         str[0] = '\0';
1353
1354         for (i = 0; i < nelem; i++) {
1355                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1356                 if (r >= len)
1357                         return;
1358                 str += r;
1359                 len -= r;
1360         }
1361 }
1362
1363 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1364 {
1365         const int *source_rates, *sink_rates;
1366         int source_len, sink_len, common_len;
1367         int common_rates[DP_MAX_SUPPORTED_RATES];
1368         char str[128]; /* FIXME: too big for stack? */
1369
1370         if ((drm_debug & DRM_UT_KMS) == 0)
1371                 return;
1372
1373         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1374         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1375         DRM_DEBUG_KMS("source rates: %s\n", str);
1376
1377         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1378         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1379         DRM_DEBUG_KMS("sink rates: %s\n", str);
1380
1381         common_len = intel_dp_common_rates(intel_dp, common_rates);
1382         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1383         DRM_DEBUG_KMS("common rates: %s\n", str);
1384 }
1385
1386 static int rate_to_index(int find, const int *rates)
1387 {
1388         int i = 0;
1389
1390         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1391                 if (find == rates[i])
1392                         break;
1393
1394         return i;
1395 }
1396
1397 int
1398 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1399 {
1400         int rates[DP_MAX_SUPPORTED_RATES] = {};
1401         int len;
1402
1403         len = intel_dp_common_rates(intel_dp, rates);
1404         if (WARN_ON(len <= 0))
1405                 return 162000;
1406
1407         return rates[rate_to_index(0, rates) - 1];
1408 }
1409
1410 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1411 {
1412         return rate_to_index(rate, intel_dp->sink_rates);
1413 }
1414
1415 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1416                            uint8_t *link_bw, uint8_t *rate_select)
1417 {
1418         if (intel_dp->num_sink_rates) {
1419                 *link_bw = 0;
1420                 *rate_select =
1421                         intel_dp_rate_select(intel_dp, port_clock);
1422         } else {
1423                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1424                 *rate_select = 0;
1425         }
1426 }
1427
1428 bool
1429 intel_dp_compute_config(struct intel_encoder *encoder,
1430                         struct intel_crtc_state *pipe_config)
1431 {
1432         struct drm_device *dev = encoder->base.dev;
1433         struct drm_i915_private *dev_priv = dev->dev_private;
1434         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1435         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1436         enum port port = dp_to_dig_port(intel_dp)->port;
1437         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1438         struct intel_connector *intel_connector = intel_dp->attached_connector;
1439         int lane_count, clock;
1440         int min_lane_count = 1;
1441         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1442         /* Conveniently, the link BW constants become indices with a shift...*/
1443         int min_clock = 0;
1444         int max_clock;
1445         int bpp, mode_rate;
1446         int link_avail, link_clock;
1447         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1448         int common_len;
1449         uint8_t link_bw, rate_select;
1450
1451         common_len = intel_dp_common_rates(intel_dp, common_rates);
1452
1453         /* No common link rates between source and sink */
1454         WARN_ON(common_len <= 0);
1455
1456         max_clock = common_len - 1;
1457
1458         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1459                 pipe_config->has_pch_encoder = true;
1460
1461         pipe_config->has_dp_encoder = true;
1462         pipe_config->has_drrs = false;
1463         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1464
1465         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1466                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1467                                        adjusted_mode);
1468
1469                 if (INTEL_INFO(dev)->gen >= 9) {
1470                         int ret;
1471                         ret = skl_update_scaler_crtc(pipe_config);
1472                         if (ret)
1473                                 return ret;
1474                 }
1475
1476                 if (HAS_GMCH_DISPLAY(dev))
1477                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1478                                                  intel_connector->panel.fitting_mode);
1479                 else
1480                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1481                                                 intel_connector->panel.fitting_mode);
1482         }
1483
1484         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1485                 return false;
1486
1487         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1488                       "max bw %d pixel clock %iKHz\n",
1489                       max_lane_count, common_rates[max_clock],
1490                       adjusted_mode->crtc_clock);
1491
1492         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1493          * bpc in between. */
1494         bpp = pipe_config->pipe_bpp;
1495         if (is_edp(intel_dp)) {
1496
1497                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1498                 if (intel_connector->base.display_info.bpc == 0 &&
1499                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1500                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1501                                       dev_priv->vbt.edp.bpp);
1502                         bpp = dev_priv->vbt.edp.bpp;
1503                 }
1504
1505                 /*
1506                  * Use the maximum clock and number of lanes the eDP panel
1507                  * advertizes being capable of. The panels are generally
1508                  * designed to support only a single clock and lane
1509                  * configuration, and typically these values correspond to the
1510                  * native resolution of the panel.
1511                  */
1512                 min_lane_count = max_lane_count;
1513                 min_clock = max_clock;
1514         }
1515
1516         for (; bpp >= 6*3; bpp -= 2*3) {
1517                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1518                                                    bpp);
1519
1520                 for (clock = min_clock; clock <= max_clock; clock++) {
1521                         for (lane_count = min_lane_count;
1522                                 lane_count <= max_lane_count;
1523                                 lane_count <<= 1) {
1524
1525                                 link_clock = common_rates[clock];
1526                                 link_avail = intel_dp_max_data_rate(link_clock,
1527                                                                     lane_count);
1528
1529                                 if (mode_rate <= link_avail) {
1530                                         goto found;
1531                                 }
1532                         }
1533                 }
1534         }
1535
1536         return false;
1537
1538 found:
1539         if (intel_dp->color_range_auto) {
1540                 /*
1541                  * See:
1542                  * CEA-861-E - 5.1 Default Encoding Parameters
1543                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1544                  */
1545                 pipe_config->limited_color_range =
1546                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1547         } else {
1548                 pipe_config->limited_color_range =
1549                         intel_dp->limited_color_range;
1550         }
1551
1552         pipe_config->lane_count = lane_count;
1553
1554         pipe_config->pipe_bpp = bpp;
1555         pipe_config->port_clock = common_rates[clock];
1556
1557         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1558                               &link_bw, &rate_select);
1559
1560         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1561                       link_bw, rate_select, pipe_config->lane_count,
1562                       pipe_config->port_clock, bpp);
1563         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1564                       mode_rate, link_avail);
1565
1566         intel_link_compute_m_n(bpp, lane_count,
1567                                adjusted_mode->crtc_clock,
1568                                pipe_config->port_clock,
1569                                &pipe_config->dp_m_n);
1570
1571         if (intel_connector->panel.downclock_mode != NULL &&
1572                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1573                         pipe_config->has_drrs = true;
1574                         intel_link_compute_m_n(bpp, lane_count,
1575                                 intel_connector->panel.downclock_mode->clock,
1576                                 pipe_config->port_clock,
1577                                 &pipe_config->dp_m2_n2);
1578         }
1579
1580         if (!HAS_DDI(dev))
1581                 intel_dp_set_clock(encoder, pipe_config);
1582
1583         return true;
1584 }
1585
1586 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1587                               const struct intel_crtc_state *pipe_config)
1588 {
1589         intel_dp->link_rate = pipe_config->port_clock;
1590         intel_dp->lane_count = pipe_config->lane_count;
1591 }
1592
1593 static void intel_dp_prepare(struct intel_encoder *encoder)
1594 {
1595         struct drm_device *dev = encoder->base.dev;
1596         struct drm_i915_private *dev_priv = dev->dev_private;
1597         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1598         enum port port = dp_to_dig_port(intel_dp)->port;
1599         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1600         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1601
1602         intel_dp_set_link_params(intel_dp, crtc->config);
1603
1604         /*
1605          * There are four kinds of DP registers:
1606          *
1607          *      IBX PCH
1608          *      SNB CPU
1609          *      IVB CPU
1610          *      CPT PCH
1611          *
1612          * IBX PCH and CPU are the same for almost everything,
1613          * except that the CPU DP PLL is configured in this
1614          * register
1615          *
1616          * CPT PCH is quite different, having many bits moved
1617          * to the TRANS_DP_CTL register instead. That
1618          * configuration happens (oddly) in ironlake_pch_enable
1619          */
1620
1621         /* Preserve the BIOS-computed detected bit. This is
1622          * supposed to be read-only.
1623          */
1624         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1625
1626         /* Handle DP bits in common between all three register formats */
1627         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1628         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1629
1630         /* Split out the IBX/CPU vs CPT settings */
1631
1632         if (IS_GEN7(dev) && port == PORT_A) {
1633                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1634                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1635                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1636                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1637                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1638
1639                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1640                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1641
1642                 intel_dp->DP |= crtc->pipe << 29;
1643         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1644                 u32 trans_dp;
1645
1646                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1647
1648                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1649                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1650                         trans_dp |= TRANS_DP_ENH_FRAMING;
1651                 else
1652                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1653                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1654         } else {
1655                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1656                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1657                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1658
1659                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1660                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1661                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1662                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1663                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1664
1665                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1666                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1667
1668                 if (IS_CHERRYVIEW(dev))
1669                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1670                 else if (crtc->pipe == PIPE_B)
1671                         intel_dp->DP |= DP_PIPEB_SELECT;
1672         }
1673 }
1674
1675 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1676 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1677
1678 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1679 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1680
1681 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1682 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1683
1684 static void wait_panel_status(struct intel_dp *intel_dp,
1685                                        u32 mask,
1686                                        u32 value)
1687 {
1688         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1691
1692         lockdep_assert_held(&dev_priv->pps_mutex);
1693
1694         pp_stat_reg = _pp_stat_reg(intel_dp);
1695         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1696
1697         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1698                         mask, value,
1699                         I915_READ(pp_stat_reg),
1700                         I915_READ(pp_ctrl_reg));
1701
1702         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1703                       5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
1704                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1705                                 I915_READ(pp_stat_reg),
1706                                 I915_READ(pp_ctrl_reg));
1707
1708         DRM_DEBUG_KMS("Wait complete\n");
1709 }
1710
1711 static void wait_panel_on(struct intel_dp *intel_dp)
1712 {
1713         DRM_DEBUG_KMS("Wait for panel power on\n");
1714         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1715 }
1716
1717 static void wait_panel_off(struct intel_dp *intel_dp)
1718 {
1719         DRM_DEBUG_KMS("Wait for panel power off time\n");
1720         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1721 }
1722
1723 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1724 {
1725         ktime_t panel_power_on_time;
1726         s64 panel_power_off_duration;
1727
1728         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1729
1730         /* take the difference of currrent time and panel power off time
1731          * and then make panel wait for t11_t12 if needed. */
1732         panel_power_on_time = ktime_get_boottime();
1733         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1734
1735         /* When we disable the VDD override bit last we have to do the manual
1736          * wait. */
1737         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1738                 wait_remaining_ms_from_jiffies(jiffies,
1739                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1740
1741         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1742 }
1743
1744 static void wait_backlight_on(struct intel_dp *intel_dp)
1745 {
1746         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1747                                        intel_dp->backlight_on_delay);
1748 }
1749
1750 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1751 {
1752         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1753                                        intel_dp->backlight_off_delay);
1754 }
1755
1756 /* Read the current pp_control value, unlocking the register if it
1757  * is locked
1758  */
1759
1760 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1761 {
1762         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1763         struct drm_i915_private *dev_priv = dev->dev_private;
1764         u32 control;
1765
1766         lockdep_assert_held(&dev_priv->pps_mutex);
1767
1768         control = I915_READ(_pp_ctrl_reg(intel_dp));
1769         if (!IS_BROXTON(dev)) {
1770                 control &= ~PANEL_UNLOCK_MASK;
1771                 control |= PANEL_UNLOCK_REGS;
1772         }
1773         return control;
1774 }
1775
1776 /*
1777  * Must be paired with edp_panel_vdd_off().
1778  * Must hold pps_mutex around the whole on/off sequence.
1779  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1780  */
1781 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1782 {
1783         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1784         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1785         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         enum intel_display_power_domain power_domain;
1788         u32 pp;
1789         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1790         bool need_to_disable = !intel_dp->want_panel_vdd;
1791
1792         lockdep_assert_held(&dev_priv->pps_mutex);
1793
1794         if (!is_edp(intel_dp))
1795                 return false;
1796
1797         cancel_delayed_work(&intel_dp->panel_vdd_work);
1798         intel_dp->want_panel_vdd = true;
1799
1800         if (edp_have_panel_vdd(intel_dp))
1801                 return need_to_disable;
1802
1803         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1804         intel_display_power_get(dev_priv, power_domain);
1805
1806         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1807                       port_name(intel_dig_port->port));
1808
1809         if (!edp_have_panel_power(intel_dp))
1810                 wait_panel_power_cycle(intel_dp);
1811
1812         pp = ironlake_get_pp_control(intel_dp);
1813         pp |= EDP_FORCE_VDD;
1814
1815         pp_stat_reg = _pp_stat_reg(intel_dp);
1816         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1817
1818         I915_WRITE(pp_ctrl_reg, pp);
1819         POSTING_READ(pp_ctrl_reg);
1820         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1821                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1822         /*
1823          * If the panel wasn't on, delay before accessing aux channel
1824          */
1825         if (!edp_have_panel_power(intel_dp)) {
1826                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1827                               port_name(intel_dig_port->port));
1828                 msleep(intel_dp->panel_power_up_delay);
1829         }
1830
1831         return need_to_disable;
1832 }
1833
1834 /*
1835  * Must be paired with intel_edp_panel_vdd_off() or
1836  * intel_edp_panel_off().
1837  * Nested calls to these functions are not allowed since
1838  * we drop the lock. Caller must use some higher level
1839  * locking to prevent nested calls from other threads.
1840  */
1841 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1842 {
1843         bool vdd;
1844
1845         if (!is_edp(intel_dp))
1846                 return;
1847
1848         pps_lock(intel_dp);
1849         vdd = edp_panel_vdd_on(intel_dp);
1850         pps_unlock(intel_dp);
1851
1852         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1853              port_name(dp_to_dig_port(intel_dp)->port));
1854 }
1855
1856 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1857 {
1858         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1859         struct drm_i915_private *dev_priv = dev->dev_private;
1860         struct intel_digital_port *intel_dig_port =
1861                 dp_to_dig_port(intel_dp);
1862         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1863         enum intel_display_power_domain power_domain;
1864         u32 pp;
1865         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1866
1867         lockdep_assert_held(&dev_priv->pps_mutex);
1868
1869         WARN_ON(intel_dp->want_panel_vdd);
1870
1871         if (!edp_have_panel_vdd(intel_dp))
1872                 return;
1873
1874         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1875                       port_name(intel_dig_port->port));
1876
1877         pp = ironlake_get_pp_control(intel_dp);
1878         pp &= ~EDP_FORCE_VDD;
1879
1880         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1881         pp_stat_reg = _pp_stat_reg(intel_dp);
1882
1883         I915_WRITE(pp_ctrl_reg, pp);
1884         POSTING_READ(pp_ctrl_reg);
1885
1886         /* Make sure sequencer is idle before allowing subsequent activity */
1887         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1888         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1889
1890         if ((pp & POWER_TARGET_ON) == 0)
1891                 intel_dp->panel_power_off_time = ktime_get_boottime();
1892
1893         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1894         intel_display_power_put(dev_priv, power_domain);
1895 }
1896
1897 static void edp_panel_vdd_work(struct work_struct *__work)
1898 {
1899         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1900                                                  struct intel_dp, panel_vdd_work);
1901
1902         pps_lock(intel_dp);
1903         if (!intel_dp->want_panel_vdd)
1904                 edp_panel_vdd_off_sync(intel_dp);
1905         pps_unlock(intel_dp);
1906 }
1907
1908 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1909 {
1910         unsigned long delay;
1911
1912         /*
1913          * Queue the timer to fire a long time from now (relative to the power
1914          * down delay) to keep the panel power up across a sequence of
1915          * operations.
1916          */
1917         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1918         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1919 }
1920
1921 /*
1922  * Must be paired with edp_panel_vdd_on().
1923  * Must hold pps_mutex around the whole on/off sequence.
1924  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1925  */
1926 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1927 {
1928         struct drm_i915_private *dev_priv =
1929                 intel_dp_to_dev(intel_dp)->dev_private;
1930
1931         lockdep_assert_held(&dev_priv->pps_mutex);
1932
1933         if (!is_edp(intel_dp))
1934                 return;
1935
1936         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1937              port_name(dp_to_dig_port(intel_dp)->port));
1938
1939         intel_dp->want_panel_vdd = false;
1940
1941         if (sync)
1942                 edp_panel_vdd_off_sync(intel_dp);
1943         else
1944                 edp_panel_vdd_schedule_off(intel_dp);
1945 }
1946
1947 static void edp_panel_on(struct intel_dp *intel_dp)
1948 {
1949         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1950         struct drm_i915_private *dev_priv = dev->dev_private;
1951         u32 pp;
1952         i915_reg_t pp_ctrl_reg;
1953
1954         lockdep_assert_held(&dev_priv->pps_mutex);
1955
1956         if (!is_edp(intel_dp))
1957                 return;
1958
1959         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1960                       port_name(dp_to_dig_port(intel_dp)->port));
1961
1962         if (WARN(edp_have_panel_power(intel_dp),
1963                  "eDP port %c panel power already on\n",
1964                  port_name(dp_to_dig_port(intel_dp)->port)))
1965                 return;
1966
1967         wait_panel_power_cycle(intel_dp);
1968
1969         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1970         pp = ironlake_get_pp_control(intel_dp);
1971         if (IS_GEN5(dev)) {
1972                 /* ILK workaround: disable reset around power sequence */
1973                 pp &= ~PANEL_POWER_RESET;
1974                 I915_WRITE(pp_ctrl_reg, pp);
1975                 POSTING_READ(pp_ctrl_reg);
1976         }
1977
1978         pp |= POWER_TARGET_ON;
1979         if (!IS_GEN5(dev))
1980                 pp |= PANEL_POWER_RESET;
1981
1982         I915_WRITE(pp_ctrl_reg, pp);
1983         POSTING_READ(pp_ctrl_reg);
1984
1985         wait_panel_on(intel_dp);
1986         intel_dp->last_power_on = jiffies;
1987
1988         if (IS_GEN5(dev)) {
1989                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1990                 I915_WRITE(pp_ctrl_reg, pp);
1991                 POSTING_READ(pp_ctrl_reg);
1992         }
1993 }
1994
1995 void intel_edp_panel_on(struct intel_dp *intel_dp)
1996 {
1997         if (!is_edp(intel_dp))
1998                 return;
1999
2000         pps_lock(intel_dp);
2001         edp_panel_on(intel_dp);
2002         pps_unlock(intel_dp);
2003 }
2004
2005
2006 static void edp_panel_off(struct intel_dp *intel_dp)
2007 {
2008         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2009         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2010         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2011         struct drm_i915_private *dev_priv = dev->dev_private;
2012         enum intel_display_power_domain power_domain;
2013         u32 pp;
2014         i915_reg_t pp_ctrl_reg;
2015
2016         lockdep_assert_held(&dev_priv->pps_mutex);
2017
2018         if (!is_edp(intel_dp))
2019                 return;
2020
2021         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2022                       port_name(dp_to_dig_port(intel_dp)->port));
2023
2024         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2025              port_name(dp_to_dig_port(intel_dp)->port));
2026
2027         pp = ironlake_get_pp_control(intel_dp);
2028         /* We need to switch off panel power _and_ force vdd, for otherwise some
2029          * panels get very unhappy and cease to work. */
2030         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2031                 EDP_BLC_ENABLE);
2032
2033         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2034
2035         intel_dp->want_panel_vdd = false;
2036
2037         I915_WRITE(pp_ctrl_reg, pp);
2038         POSTING_READ(pp_ctrl_reg);
2039
2040         intel_dp->panel_power_off_time = ktime_get_boottime();
2041         wait_panel_off(intel_dp);
2042
2043         /* We got a reference when we enabled the VDD. */
2044         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2045         intel_display_power_put(dev_priv, power_domain);
2046 }
2047
2048 void intel_edp_panel_off(struct intel_dp *intel_dp)
2049 {
2050         if (!is_edp(intel_dp))
2051                 return;
2052
2053         pps_lock(intel_dp);
2054         edp_panel_off(intel_dp);
2055         pps_unlock(intel_dp);
2056 }
2057
2058 /* Enable backlight in the panel power control. */
2059 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2060 {
2061         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2062         struct drm_device *dev = intel_dig_port->base.base.dev;
2063         struct drm_i915_private *dev_priv = dev->dev_private;
2064         u32 pp;
2065         i915_reg_t pp_ctrl_reg;
2066
2067         /*
2068          * If we enable the backlight right away following a panel power
2069          * on, we may see slight flicker as the panel syncs with the eDP
2070          * link.  So delay a bit to make sure the image is solid before
2071          * allowing it to appear.
2072          */
2073         wait_backlight_on(intel_dp);
2074
2075         pps_lock(intel_dp);
2076
2077         pp = ironlake_get_pp_control(intel_dp);
2078         pp |= EDP_BLC_ENABLE;
2079
2080         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2081
2082         I915_WRITE(pp_ctrl_reg, pp);
2083         POSTING_READ(pp_ctrl_reg);
2084
2085         pps_unlock(intel_dp);
2086 }
2087
2088 /* Enable backlight PWM and backlight PP control. */
2089 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2090 {
2091         if (!is_edp(intel_dp))
2092                 return;
2093
2094         DRM_DEBUG_KMS("\n");
2095
2096         intel_panel_enable_backlight(intel_dp->attached_connector);
2097         _intel_edp_backlight_on(intel_dp);
2098 }
2099
2100 /* Disable backlight in the panel power control. */
2101 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2102 {
2103         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2104         struct drm_i915_private *dev_priv = dev->dev_private;
2105         u32 pp;
2106         i915_reg_t pp_ctrl_reg;
2107
2108         if (!is_edp(intel_dp))
2109                 return;
2110
2111         pps_lock(intel_dp);
2112
2113         pp = ironlake_get_pp_control(intel_dp);
2114         pp &= ~EDP_BLC_ENABLE;
2115
2116         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2117
2118         I915_WRITE(pp_ctrl_reg, pp);
2119         POSTING_READ(pp_ctrl_reg);
2120
2121         pps_unlock(intel_dp);
2122
2123         intel_dp->last_backlight_off = jiffies;
2124         edp_wait_backlight_off(intel_dp);
2125 }
2126
2127 /* Disable backlight PP control and backlight PWM. */
2128 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2129 {
2130         if (!is_edp(intel_dp))
2131                 return;
2132
2133         DRM_DEBUG_KMS("\n");
2134
2135         _intel_edp_backlight_off(intel_dp);
2136         intel_panel_disable_backlight(intel_dp->attached_connector);
2137 }
2138
2139 /*
2140  * Hook for controlling the panel power control backlight through the bl_power
2141  * sysfs attribute. Take care to handle multiple calls.
2142  */
2143 static void intel_edp_backlight_power(struct intel_connector *connector,
2144                                       bool enable)
2145 {
2146         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2147         bool is_enabled;
2148
2149         pps_lock(intel_dp);
2150         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2151         pps_unlock(intel_dp);
2152
2153         if (is_enabled == enable)
2154                 return;
2155
2156         DRM_DEBUG_KMS("panel power control backlight %s\n",
2157                       enable ? "enable" : "disable");
2158
2159         if (enable)
2160                 _intel_edp_backlight_on(intel_dp);
2161         else
2162                 _intel_edp_backlight_off(intel_dp);
2163 }
2164
2165 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2166 {
2167         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2168         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2169         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2170
2171         I915_STATE_WARN(cur_state != state,
2172                         "DP port %c state assertion failure (expected %s, current %s)\n",
2173                         port_name(dig_port->port),
2174                         onoff(state), onoff(cur_state));
2175 }
2176 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2177
2178 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2179 {
2180         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2181
2182         I915_STATE_WARN(cur_state != state,
2183                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2184                         onoff(state), onoff(cur_state));
2185 }
2186 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2187 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2188
2189 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2190 {
2191         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2192         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2193         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2194
2195         assert_pipe_disabled(dev_priv, crtc->pipe);
2196         assert_dp_port_disabled(intel_dp);
2197         assert_edp_pll_disabled(dev_priv);
2198
2199         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2200                       crtc->config->port_clock);
2201
2202         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2203
2204         if (crtc->config->port_clock == 162000)
2205                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2206         else
2207                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2208
2209         I915_WRITE(DP_A, intel_dp->DP);
2210         POSTING_READ(DP_A);
2211         udelay(500);
2212
2213         /*
2214          * [DevILK] Work around required when enabling DP PLL
2215          * while a pipe is enabled going to FDI:
2216          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2217          * 2. Program DP PLL enable
2218          */
2219         if (IS_GEN5(dev_priv))
2220                 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2221
2222         intel_dp->DP |= DP_PLL_ENABLE;
2223
2224         I915_WRITE(DP_A, intel_dp->DP);
2225         POSTING_READ(DP_A);
2226         udelay(200);
2227 }
2228
2229 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2230 {
2231         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2232         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2233         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2234
2235         assert_pipe_disabled(dev_priv, crtc->pipe);
2236         assert_dp_port_disabled(intel_dp);
2237         assert_edp_pll_enabled(dev_priv);
2238
2239         DRM_DEBUG_KMS("disabling eDP PLL\n");
2240
2241         intel_dp->DP &= ~DP_PLL_ENABLE;
2242
2243         I915_WRITE(DP_A, intel_dp->DP);
2244         POSTING_READ(DP_A);
2245         udelay(200);
2246 }
2247
2248 /* If the sink supports it, try to set the power state appropriately */
2249 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2250 {
2251         int ret, i;
2252
2253         /* Should have a valid DPCD by this point */
2254         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2255                 return;
2256
2257         if (mode != DRM_MODE_DPMS_ON) {
2258                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2259                                          DP_SET_POWER_D3);
2260         } else {
2261                 /*
2262                  * When turning on, we need to retry for 1ms to give the sink
2263                  * time to wake up.
2264                  */
2265                 for (i = 0; i < 3; i++) {
2266                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2267                                                  DP_SET_POWER_D0);
2268                         if (ret == 1)
2269                                 break;
2270                         msleep(1);
2271                 }
2272         }
2273
2274         if (ret != 1)
2275                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2276                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2277 }
2278
2279 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2280                                   enum pipe *pipe)
2281 {
2282         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2283         enum port port = dp_to_dig_port(intel_dp)->port;
2284         struct drm_device *dev = encoder->base.dev;
2285         struct drm_i915_private *dev_priv = dev->dev_private;
2286         enum intel_display_power_domain power_domain;
2287         u32 tmp;
2288         bool ret;
2289
2290         power_domain = intel_display_port_power_domain(encoder);
2291         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2292                 return false;
2293
2294         ret = false;
2295
2296         tmp = I915_READ(intel_dp->output_reg);
2297
2298         if (!(tmp & DP_PORT_EN))
2299                 goto out;
2300
2301         if (IS_GEN7(dev) && port == PORT_A) {
2302                 *pipe = PORT_TO_PIPE_CPT(tmp);
2303         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2304                 enum pipe p;
2305
2306                 for_each_pipe(dev_priv, p) {
2307                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2308                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2309                                 *pipe = p;
2310                                 ret = true;
2311
2312                                 goto out;
2313                         }
2314                 }
2315
2316                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2317                               i915_mmio_reg_offset(intel_dp->output_reg));
2318         } else if (IS_CHERRYVIEW(dev)) {
2319                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2320         } else {
2321                 *pipe = PORT_TO_PIPE(tmp);
2322         }
2323
2324         ret = true;
2325
2326 out:
2327         intel_display_power_put(dev_priv, power_domain);
2328
2329         return ret;
2330 }
2331
2332 static void intel_dp_get_config(struct intel_encoder *encoder,
2333                                 struct intel_crtc_state *pipe_config)
2334 {
2335         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2336         u32 tmp, flags = 0;
2337         struct drm_device *dev = encoder->base.dev;
2338         struct drm_i915_private *dev_priv = dev->dev_private;
2339         enum port port = dp_to_dig_port(intel_dp)->port;
2340         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2341
2342         tmp = I915_READ(intel_dp->output_reg);
2343
2344         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2345
2346         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2347                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2348
2349                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2350                         flags |= DRM_MODE_FLAG_PHSYNC;
2351                 else
2352                         flags |= DRM_MODE_FLAG_NHSYNC;
2353
2354                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2355                         flags |= DRM_MODE_FLAG_PVSYNC;
2356                 else
2357                         flags |= DRM_MODE_FLAG_NVSYNC;
2358         } else {
2359                 if (tmp & DP_SYNC_HS_HIGH)
2360                         flags |= DRM_MODE_FLAG_PHSYNC;
2361                 else
2362                         flags |= DRM_MODE_FLAG_NHSYNC;
2363
2364                 if (tmp & DP_SYNC_VS_HIGH)
2365                         flags |= DRM_MODE_FLAG_PVSYNC;
2366                 else
2367                         flags |= DRM_MODE_FLAG_NVSYNC;
2368         }
2369
2370         pipe_config->base.adjusted_mode.flags |= flags;
2371
2372         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2373             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2374                 pipe_config->limited_color_range = true;
2375
2376         pipe_config->has_dp_encoder = true;
2377
2378         pipe_config->lane_count =
2379                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2380
2381         intel_dp_get_m_n(crtc, pipe_config);
2382
2383         if (port == PORT_A) {
2384                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2385                         pipe_config->port_clock = 162000;
2386                 else
2387                         pipe_config->port_clock = 270000;
2388         }
2389
2390         pipe_config->base.adjusted_mode.crtc_clock =
2391                 intel_dotclock_calculate(pipe_config->port_clock,
2392                                          &pipe_config->dp_m_n);
2393
2394         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2395             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2396                 /*
2397                  * This is a big fat ugly hack.
2398                  *
2399                  * Some machines in UEFI boot mode provide us a VBT that has 18
2400                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2401                  * unknown we fail to light up. Yet the same BIOS boots up with
2402                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2403                  * max, not what it tells us to use.
2404                  *
2405                  * Note: This will still be broken if the eDP panel is not lit
2406                  * up by the BIOS, and thus we can't get the mode at module
2407                  * load.
2408                  */
2409                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2410                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2411                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2412         }
2413 }
2414
2415 static void intel_disable_dp(struct intel_encoder *encoder)
2416 {
2417         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2418         struct drm_device *dev = encoder->base.dev;
2419         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2420
2421         if (crtc->config->has_audio)
2422                 intel_audio_codec_disable(encoder);
2423
2424         if (HAS_PSR(dev) && !HAS_DDI(dev))
2425                 intel_psr_disable(intel_dp);
2426
2427         /* Make sure the panel is off before trying to change the mode. But also
2428          * ensure that we have vdd while we switch off the panel. */
2429         intel_edp_panel_vdd_on(intel_dp);
2430         intel_edp_backlight_off(intel_dp);
2431         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2432         intel_edp_panel_off(intel_dp);
2433
2434         /* disable the port before the pipe on g4x */
2435         if (INTEL_INFO(dev)->gen < 5)
2436                 intel_dp_link_down(intel_dp);
2437 }
2438
2439 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2440 {
2441         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2442         enum port port = dp_to_dig_port(intel_dp)->port;
2443
2444         intel_dp_link_down(intel_dp);
2445
2446         /* Only ilk+ has port A */
2447         if (port == PORT_A)
2448                 ironlake_edp_pll_off(intel_dp);
2449 }
2450
2451 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2452 {
2453         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2454
2455         intel_dp_link_down(intel_dp);
2456 }
2457
2458 static void chv_post_disable_dp(struct intel_encoder *encoder)
2459 {
2460         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2461         struct drm_device *dev = encoder->base.dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463
2464         intel_dp_link_down(intel_dp);
2465
2466         mutex_lock(&dev_priv->sb_lock);
2467
2468         /* Assert data lane reset */
2469         chv_data_lane_soft_reset(encoder, true);
2470
2471         mutex_unlock(&dev_priv->sb_lock);
2472 }
2473
2474 static void
2475 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2476                          uint32_t *DP,
2477                          uint8_t dp_train_pat)
2478 {
2479         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2480         struct drm_device *dev = intel_dig_port->base.base.dev;
2481         struct drm_i915_private *dev_priv = dev->dev_private;
2482         enum port port = intel_dig_port->port;
2483
2484         if (HAS_DDI(dev)) {
2485                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2486
2487                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2488                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2489                 else
2490                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2491
2492                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2493                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2494                 case DP_TRAINING_PATTERN_DISABLE:
2495                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2496
2497                         break;
2498                 case DP_TRAINING_PATTERN_1:
2499                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2500                         break;
2501                 case DP_TRAINING_PATTERN_2:
2502                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2503                         break;
2504                 case DP_TRAINING_PATTERN_3:
2505                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2506                         break;
2507                 }
2508                 I915_WRITE(DP_TP_CTL(port), temp);
2509
2510         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2511                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2512                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2513
2514                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2515                 case DP_TRAINING_PATTERN_DISABLE:
2516                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2517                         break;
2518                 case DP_TRAINING_PATTERN_1:
2519                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2520                         break;
2521                 case DP_TRAINING_PATTERN_2:
2522                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2523                         break;
2524                 case DP_TRAINING_PATTERN_3:
2525                         DRM_ERROR("DP training pattern 3 not supported\n");
2526                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2527                         break;
2528                 }
2529
2530         } else {
2531                 if (IS_CHERRYVIEW(dev))
2532                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2533                 else
2534                         *DP &= ~DP_LINK_TRAIN_MASK;
2535
2536                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2537                 case DP_TRAINING_PATTERN_DISABLE:
2538                         *DP |= DP_LINK_TRAIN_OFF;
2539                         break;
2540                 case DP_TRAINING_PATTERN_1:
2541                         *DP |= DP_LINK_TRAIN_PAT_1;
2542                         break;
2543                 case DP_TRAINING_PATTERN_2:
2544                         *DP |= DP_LINK_TRAIN_PAT_2;
2545                         break;
2546                 case DP_TRAINING_PATTERN_3:
2547                         if (IS_CHERRYVIEW(dev)) {
2548                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2549                         } else {
2550                                 DRM_ERROR("DP training pattern 3 not supported\n");
2551                                 *DP |= DP_LINK_TRAIN_PAT_2;
2552                         }
2553                         break;
2554                 }
2555         }
2556 }
2557
2558 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2559 {
2560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         struct intel_crtc *crtc =
2563                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2564
2565         /* enable with pattern 1 (as per spec) */
2566         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2567                                  DP_TRAINING_PATTERN_1);
2568
2569         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2570         POSTING_READ(intel_dp->output_reg);
2571
2572         /*
2573          * Magic for VLV/CHV. We _must_ first set up the register
2574          * without actually enabling the port, and then do another
2575          * write to enable the port. Otherwise link training will
2576          * fail when the power sequencer is freshly used for this port.
2577          */
2578         intel_dp->DP |= DP_PORT_EN;
2579         if (crtc->config->has_audio)
2580                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2581
2582         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2583         POSTING_READ(intel_dp->output_reg);
2584 }
2585
2586 static void intel_enable_dp(struct intel_encoder *encoder)
2587 {
2588         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2589         struct drm_device *dev = encoder->base.dev;
2590         struct drm_i915_private *dev_priv = dev->dev_private;
2591         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2592         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2593         enum pipe pipe = crtc->pipe;
2594
2595         if (WARN_ON(dp_reg & DP_PORT_EN))
2596                 return;
2597
2598         pps_lock(intel_dp);
2599
2600         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2601                 vlv_init_panel_power_sequencer(intel_dp);
2602
2603         intel_dp_enable_port(intel_dp);
2604
2605         edp_panel_vdd_on(intel_dp);
2606         edp_panel_on(intel_dp);
2607         edp_panel_vdd_off(intel_dp, true);
2608
2609         pps_unlock(intel_dp);
2610
2611         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2612                 unsigned int lane_mask = 0x0;
2613
2614                 if (IS_CHERRYVIEW(dev))
2615                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2616
2617                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2618                                     lane_mask);
2619         }
2620
2621         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2622         intel_dp_start_link_train(intel_dp);
2623         intel_dp_stop_link_train(intel_dp);
2624
2625         if (crtc->config->has_audio) {
2626                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2627                                  pipe_name(pipe));
2628                 intel_audio_codec_enable(encoder);
2629         }
2630 }
2631
2632 static void g4x_enable_dp(struct intel_encoder *encoder)
2633 {
2634         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2635
2636         intel_enable_dp(encoder);
2637         intel_edp_backlight_on(intel_dp);
2638 }
2639
2640 static void vlv_enable_dp(struct intel_encoder *encoder)
2641 {
2642         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2643
2644         intel_edp_backlight_on(intel_dp);
2645         intel_psr_enable(intel_dp);
2646 }
2647
2648 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2649 {
2650         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2651         enum port port = dp_to_dig_port(intel_dp)->port;
2652
2653         intel_dp_prepare(encoder);
2654
2655         /* Only ilk+ has port A */
2656         if (port == PORT_A)
2657                 ironlake_edp_pll_on(intel_dp);
2658 }
2659
2660 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2661 {
2662         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2663         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2664         enum pipe pipe = intel_dp->pps_pipe;
2665         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2666
2667         edp_panel_vdd_off_sync(intel_dp);
2668
2669         /*
2670          * VLV seems to get confused when multiple power seqeuencers
2671          * have the same port selected (even if only one has power/vdd
2672          * enabled). The failure manifests as vlv_wait_port_ready() failing
2673          * CHV on the other hand doesn't seem to mind having the same port
2674          * selected in multiple power seqeuencers, but let's clear the
2675          * port select always when logically disconnecting a power sequencer
2676          * from a port.
2677          */
2678         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2679                       pipe_name(pipe), port_name(intel_dig_port->port));
2680         I915_WRITE(pp_on_reg, 0);
2681         POSTING_READ(pp_on_reg);
2682
2683         intel_dp->pps_pipe = INVALID_PIPE;
2684 }
2685
2686 static void vlv_steal_power_sequencer(struct drm_device *dev,
2687                                       enum pipe pipe)
2688 {
2689         struct drm_i915_private *dev_priv = dev->dev_private;
2690         struct intel_encoder *encoder;
2691
2692         lockdep_assert_held(&dev_priv->pps_mutex);
2693
2694         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2695                 return;
2696
2697         for_each_intel_encoder(dev, encoder) {
2698                 struct intel_dp *intel_dp;
2699                 enum port port;
2700
2701                 if (encoder->type != INTEL_OUTPUT_EDP)
2702                         continue;
2703
2704                 intel_dp = enc_to_intel_dp(&encoder->base);
2705                 port = dp_to_dig_port(intel_dp)->port;
2706
2707                 if (intel_dp->pps_pipe != pipe)
2708                         continue;
2709
2710                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2711                               pipe_name(pipe), port_name(port));
2712
2713                 WARN(encoder->base.crtc,
2714                      "stealing pipe %c power sequencer from active eDP port %c\n",
2715                      pipe_name(pipe), port_name(port));
2716
2717                 /* make sure vdd is off before we steal it */
2718                 vlv_detach_power_sequencer(intel_dp);
2719         }
2720 }
2721
2722 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2723 {
2724         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2725         struct intel_encoder *encoder = &intel_dig_port->base;
2726         struct drm_device *dev = encoder->base.dev;
2727         struct drm_i915_private *dev_priv = dev->dev_private;
2728         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2729
2730         lockdep_assert_held(&dev_priv->pps_mutex);
2731
2732         if (!is_edp(intel_dp))
2733                 return;
2734
2735         if (intel_dp->pps_pipe == crtc->pipe)
2736                 return;
2737
2738         /*
2739          * If another power sequencer was being used on this
2740          * port previously make sure to turn off vdd there while
2741          * we still have control of it.
2742          */
2743         if (intel_dp->pps_pipe != INVALID_PIPE)
2744                 vlv_detach_power_sequencer(intel_dp);
2745
2746         /*
2747          * We may be stealing the power
2748          * sequencer from another port.
2749          */
2750         vlv_steal_power_sequencer(dev, crtc->pipe);
2751
2752         /* now it's all ours */
2753         intel_dp->pps_pipe = crtc->pipe;
2754
2755         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2756                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2757
2758         /* init power sequencer on this pipe and port */
2759         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2760         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2761 }
2762
2763 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2764 {
2765         vlv_phy_pre_encoder_enable(encoder);
2766
2767         intel_enable_dp(encoder);
2768 }
2769
2770 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2771 {
2772         intel_dp_prepare(encoder);
2773
2774         vlv_phy_pre_pll_enable(encoder);
2775 }
2776
2777 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2778 {
2779         chv_phy_pre_encoder_enable(encoder);
2780
2781         intel_enable_dp(encoder);
2782
2783         /* Second common lane will stay alive on its own now */
2784         chv_phy_release_cl2_override(encoder);
2785 }
2786
2787 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2788 {
2789         intel_dp_prepare(encoder);
2790
2791         chv_phy_pre_pll_enable(encoder);
2792 }
2793
2794 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2795 {
2796         chv_phy_post_pll_disable(encoder);
2797 }
2798
2799 /*
2800  * Fetch AUX CH registers 0x202 - 0x207 which contain
2801  * link status information
2802  */
2803 bool
2804 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2805 {
2806         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2807                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2808 }
2809
2810 /* These are source-specific values. */
2811 uint8_t
2812 intel_dp_voltage_max(struct intel_dp *intel_dp)
2813 {
2814         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2815         struct drm_i915_private *dev_priv = dev->dev_private;
2816         enum port port = dp_to_dig_port(intel_dp)->port;
2817
2818         if (IS_BROXTON(dev))
2819                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2820         else if (INTEL_INFO(dev)->gen >= 9) {
2821                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2822                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2823                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2824         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2825                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2826         else if (IS_GEN7(dev) && port == PORT_A)
2827                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2828         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2829                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2830         else
2831                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2832 }
2833
2834 uint8_t
2835 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2836 {
2837         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2838         enum port port = dp_to_dig_port(intel_dp)->port;
2839
2840         if (INTEL_INFO(dev)->gen >= 9) {
2841                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2842                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2843                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2844                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2845                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2846                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2847                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2848                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2849                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2850                 default:
2851                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2852                 }
2853         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2854                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2855                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2856                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2857                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2858                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2859                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2860                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2861                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2862                 default:
2863                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2864                 }
2865         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2866                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2867                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2868                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2869                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2870                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2871                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2872                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2873                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2874                 default:
2875                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2876                 }
2877         } else if (IS_GEN7(dev) && port == PORT_A) {
2878                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2879                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2880                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2881                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2882                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2883                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2884                 default:
2885                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2886                 }
2887         } else {
2888                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2889                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2890                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2891                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2892                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
2893                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2894                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
2895                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2896                 default:
2897                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
2898                 }
2899         }
2900 }
2901
2902 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
2903 {
2904         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2905         unsigned long demph_reg_value, preemph_reg_value,
2906                 uniqtranscale_reg_value;
2907         uint8_t train_set = intel_dp->train_set[0];
2908
2909         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2910         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2911                 preemph_reg_value = 0x0004000;
2912                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2913                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2914                         demph_reg_value = 0x2B405555;
2915                         uniqtranscale_reg_value = 0x552AB83A;
2916                         break;
2917                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2918                         demph_reg_value = 0x2B404040;
2919                         uniqtranscale_reg_value = 0x5548B83A;
2920                         break;
2921                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2922                         demph_reg_value = 0x2B245555;
2923                         uniqtranscale_reg_value = 0x5560B83A;
2924                         break;
2925                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2926                         demph_reg_value = 0x2B405555;
2927                         uniqtranscale_reg_value = 0x5598DA3A;
2928                         break;
2929                 default:
2930                         return 0;
2931                 }
2932                 break;
2933         case DP_TRAIN_PRE_EMPH_LEVEL_1:
2934                 preemph_reg_value = 0x0002000;
2935                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2936                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2937                         demph_reg_value = 0x2B404040;
2938                         uniqtranscale_reg_value = 0x5552B83A;
2939                         break;
2940                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2941                         demph_reg_value = 0x2B404848;
2942                         uniqtranscale_reg_value = 0x5580B83A;
2943                         break;
2944                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2945                         demph_reg_value = 0x2B404040;
2946                         uniqtranscale_reg_value = 0x55ADDA3A;
2947                         break;
2948                 default:
2949                         return 0;
2950                 }
2951                 break;
2952         case DP_TRAIN_PRE_EMPH_LEVEL_2:
2953                 preemph_reg_value = 0x0000000;
2954                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2955                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2956                         demph_reg_value = 0x2B305555;
2957                         uniqtranscale_reg_value = 0x5570B83A;
2958                         break;
2959                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2960                         demph_reg_value = 0x2B2B4040;
2961                         uniqtranscale_reg_value = 0x55ADDA3A;
2962                         break;
2963                 default:
2964                         return 0;
2965                 }
2966                 break;
2967         case DP_TRAIN_PRE_EMPH_LEVEL_3:
2968                 preemph_reg_value = 0x0006000;
2969                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2970                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971                         demph_reg_value = 0x1B405555;
2972                         uniqtranscale_reg_value = 0x55ADDA3A;
2973                         break;
2974                 default:
2975                         return 0;
2976                 }
2977                 break;
2978         default:
2979                 return 0;
2980         }
2981
2982         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
2983                                  uniqtranscale_reg_value, 0);
2984
2985         return 0;
2986 }
2987
2988 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
2989 {
2990         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2991         u32 deemph_reg_value, margin_reg_value;
2992         bool uniq_trans_scale = false;
2993         uint8_t train_set = intel_dp->train_set[0];
2994
2995         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2996         case DP_TRAIN_PRE_EMPH_LEVEL_0:
2997                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2998                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2999                         deemph_reg_value = 128;
3000                         margin_reg_value = 52;
3001                         break;
3002                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3003                         deemph_reg_value = 128;
3004                         margin_reg_value = 77;
3005                         break;
3006                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3007                         deemph_reg_value = 128;
3008                         margin_reg_value = 102;
3009                         break;
3010                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3011                         deemph_reg_value = 128;
3012                         margin_reg_value = 154;
3013                         uniq_trans_scale = true;
3014                         break;
3015                 default:
3016                         return 0;
3017                 }
3018                 break;
3019         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3020                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3021                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3022                         deemph_reg_value = 85;
3023                         margin_reg_value = 78;
3024                         break;
3025                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3026                         deemph_reg_value = 85;
3027                         margin_reg_value = 116;
3028                         break;
3029                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3030                         deemph_reg_value = 85;
3031                         margin_reg_value = 154;
3032                         break;
3033                 default:
3034                         return 0;
3035                 }
3036                 break;
3037         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3038                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3039                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3040                         deemph_reg_value = 64;
3041                         margin_reg_value = 104;
3042                         break;
3043                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3044                         deemph_reg_value = 64;
3045                         margin_reg_value = 154;
3046                         break;
3047                 default:
3048                         return 0;
3049                 }
3050                 break;
3051         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3052                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3053                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3054                         deemph_reg_value = 43;
3055                         margin_reg_value = 154;
3056                         break;
3057                 default:
3058                         return 0;
3059                 }
3060                 break;
3061         default:
3062                 return 0;
3063         }
3064
3065         chv_set_phy_signal_level(encoder, deemph_reg_value,
3066                                  margin_reg_value, uniq_trans_scale);
3067
3068         return 0;
3069 }
3070
3071 static uint32_t
3072 gen4_signal_levels(uint8_t train_set)
3073 {
3074         uint32_t        signal_levels = 0;
3075
3076         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3077         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3078         default:
3079                 signal_levels |= DP_VOLTAGE_0_4;
3080                 break;
3081         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3082                 signal_levels |= DP_VOLTAGE_0_6;
3083                 break;
3084         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3085                 signal_levels |= DP_VOLTAGE_0_8;
3086                 break;
3087         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3088                 signal_levels |= DP_VOLTAGE_1_2;
3089                 break;
3090         }
3091         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3092         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3093         default:
3094                 signal_levels |= DP_PRE_EMPHASIS_0;
3095                 break;
3096         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3097                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3098                 break;
3099         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3100                 signal_levels |= DP_PRE_EMPHASIS_6;
3101                 break;
3102         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3103                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3104                 break;
3105         }
3106         return signal_levels;
3107 }
3108
3109 /* Gen6's DP voltage swing and pre-emphasis control */
3110 static uint32_t
3111 gen6_edp_signal_levels(uint8_t train_set)
3112 {
3113         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3114                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3115         switch (signal_levels) {
3116         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3117         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3118                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3119         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3120                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3121         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3122         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3123                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3124         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3125         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3126                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3127         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3128         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3129                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3130         default:
3131                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3132                               "0x%x\n", signal_levels);
3133                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3134         }
3135 }
3136
3137 /* Gen7's DP voltage swing and pre-emphasis control */
3138 static uint32_t
3139 gen7_edp_signal_levels(uint8_t train_set)
3140 {
3141         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3142                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3143         switch (signal_levels) {
3144         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3145                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3146         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3147                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3148         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3149                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3150
3151         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3152                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3153         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3154                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3155
3156         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3157                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3158         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3159                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3160
3161         default:
3162                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3163                               "0x%x\n", signal_levels);
3164                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3165         }
3166 }
3167
3168 void
3169 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3170 {
3171         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3172         enum port port = intel_dig_port->port;
3173         struct drm_device *dev = intel_dig_port->base.base.dev;
3174         struct drm_i915_private *dev_priv = to_i915(dev);
3175         uint32_t signal_levels, mask = 0;
3176         uint8_t train_set = intel_dp->train_set[0];
3177
3178         if (HAS_DDI(dev)) {
3179                 signal_levels = ddi_signal_levels(intel_dp);
3180
3181                 if (IS_BROXTON(dev))
3182                         signal_levels = 0;
3183                 else
3184                         mask = DDI_BUF_EMP_MASK;
3185         } else if (IS_CHERRYVIEW(dev)) {
3186                 signal_levels = chv_signal_levels(intel_dp);
3187         } else if (IS_VALLEYVIEW(dev)) {
3188                 signal_levels = vlv_signal_levels(intel_dp);
3189         } else if (IS_GEN7(dev) && port == PORT_A) {
3190                 signal_levels = gen7_edp_signal_levels(train_set);
3191                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3192         } else if (IS_GEN6(dev) && port == PORT_A) {
3193                 signal_levels = gen6_edp_signal_levels(train_set);
3194                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3195         } else {
3196                 signal_levels = gen4_signal_levels(train_set);
3197                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3198         }
3199
3200         if (mask)
3201                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3202
3203         DRM_DEBUG_KMS("Using vswing level %d\n",
3204                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3205         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3206                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3207                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3208
3209         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3210
3211         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3212         POSTING_READ(intel_dp->output_reg);
3213 }
3214
3215 void
3216 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3217                                        uint8_t dp_train_pat)
3218 {
3219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3220         struct drm_i915_private *dev_priv =
3221                 to_i915(intel_dig_port->base.base.dev);
3222
3223         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3224
3225         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3226         POSTING_READ(intel_dp->output_reg);
3227 }
3228
3229 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3230 {
3231         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3232         struct drm_device *dev = intel_dig_port->base.base.dev;
3233         struct drm_i915_private *dev_priv = dev->dev_private;
3234         enum port port = intel_dig_port->port;
3235         uint32_t val;
3236
3237         if (!HAS_DDI(dev))
3238                 return;
3239
3240         val = I915_READ(DP_TP_CTL(port));
3241         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3242         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3243         I915_WRITE(DP_TP_CTL(port), val);
3244
3245         /*
3246          * On PORT_A we can have only eDP in SST mode. There the only reason
3247          * we need to set idle transmission mode is to work around a HW issue
3248          * where we enable the pipe while not in idle link-training mode.
3249          * In this case there is requirement to wait for a minimum number of
3250          * idle patterns to be sent.
3251          */
3252         if (port == PORT_A)
3253                 return;
3254
3255         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3256                      1))
3257                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3258 }
3259
3260 static void
3261 intel_dp_link_down(struct intel_dp *intel_dp)
3262 {
3263         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3264         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3265         enum port port = intel_dig_port->port;
3266         struct drm_device *dev = intel_dig_port->base.base.dev;
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         uint32_t DP = intel_dp->DP;
3269
3270         if (WARN_ON(HAS_DDI(dev)))
3271                 return;
3272
3273         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3274                 return;
3275
3276         DRM_DEBUG_KMS("\n");
3277
3278         if ((IS_GEN7(dev) && port == PORT_A) ||
3279             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3280                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3281                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3282         } else {
3283                 if (IS_CHERRYVIEW(dev))
3284                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3285                 else
3286                         DP &= ~DP_LINK_TRAIN_MASK;
3287                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3288         }
3289         I915_WRITE(intel_dp->output_reg, DP);
3290         POSTING_READ(intel_dp->output_reg);
3291
3292         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3293         I915_WRITE(intel_dp->output_reg, DP);
3294         POSTING_READ(intel_dp->output_reg);
3295
3296         /*
3297          * HW workaround for IBX, we need to move the port
3298          * to transcoder A after disabling it to allow the
3299          * matching HDMI port to be enabled on transcoder A.
3300          */
3301         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3302                 /*
3303                  * We get CPU/PCH FIFO underruns on the other pipe when
3304                  * doing the workaround. Sweep them under the rug.
3305                  */
3306                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3307                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3308
3309                 /* always enable with pattern 1 (as per spec) */
3310                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3311                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3312                 I915_WRITE(intel_dp->output_reg, DP);
3313                 POSTING_READ(intel_dp->output_reg);
3314
3315                 DP &= ~DP_PORT_EN;
3316                 I915_WRITE(intel_dp->output_reg, DP);
3317                 POSTING_READ(intel_dp->output_reg);
3318
3319                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3320                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3321                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3322         }
3323
3324         msleep(intel_dp->panel_power_down_delay);
3325
3326         intel_dp->DP = DP;
3327 }
3328
3329 static bool
3330 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3331 {
3332         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3333         struct drm_device *dev = dig_port->base.base.dev;
3334         struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3337                              sizeof(intel_dp->dpcd)) < 0)
3338                 return false; /* aux transfer failed */
3339
3340         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3341
3342         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3343                 return false; /* DPCD not present */
3344
3345         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3346                              &intel_dp->sink_count, 1) < 0)
3347                 return false;
3348
3349         /*
3350          * Sink count can change between short pulse hpd hence
3351          * a member variable in intel_dp will track any changes
3352          * between short pulse interrupts.
3353          */
3354         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3355
3356         /*
3357          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3358          * a dongle is present but no display. Unless we require to know
3359          * if a dongle is present or not, we don't need to update
3360          * downstream port information. So, an early return here saves
3361          * time from performing other operations which are not required.
3362          */
3363         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3364                 return false;
3365
3366         /* Check if the panel supports PSR */
3367         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3368         if (is_edp(intel_dp)) {
3369                 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3370                                  intel_dp->psr_dpcd,
3371                                  sizeof(intel_dp->psr_dpcd));
3372                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3373                         dev_priv->psr.sink_support = true;
3374                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3375                 }
3376
3377                 if (INTEL_INFO(dev)->gen >= 9 &&
3378                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3379                         uint8_t frame_sync_cap;
3380
3381                         dev_priv->psr.sink_support = true;
3382                         drm_dp_dpcd_read(&intel_dp->aux,
3383                                          DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3384                                          &frame_sync_cap, 1);
3385                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3386                         /* PSR2 needs frame sync as well */
3387                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3388                         DRM_DEBUG_KMS("PSR2 %s on sink",
3389                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3390                 }
3391
3392                 /* Read the eDP Display control capabilities registers */
3393                 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3394                 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3395                                 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3396                                                 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3397                                                                 sizeof(intel_dp->edp_dpcd)))
3398                         DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3399                                         intel_dp->edp_dpcd);
3400         }
3401
3402         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3403                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3404                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3405
3406         /* Intermediate frequency support */
3407         if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
3408                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3409                 int i;
3410
3411                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3412                                 sink_rates, sizeof(sink_rates));
3413
3414                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3415                         int val = le16_to_cpu(sink_rates[i]);
3416
3417                         if (val == 0)
3418                                 break;
3419
3420                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3421                         intel_dp->sink_rates[i] = (val * 200) / 10;
3422                 }
3423                 intel_dp->num_sink_rates = i;
3424         }
3425
3426         intel_dp_print_rates(intel_dp);
3427
3428         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3429               DP_DWN_STRM_PORT_PRESENT))
3430                 return true; /* native DP sink */
3431
3432         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3433                 return true; /* no per-port downstream info */
3434
3435         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3436                              intel_dp->downstream_ports,
3437                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3438                 return false; /* downstream port status fetch failed */
3439
3440         return true;
3441 }
3442
3443 static void
3444 intel_dp_probe_oui(struct intel_dp *intel_dp)
3445 {
3446         u8 buf[3];
3447
3448         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3449                 return;
3450
3451         if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3452                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3453                               buf[0], buf[1], buf[2]);
3454
3455         if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3456                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3457                               buf[0], buf[1], buf[2]);
3458 }
3459
3460 static bool
3461 intel_dp_probe_mst(struct intel_dp *intel_dp)
3462 {
3463         u8 buf[1];
3464
3465         if (!i915.enable_dp_mst)
3466                 return false;
3467
3468         if (!intel_dp->can_mst)
3469                 return false;
3470
3471         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3472                 return false;
3473
3474         if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3475                 if (buf[0] & DP_MST_CAP) {
3476                         DRM_DEBUG_KMS("Sink is MST capable\n");
3477                         intel_dp->is_mst = true;
3478                 } else {
3479                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3480                         intel_dp->is_mst = false;
3481                 }
3482         }
3483
3484         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3485         return intel_dp->is_mst;
3486 }
3487
3488 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3489 {
3490         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3491         struct drm_device *dev = dig_port->base.base.dev;
3492         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3493         u8 buf;
3494         int ret = 0;
3495         int count = 0;
3496         int attempts = 10;
3497
3498         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3499                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3500                 ret = -EIO;
3501                 goto out;
3502         }
3503
3504         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3505                                buf & ~DP_TEST_SINK_START) < 0) {
3506                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3507                 ret = -EIO;
3508                 goto out;
3509         }
3510
3511         do {
3512                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3513
3514                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3515                                       DP_TEST_SINK_MISC, &buf) < 0) {
3516                         ret = -EIO;
3517                         goto out;
3518                 }
3519                 count = buf & DP_TEST_COUNT_MASK;
3520         } while (--attempts && count);
3521
3522         if (attempts == 0) {
3523                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3524                 ret = -ETIMEDOUT;
3525         }
3526
3527  out:
3528         hsw_enable_ips(intel_crtc);
3529         return ret;
3530 }
3531
3532 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3533 {
3534         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3535         struct drm_device *dev = dig_port->base.base.dev;
3536         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3537         u8 buf;
3538         int ret;
3539
3540         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3541                 return -EIO;
3542
3543         if (!(buf & DP_TEST_CRC_SUPPORTED))
3544                 return -ENOTTY;
3545
3546         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3547                 return -EIO;
3548
3549         if (buf & DP_TEST_SINK_START) {
3550                 ret = intel_dp_sink_crc_stop(intel_dp);
3551                 if (ret)
3552                         return ret;
3553         }
3554
3555         hsw_disable_ips(intel_crtc);
3556
3557         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3558                                buf | DP_TEST_SINK_START) < 0) {
3559                 hsw_enable_ips(intel_crtc);
3560                 return -EIO;
3561         }
3562
3563         intel_wait_for_vblank(dev, intel_crtc->pipe);
3564         return 0;
3565 }
3566
3567 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3568 {
3569         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3570         struct drm_device *dev = dig_port->base.base.dev;
3571         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3572         u8 buf;
3573         int count, ret;
3574         int attempts = 6;
3575
3576         ret = intel_dp_sink_crc_start(intel_dp);
3577         if (ret)
3578                 return ret;
3579
3580         do {
3581                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3582
3583                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3584                                       DP_TEST_SINK_MISC, &buf) < 0) {
3585                         ret = -EIO;
3586                         goto stop;
3587                 }
3588                 count = buf & DP_TEST_COUNT_MASK;
3589
3590         } while (--attempts && count == 0);
3591
3592         if (attempts == 0) {
3593                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3594                 ret = -ETIMEDOUT;
3595                 goto stop;
3596         }
3597
3598         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3599                 ret = -EIO;
3600                 goto stop;
3601         }
3602
3603 stop:
3604         intel_dp_sink_crc_stop(intel_dp);
3605         return ret;
3606 }
3607
3608 static bool
3609 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3610 {
3611         return drm_dp_dpcd_read(&intel_dp->aux,
3612                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3613                                        sink_irq_vector, 1) == 1;
3614 }
3615
3616 static bool
3617 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3618 {
3619         int ret;
3620
3621         ret = drm_dp_dpcd_read(&intel_dp->aux,
3622                                              DP_SINK_COUNT_ESI,
3623                                              sink_irq_vector, 14);
3624         if (ret != 14)
3625                 return false;
3626
3627         return true;
3628 }
3629
3630 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3631 {
3632         uint8_t test_result = DP_TEST_ACK;
3633         return test_result;
3634 }
3635
3636 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3637 {
3638         uint8_t test_result = DP_TEST_NAK;
3639         return test_result;
3640 }
3641
3642 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3643 {
3644         uint8_t test_result = DP_TEST_NAK;
3645         struct intel_connector *intel_connector = intel_dp->attached_connector;
3646         struct drm_connector *connector = &intel_connector->base;
3647
3648         if (intel_connector->detect_edid == NULL ||
3649             connector->edid_corrupt ||
3650             intel_dp->aux.i2c_defer_count > 6) {
3651                 /* Check EDID read for NACKs, DEFERs and corruption
3652                  * (DP CTS 1.2 Core r1.1)
3653                  *    4.2.2.4 : Failed EDID read, I2C_NAK
3654                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
3655                  *    4.2.2.6 : EDID corruption detected
3656                  * Use failsafe mode for all cases
3657                  */
3658                 if (intel_dp->aux.i2c_nack_count > 0 ||
3659                         intel_dp->aux.i2c_defer_count > 0)
3660                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3661                                       intel_dp->aux.i2c_nack_count,
3662                                       intel_dp->aux.i2c_defer_count);
3663                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3664         } else {
3665                 struct edid *block = intel_connector->detect_edid;
3666
3667                 /* We have to write the checksum
3668                  * of the last block read
3669                  */
3670                 block += intel_connector->detect_edid->extensions;
3671
3672                 if (!drm_dp_dpcd_write(&intel_dp->aux,
3673                                         DP_TEST_EDID_CHECKSUM,
3674                                         &block->checksum,
3675                                         1))
3676                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3677
3678                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3679                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3680         }
3681
3682         /* Set test active flag here so userspace doesn't interrupt things */
3683         intel_dp->compliance_test_active = 1;
3684
3685         return test_result;
3686 }
3687
3688 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3689 {
3690         uint8_t test_result = DP_TEST_NAK;
3691         return test_result;
3692 }
3693
3694 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3695 {
3696         uint8_t response = DP_TEST_NAK;
3697         uint8_t rxdata = 0;
3698         int status = 0;
3699
3700         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3701         if (status <= 0) {
3702                 DRM_DEBUG_KMS("Could not read test request from sink\n");
3703                 goto update_status;
3704         }
3705
3706         switch (rxdata) {
3707         case DP_TEST_LINK_TRAINING:
3708                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3709                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3710                 response = intel_dp_autotest_link_training(intel_dp);
3711                 break;
3712         case DP_TEST_LINK_VIDEO_PATTERN:
3713                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3714                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3715                 response = intel_dp_autotest_video_pattern(intel_dp);
3716                 break;
3717         case DP_TEST_LINK_EDID_READ:
3718                 DRM_DEBUG_KMS("EDID test requested\n");
3719                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3720                 response = intel_dp_autotest_edid(intel_dp);
3721                 break;
3722         case DP_TEST_LINK_PHY_TEST_PATTERN:
3723                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3724                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3725                 response = intel_dp_autotest_phy_pattern(intel_dp);
3726                 break;
3727         default:
3728                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3729                 break;
3730         }
3731
3732 update_status:
3733         status = drm_dp_dpcd_write(&intel_dp->aux,
3734                                    DP_TEST_RESPONSE,
3735                                    &response, 1);
3736         if (status <= 0)
3737                 DRM_DEBUG_KMS("Could not write test response to sink\n");
3738 }
3739
3740 static int
3741 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3742 {
3743         bool bret;
3744
3745         if (intel_dp->is_mst) {
3746                 u8 esi[16] = { 0 };
3747                 int ret = 0;
3748                 int retry;
3749                 bool handled;
3750                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3751 go_again:
3752                 if (bret == true) {
3753
3754                         /* check link status - esi[10] = 0x200c */
3755                         if (intel_dp->active_mst_links &&
3756                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3757                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3758                                 intel_dp_start_link_train(intel_dp);
3759                                 intel_dp_stop_link_train(intel_dp);
3760                         }
3761
3762                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
3763                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3764
3765                         if (handled) {
3766                                 for (retry = 0; retry < 3; retry++) {
3767                                         int wret;
3768                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3769                                                                  DP_SINK_COUNT_ESI+1,
3770                                                                  &esi[1], 3);
3771                                         if (wret == 3) {
3772                                                 break;
3773                                         }
3774                                 }
3775
3776                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3777                                 if (bret == true) {
3778                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3779                                         goto go_again;
3780                                 }
3781                         } else
3782                                 ret = 0;
3783
3784                         return ret;
3785                 } else {
3786                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3787                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3788                         intel_dp->is_mst = false;
3789                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3790                         /* send a hotplug event */
3791                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3792                 }
3793         }
3794         return -EINVAL;
3795 }
3796
3797 static void
3798 intel_dp_check_link_status(struct intel_dp *intel_dp)
3799 {
3800         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3801         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3802         u8 link_status[DP_LINK_STATUS_SIZE];
3803
3804         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3805
3806         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3807                 DRM_ERROR("Failed to get link status\n");
3808                 return;
3809         }
3810
3811         if (!intel_encoder->base.crtc)
3812                 return;
3813
3814         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3815                 return;
3816
3817         /* if link training is requested we should perform it always */
3818         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3819             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3820                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3821                               intel_encoder->base.name);
3822                 intel_dp_start_link_train(intel_dp);
3823                 intel_dp_stop_link_train(intel_dp);
3824         }
3825 }
3826
3827 /*
3828  * According to DP spec
3829  * 5.1.2:
3830  *  1. Read DPCD
3831  *  2. Configure link according to Receiver Capabilities
3832  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3833  *  4. Check link status on receipt of hot-plug interrupt
3834  *
3835  * intel_dp_short_pulse -  handles short pulse interrupts
3836  * when full detection is not required.
3837  * Returns %true if short pulse is handled and full detection
3838  * is NOT required and %false otherwise.
3839  */
3840 static bool
3841 intel_dp_short_pulse(struct intel_dp *intel_dp)
3842 {
3843         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3844         u8 sink_irq_vector;
3845         u8 old_sink_count = intel_dp->sink_count;
3846         bool ret;
3847
3848         /*
3849          * Clearing compliance test variables to allow capturing
3850          * of values for next automated test request.
3851          */
3852         intel_dp->compliance_test_active = 0;
3853         intel_dp->compliance_test_type = 0;
3854         intel_dp->compliance_test_data = 0;
3855
3856         /*
3857          * Now read the DPCD to see if it's actually running
3858          * If the current value of sink count doesn't match with
3859          * the value that was stored earlier or dpcd read failed
3860          * we need to do full detection
3861          */
3862         ret = intel_dp_get_dpcd(intel_dp);
3863
3864         if ((old_sink_count != intel_dp->sink_count) || !ret) {
3865                 /* No need to proceed if we are going to do full detect */
3866                 return false;
3867         }
3868
3869         /* Try to read the source of the interrupt */
3870         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3871             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3872                 /* Clear interrupt source */
3873                 drm_dp_dpcd_writeb(&intel_dp->aux,
3874                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3875                                    sink_irq_vector);
3876
3877                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3878                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
3879                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3880                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3881         }
3882
3883         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3884         intel_dp_check_link_status(intel_dp);
3885         drm_modeset_unlock(&dev->mode_config.connection_mutex);
3886
3887         return true;
3888 }
3889
3890 /* XXX this is probably wrong for multiple downstream ports */
3891 static enum drm_connector_status
3892 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3893 {
3894         uint8_t *dpcd = intel_dp->dpcd;
3895         uint8_t type;
3896
3897         if (!intel_dp_get_dpcd(intel_dp))
3898                 return connector_status_disconnected;
3899
3900         if (is_edp(intel_dp))
3901                 return connector_status_connected;
3902
3903         /* if there's no downstream port, we're done */
3904         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3905                 return connector_status_connected;
3906
3907         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3908         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3909             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3910
3911                 return intel_dp->sink_count ?
3912                 connector_status_connected : connector_status_disconnected;
3913         }
3914
3915         /* If no HPD, poke DDC gently */
3916         if (drm_probe_ddc(&intel_dp->aux.ddc))
3917                 return connector_status_connected;
3918
3919         /* Well we tried, say unknown for unreliable port types */
3920         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3921                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3922                 if (type == DP_DS_PORT_TYPE_VGA ||
3923                     type == DP_DS_PORT_TYPE_NON_EDID)
3924                         return connector_status_unknown;
3925         } else {
3926                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3927                         DP_DWN_STRM_PORT_TYPE_MASK;
3928                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3929                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3930                         return connector_status_unknown;
3931         }
3932
3933         /* Anything else is out of spec, warn and ignore */
3934         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3935         return connector_status_disconnected;
3936 }
3937
3938 static enum drm_connector_status
3939 edp_detect(struct intel_dp *intel_dp)
3940 {
3941         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3942         enum drm_connector_status status;
3943
3944         status = intel_panel_detect(dev);
3945         if (status == connector_status_unknown)
3946                 status = connector_status_connected;
3947
3948         return status;
3949 }
3950
3951 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
3952                                        struct intel_digital_port *port)
3953 {
3954         u32 bit;
3955
3956         switch (port->port) {
3957         case PORT_A:
3958                 return true;
3959         case PORT_B:
3960                 bit = SDE_PORTB_HOTPLUG;
3961                 break;
3962         case PORT_C:
3963                 bit = SDE_PORTC_HOTPLUG;
3964                 break;
3965         case PORT_D:
3966                 bit = SDE_PORTD_HOTPLUG;
3967                 break;
3968         default:
3969                 MISSING_CASE(port->port);
3970                 return false;
3971         }
3972
3973         return I915_READ(SDEISR) & bit;
3974 }
3975
3976 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
3977                                        struct intel_digital_port *port)
3978 {
3979         u32 bit;
3980
3981         switch (port->port) {
3982         case PORT_A:
3983                 return true;
3984         case PORT_B:
3985                 bit = SDE_PORTB_HOTPLUG_CPT;
3986                 break;
3987         case PORT_C:
3988                 bit = SDE_PORTC_HOTPLUG_CPT;
3989                 break;
3990         case PORT_D:
3991                 bit = SDE_PORTD_HOTPLUG_CPT;
3992                 break;
3993         case PORT_E:
3994                 bit = SDE_PORTE_HOTPLUG_SPT;
3995                 break;
3996         default:
3997                 MISSING_CASE(port->port);
3998                 return false;
3999         }
4000
4001         return I915_READ(SDEISR) & bit;
4002 }
4003
4004 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4005                                        struct intel_digital_port *port)
4006 {
4007         u32 bit;
4008
4009         switch (port->port) {
4010         case PORT_B:
4011                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4012                 break;
4013         case PORT_C:
4014                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4015                 break;
4016         case PORT_D:
4017                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4018                 break;
4019         default:
4020                 MISSING_CASE(port->port);
4021                 return false;
4022         }
4023
4024         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4025 }
4026
4027 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4028                                         struct intel_digital_port *port)
4029 {
4030         u32 bit;
4031
4032         switch (port->port) {
4033         case PORT_B:
4034                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4035                 break;
4036         case PORT_C:
4037                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4038                 break;
4039         case PORT_D:
4040                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4041                 break;
4042         default:
4043                 MISSING_CASE(port->port);
4044                 return false;
4045         }
4046
4047         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4048 }
4049
4050 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4051                                        struct intel_digital_port *intel_dig_port)
4052 {
4053         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4054         enum port port;
4055         u32 bit;
4056
4057         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4058         switch (port) {
4059         case PORT_A:
4060                 bit = BXT_DE_PORT_HP_DDIA;
4061                 break;
4062         case PORT_B:
4063                 bit = BXT_DE_PORT_HP_DDIB;
4064                 break;
4065         case PORT_C:
4066                 bit = BXT_DE_PORT_HP_DDIC;
4067                 break;
4068         default:
4069                 MISSING_CASE(port);
4070                 return false;
4071         }
4072
4073         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4074 }
4075
4076 /*
4077  * intel_digital_port_connected - is the specified port connected?
4078  * @dev_priv: i915 private structure
4079  * @port: the port to test
4080  *
4081  * Return %true if @port is connected, %false otherwise.
4082  */
4083 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4084                                          struct intel_digital_port *port)
4085 {
4086         if (HAS_PCH_IBX(dev_priv))
4087                 return ibx_digital_port_connected(dev_priv, port);
4088         else if (HAS_PCH_SPLIT(dev_priv))
4089                 return cpt_digital_port_connected(dev_priv, port);
4090         else if (IS_BROXTON(dev_priv))
4091                 return bxt_digital_port_connected(dev_priv, port);
4092         else if (IS_GM45(dev_priv))
4093                 return gm45_digital_port_connected(dev_priv, port);
4094         else
4095                 return g4x_digital_port_connected(dev_priv, port);
4096 }
4097
4098 static struct edid *
4099 intel_dp_get_edid(struct intel_dp *intel_dp)
4100 {
4101         struct intel_connector *intel_connector = intel_dp->attached_connector;
4102
4103         /* use cached edid if we have one */
4104         if (intel_connector->edid) {
4105                 /* invalid edid */
4106                 if (IS_ERR(intel_connector->edid))
4107                         return NULL;
4108
4109                 return drm_edid_duplicate(intel_connector->edid);
4110         } else
4111                 return drm_get_edid(&intel_connector->base,
4112                                     &intel_dp->aux.ddc);
4113 }
4114
4115 static void
4116 intel_dp_set_edid(struct intel_dp *intel_dp)
4117 {
4118         struct intel_connector *intel_connector = intel_dp->attached_connector;
4119         struct edid *edid;
4120
4121         intel_dp_unset_edid(intel_dp);
4122         edid = intel_dp_get_edid(intel_dp);
4123         intel_connector->detect_edid = edid;
4124
4125         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4126                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4127         else
4128                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4129 }
4130
4131 static void
4132 intel_dp_unset_edid(struct intel_dp *intel_dp)
4133 {
4134         struct intel_connector *intel_connector = intel_dp->attached_connector;
4135
4136         kfree(intel_connector->detect_edid);
4137         intel_connector->detect_edid = NULL;
4138
4139         intel_dp->has_audio = false;
4140 }
4141
4142 static void
4143 intel_dp_long_pulse(struct intel_connector *intel_connector)
4144 {
4145         struct drm_connector *connector = &intel_connector->base;
4146         struct intel_dp *intel_dp = intel_attached_dp(connector);
4147         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4148         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4149         struct drm_device *dev = connector->dev;
4150         enum drm_connector_status status;
4151         enum intel_display_power_domain power_domain;
4152         bool ret;
4153         u8 sink_irq_vector;
4154
4155         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4156         intel_display_power_get(to_i915(dev), power_domain);
4157
4158         /* Can't disconnect eDP, but you can close the lid... */
4159         if (is_edp(intel_dp))
4160                 status = edp_detect(intel_dp);
4161         else if (intel_digital_port_connected(to_i915(dev),
4162                                               dp_to_dig_port(intel_dp)))
4163                 status = intel_dp_detect_dpcd(intel_dp);
4164         else
4165                 status = connector_status_disconnected;
4166
4167         if (status != connector_status_connected) {
4168                 intel_dp->compliance_test_active = 0;
4169                 intel_dp->compliance_test_type = 0;
4170                 intel_dp->compliance_test_data = 0;
4171
4172                 if (intel_dp->is_mst) {
4173                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4174                                       intel_dp->is_mst,
4175                                       intel_dp->mst_mgr.mst_state);
4176                         intel_dp->is_mst = false;
4177                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4178                                                         intel_dp->is_mst);
4179                 }
4180
4181                 goto out;
4182         }
4183
4184         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4185                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4186
4187         intel_dp_probe_oui(intel_dp);
4188
4189         ret = intel_dp_probe_mst(intel_dp);
4190         if (ret) {
4191                 /*
4192                  * If we are in MST mode then this connector
4193                  * won't appear connected or have anything
4194                  * with EDID on it
4195                  */
4196                 status = connector_status_disconnected;
4197                 goto out;
4198         } else if (connector->status == connector_status_connected) {
4199                 /*
4200                  * If display was connected already and is still connected
4201                  * check links status, there has been known issues of
4202                  * link loss triggerring long pulse!!!!
4203                  */
4204                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4205                 intel_dp_check_link_status(intel_dp);
4206                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4207                 goto out;
4208         }
4209
4210         /*
4211          * Clearing NACK and defer counts to get their exact values
4212          * while reading EDID which are required by Compliance tests
4213          * 4.2.2.4 and 4.2.2.5
4214          */
4215         intel_dp->aux.i2c_nack_count = 0;
4216         intel_dp->aux.i2c_defer_count = 0;
4217
4218         intel_dp_set_edid(intel_dp);
4219
4220         status = connector_status_connected;
4221         intel_dp->detect_done = true;
4222
4223         /* Try to read the source of the interrupt */
4224         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4225             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4226                 /* Clear interrupt source */
4227                 drm_dp_dpcd_writeb(&intel_dp->aux,
4228                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4229                                    sink_irq_vector);
4230
4231                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4232                         intel_dp_handle_test_request(intel_dp);
4233                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4234                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4235         }
4236
4237 out:
4238         if ((status != connector_status_connected) &&
4239             (intel_dp->is_mst == false))
4240                 intel_dp_unset_edid(intel_dp);
4241
4242         intel_display_power_put(to_i915(dev), power_domain);
4243         return;
4244 }
4245
4246 static enum drm_connector_status
4247 intel_dp_detect(struct drm_connector *connector, bool force)
4248 {
4249         struct intel_dp *intel_dp = intel_attached_dp(connector);
4250         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4251         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4252         struct intel_connector *intel_connector = to_intel_connector(connector);
4253
4254         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4255                       connector->base.id, connector->name);
4256
4257         if (intel_dp->is_mst) {
4258                 /* MST devices are disconnected from a monitor POV */
4259                 intel_dp_unset_edid(intel_dp);
4260                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4261                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4262                 return connector_status_disconnected;
4263         }
4264
4265         /* If full detect is not performed yet, do a full detect */
4266         if (!intel_dp->detect_done)
4267                 intel_dp_long_pulse(intel_dp->attached_connector);
4268
4269         intel_dp->detect_done = false;
4270
4271         if (intel_connector->detect_edid)
4272                 return connector_status_connected;
4273         else
4274                 return connector_status_disconnected;
4275 }
4276
4277 static void
4278 intel_dp_force(struct drm_connector *connector)
4279 {
4280         struct intel_dp *intel_dp = intel_attached_dp(connector);
4281         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4282         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4283         enum intel_display_power_domain power_domain;
4284
4285         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4286                       connector->base.id, connector->name);
4287         intel_dp_unset_edid(intel_dp);
4288
4289         if (connector->status != connector_status_connected)
4290                 return;
4291
4292         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4293         intel_display_power_get(dev_priv, power_domain);
4294
4295         intel_dp_set_edid(intel_dp);
4296
4297         intel_display_power_put(dev_priv, power_domain);
4298
4299         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4300                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4301 }
4302
4303 static int intel_dp_get_modes(struct drm_connector *connector)
4304 {
4305         struct intel_connector *intel_connector = to_intel_connector(connector);
4306         struct edid *edid;
4307
4308         edid = intel_connector->detect_edid;
4309         if (edid) {
4310                 int ret = intel_connector_update_modes(connector, edid);
4311                 if (ret)
4312                         return ret;
4313         }
4314
4315         /* if eDP has no EDID, fall back to fixed mode */
4316         if (is_edp(intel_attached_dp(connector)) &&
4317             intel_connector->panel.fixed_mode) {
4318                 struct drm_display_mode *mode;
4319
4320                 mode = drm_mode_duplicate(connector->dev,
4321                                           intel_connector->panel.fixed_mode);
4322                 if (mode) {
4323                         drm_mode_probed_add(connector, mode);
4324                         return 1;
4325                 }
4326         }
4327
4328         return 0;
4329 }
4330
4331 static bool
4332 intel_dp_detect_audio(struct drm_connector *connector)
4333 {
4334         bool has_audio = false;
4335         struct edid *edid;
4336
4337         edid = to_intel_connector(connector)->detect_edid;
4338         if (edid)
4339                 has_audio = drm_detect_monitor_audio(edid);
4340
4341         return has_audio;
4342 }
4343
4344 static int
4345 intel_dp_set_property(struct drm_connector *connector,
4346                       struct drm_property *property,
4347                       uint64_t val)
4348 {
4349         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4350         struct intel_connector *intel_connector = to_intel_connector(connector);
4351         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4352         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4353         int ret;
4354
4355         ret = drm_object_property_set_value(&connector->base, property, val);
4356         if (ret)
4357                 return ret;
4358
4359         if (property == dev_priv->force_audio_property) {
4360                 int i = val;
4361                 bool has_audio;
4362
4363                 if (i == intel_dp->force_audio)
4364                         return 0;
4365
4366                 intel_dp->force_audio = i;
4367
4368                 if (i == HDMI_AUDIO_AUTO)
4369                         has_audio = intel_dp_detect_audio(connector);
4370                 else
4371                         has_audio = (i == HDMI_AUDIO_ON);
4372
4373                 if (has_audio == intel_dp->has_audio)
4374                         return 0;
4375
4376                 intel_dp->has_audio = has_audio;
4377                 goto done;
4378         }
4379
4380         if (property == dev_priv->broadcast_rgb_property) {
4381                 bool old_auto = intel_dp->color_range_auto;
4382                 bool old_range = intel_dp->limited_color_range;
4383
4384                 switch (val) {
4385                 case INTEL_BROADCAST_RGB_AUTO:
4386                         intel_dp->color_range_auto = true;
4387                         break;
4388                 case INTEL_BROADCAST_RGB_FULL:
4389                         intel_dp->color_range_auto = false;
4390                         intel_dp->limited_color_range = false;
4391                         break;
4392                 case INTEL_BROADCAST_RGB_LIMITED:
4393                         intel_dp->color_range_auto = false;
4394                         intel_dp->limited_color_range = true;
4395                         break;
4396                 default:
4397                         return -EINVAL;
4398                 }
4399
4400                 if (old_auto == intel_dp->color_range_auto &&
4401                     old_range == intel_dp->limited_color_range)
4402                         return 0;
4403
4404                 goto done;
4405         }
4406
4407         if (is_edp(intel_dp) &&
4408             property == connector->dev->mode_config.scaling_mode_property) {
4409                 if (val == DRM_MODE_SCALE_NONE) {
4410                         DRM_DEBUG_KMS("no scaling not supported\n");
4411                         return -EINVAL;
4412                 }
4413                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4414                     val == DRM_MODE_SCALE_CENTER) {
4415                         DRM_DEBUG_KMS("centering not supported\n");
4416                         return -EINVAL;
4417                 }
4418
4419                 if (intel_connector->panel.fitting_mode == val) {
4420                         /* the eDP scaling property is not changed */
4421                         return 0;
4422                 }
4423                 intel_connector->panel.fitting_mode = val;
4424
4425                 goto done;
4426         }
4427
4428         return -EINVAL;
4429
4430 done:
4431         if (intel_encoder->base.crtc)
4432                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4433
4434         return 0;
4435 }
4436
4437 static void
4438 intel_dp_connector_destroy(struct drm_connector *connector)
4439 {
4440         struct intel_connector *intel_connector = to_intel_connector(connector);
4441
4442         kfree(intel_connector->detect_edid);
4443
4444         if (!IS_ERR_OR_NULL(intel_connector->edid))
4445                 kfree(intel_connector->edid);
4446
4447         /* Can't call is_edp() since the encoder may have been destroyed
4448          * already. */
4449         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4450                 intel_panel_fini(&intel_connector->panel);
4451
4452         drm_connector_cleanup(connector);
4453         kfree(connector);
4454 }
4455
4456 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4457 {
4458         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4459         struct intel_dp *intel_dp = &intel_dig_port->dp;
4460
4461         intel_dp_mst_encoder_cleanup(intel_dig_port);
4462         if (is_edp(intel_dp)) {
4463                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4464                 /*
4465                  * vdd might still be enabled do to the delayed vdd off.
4466                  * Make sure vdd is actually turned off here.
4467                  */
4468                 pps_lock(intel_dp);
4469                 edp_panel_vdd_off_sync(intel_dp);
4470                 pps_unlock(intel_dp);
4471
4472                 if (intel_dp->edp_notifier.notifier_call) {
4473                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4474                         intel_dp->edp_notifier.notifier_call = NULL;
4475                 }
4476         }
4477         drm_encoder_cleanup(encoder);
4478         kfree(intel_dig_port);
4479 }
4480
4481 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4482 {
4483         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4484
4485         if (!is_edp(intel_dp))
4486                 return;
4487
4488         /*
4489          * vdd might still be enabled do to the delayed vdd off.
4490          * Make sure vdd is actually turned off here.
4491          */
4492         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4493         pps_lock(intel_dp);
4494         edp_panel_vdd_off_sync(intel_dp);
4495         pps_unlock(intel_dp);
4496 }
4497
4498 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4499 {
4500         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4501         struct drm_device *dev = intel_dig_port->base.base.dev;
4502         struct drm_i915_private *dev_priv = dev->dev_private;
4503         enum intel_display_power_domain power_domain;
4504
4505         lockdep_assert_held(&dev_priv->pps_mutex);
4506
4507         if (!edp_have_panel_vdd(intel_dp))
4508                 return;
4509
4510         /*
4511          * The VDD bit needs a power domain reference, so if the bit is
4512          * already enabled when we boot or resume, grab this reference and
4513          * schedule a vdd off, so we don't hold on to the reference
4514          * indefinitely.
4515          */
4516         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4517         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4518         intel_display_power_get(dev_priv, power_domain);
4519
4520         edp_panel_vdd_schedule_off(intel_dp);
4521 }
4522
4523 void intel_dp_encoder_reset(struct drm_encoder *encoder)
4524 {
4525         struct intel_dp *intel_dp;
4526
4527         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4528                 return;
4529
4530         intel_dp = enc_to_intel_dp(encoder);
4531
4532         pps_lock(intel_dp);
4533
4534         /*
4535          * Read out the current power sequencer assignment,
4536          * in case the BIOS did something with it.
4537          */
4538         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4539                 vlv_initial_power_sequencer_setup(intel_dp);
4540
4541         intel_edp_panel_vdd_sanitize(intel_dp);
4542
4543         pps_unlock(intel_dp);
4544 }
4545
4546 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4547         .dpms = drm_atomic_helper_connector_dpms,
4548         .detect = intel_dp_detect,
4549         .force = intel_dp_force,
4550         .fill_modes = drm_helper_probe_single_connector_modes,
4551         .set_property = intel_dp_set_property,
4552         .atomic_get_property = intel_connector_atomic_get_property,
4553         .destroy = intel_dp_connector_destroy,
4554         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4555         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4556 };
4557
4558 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4559         .get_modes = intel_dp_get_modes,
4560         .mode_valid = intel_dp_mode_valid,
4561         .best_encoder = intel_best_encoder,
4562 };
4563
4564 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4565         .reset = intel_dp_encoder_reset,
4566         .destroy = intel_dp_encoder_destroy,
4567 };
4568
4569 enum irqreturn
4570 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4571 {
4572         struct intel_dp *intel_dp = &intel_dig_port->dp;
4573         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4574         struct drm_device *dev = intel_dig_port->base.base.dev;
4575         struct drm_i915_private *dev_priv = dev->dev_private;
4576         enum intel_display_power_domain power_domain;
4577         enum irqreturn ret = IRQ_NONE;
4578
4579         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4580             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4581                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4582
4583         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4584                 /*
4585                  * vdd off can generate a long pulse on eDP which
4586                  * would require vdd on to handle it, and thus we
4587                  * would end up in an endless cycle of
4588                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4589                  */
4590                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4591                               port_name(intel_dig_port->port));
4592                 return IRQ_HANDLED;
4593         }
4594
4595         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4596                       port_name(intel_dig_port->port),
4597                       long_hpd ? "long" : "short");
4598
4599         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4600         intel_display_power_get(dev_priv, power_domain);
4601
4602         if (long_hpd) {
4603                 /* indicate that we need to restart link training */
4604                 intel_dp->train_set_valid = false;
4605
4606                 intel_dp_long_pulse(intel_dp->attached_connector);
4607                 if (intel_dp->is_mst)
4608                         ret = IRQ_HANDLED;
4609                 goto put_power;
4610
4611         } else {
4612                 if (intel_dp->is_mst) {
4613                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4614                                 /*
4615                                  * If we were in MST mode, and device is not
4616                                  * there, get out of MST mode
4617                                  */
4618                                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4619                                               intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4620                                 intel_dp->is_mst = false;
4621                                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4622                                                                 intel_dp->is_mst);
4623                                 goto put_power;
4624                         }
4625                 }
4626
4627                 if (!intel_dp->is_mst) {
4628                         if (!intel_dp_short_pulse(intel_dp)) {
4629                                 intel_dp_long_pulse(intel_dp->attached_connector);
4630                                 goto put_power;
4631                         }
4632                 }
4633         }
4634
4635         ret = IRQ_HANDLED;
4636
4637 put_power:
4638         intel_display_power_put(dev_priv, power_domain);
4639
4640         return ret;
4641 }
4642
4643 /* check the VBT to see whether the eDP is on another port */
4644 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4645 {
4646         struct drm_i915_private *dev_priv = dev->dev_private;
4647
4648         /*
4649          * eDP not supported on g4x. so bail out early just
4650          * for a bit extra safety in case the VBT is bonkers.
4651          */
4652         if (INTEL_INFO(dev)->gen < 5)
4653                 return false;
4654
4655         if (port == PORT_A)
4656                 return true;
4657
4658         return intel_bios_is_port_edp(dev_priv, port);
4659 }
4660
4661 void
4662 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4663 {
4664         struct intel_connector *intel_connector = to_intel_connector(connector);
4665
4666         intel_attach_force_audio_property(connector);
4667         intel_attach_broadcast_rgb_property(connector);
4668         intel_dp->color_range_auto = true;
4669
4670         if (is_edp(intel_dp)) {
4671                 drm_mode_create_scaling_mode_property(connector->dev);
4672                 drm_object_attach_property(
4673                         &connector->base,
4674                         connector->dev->mode_config.scaling_mode_property,
4675                         DRM_MODE_SCALE_ASPECT);
4676                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4677         }
4678 }
4679
4680 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4681 {
4682         intel_dp->panel_power_off_time = ktime_get_boottime();
4683         intel_dp->last_power_on = jiffies;
4684         intel_dp->last_backlight_off = jiffies;
4685 }
4686
4687 static void
4688 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4689                                     struct intel_dp *intel_dp)
4690 {
4691         struct drm_i915_private *dev_priv = dev->dev_private;
4692         struct edp_power_seq cur, vbt, spec,
4693                 *final = &intel_dp->pps_delays;
4694         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4695         i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4696
4697         lockdep_assert_held(&dev_priv->pps_mutex);
4698
4699         /* already initialized? */
4700         if (final->t11_t12 != 0)
4701                 return;
4702
4703         if (IS_BROXTON(dev)) {
4704                 /*
4705                  * TODO: BXT has 2 sets of PPS registers.
4706                  * Correct Register for Broxton need to be identified
4707                  * using VBT. hardcoding for now
4708                  */
4709                 pp_ctrl_reg = BXT_PP_CONTROL(0);
4710                 pp_on_reg = BXT_PP_ON_DELAYS(0);
4711                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
4712         } else if (HAS_PCH_SPLIT(dev)) {
4713                 pp_ctrl_reg = PCH_PP_CONTROL;
4714                 pp_on_reg = PCH_PP_ON_DELAYS;
4715                 pp_off_reg = PCH_PP_OFF_DELAYS;
4716                 pp_div_reg = PCH_PP_DIVISOR;
4717         } else {
4718                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4719
4720                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4721                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4722                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4723                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4724         }
4725
4726         /* Workaround: Need to write PP_CONTROL with the unlock key as
4727          * the very first thing. */
4728         pp_ctl = ironlake_get_pp_control(intel_dp);
4729
4730         pp_on = I915_READ(pp_on_reg);
4731         pp_off = I915_READ(pp_off_reg);
4732         if (!IS_BROXTON(dev)) {
4733                 I915_WRITE(pp_ctrl_reg, pp_ctl);
4734                 pp_div = I915_READ(pp_div_reg);
4735         }
4736
4737         /* Pull timing values out of registers */
4738         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4739                 PANEL_POWER_UP_DELAY_SHIFT;
4740
4741         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4742                 PANEL_LIGHT_ON_DELAY_SHIFT;
4743
4744         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4745                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4746
4747         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4748                 PANEL_POWER_DOWN_DELAY_SHIFT;
4749
4750         if (IS_BROXTON(dev)) {
4751                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4752                         BXT_POWER_CYCLE_DELAY_SHIFT;
4753                 if (tmp > 0)
4754                         cur.t11_t12 = (tmp - 1) * 1000;
4755                 else
4756                         cur.t11_t12 = 0;
4757         } else {
4758                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4759                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4760         }
4761
4762         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4763                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4764
4765         vbt = dev_priv->vbt.edp.pps;
4766
4767         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4768          * our hw here, which are all in 100usec. */
4769         spec.t1_t3 = 210 * 10;
4770         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4771         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4772         spec.t10 = 500 * 10;
4773         /* This one is special and actually in units of 100ms, but zero
4774          * based in the hw (so we need to add 100 ms). But the sw vbt
4775          * table multiplies it with 1000 to make it in units of 100usec,
4776          * too. */
4777         spec.t11_t12 = (510 + 100) * 10;
4778
4779         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4780                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4781
4782         /* Use the max of the register settings and vbt. If both are
4783          * unset, fall back to the spec limits. */
4784 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
4785                                        spec.field : \
4786                                        max(cur.field, vbt.field))
4787         assign_final(t1_t3);
4788         assign_final(t8);
4789         assign_final(t9);
4790         assign_final(t10);
4791         assign_final(t11_t12);
4792 #undef assign_final
4793
4794 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
4795         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4796         intel_dp->backlight_on_delay = get_delay(t8);
4797         intel_dp->backlight_off_delay = get_delay(t9);
4798         intel_dp->panel_power_down_delay = get_delay(t10);
4799         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4800 #undef get_delay
4801
4802         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4803                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4804                       intel_dp->panel_power_cycle_delay);
4805
4806         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4807                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4808 }
4809
4810 static void
4811 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4812                                               struct intel_dp *intel_dp)
4813 {
4814         struct drm_i915_private *dev_priv = dev->dev_private;
4815         u32 pp_on, pp_off, pp_div, port_sel = 0;
4816         int div = dev_priv->rawclk_freq / 1000;
4817         i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
4818         enum port port = dp_to_dig_port(intel_dp)->port;
4819         const struct edp_power_seq *seq = &intel_dp->pps_delays;
4820
4821         lockdep_assert_held(&dev_priv->pps_mutex);
4822
4823         if (IS_BROXTON(dev)) {
4824                 /*
4825                  * TODO: BXT has 2 sets of PPS registers.
4826                  * Correct Register for Broxton need to be identified
4827                  * using VBT. hardcoding for now
4828                  */
4829                 pp_ctrl_reg = BXT_PP_CONTROL(0);
4830                 pp_on_reg = BXT_PP_ON_DELAYS(0);
4831                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
4832
4833         } else if (HAS_PCH_SPLIT(dev)) {
4834                 pp_on_reg = PCH_PP_ON_DELAYS;
4835                 pp_off_reg = PCH_PP_OFF_DELAYS;
4836                 pp_div_reg = PCH_PP_DIVISOR;
4837         } else {
4838                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4839
4840                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4841                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4842                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4843         }
4844
4845         /*
4846          * And finally store the new values in the power sequencer. The
4847          * backlight delays are set to 1 because we do manual waits on them. For
4848          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4849          * we'll end up waiting for the backlight off delay twice: once when we
4850          * do the manual sleep, and once when we disable the panel and wait for
4851          * the PP_STATUS bit to become zero.
4852          */
4853         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4854                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4855         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4856                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4857         /* Compute the divisor for the pp clock, simply match the Bspec
4858          * formula. */
4859         if (IS_BROXTON(dev)) {
4860                 pp_div = I915_READ(pp_ctrl_reg);
4861                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4862                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4863                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
4864         } else {
4865                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4866                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4867                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4868         }
4869
4870         /* Haswell doesn't have any port selection bits for the panel
4871          * power sequencer any more. */
4872         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4873                 port_sel = PANEL_PORT_SELECT_VLV(port);
4874         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4875                 if (port == PORT_A)
4876                         port_sel = PANEL_PORT_SELECT_DPA;
4877                 else
4878                         port_sel = PANEL_PORT_SELECT_DPD;
4879         }
4880
4881         pp_on |= port_sel;
4882
4883         I915_WRITE(pp_on_reg, pp_on);
4884         I915_WRITE(pp_off_reg, pp_off);
4885         if (IS_BROXTON(dev))
4886                 I915_WRITE(pp_ctrl_reg, pp_div);
4887         else
4888                 I915_WRITE(pp_div_reg, pp_div);
4889
4890         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4891                       I915_READ(pp_on_reg),
4892                       I915_READ(pp_off_reg),
4893                       IS_BROXTON(dev) ?
4894                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
4895                       I915_READ(pp_div_reg));
4896 }
4897
4898 /**
4899  * intel_dp_set_drrs_state - program registers for RR switch to take effect
4900  * @dev: DRM device
4901  * @refresh_rate: RR to be programmed
4902  *
4903  * This function gets called when refresh rate (RR) has to be changed from
4904  * one frequency to another. Switches can be between high and low RR
4905  * supported by the panel or to any other RR based on media playback (in
4906  * this case, RR value needs to be passed from user space).
4907  *
4908  * The caller of this function needs to take a lock on dev_priv->drrs.
4909  */
4910 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4911 {
4912         struct drm_i915_private *dev_priv = dev->dev_private;
4913         struct intel_encoder *encoder;
4914         struct intel_digital_port *dig_port = NULL;
4915         struct intel_dp *intel_dp = dev_priv->drrs.dp;
4916         struct intel_crtc_state *config = NULL;
4917         struct intel_crtc *intel_crtc = NULL;
4918         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4919
4920         if (refresh_rate <= 0) {
4921                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4922                 return;
4923         }
4924
4925         if (intel_dp == NULL) {
4926                 DRM_DEBUG_KMS("DRRS not supported.\n");
4927                 return;
4928         }
4929
4930         /*
4931          * FIXME: This needs proper synchronization with psr state for some
4932          * platforms that cannot have PSR and DRRS enabled at the same time.
4933          */
4934
4935         dig_port = dp_to_dig_port(intel_dp);
4936         encoder = &dig_port->base;
4937         intel_crtc = to_intel_crtc(encoder->base.crtc);
4938
4939         if (!intel_crtc) {
4940                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4941                 return;
4942         }
4943
4944         config = intel_crtc->config;
4945
4946         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4947                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4948                 return;
4949         }
4950
4951         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4952                         refresh_rate)
4953                 index = DRRS_LOW_RR;
4954
4955         if (index == dev_priv->drrs.refresh_rate_type) {
4956                 DRM_DEBUG_KMS(
4957                         "DRRS requested for previously set RR...ignoring\n");
4958                 return;
4959         }
4960
4961         if (!intel_crtc->active) {
4962                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4963                 return;
4964         }
4965
4966         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
4967                 switch (index) {
4968                 case DRRS_HIGH_RR:
4969                         intel_dp_set_m_n(intel_crtc, M1_N1);
4970                         break;
4971                 case DRRS_LOW_RR:
4972                         intel_dp_set_m_n(intel_crtc, M2_N2);
4973                         break;
4974                 case DRRS_MAX_RR:
4975                 default:
4976                         DRM_ERROR("Unsupported refreshrate type\n");
4977                 }
4978         } else if (INTEL_INFO(dev)->gen > 6) {
4979                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4980                 u32 val;
4981
4982                 val = I915_READ(reg);
4983                 if (index > DRRS_HIGH_RR) {
4984                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4985                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4986                         else
4987                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4988                 } else {
4989                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4990                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
4991                         else
4992                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4993                 }
4994                 I915_WRITE(reg, val);
4995         }
4996
4997         dev_priv->drrs.refresh_rate_type = index;
4998
4999         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5000 }
5001
5002 /**
5003  * intel_edp_drrs_enable - init drrs struct if supported
5004  * @intel_dp: DP struct
5005  *
5006  * Initializes frontbuffer_bits and drrs.dp
5007  */
5008 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5009 {
5010         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5013         struct drm_crtc *crtc = dig_port->base.base.crtc;
5014         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5015
5016         if (!intel_crtc->config->has_drrs) {
5017                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5018                 return;
5019         }
5020
5021         mutex_lock(&dev_priv->drrs.mutex);
5022         if (WARN_ON(dev_priv->drrs.dp)) {
5023                 DRM_ERROR("DRRS already enabled\n");
5024                 goto unlock;
5025         }
5026
5027         dev_priv->drrs.busy_frontbuffer_bits = 0;
5028
5029         dev_priv->drrs.dp = intel_dp;
5030
5031 unlock:
5032         mutex_unlock(&dev_priv->drrs.mutex);
5033 }
5034
5035 /**
5036  * intel_edp_drrs_disable - Disable DRRS
5037  * @intel_dp: DP struct
5038  *
5039  */
5040 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5041 {
5042         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5043         struct drm_i915_private *dev_priv = dev->dev_private;
5044         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5045         struct drm_crtc *crtc = dig_port->base.base.crtc;
5046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047
5048         if (!intel_crtc->config->has_drrs)
5049                 return;
5050
5051         mutex_lock(&dev_priv->drrs.mutex);
5052         if (!dev_priv->drrs.dp) {
5053                 mutex_unlock(&dev_priv->drrs.mutex);
5054                 return;
5055         }
5056
5057         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5058                 intel_dp_set_drrs_state(dev_priv->dev,
5059                         intel_dp->attached_connector->panel.
5060                         fixed_mode->vrefresh);
5061
5062         dev_priv->drrs.dp = NULL;
5063         mutex_unlock(&dev_priv->drrs.mutex);
5064
5065         cancel_delayed_work_sync(&dev_priv->drrs.work);
5066 }
5067
5068 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5069 {
5070         struct drm_i915_private *dev_priv =
5071                 container_of(work, typeof(*dev_priv), drrs.work.work);
5072         struct intel_dp *intel_dp;
5073
5074         mutex_lock(&dev_priv->drrs.mutex);
5075
5076         intel_dp = dev_priv->drrs.dp;
5077
5078         if (!intel_dp)
5079                 goto unlock;
5080
5081         /*
5082          * The delayed work can race with an invalidate hence we need to
5083          * recheck.
5084          */
5085
5086         if (dev_priv->drrs.busy_frontbuffer_bits)
5087                 goto unlock;
5088
5089         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5090                 intel_dp_set_drrs_state(dev_priv->dev,
5091                         intel_dp->attached_connector->panel.
5092                         downclock_mode->vrefresh);
5093
5094 unlock:
5095         mutex_unlock(&dev_priv->drrs.mutex);
5096 }
5097
5098 /**
5099  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5100  * @dev: DRM device
5101  * @frontbuffer_bits: frontbuffer plane tracking bits
5102  *
5103  * This function gets called everytime rendering on the given planes start.
5104  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5105  *
5106  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5107  */
5108 void intel_edp_drrs_invalidate(struct drm_device *dev,
5109                 unsigned frontbuffer_bits)
5110 {
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         struct drm_crtc *crtc;
5113         enum pipe pipe;
5114
5115         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5116                 return;
5117
5118         cancel_delayed_work(&dev_priv->drrs.work);
5119
5120         mutex_lock(&dev_priv->drrs.mutex);
5121         if (!dev_priv->drrs.dp) {
5122                 mutex_unlock(&dev_priv->drrs.mutex);
5123                 return;
5124         }
5125
5126         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5127         pipe = to_intel_crtc(crtc)->pipe;
5128
5129         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5130         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5131
5132         /* invalidate means busy screen hence upclock */
5133         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5134                 intel_dp_set_drrs_state(dev_priv->dev,
5135                                 dev_priv->drrs.dp->attached_connector->panel.
5136                                 fixed_mode->vrefresh);
5137
5138         mutex_unlock(&dev_priv->drrs.mutex);
5139 }
5140
5141 /**
5142  * intel_edp_drrs_flush - Restart Idleness DRRS
5143  * @dev: DRM device
5144  * @frontbuffer_bits: frontbuffer plane tracking bits
5145  *
5146  * This function gets called every time rendering on the given planes has
5147  * completed or flip on a crtc is completed. So DRRS should be upclocked
5148  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5149  * if no other planes are dirty.
5150  *
5151  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5152  */
5153 void intel_edp_drrs_flush(struct drm_device *dev,
5154                 unsigned frontbuffer_bits)
5155 {
5156         struct drm_i915_private *dev_priv = dev->dev_private;
5157         struct drm_crtc *crtc;
5158         enum pipe pipe;
5159
5160         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5161                 return;
5162
5163         cancel_delayed_work(&dev_priv->drrs.work);
5164
5165         mutex_lock(&dev_priv->drrs.mutex);
5166         if (!dev_priv->drrs.dp) {
5167                 mutex_unlock(&dev_priv->drrs.mutex);
5168                 return;
5169         }
5170
5171         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5172         pipe = to_intel_crtc(crtc)->pipe;
5173
5174         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5175         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5176
5177         /* flush means busy screen hence upclock */
5178         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5179                 intel_dp_set_drrs_state(dev_priv->dev,
5180                                 dev_priv->drrs.dp->attached_connector->panel.
5181                                 fixed_mode->vrefresh);
5182
5183         /*
5184          * flush also means no more activity hence schedule downclock, if all
5185          * other fbs are quiescent too
5186          */
5187         if (!dev_priv->drrs.busy_frontbuffer_bits)
5188                 schedule_delayed_work(&dev_priv->drrs.work,
5189                                 msecs_to_jiffies(1000));
5190         mutex_unlock(&dev_priv->drrs.mutex);
5191 }
5192
5193 /**
5194  * DOC: Display Refresh Rate Switching (DRRS)
5195  *
5196  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5197  * which enables swtching between low and high refresh rates,
5198  * dynamically, based on the usage scenario. This feature is applicable
5199  * for internal panels.
5200  *
5201  * Indication that the panel supports DRRS is given by the panel EDID, which
5202  * would list multiple refresh rates for one resolution.
5203  *
5204  * DRRS is of 2 types - static and seamless.
5205  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5206  * (may appear as a blink on screen) and is used in dock-undock scenario.
5207  * Seamless DRRS involves changing RR without any visual effect to the user
5208  * and can be used during normal system usage. This is done by programming
5209  * certain registers.
5210  *
5211  * Support for static/seamless DRRS may be indicated in the VBT based on
5212  * inputs from the panel spec.
5213  *
5214  * DRRS saves power by switching to low RR based on usage scenarios.
5215  *
5216  * eDP DRRS:-
5217  *        The implementation is based on frontbuffer tracking implementation.
5218  * When there is a disturbance on the screen triggered by user activity or a
5219  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5220  * When there is no movement on screen, after a timeout of 1 second, a switch
5221  * to low RR is made.
5222  *        For integration with frontbuffer tracking code,
5223  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5224  *
5225  * DRRS can be further extended to support other internal panels and also
5226  * the scenario of video playback wherein RR is set based on the rate
5227  * requested by userspace.
5228  */
5229
5230 /**
5231  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5232  * @intel_connector: eDP connector
5233  * @fixed_mode: preferred mode of panel
5234  *
5235  * This function is  called only once at driver load to initialize basic
5236  * DRRS stuff.
5237  *
5238  * Returns:
5239  * Downclock mode if panel supports it, else return NULL.
5240  * DRRS support is determined by the presence of downclock mode (apart
5241  * from VBT setting).
5242  */
5243 static struct drm_display_mode *
5244 intel_dp_drrs_init(struct intel_connector *intel_connector,
5245                 struct drm_display_mode *fixed_mode)
5246 {
5247         struct drm_connector *connector = &intel_connector->base;
5248         struct drm_device *dev = connector->dev;
5249         struct drm_i915_private *dev_priv = dev->dev_private;
5250         struct drm_display_mode *downclock_mode = NULL;
5251
5252         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5253         mutex_init(&dev_priv->drrs.mutex);
5254
5255         if (INTEL_INFO(dev)->gen <= 6) {
5256                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5257                 return NULL;
5258         }
5259
5260         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5261                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5262                 return NULL;
5263         }
5264
5265         downclock_mode = intel_find_panel_downclock
5266                                         (dev, fixed_mode, connector);
5267
5268         if (!downclock_mode) {
5269                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5270                 return NULL;
5271         }
5272
5273         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5274
5275         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5276         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5277         return downclock_mode;
5278 }
5279
5280 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5281                                      struct intel_connector *intel_connector)
5282 {
5283         struct drm_connector *connector = &intel_connector->base;
5284         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5285         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5286         struct drm_device *dev = intel_encoder->base.dev;
5287         struct drm_i915_private *dev_priv = dev->dev_private;
5288         struct drm_display_mode *fixed_mode = NULL;
5289         struct drm_display_mode *downclock_mode = NULL;
5290         bool has_dpcd;
5291         struct drm_display_mode *scan;
5292         struct edid *edid;
5293         enum pipe pipe = INVALID_PIPE;
5294
5295         if (!is_edp(intel_dp))
5296                 return true;
5297
5298         pps_lock(intel_dp);
5299         intel_edp_panel_vdd_sanitize(intel_dp);
5300         pps_unlock(intel_dp);
5301
5302         /* Cache DPCD and EDID for edp. */
5303         has_dpcd = intel_dp_get_dpcd(intel_dp);
5304
5305         if (has_dpcd) {
5306                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5307                         dev_priv->no_aux_handshake =
5308                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5309                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5310         } else {
5311                 /* if this fails, presume the device is a ghost */
5312                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5313                 return false;
5314         }
5315
5316         /* We now know it's not a ghost, init power sequence regs. */
5317         pps_lock(intel_dp);
5318         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5319         pps_unlock(intel_dp);
5320
5321         mutex_lock(&dev->mode_config.mutex);
5322         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5323         if (edid) {
5324                 if (drm_add_edid_modes(connector, edid)) {
5325                         drm_mode_connector_update_edid_property(connector,
5326                                                                 edid);
5327                         drm_edid_to_eld(connector, edid);
5328                 } else {
5329                         kfree(edid);
5330                         edid = ERR_PTR(-EINVAL);
5331                 }
5332         } else {
5333                 edid = ERR_PTR(-ENOENT);
5334         }
5335         intel_connector->edid = edid;
5336
5337         /* prefer fixed mode from EDID if available */
5338         list_for_each_entry(scan, &connector->probed_modes, head) {
5339                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5340                         fixed_mode = drm_mode_duplicate(dev, scan);
5341                         downclock_mode = intel_dp_drrs_init(
5342                                                 intel_connector, fixed_mode);
5343                         break;
5344                 }
5345         }
5346
5347         /* fallback to VBT if available for eDP */
5348         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5349                 fixed_mode = drm_mode_duplicate(dev,
5350                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5351                 if (fixed_mode)
5352                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5353         }
5354         mutex_unlock(&dev->mode_config.mutex);
5355
5356         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5357                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5358                 register_reboot_notifier(&intel_dp->edp_notifier);
5359
5360                 /*
5361                  * Figure out the current pipe for the initial backlight setup.
5362                  * If the current pipe isn't valid, try the PPS pipe, and if that
5363                  * fails just assume pipe A.
5364                  */
5365                 if (IS_CHERRYVIEW(dev))
5366                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5367                 else
5368                         pipe = PORT_TO_PIPE(intel_dp->DP);
5369
5370                 if (pipe != PIPE_A && pipe != PIPE_B)
5371                         pipe = intel_dp->pps_pipe;
5372
5373                 if (pipe != PIPE_A && pipe != PIPE_B)
5374                         pipe = PIPE_A;
5375
5376                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5377                               pipe_name(pipe));
5378         }
5379
5380         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5381         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5382         intel_panel_setup_backlight(connector, pipe);
5383
5384         return true;
5385 }
5386
5387 bool
5388 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5389                         struct intel_connector *intel_connector)
5390 {
5391         struct drm_connector *connector = &intel_connector->base;
5392         struct intel_dp *intel_dp = &intel_dig_port->dp;
5393         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5394         struct drm_device *dev = intel_encoder->base.dev;
5395         struct drm_i915_private *dev_priv = dev->dev_private;
5396         enum port port = intel_dig_port->port;
5397         int type, ret;
5398
5399         if (WARN(intel_dig_port->max_lanes < 1,
5400                  "Not enough lanes (%d) for DP on port %c\n",
5401                  intel_dig_port->max_lanes, port_name(port)))
5402                 return false;
5403
5404         intel_dp->pps_pipe = INVALID_PIPE;
5405
5406         /* intel_dp vfuncs */
5407         if (INTEL_INFO(dev)->gen >= 9)
5408                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5409         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5410                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5411         else if (HAS_PCH_SPLIT(dev))
5412                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5413         else
5414                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5415
5416         if (INTEL_INFO(dev)->gen >= 9)
5417                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5418         else
5419                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5420
5421         if (HAS_DDI(dev))
5422                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5423
5424         /* Preserve the current hw state. */
5425         intel_dp->DP = I915_READ(intel_dp->output_reg);
5426         intel_dp->attached_connector = intel_connector;
5427
5428         if (intel_dp_is_edp(dev, port))
5429                 type = DRM_MODE_CONNECTOR_eDP;
5430         else
5431                 type = DRM_MODE_CONNECTOR_DisplayPort;
5432
5433         /*
5434          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5435          * for DP the encoder type can be set by the caller to
5436          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5437          */
5438         if (type == DRM_MODE_CONNECTOR_eDP)
5439                 intel_encoder->type = INTEL_OUTPUT_EDP;
5440
5441         /* eDP only on port B and/or C on vlv/chv */
5442         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5443                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5444                 return false;
5445
5446         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5447                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5448                         port_name(port));
5449
5450         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5451         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5452
5453         connector->interlace_allowed = true;
5454         connector->doublescan_allowed = 0;
5455
5456         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5457                           edp_panel_vdd_work);
5458
5459         intel_connector_attach_encoder(intel_connector, intel_encoder);
5460         drm_connector_register(connector);
5461
5462         if (HAS_DDI(dev))
5463                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5464         else
5465                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5466         intel_connector->unregister = intel_dp_connector_unregister;
5467
5468         /* Set up the hotplug pin. */
5469         switch (port) {
5470         case PORT_A:
5471                 intel_encoder->hpd_pin = HPD_PORT_A;
5472                 break;
5473         case PORT_B:
5474                 intel_encoder->hpd_pin = HPD_PORT_B;
5475                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5476                         intel_encoder->hpd_pin = HPD_PORT_A;
5477                 break;
5478         case PORT_C:
5479                 intel_encoder->hpd_pin = HPD_PORT_C;
5480                 break;
5481         case PORT_D:
5482                 intel_encoder->hpd_pin = HPD_PORT_D;
5483                 break;
5484         case PORT_E:
5485                 intel_encoder->hpd_pin = HPD_PORT_E;
5486                 break;
5487         default:
5488                 BUG();
5489         }
5490
5491         if (is_edp(intel_dp)) {
5492                 pps_lock(intel_dp);
5493                 intel_dp_init_panel_power_timestamps(intel_dp);
5494                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5495                         vlv_initial_power_sequencer_setup(intel_dp);
5496                 else
5497                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5498                 pps_unlock(intel_dp);
5499         }
5500
5501         ret = intel_dp_aux_init(intel_dp, intel_connector);
5502         if (ret)
5503                 goto fail;
5504
5505         /* init MST on ports that can support it */
5506         if (HAS_DP_MST(dev) &&
5507             (port == PORT_B || port == PORT_C || port == PORT_D))
5508                 intel_dp_mst_encoder_init(intel_dig_port,
5509                                           intel_connector->base.base.id);
5510
5511         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5512                 intel_dp_aux_fini(intel_dp);
5513                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5514                 goto fail;
5515         }
5516
5517         intel_dp_add_properties(intel_dp, connector);
5518
5519         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5520          * 0xd.  Failure to do so will result in spurious interrupts being
5521          * generated on the port when a cable is not attached.
5522          */
5523         if (IS_G4X(dev) && !IS_GM45(dev)) {
5524                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5525                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5526         }
5527
5528         i915_debugfs_connector_add(connector);
5529
5530         return true;
5531
5532 fail:
5533         if (is_edp(intel_dp)) {
5534                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5535                 /*
5536                  * vdd might still be enabled do to the delayed vdd off.
5537                  * Make sure vdd is actually turned off here.
5538                  */
5539                 pps_lock(intel_dp);
5540                 edp_panel_vdd_off_sync(intel_dp);
5541                 pps_unlock(intel_dp);
5542         }
5543         drm_connector_unregister(connector);
5544         drm_connector_cleanup(connector);
5545
5546         return false;
5547 }
5548
5549 void
5550 intel_dp_init(struct drm_device *dev,
5551               i915_reg_t output_reg, enum port port)
5552 {
5553         struct drm_i915_private *dev_priv = dev->dev_private;
5554         struct intel_digital_port *intel_dig_port;
5555         struct intel_encoder *intel_encoder;
5556         struct drm_encoder *encoder;
5557         struct intel_connector *intel_connector;
5558
5559         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5560         if (!intel_dig_port)
5561                 return;
5562
5563         intel_connector = intel_connector_alloc();
5564         if (!intel_connector)
5565                 goto err_connector_alloc;
5566
5567         intel_encoder = &intel_dig_port->base;
5568         encoder = &intel_encoder->base;
5569
5570         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5571                              DRM_MODE_ENCODER_TMDS, NULL))
5572                 goto err_encoder_init;
5573
5574         intel_encoder->compute_config = intel_dp_compute_config;
5575         intel_encoder->disable = intel_disable_dp;
5576         intel_encoder->get_hw_state = intel_dp_get_hw_state;
5577         intel_encoder->get_config = intel_dp_get_config;
5578         intel_encoder->suspend = intel_dp_encoder_suspend;
5579         if (IS_CHERRYVIEW(dev)) {
5580                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5581                 intel_encoder->pre_enable = chv_pre_enable_dp;
5582                 intel_encoder->enable = vlv_enable_dp;
5583                 intel_encoder->post_disable = chv_post_disable_dp;
5584                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5585         } else if (IS_VALLEYVIEW(dev)) {
5586                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5587                 intel_encoder->pre_enable = vlv_pre_enable_dp;
5588                 intel_encoder->enable = vlv_enable_dp;
5589                 intel_encoder->post_disable = vlv_post_disable_dp;
5590         } else {
5591                 intel_encoder->pre_enable = g4x_pre_enable_dp;
5592                 intel_encoder->enable = g4x_enable_dp;
5593                 if (INTEL_INFO(dev)->gen >= 5)
5594                         intel_encoder->post_disable = ilk_post_disable_dp;
5595         }
5596
5597         intel_dig_port->port = port;
5598         intel_dig_port->dp.output_reg = output_reg;
5599         intel_dig_port->max_lanes = 4;
5600
5601         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5602         if (IS_CHERRYVIEW(dev)) {
5603                 if (port == PORT_D)
5604                         intel_encoder->crtc_mask = 1 << 2;
5605                 else
5606                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5607         } else {
5608                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5609         }
5610         intel_encoder->cloneable = 0;
5611
5612         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5613         dev_priv->hotplug.irq_port[port] = intel_dig_port;
5614
5615         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5616                 goto err_init_connector;
5617
5618         return;
5619
5620 err_init_connector:
5621         drm_encoder_cleanup(encoder);
5622 err_encoder_init:
5623         kfree(intel_connector);
5624 err_connector_alloc:
5625         kfree(intel_dig_port);
5626
5627         return;
5628 }
5629
5630 void intel_dp_mst_suspend(struct drm_device *dev)
5631 {
5632         struct drm_i915_private *dev_priv = dev->dev_private;
5633         int i;
5634
5635         /* disable MST */
5636         for (i = 0; i < I915_MAX_PORTS; i++) {
5637                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5638                 if (!intel_dig_port)
5639                         continue;
5640
5641                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5642                         if (!intel_dig_port->dp.can_mst)
5643                                 continue;
5644                         if (intel_dig_port->dp.is_mst)
5645                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5646                 }
5647         }
5648 }
5649
5650 void intel_dp_mst_resume(struct drm_device *dev)
5651 {
5652         struct drm_i915_private *dev_priv = dev->dev_private;
5653         int i;
5654
5655         for (i = 0; i < I915_MAX_PORTS; i++) {
5656                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5657                 if (!intel_dig_port)
5658                         continue;
5659                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5660                         int ret;
5661
5662                         if (!intel_dig_port->dp.can_mst)
5663                                 continue;
5664
5665                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5666                         if (ret != 0) {
5667                                 intel_dp_check_mst_status(&intel_dig_port->dp);
5668                         }
5669                 }
5670         }
5671 }