drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 130 {
 131         union drm_amdgpu_cs *cs = data;
 132         uint64_t *chunk_array_user;
 133         uint64_t *chunk_array = NULL;
 134         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 135         unsigned size, i;
 136         int r = 0;
 137
 138         if (!cs->in.num_chunks)
 139                 goto out;
 140
 141         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 142         if (!p->ctx) {
 143                 r = -EINVAL;
 144                 goto out;
 145         }
 146         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 147
 148         /* get chunks */
 149         INIT_LIST_HEAD(&p->validated);
 150         chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 151         if (chunk_array == NULL) {
 152                 r = -ENOMEM;
 153                 goto out;
 154         }
 155
 156         chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks);
 157         if (copy_from_user(chunk_array, chunk_array_user,
 158                            sizeof(uint64_t)*cs->in.num_chunks)) {
 159                 r = -EFAULT;
 160                 goto out;
 161         }
 162
 163         p->nchunks = cs->in.num_chunks;
 164         p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 165                             GFP_KERNEL);
 166         if (p->chunks == NULL) {
 167                 r = -ENOMEM;
 168                 goto out;
 169         }
 170
 171         for (i = 0; i < p->nchunks; i++) {
 172                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 173                 struct drm_amdgpu_cs_chunk user_chunk;
 174                 uint32_t __user *cdata;
 175
 176                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 177                 if (copy_from_user(&user_chunk, chunk_ptr,
 178                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 179                         r = -EFAULT;
 180                         goto out;
 181                 }
 182                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 183                 p->chunks[i].length_dw = user_chunk.length_dw;
 184
 185                 size = p->chunks[i].length_dw;
 186                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 187                 p->chunks[i].user_ptr = cdata;
 188
 189                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 190                 if (p->chunks[i].kdata == NULL) {
 191                         r = -ENOMEM;
 192                         goto out;
 193                 }
 194                 size *= sizeof(uint32_t);
 195                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 196                         r = -EFAULT;
 197                         goto out;
 198                 }
 199
 200                 switch (p->chunks[i].chunk_id) {
 201                 case AMDGPU_CHUNK_ID_IB:
 202                         p->num_ibs++;
 203                         break;
 204
 205                 case AMDGPU_CHUNK_ID_FENCE:
 206                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 207                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 208                                 uint32_t handle;
 209                                 struct drm_gem_object *gobj;
 210                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 211
 212                                 fence_data = (void *)p->chunks[i].kdata;
 213                                 handle = fence_data->handle;
 214                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 215                                                              p->filp, handle);
 216                                 if (gobj == NULL) {
 217                                         r = -EINVAL;
 218                                         goto out;
 219                                 }
 220
 221                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 222                                 p->uf.offset = fence_data->offset;
 223                         } else {
 224                                 r = -EINVAL;
 225                                 goto out;
 226                         }
 227                         break;
 228
 229                 default:
 230                         r = -EINVAL;
 231                         goto out;
 232                 }
 233         }
 234
 235         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 236         if (!p->ibs) {
 237                 r = -ENOMEM;
 238                 goto out;
 239         }
 240
 241 out:
 242         kfree(chunk_array);
 243         return r;
 244 }
 245
 246 /* Returns how many bytes TTM can move per IB.
 247  */
 248 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 249 {
 250         u64 real_vram_size = adev->mc.real_vram_size;
 251         u64 vram_usage = atomic64_read(&adev->vram_usage);
 252
 253         /* This function is based on the current VRAM usage.
 254          *
 255          * - If all of VRAM is free, allow relocating the number of bytes that
 256          *   is equal to 1/4 of the size of VRAM for this IB.
 257
 258          * - If more than one half of VRAM is occupied, only allow relocating
 259          *   1 MB of data for this IB.
 260          *
 261          * - From 0 to one half of used VRAM, the threshold decreases
 262          *   linearly.
 263          *         __________________
 264          * 1/4 of -|\               |
 265          * VRAM    | \              |
 266          *         |  \             |
 267          *         |   \            |
 268          *         |    \           |
 269          *         |     \          |
 270          *         |      \         |
 271          *         |       \________|1 MB
 272          *         |----------------|
 273          *    VRAM 0 %             100 %
 274          *         used            used
 275          *
 276          * Note: It's a threshold, not a limit. The threshold must be crossed
 277          * for buffer relocations to stop, so any buffer of an arbitrary size
 278          * can be moved as long as the threshold isn't crossed before
 279          * the relocation takes place. We don't want to disable buffer
 280          * relocations completely.
 281          *
 282          * The idea is that buffers should be placed in VRAM at creation time
 283          * and TTM should only do a minimum number of relocations during
 284          * command submission. In practice, you need to submit at least
 285          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 286          *
 287          * Also, things can get pretty crazy under memory pressure and actual
 288          * VRAM usage can change a lot, so playing safe even at 50% does
 289          * consistently increase performance.
 290          */
 291
 292         u64 half_vram = real_vram_size >> 1;
 293         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 294         u64 bytes_moved_threshold = half_free_vram >> 1;
 295         return max(bytes_moved_threshold, 1024*1024ull);
 296 }
 297
 298 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
 299 {
 300         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 301         struct amdgpu_vm *vm = &fpriv->vm;
 302         struct amdgpu_device *adev = p->adev;
 303         struct amdgpu_bo_list_entry *lobj;
 304         struct list_head duplicates;
 305         struct amdgpu_bo *bo;
 306         u64 bytes_moved = 0, initial_bytes_moved;
 307         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 308         int r;
 309
 310         INIT_LIST_HEAD(&duplicates);
 311         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 312         if (unlikely(r != 0)) {
 313                 return r;
 314         }
 315
 316         list_for_each_entry(lobj, &p->validated, tv.head) {
 317                 bo = lobj->robj;
 318                 if (!bo->pin_count) {
 319                         u32 domain = lobj->prefered_domains;
 320                         u32 current_domain =
 321                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 322
 323                         /* Check if this buffer will be moved and don't move it
 324                          * if we have moved too many buffers for this IB already.
 325                          *
 326                          * Note that this allows moving at least one buffer of
 327                          * any size, because it doesn't take the current "bo"
 328                          * into account. We don't want to disallow buffer moves
 329                          * completely.
 330                          */
 331                         if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
 332                             (domain & current_domain) == 0 && /* will be moved */
 333                             bytes_moved > bytes_moved_threshold) {
 334                                 /* don't move it */
 335                                 domain = current_domain;
 336                         }
 337
 338                 retry:
 339                         amdgpu_ttm_placement_from_domain(bo, domain);
 340                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 341                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 342                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 343                                        initial_bytes_moved;
 344
 345                         if (unlikely(r)) {
 346                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 347                                         domain = lobj->allowed_domains;
 348                                         goto retry;
 349                                 }
 350                                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 351                                 return r;
 352                         }
 353                 }
 354                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 355         }
 356         return 0;
 357 }
 358
 359 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 360 {
 361         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 362         struct amdgpu_cs_buckets buckets;
 363         bool need_mmap_lock = false;
 364         int i, r;
 365
 366         if (p->bo_list) {
 367                 need_mmap_lock = p->bo_list->has_userptr;
 368                 amdgpu_cs_buckets_init(&buckets);
 369                 for (i = 0; i < p->bo_list->num_entries; i++)
 370                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 371                                                                   p->bo_list->array[i].priority);
 372
 373                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 374         }
 375
 376         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 377                                       &p->validated);
 378
 379         if (need_mmap_lock)
 380                 down_read(&current->mm->mmap_sem);
 381
 382         r = amdgpu_cs_list_validate(p);
 383
 384         if (need_mmap_lock)
 385                 up_read(&current->mm->mmap_sem);
 386
 387         return r;
 388 }
 389
 390 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 391 {
 392         struct amdgpu_bo_list_entry *e;
 393         int r;
 394
 395         list_for_each_entry(e, &p->validated, tv.head) {
 396                 struct reservation_object *resv = e->robj->tbo.resv;
 397                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 398
 399                 if (r)
 400                         return r;
 401         }
 402         return 0;
 403 }
 404
 405 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 406                                   struct list_head *b)
 407 {
 408         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 409         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 410
 411         /* Sort A before B if A is smaller. */
 412         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 413 }
 414
 415 /**
 416  * cs_parser_fini() - clean parser states
 417  * @parser:     parser structure holding parsing context.
 418  * @error:      error number
 419  *
 420  * If error is set than unvalidate buffer, otherwise just free memory
 421  * used by parsing context.
 422  **/
 423 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 424 {
 425         unsigned i;
 426
 427         if (!error) {
 428                 /* Sort the buffer list from the smallest to largest buffer,
 429                  * which affects the order of buffers in the LRU list.
 430                  * This assures that the smallest buffers are added first
 431                  * to the LRU list, so they are likely to be later evicted
 432                  * first, instead of large buffers whose eviction is more
 433                  * expensive.
 434                  *
 435                  * This slightly lowers the number of bytes moved by TTM
 436                  * per frame under memory pressure.
 437                  */
 438                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 439
 440                 ttm_eu_fence_buffer_objects(&parser->ticket,
 441                                 &parser->validated,
 442                                 &parser->ibs[parser->num_ibs-1].fence->base);
 443         } else if (backoff) {
 444                 ttm_eu_backoff_reservation(&parser->ticket,
 445                                            &parser->validated);
 446         }
 447
 448         if (parser->ctx)
 449                 amdgpu_ctx_put(parser->ctx);
 450         if (parser->bo_list)
 451                 amdgpu_bo_list_put(parser->bo_list);
 452         drm_free_large(parser->vm_bos);
 453         for (i = 0; i < parser->nchunks; i++)
 454                 drm_free_large(parser->chunks[i].kdata);
 455         kfree(parser->chunks);
 456         if (parser->ibs)
 457                 for (i = 0; i < parser->num_ibs; i++)
 458                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 459         kfree(parser->ibs);
 460         if (parser->uf.bo)
 461                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 462 }
 463
 464 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 465                                    struct amdgpu_vm *vm)
 466 {
 467         struct amdgpu_device *adev = p->adev;
 468         struct amdgpu_bo_va *bo_va;
 469         struct amdgpu_bo *bo;
 470         int i, r;
 471
 472         r = amdgpu_vm_update_page_directory(adev, vm);
 473         if (r)
 474                 return r;
 475
 476         r = amdgpu_vm_clear_freed(adev, vm);
 477         if (r)
 478                 return r;
 479
 480         if (p->bo_list) {
 481                 for (i = 0; i < p->bo_list->num_entries; i++) {
 482                         /* ignore duplicates */
 483                         bo = p->bo_list->array[i].robj;
 484                         if (!bo)
 485                                 continue;
 486
 487                         bo_va = p->bo_list->array[i].bo_va;
 488                         if (bo_va == NULL)
 489                                 continue;
 490
 491                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 492                         if (r)
 493                                 return r;
 494
 495                         amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
 496                 }
 497         }
 498
 499         return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 500 }
 501
 502 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 503                                  struct amdgpu_cs_parser *parser)
 504 {
 505         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 506         struct amdgpu_vm *vm = &fpriv->vm;
 507         struct amdgpu_ring *ring;
 508         int i, r;
 509
 510         if (parser->num_ibs == 0)
 511                 return 0;
 512
 513         /* Only for UVD/VCE VM emulation */
 514         for (i = 0; i < parser->num_ibs; i++) {
 515                 ring = parser->ibs[i].ring;
 516                 if (ring->funcs->parse_cs) {
 517                         r = amdgpu_ring_parse_cs(ring, parser, i);
 518                         if (r)
 519                                 return r;
 520                 }
 521         }
 522
 523         mutex_lock(&vm->mutex);
 524         r = amdgpu_bo_vm_update_pte(parser, vm);
 525         if (r) {
 526                 goto out;
 527         }
 528         amdgpu_cs_sync_rings(parser);
 529
 530         r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 531                                parser->filp);
 532
 533 out:
 534         mutex_unlock(&vm->mutex);
 535         return r;
 536 }
 537
 538 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 539 {
 540         if (r == -EDEADLK) {
 541                 r = amdgpu_gpu_reset(adev);
 542                 if (!r)
 543                         r = -EAGAIN;
 544         }
 545         return r;
 546 }
 547
 548 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 549                              struct amdgpu_cs_parser *parser)
 550 {
 551         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 552         struct amdgpu_vm *vm = &fpriv->vm;
 553         int i, j;
 554         int r;
 555
 556         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 557                 struct amdgpu_cs_chunk *chunk;
 558                 struct amdgpu_ib *ib;
 559                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 560                 struct amdgpu_ring *ring;
 561
 562                 chunk = &parser->chunks[i];
 563                 ib = &parser->ibs[j];
 564                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 565
 566                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 567                         continue;
 568
 569                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 570                                        chunk_ib->ip_instance, chunk_ib->ring,
 571                                        &ring);
 572                 if (r)
 573                         return r;
 574
 575                 if (ring->funcs->parse_cs) {
 576                         struct amdgpu_bo_va_mapping *m;
 577                         struct amdgpu_bo *aobj = NULL;
 578                         uint64_t offset;
 579                         uint8_t *kptr;
 580
 581                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 582                                                    &aobj);
 583                         if (!aobj) {
 584                                 DRM_ERROR("IB va_start is invalid\n");
 585                                 return -EINVAL;
 586                         }
 587
 588                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 589                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 590                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 591                                 return -EINVAL;
 592                         }
 593
 594                         /* the IB should be reserved at this point */
 595                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 596                         if (r) {
 597                                 return r;
 598                         }
 599
 600                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 601                         kptr += chunk_ib->va_start - offset;
 602
 603                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 604                         if (r) {
 605                                 DRM_ERROR("Failed to get ib !\n");
 606                                 return r;
 607                         }
 608
 609                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 610                         amdgpu_bo_kunmap(aobj);
 611                 } else {
 612                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 613                         if (r) {
 614                                 DRM_ERROR("Failed to get ib !\n");
 615                                 return r;
 616                         }
 617
 618                         ib->gpu_addr = chunk_ib->va_start;
 619                 }
 620
 621                 ib->length_dw = chunk_ib->ib_bytes / 4;
 622                 ib->flags = chunk_ib->flags;
 623                 ib->ctx = parser->ctx;
 624                 j++;
 625         }
 626
 627         if (!parser->num_ibs)
 628                 return 0;
 629
 630         /* add GDS resources to first IB */
 631         if (parser->bo_list) {
 632                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 633                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 634                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 635                 struct amdgpu_ib *ib = &parser->ibs[0];
 636
 637                 if (gds) {
 638                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 639                         ib->gds_size = amdgpu_bo_size(gds);
 640                 }
 641                 if (gws) {
 642                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 643                         ib->gws_size = amdgpu_bo_size(gws);
 644                 }
 645                 if (oa) {
 646                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 647                         ib->oa_size = amdgpu_bo_size(oa);
 648                 }
 649         }
 650
 651         /* wrap the last IB with user fence */
 652         if (parser->uf.bo) {
 653                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 654
 655                 /* UVD & VCE fw doesn't support user fences */
 656                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 657                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 658                         return -EINVAL;
 659
 660                 ib->user = &parser->uf;
 661         }
 662
 663         return 0;
 664 }
 665
 666 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 667 {
 668         struct amdgpu_device *adev = dev->dev_private;
 669         union drm_amdgpu_cs *cs = data;
 670         struct amdgpu_cs_parser parser;
 671         int r, i;
 672         bool reserved_buffers = false;
 673
 674         down_read(&adev->exclusive_lock);
 675         if (!adev->accel_working) {
 676                 up_read(&adev->exclusive_lock);
 677                 return -EBUSY;
 678         }
 679         /* initialize parser */
 680         memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
 681         parser.filp = filp;
 682         parser.adev = adev;
 683         r = amdgpu_cs_parser_init(&parser, data);
 684         if (r) {
 685                 DRM_ERROR("Failed to initialize parser !\n");
 686                 amdgpu_cs_parser_fini(&parser, r, false);
 687                 up_read(&adev->exclusive_lock);
 688                 r = amdgpu_cs_handle_lockup(adev, r);
 689                 return r;
 690         }
 691
 692         r = amdgpu_cs_parser_relocs(&parser);
 693         if (r) {
 694                 if (r != -ERESTARTSYS) {
 695                         if (r == -ENOMEM)
 696                                 DRM_ERROR("Not enough memory for command submission!\n");
 697                         else
 698                                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 699                 }
 700         } else {
 701                 reserved_buffers = true;
 702                 r = amdgpu_cs_ib_fill(adev, &parser);
 703         }
 704
 705         if (r) {
 706                 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 707                 up_read(&adev->exclusive_lock);
 708                 r = amdgpu_cs_handle_lockup(adev, r);
 709                 return r;
 710         }
 711
 712         for (i = 0; i < parser.num_ibs; i++)
 713                 trace_amdgpu_cs(&parser, i);
 714
 715         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 716         if (r) {
 717                 goto out;
 718         }
 719
 720         cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq;
 721 out:
 722         amdgpu_cs_parser_fini(&parser, r, true);
 723         up_read(&adev->exclusive_lock);
 724         r = amdgpu_cs_handle_lockup(adev, r);
 725         return r;
 726 }
 727
 728 /**
 729  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 730  *
 731  * @dev: drm device
 732  * @data: data from userspace
 733  * @filp: file private
 734  *
 735  * Wait for the command submission identified by handle to finish.
 736  */
 737 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 738                          struct drm_file *filp)
 739 {
 740         union drm_amdgpu_wait_cs *wait = data;
 741         struct amdgpu_device *adev = dev->dev_private;
 742         uint64_t seq[AMDGPU_MAX_RINGS] = {0};
 743         struct amdgpu_ring *ring = NULL;
 744         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 745         struct amdgpu_ctx *ctx;
 746         long r;
 747
 748         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 749         if (ctx == NULL)
 750                 return -EINVAL;
 751
 752         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 753                                wait->in.ring, &ring);
 754         if (r)
 755                 return r;
 756
 757         seq[ring->idx] = wait->in.handle;
 758
 759         r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout);
 760         amdgpu_ctx_put(ctx);
 761         if (r < 0)
 762                 return r;
 763
 764         memset(wait, 0, sizeof(*wait));
 765         wait->out.status = (r == 0);
 766
 767         return 0;
 768 }
 769
 770 /**
 771  * amdgpu_cs_find_bo_va - find bo_va for VM address
 772  *
 773  * @parser: command submission parser context
 774  * @addr: VM address
 775  * @bo: resulting BO of the mapping found
 776  *
 777  * Search the buffer objects in the command submission context for a certain
 778  * virtual memory address. Returns allocation structure when found, NULL
 779  * otherwise.
 780  */
 781 struct amdgpu_bo_va_mapping *
 782 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 783                        uint64_t addr, struct amdgpu_bo **bo)
 784 {
 785         struct amdgpu_bo_list_entry *reloc;
 786         struct amdgpu_bo_va_mapping *mapping;
 787
 788         addr /= AMDGPU_GPU_PAGE_SIZE;
 789
 790         list_for_each_entry(reloc, &parser->validated, tv.head) {
 791                 if (!reloc->bo_va)
 792                         continue;
 793
 794                 list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
 795                         if (mapping->it.start > addr ||
 796                             addr > mapping->it.last)
 797                                 continue;
 798
 799                         *bo = reloc->bo_va->bo;
 800                         return mapping;
 801                 }
 802         }
 803
 804         return NULL;
 805 }