drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "amdgpu_smu.h"
  38 #include "atom.h"
  39 #include "amd_pcie.h"
  40
  41 #include "gc/gc_10_1_0_offset.h"
  42 #include "gc/gc_10_1_0_sh_mask.h"
  43 #include "mp/mp_11_0_offset.h"
  44
  45 #include "soc15.h"
  46 #include "soc15_common.h"
  47 #include "gmc_v10_0.h"
  48 #include "gfxhub_v2_0.h"
  49 #include "mmhub_v2_0.h"
  50 #include "nbio_v2_3.h"
  51 #include "nbio_v7_2.h"
  52 #include "hdp_v5_0.h"
  53 #include "nv.h"
  54 #include "navi10_ih.h"
  55 #include "gfx_v10_0.h"
  56 #include "sdma_v5_0.h"
  57 #include "sdma_v5_2.h"
  58 #include "vcn_v2_0.h"
  59 #include "jpeg_v2_0.h"
  60 #include "vcn_v3_0.h"
  61 #include "jpeg_v3_0.h"
  62 #include "dce_virtual.h"
  63 #include "mes_v10_1.h"
  64 #include "mxgpu_nv.h"
  65 #include "smuio_v11_0.h"
  66 #include "smuio_v11_0_6.h"
  67
  68 static const struct amd_ip_funcs nv_common_ip_funcs;
  69
  70 /* Navi */
  71 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  72 {
  73         {
  74                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
  75                 .max_width = 4096,
  76                 .max_height = 2304,
  77                 .max_pixels_per_frame = 4096 * 2304,
  78                 .max_level = 0,
  79         },
  80         {
  81                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
  82                 .max_width = 4096,
  83                 .max_height = 2304,
  84                 .max_pixels_per_frame = 4096 * 2304,
  85                 .max_level = 0,
  86         },
  87 };
  88
  89 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  90 {
  91         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  92         .codec_array = nv_video_codecs_encode_array,
  93 };
  94
  95 /* Navi1x */
  96 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  97 {
  98         {
  99                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 100                 .max_width = 4096,
 101                 .max_height = 4096,
 102                 .max_pixels_per_frame = 4096 * 4096,
 103                 .max_level = 3,
 104         },
 105         {
 106                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 107                 .max_width = 4096,
 108                 .max_height = 4096,
 109                 .max_pixels_per_frame = 4096 * 4096,
 110                 .max_level = 5,
 111         },
 112         {
 113                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 114                 .max_width = 4096,
 115                 .max_height = 4096,
 116                 .max_pixels_per_frame = 4096 * 4096,
 117                 .max_level = 52,
 118         },
 119         {
 120                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 121                 .max_width = 4096,
 122                 .max_height = 4096,
 123                 .max_pixels_per_frame = 4096 * 4096,
 124                 .max_level = 4,
 125         },
 126         {
 127                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 128                 .max_width = 8192,
 129                 .max_height = 4352,
 130                 .max_pixels_per_frame = 8192 * 4352,
 131                 .max_level = 186,
 132         },
 133         {
 134                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 135                 .max_width = 4096,
 136                 .max_height = 4096,
 137                 .max_pixels_per_frame = 4096 * 4096,
 138                 .max_level = 0,
 139         },
 140         {
 141                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 142                 .max_width = 8192,
 143                 .max_height = 4352,
 144                 .max_pixels_per_frame = 8192 * 4352,
 145                 .max_level = 0,
 146         },
 147 };
 148
 149 static const struct amdgpu_video_codecs nv_video_codecs_decode =
 150 {
 151         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
 152         .codec_array = nv_video_codecs_decode_array,
 153 };
 154
 155 /* Sienna Cichlid */
 156 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 157 {
 158         {
 159                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,
 160                 .max_width = 4096,
 161                 .max_height = 4096,
 162                 .max_pixels_per_frame = 4096 * 4096,
 163                 .max_level = 3,
 164         },
 165         {
 166                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,
 167                 .max_width = 4096,
 168                 .max_height = 4096,
 169                 .max_pixels_per_frame = 4096 * 4096,
 170                 .max_level = 5,
 171         },
 172         {
 173                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,
 174                 .max_width = 4096,
 175                 .max_height = 4096,
 176                 .max_pixels_per_frame = 4096 * 4096,
 177                 .max_level = 52,
 178         },
 179         {
 180                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,
 181                 .max_width = 4096,
 182                 .max_height = 4096,
 183                 .max_pixels_per_frame = 4096 * 4096,
 184                 .max_level = 4,
 185         },
 186         {
 187                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,
 188                 .max_width = 8192,
 189                 .max_height = 4352,
 190                 .max_pixels_per_frame = 8192 * 4352,
 191                 .max_level = 186,
 192         },
 193         {
 194                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,
 195                 .max_width = 4096,
 196                 .max_height = 4096,
 197                 .max_pixels_per_frame = 4096 * 4096,
 198                 .max_level = 0,
 199         },
 200         {
 201                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,
 202                 .max_width = 8192,
 203                 .max_height = 4352,
 204                 .max_pixels_per_frame = 8192 * 4352,
 205                 .max_level = 0,
 206         },
 207         {
 208                 .codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,
 209                 .max_width = 8192,
 210                 .max_height = 4352,
 211                 .max_pixels_per_frame = 8192 * 4352,
 212                 .max_level = 0,
 213         },
 214 };
 215
 216 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 217 {
 218         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 219         .codec_array = sc_video_codecs_decode_array,
 220 };
 221
 222 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 223                                  const struct amdgpu_video_codecs **codecs)
 224 {
 225         switch (adev->asic_type) {
 226         case CHIP_SIENNA_CICHLID:
 227         case CHIP_NAVY_FLOUNDER:
 228         case CHIP_DIMGREY_CAVEFISH:
 229         case CHIP_VANGOGH:
 230                 if (encode)
 231                         *codecs = &nv_video_codecs_encode;
 232                 else
 233                         *codecs = &sc_video_codecs_decode;
 234                 return 0;
 235         case CHIP_NAVI10:
 236         case CHIP_NAVI14:
 237         case CHIP_NAVI12:
 238                 if (encode)
 239                         *codecs = &nv_video_codecs_encode;
 240                 else
 241                         *codecs = &nv_video_codecs_decode;
 242                 return 0;
 243         default:
 244                 return -EINVAL;
 245         }
 246 }
 247
 248 /*
 249  * Indirect registers accessor
 250  */
 251 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 252 {
 253         unsigned long address, data;
 254         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 255         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 256
 257         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 258 }
 259
 260 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 261 {
 262         unsigned long address, data;
 263
 264         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 265         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 266
 267         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 268 }
 269
 270 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 271 {
 272         unsigned long address, data;
 273         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 274         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 275
 276         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 277 }
 278
 279 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
 280 {
 281         unsigned long flags, address, data;
 282         u32 r;
 283         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 284         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 285
 286         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 287         WREG32(address, reg * 4);
 288         (void)RREG32(address);
 289         r = RREG32(data);
 290         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 291         return r;
 292 }
 293
 294 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 295 {
 296         unsigned long address, data;
 297
 298         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 299         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 300
 301         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 302 }
 303
 304 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 305 {
 306         unsigned long flags, address, data;
 307
 308         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 309         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 310
 311         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 312         WREG32(address, reg * 4);
 313         (void)RREG32(address);
 314         WREG32(data, v);
 315         (void)RREG32(data);
 316         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 317 }
 318
 319 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 320 {
 321         unsigned long flags, address, data;
 322         u32 r;
 323
 324         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 325         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 326
 327         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 328         WREG32(address, (reg));
 329         r = RREG32(data);
 330         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 331         return r;
 332 }
 333
 334 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 335 {
 336         unsigned long flags, address, data;
 337
 338         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 339         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 340
 341         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 342         WREG32(address, (reg));
 343         WREG32(data, (v));
 344         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 345 }
 346
 347 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 348 {
 349         return adev->nbio.funcs->get_memsize(adev);
 350 }
 351
 352 static u32 nv_get_xclk(struct amdgpu_device *adev)
 353 {
 354         return adev->clock.spll.reference_freq;
 355 }
 356
 357
 358 void nv_grbm_select(struct amdgpu_device *adev,
 359                      u32 me, u32 pipe, u32 queue, u32 vmid)
 360 {
 361         u32 grbm_gfx_cntl = 0;
 362         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 363         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 364         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 365         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 366
 367         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 368 }
 369
 370 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 371 {
 372         /* todo */
 373 }
 374
 375 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 376 {
 377         /* todo */
 378         return false;
 379 }
 380
 381 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 382                                   u8 *bios, u32 length_bytes)
 383 {
 384         u32 *dw_ptr;
 385         u32 i, length_dw;
 386         u32 rom_index_offset, rom_data_offset;
 387
 388         if (bios == NULL)
 389                 return false;
 390         if (length_bytes == 0)
 391                 return false;
 392         /* APU vbios image is part of sbios image */
 393         if (adev->flags & AMD_IS_APU)
 394                 return false;
 395
 396         dw_ptr = (u32 *)bios;
 397         length_dw = ALIGN(length_bytes, 4) / 4;
 398
 399         rom_index_offset =
 400                 adev->smuio.funcs->get_rom_index_offset(adev);
 401         rom_data_offset =
 402                 adev->smuio.funcs->get_rom_data_offset(adev);
 403
 404         /* set rom index to 0 */
 405         WREG32(rom_index_offset, 0);
 406         /* read out the rom data */
 407         for (i = 0; i < length_dw; i++)
 408                 dw_ptr[i] = RREG32(rom_data_offset);
 409
 410         return true;
 411 }
 412
 413 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 414         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 415         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 416         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 417         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 418         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 419         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 420         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 421         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 422         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 423         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 424         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 425         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 426         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 427         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 428         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 429         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 430         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 431         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 432         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 433 };
 434
 435 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 436                                          u32 sh_num, u32 reg_offset)
 437 {
 438         uint32_t val;
 439
 440         mutex_lock(&adev->grbm_idx_mutex);
 441         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 442                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 443
 444         val = RREG32(reg_offset);
 445
 446         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 447                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 448         mutex_unlock(&adev->grbm_idx_mutex);
 449         return val;
 450 }
 451
 452 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 453                                       bool indexed, u32 se_num,
 454                                       u32 sh_num, u32 reg_offset)
 455 {
 456         if (indexed) {
 457                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 458         } else {
 459                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 460                         return adev->gfx.config.gb_addr_config;
 461                 return RREG32(reg_offset);
 462         }
 463 }
 464
 465 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 466                             u32 sh_num, u32 reg_offset, u32 *value)
 467 {
 468         uint32_t i;
 469         struct soc15_allowed_register_entry  *en;
 470
 471         *value = 0;
 472         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 473                 en = &nv_allowed_read_registers[i];
 474                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 475                     reg_offset !=
 476                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 477                         continue;
 478
 479                 *value = nv_get_register_value(adev,
 480                                                nv_allowed_read_registers[i].grbm_indexed,
 481                                                se_num, sh_num, reg_offset);
 482                 return 0;
 483         }
 484         return -EINVAL;
 485 }
 486
 487 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 488 {
 489         u32 i;
 490         int ret = 0;
 491
 492         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 493
 494         /* disable BM */
 495         pci_clear_master(adev->pdev);
 496
 497         amdgpu_device_cache_pci_state(adev->pdev);
 498
 499         ret = amdgpu_dpm_mode2_reset(adev);
 500         if (ret)
 501                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 502
 503         amdgpu_device_load_pci_state(adev->pdev);
 504
 505         /* wait for asic to come out of reset */
 506         for (i = 0; i < adev->usec_timeout; i++) {
 507                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 508
 509                 if (memsize != 0xffffffff)
 510                         break;
 511                 udelay(1);
 512         }
 513
 514         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 515
 516         return ret;
 517 }
 518
 519 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 520 {
 521         struct smu_context *smu = &adev->smu;
 522
 523         if (smu_baco_is_support(smu))
 524                 return true;
 525         else
 526                 return false;
 527 }
 528
 529 static enum amd_reset_method
 530 nv_asic_reset_method(struct amdgpu_device *adev)
 531 {
 532         struct smu_context *smu = &adev->smu;
 533
 534         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 535             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 536             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 537             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 538                 return amdgpu_reset_method;
 539
 540         if (amdgpu_reset_method != -1)
 541                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 542                                   amdgpu_reset_method);
 543
 544         switch (adev->asic_type) {
 545         case CHIP_VANGOGH:
 546                 return AMD_RESET_METHOD_MODE2;
 547         case CHIP_SIENNA_CICHLID:
 548         case CHIP_NAVY_FLOUNDER:
 549         case CHIP_DIMGREY_CAVEFISH:
 550                 return AMD_RESET_METHOD_MODE1;
 551         default:
 552                 if (smu_baco_is_support(smu))
 553                         return AMD_RESET_METHOD_BACO;
 554                 else
 555                         return AMD_RESET_METHOD_MODE1;
 556         }
 557 }
 558
 559 static int nv_asic_reset(struct amdgpu_device *adev)
 560 {
 561         int ret = 0;
 562         struct smu_context *smu = &adev->smu;
 563
 564         /* skip reset on vangogh for now */
 565         if (adev->asic_type == CHIP_VANGOGH)
 566                 return 0;
 567
 568         switch (nv_asic_reset_method(adev)) {
 569         case AMD_RESET_METHOD_PCI:
 570                 dev_info(adev->dev, "PCI reset\n");
 571                 ret = amdgpu_device_pci_reset(adev);
 572                 break;
 573         case AMD_RESET_METHOD_BACO:
 574                 dev_info(adev->dev, "BACO reset\n");
 575
 576                 ret = smu_baco_enter(smu);
 577                 if (ret)
 578                         return ret;
 579                 ret = smu_baco_exit(smu);
 580                 if (ret)
 581                         return ret;
 582                 break;
 583         case AMD_RESET_METHOD_MODE2:
 584                 dev_info(adev->dev, "MODE2 reset\n");
 585                 ret = nv_asic_mode2_reset(adev);
 586                 break;
 587         default:
 588                 dev_info(adev->dev, "MODE1 reset\n");
 589                 ret = amdgpu_device_mode1_reset(adev);
 590                 break;
 591         }
 592
 593         return ret;
 594 }
 595
 596 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 597 {
 598         /* todo */
 599         return 0;
 600 }
 601
 602 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 603 {
 604         /* todo */
 605         return 0;
 606 }
 607
 608 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 609 {
 610         if (pci_is_root_bus(adev->pdev->bus))
 611                 return;
 612
 613         if (amdgpu_pcie_gen2 == 0)
 614                 return;
 615
 616         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 617                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 618                 return;
 619
 620         /* todo */
 621 }
 622
 623 static void nv_program_aspm(struct amdgpu_device *adev)
 624 {
 625         if (amdgpu_aspm != 1)
 626                 return;
 627
 628         if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
 629             !(adev->flags & AMD_IS_APU) &&
 630             (adev->nbio.funcs->program_aspm))
 631                 adev->nbio.funcs->program_aspm(adev);
 632
 633 }
 634
 635 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 636                                         bool enable)
 637 {
 638         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 639         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 640 }
 641
 642 static const struct amdgpu_ip_block_version nv_common_ip_block =
 643 {
 644         .type = AMD_IP_BLOCK_TYPE_COMMON,
 645         .major = 1,
 646         .minor = 0,
 647         .rev = 0,
 648         .funcs = &nv_common_ip_funcs,
 649 };
 650
 651 static int nv_reg_base_init(struct amdgpu_device *adev)
 652 {
 653         int r;
 654
 655         if (amdgpu_discovery) {
 656                 r = amdgpu_discovery_reg_base_init(adev);
 657                 if (r) {
 658                         DRM_WARN("failed to init reg base from ip discovery table, "
 659                                         "fallback to legacy init method\n");
 660                         goto legacy_init;
 661                 }
 662
 663                 return 0;
 664         }
 665
 666 legacy_init:
 667         switch (adev->asic_type) {
 668         case CHIP_NAVI10:
 669                 navi10_reg_base_init(adev);
 670                 break;
 671         case CHIP_NAVI14:
 672                 navi14_reg_base_init(adev);
 673                 break;
 674         case CHIP_NAVI12:
 675                 navi12_reg_base_init(adev);
 676                 break;
 677         case CHIP_SIENNA_CICHLID:
 678         case CHIP_NAVY_FLOUNDER:
 679                 sienna_cichlid_reg_base_init(adev);
 680                 break;
 681         case CHIP_VANGOGH:
 682                 vangogh_reg_base_init(adev);
 683                 break;
 684         case CHIP_DIMGREY_CAVEFISH:
 685                 dimgrey_cavefish_reg_base_init(adev);
 686                 break;
 687         default:
 688                 return -EINVAL;
 689         }
 690
 691         return 0;
 692 }
 693
 694 void nv_set_virt_ops(struct amdgpu_device *adev)
 695 {
 696         adev->virt.ops = &xgpu_nv_virt_ops;
 697 }
 698
 699 static bool nv_is_headless_sku(struct pci_dev *pdev)
 700 {
 701         if ((pdev->device == 0x731E &&
 702             (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
 703             (pdev->device == 0x7340 && pdev->revision == 0xC9)  ||
 704             (pdev->device == 0x7360 && pdev->revision == 0xC7))
 705                 return true;
 706         return false;
 707 }
 708
 709 int nv_set_ip_blocks(struct amdgpu_device *adev)
 710 {
 711         int r;
 712
 713         if (adev->flags & AMD_IS_APU) {
 714                 adev->nbio.funcs = &nbio_v7_2_funcs;
 715                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
 716         } else {
 717                 adev->nbio.funcs = &nbio_v2_3_funcs;
 718                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 719         }
 720         adev->hdp.funcs = &hdp_v5_0_funcs;
 721
 722         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 723                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
 724         else
 725                 adev->smuio.funcs = &smuio_v11_0_funcs;
 726
 727         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 728                 adev->gmc.xgmi.supported = true;
 729
 730         /* Set IP register base before any HW register access */
 731         r = nv_reg_base_init(adev);
 732         if (r)
 733                 return r;
 734
 735         switch (adev->asic_type) {
 736         case CHIP_NAVI10:
 737         case CHIP_NAVI14:
 738                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 739                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 740                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 741                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 742                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 743                     !amdgpu_sriov_vf(adev))
 744                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 745                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 746                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 747 #if defined(CONFIG_DRM_AMD_DC)
 748                 else if (amdgpu_device_has_dc_support(adev))
 749                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 750 #endif
 751                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 752                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 753                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 754                     !amdgpu_sriov_vf(adev))
 755                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 756                 if (!nv_is_headless_sku(adev->pdev))
 757                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 758                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 759                 if (adev->enable_mes)
 760                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 761                 break;
 762         case CHIP_NAVI12:
 763                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 764                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 765                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 766                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 767                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 768                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 769                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 770                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 771 #if defined(CONFIG_DRM_AMD_DC)
 772                 else if (amdgpu_device_has_dc_support(adev))
 773                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 774 #endif
 775                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 776                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 777                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 778                     !amdgpu_sriov_vf(adev))
 779                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 780                 if (!nv_is_headless_sku(adev->pdev))
 781                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 782                 if (!amdgpu_sriov_vf(adev))
 783                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 784                 break;
 785         case CHIP_SIENNA_CICHLID:
 786                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 787                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 788                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 789                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 790                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 791                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 792                     is_support_sw_smu(adev))
 793                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 794                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 795                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 796 #if defined(CONFIG_DRM_AMD_DC)
 797                 else if (amdgpu_device_has_dc_support(adev))
 798                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 799 #endif
 800                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 801                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 802                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 803                 if (!amdgpu_sriov_vf(adev))
 804                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 805
 806                 if (adev->enable_mes)
 807                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 808                 break;
 809         case CHIP_NAVY_FLOUNDER:
 810                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 811                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 812                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 813                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 814                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 815                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 816                     is_support_sw_smu(adev))
 817                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 818                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 819                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 820 #if defined(CONFIG_DRM_AMD_DC)
 821                 else if (amdgpu_device_has_dc_support(adev))
 822                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 823 #endif
 824                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 825                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 826                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 827                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 828                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 829                     is_support_sw_smu(adev))
 830                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 831                 break;
 832         case CHIP_VANGOGH:
 833                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 834                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 835                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 836                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 837                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 838                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 839                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 840                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 841 #if defined(CONFIG_DRM_AMD_DC)
 842                 else if (amdgpu_device_has_dc_support(adev))
 843                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 844 #endif
 845                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 846                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 847                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 848                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 849                 break;
 850         case CHIP_DIMGREY_CAVEFISH:
 851                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 852                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 853                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 854                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 855                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 856                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 857                     is_support_sw_smu(adev))
 858                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 859                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 860                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 861 #if defined(CONFIG_DRM_AMD_DC)
 862                 else if (amdgpu_device_has_dc_support(adev))
 863                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 864 #endif
 865                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 866                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 867                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 868                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 869                 break;
 870         default:
 871                 return -EINVAL;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 878 {
 879         return adev->nbio.funcs->get_rev_id(adev);
 880 }
 881
 882 static bool nv_need_full_reset(struct amdgpu_device *adev)
 883 {
 884         return true;
 885 }
 886
 887 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 888 {
 889         u32 sol_reg;
 890
 891         if (adev->flags & AMD_IS_APU)
 892                 return false;
 893
 894         /* Check sOS sign of life register to confirm sys driver and sOS
 895          * are already been loaded.
 896          */
 897         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 898         if (sol_reg)
 899                 return true;
 900
 901         return false;
 902 }
 903
 904 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 905 {
 906
 907         /* TODO
 908          * dummy implement for pcie_replay_count sysfs interface
 909          * */
 910
 911         return 0;
 912 }
 913
 914 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 915 {
 916         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 917         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 918         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 919         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 920         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 921         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 922         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 923         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 924         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 925         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 926         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 927         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 928         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 929         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 930         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 931         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 932         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 933         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 934         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 935         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 936         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 937         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 938         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 939         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 940         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 941
 942         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 943         adev->doorbell_index.sdma_doorbell_range = 20;
 944 }
 945
 946 static void nv_pre_asic_init(struct amdgpu_device *adev)
 947 {
 948 }
 949
 950 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 951                                        bool enter)
 952 {
 953         if (enter)
 954                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 955         else
 956                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 957
 958         if (adev->gfx.funcs->update_perfmon_mgcg)
 959                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 960
 961         /*
 962          * The ASPM function is not fully enabled and verified on
 963          * Navi yet. Temporarily skip this until ASPM enabled.
 964          */
 965         if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
 966             !(adev->flags & AMD_IS_APU) &&
 967             (adev->nbio.funcs->enable_aspm))
 968                 adev->nbio.funcs->enable_aspm(adev, !enter);
 969
 970         return 0;
 971 }
 972
 973 static const struct amdgpu_asic_funcs nv_asic_funcs =
 974 {
 975         .read_disabled_bios = &nv_read_disabled_bios,
 976         .read_bios_from_rom = &nv_read_bios_from_rom,
 977         .read_register = &nv_read_register,
 978         .reset = &nv_asic_reset,
 979         .reset_method = &nv_asic_reset_method,
 980         .set_vga_state = &nv_vga_set_state,
 981         .get_xclk = &nv_get_xclk,
 982         .set_uvd_clocks = &nv_set_uvd_clocks,
 983         .set_vce_clocks = &nv_set_vce_clocks,
 984         .get_config_memsize = &nv_get_config_memsize,
 985         .init_doorbell_index = &nv_init_doorbell_index,
 986         .need_full_reset = &nv_need_full_reset,
 987         .need_reset_on_init = &nv_need_reset_on_init,
 988         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 989         .supports_baco = &nv_asic_supports_baco,
 990         .pre_asic_init = &nv_pre_asic_init,
 991         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 992         .query_video_codecs = &nv_query_video_codecs,
 993 };
 994
 995 static int nv_common_early_init(void *handle)
 996 {
 997 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 998         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 999
1000         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
1001         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
1002         adev->smc_rreg = NULL;
1003         adev->smc_wreg = NULL;
1004         adev->pcie_rreg = &nv_pcie_rreg;
1005         adev->pcie_wreg = &nv_pcie_wreg;
1006         adev->pcie_rreg64 = &nv_pcie_rreg64;
1007         adev->pcie_wreg64 = &nv_pcie_wreg64;
1008         adev->pciep_rreg = &nv_pcie_port_rreg;
1009         adev->pciep_wreg = &nv_pcie_port_wreg;
1010
1011         /* TODO: will add them during VCN v2 implementation */
1012         adev->uvd_ctx_rreg = NULL;
1013         adev->uvd_ctx_wreg = NULL;
1014
1015         adev->didt_rreg = &nv_didt_rreg;
1016         adev->didt_wreg = &nv_didt_wreg;
1017
1018         adev->asic_funcs = &nv_asic_funcs;
1019
1020         adev->rev_id = nv_get_rev_id(adev);
1021         adev->external_rev_id = 0xff;
1022         switch (adev->asic_type) {
1023         case CHIP_NAVI10:
1024                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1025                         AMD_CG_SUPPORT_GFX_CGCG |
1026                         AMD_CG_SUPPORT_IH_CG |
1027                         AMD_CG_SUPPORT_HDP_MGCG |
1028                         AMD_CG_SUPPORT_HDP_LS |
1029                         AMD_CG_SUPPORT_SDMA_MGCG |
1030                         AMD_CG_SUPPORT_SDMA_LS |
1031                         AMD_CG_SUPPORT_MC_MGCG |
1032                         AMD_CG_SUPPORT_MC_LS |
1033                         AMD_CG_SUPPORT_ATHUB_MGCG |
1034                         AMD_CG_SUPPORT_ATHUB_LS |
1035                         AMD_CG_SUPPORT_VCN_MGCG |
1036                         AMD_CG_SUPPORT_JPEG_MGCG |
1037                         AMD_CG_SUPPORT_BIF_MGCG |
1038                         AMD_CG_SUPPORT_BIF_LS;
1039                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1040                         AMD_PG_SUPPORT_VCN_DPG |
1041                         AMD_PG_SUPPORT_JPEG |
1042                         AMD_PG_SUPPORT_ATHUB;
1043                 adev->external_rev_id = adev->rev_id + 0x1;
1044                 break;
1045         case CHIP_NAVI14:
1046                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1047                         AMD_CG_SUPPORT_GFX_CGCG |
1048                         AMD_CG_SUPPORT_IH_CG |
1049                         AMD_CG_SUPPORT_HDP_MGCG |
1050                         AMD_CG_SUPPORT_HDP_LS |
1051                         AMD_CG_SUPPORT_SDMA_MGCG |
1052                         AMD_CG_SUPPORT_SDMA_LS |
1053                         AMD_CG_SUPPORT_MC_MGCG |
1054                         AMD_CG_SUPPORT_MC_LS |
1055                         AMD_CG_SUPPORT_ATHUB_MGCG |
1056                         AMD_CG_SUPPORT_ATHUB_LS |
1057                         AMD_CG_SUPPORT_VCN_MGCG |
1058                         AMD_CG_SUPPORT_JPEG_MGCG |
1059                         AMD_CG_SUPPORT_BIF_MGCG |
1060                         AMD_CG_SUPPORT_BIF_LS;
1061                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1062                         AMD_PG_SUPPORT_JPEG |
1063                         AMD_PG_SUPPORT_VCN_DPG;
1064                 adev->external_rev_id = adev->rev_id + 20;
1065                 break;
1066         case CHIP_NAVI12:
1067                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1068                         AMD_CG_SUPPORT_GFX_MGLS |
1069                         AMD_CG_SUPPORT_GFX_CGCG |
1070                         AMD_CG_SUPPORT_GFX_CP_LS |
1071                         AMD_CG_SUPPORT_GFX_RLC_LS |
1072                         AMD_CG_SUPPORT_IH_CG |
1073                         AMD_CG_SUPPORT_HDP_MGCG |
1074                         AMD_CG_SUPPORT_HDP_LS |
1075                         AMD_CG_SUPPORT_SDMA_MGCG |
1076                         AMD_CG_SUPPORT_SDMA_LS |
1077                         AMD_CG_SUPPORT_MC_MGCG |
1078                         AMD_CG_SUPPORT_MC_LS |
1079                         AMD_CG_SUPPORT_ATHUB_MGCG |
1080                         AMD_CG_SUPPORT_ATHUB_LS |
1081                         AMD_CG_SUPPORT_VCN_MGCG |
1082                         AMD_CG_SUPPORT_JPEG_MGCG;
1083                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1084                         AMD_PG_SUPPORT_VCN_DPG |
1085                         AMD_PG_SUPPORT_JPEG |
1086                         AMD_PG_SUPPORT_ATHUB;
1087                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
1088                  * as a consequence, the rev_id and external_rev_id are wrong.
1089                  * workaround it by hardcoding rev_id to 0 (default value).
1090                  */
1091                 if (amdgpu_sriov_vf(adev))
1092                         adev->rev_id = 0;
1093                 adev->external_rev_id = adev->rev_id + 0xa;
1094                 break;
1095         case CHIP_SIENNA_CICHLID:
1096                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1097                         AMD_CG_SUPPORT_GFX_CGCG |
1098                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1099                         AMD_CG_SUPPORT_MC_MGCG |
1100                         AMD_CG_SUPPORT_VCN_MGCG |
1101                         AMD_CG_SUPPORT_JPEG_MGCG |
1102                         AMD_CG_SUPPORT_HDP_MGCG |
1103                         AMD_CG_SUPPORT_HDP_LS |
1104                         AMD_CG_SUPPORT_IH_CG |
1105                         AMD_CG_SUPPORT_MC_LS;
1106                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1107                         AMD_PG_SUPPORT_VCN_DPG |
1108                         AMD_PG_SUPPORT_JPEG |
1109                         AMD_PG_SUPPORT_ATHUB |
1110                         AMD_PG_SUPPORT_MMHUB;
1111                 if (amdgpu_sriov_vf(adev)) {
1112                         /* hypervisor control CG and PG enablement */
1113                         adev->cg_flags = 0;
1114                         adev->pg_flags = 0;
1115                 }
1116                 adev->external_rev_id = adev->rev_id + 0x28;
1117                 break;
1118         case CHIP_NAVY_FLOUNDER:
1119                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1120                         AMD_CG_SUPPORT_GFX_CGCG |
1121                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1122                         AMD_CG_SUPPORT_VCN_MGCG |
1123                         AMD_CG_SUPPORT_JPEG_MGCG |
1124                         AMD_CG_SUPPORT_MC_MGCG |
1125                         AMD_CG_SUPPORT_MC_LS |
1126                         AMD_CG_SUPPORT_HDP_MGCG |
1127                         AMD_CG_SUPPORT_HDP_LS |
1128                         AMD_CG_SUPPORT_IH_CG;
1129                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1130                         AMD_PG_SUPPORT_VCN_DPG |
1131                         AMD_PG_SUPPORT_JPEG |
1132                         AMD_PG_SUPPORT_ATHUB |
1133                         AMD_PG_SUPPORT_MMHUB;
1134                 adev->external_rev_id = adev->rev_id + 0x32;
1135                 break;
1136
1137         case CHIP_VANGOGH:
1138                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
1139                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1140                         AMD_CG_SUPPORT_GFX_MGLS |
1141                         AMD_CG_SUPPORT_GFX_CP_LS |
1142                         AMD_CG_SUPPORT_GFX_RLC_LS |
1143                         AMD_CG_SUPPORT_GFX_CGCG |
1144                         AMD_CG_SUPPORT_GFX_CGLS |
1145                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1146                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1147                         AMD_CG_SUPPORT_MC_MGCG |
1148                         AMD_CG_SUPPORT_MC_LS |
1149                         AMD_CG_SUPPORT_GFX_FGCG |
1150                         AMD_CG_SUPPORT_VCN_MGCG |
1151                         AMD_CG_SUPPORT_JPEG_MGCG;
1152                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1153                         AMD_PG_SUPPORT_VCN |
1154                         AMD_PG_SUPPORT_VCN_DPG |
1155                         AMD_PG_SUPPORT_JPEG;
1156                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
1157                         adev->external_rev_id = adev->rev_id + 0x01;
1158                 break;
1159         case CHIP_DIMGREY_CAVEFISH:
1160                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1161                         AMD_CG_SUPPORT_GFX_CGCG |
1162                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1163                         AMD_CG_SUPPORT_VCN_MGCG |
1164                         AMD_CG_SUPPORT_JPEG_MGCG |
1165                         AMD_CG_SUPPORT_MC_MGCG |
1166                         AMD_CG_SUPPORT_MC_LS |
1167                         AMD_CG_SUPPORT_HDP_MGCG |
1168                         AMD_CG_SUPPORT_HDP_LS |
1169                         AMD_CG_SUPPORT_IH_CG;
1170                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1171                         AMD_PG_SUPPORT_VCN_DPG |
1172                         AMD_PG_SUPPORT_JPEG |
1173                         AMD_PG_SUPPORT_ATHUB |
1174                         AMD_PG_SUPPORT_MMHUB;
1175                 adev->external_rev_id = adev->rev_id + 0x3c;
1176                 break;
1177         default:
1178                 /* FIXME: not supported yet */
1179                 return -EINVAL;
1180         }
1181
1182         if (amdgpu_sriov_vf(adev)) {
1183                 amdgpu_virt_init_setting(adev);
1184                 xgpu_nv_mailbox_set_irq_funcs(adev);
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int nv_common_late_init(void *handle)
1191 {
1192         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1193
1194         if (amdgpu_sriov_vf(adev))
1195                 xgpu_nv_mailbox_get_irq(adev);
1196
1197         return 0;
1198 }
1199
1200 static int nv_common_sw_init(void *handle)
1201 {
1202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1203
1204         if (amdgpu_sriov_vf(adev))
1205                 xgpu_nv_mailbox_add_irq_id(adev);
1206
1207         return 0;
1208 }
1209
1210 static int nv_common_sw_fini(void *handle)
1211 {
1212         return 0;
1213 }
1214
1215 static int nv_common_hw_init(void *handle)
1216 {
1217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1218
1219         /* enable pcie gen2/3 link */
1220         nv_pcie_gen3_enable(adev);
1221         /* enable aspm */
1222         nv_program_aspm(adev);
1223         /* setup nbio registers */
1224         adev->nbio.funcs->init_registers(adev);
1225         /* remap HDP registers to a hole in mmio space,
1226          * for the purpose of expose those registers
1227          * to process space
1228          */
1229         if (adev->nbio.funcs->remap_hdp_registers)
1230                 adev->nbio.funcs->remap_hdp_registers(adev);
1231         /* enable the doorbell aperture */
1232         nv_enable_doorbell_aperture(adev, true);
1233
1234         return 0;
1235 }
1236
1237 static int nv_common_hw_fini(void *handle)
1238 {
1239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241         /* disable the doorbell aperture */
1242         nv_enable_doorbell_aperture(adev, false);
1243
1244         return 0;
1245 }
1246
1247 static int nv_common_suspend(void *handle)
1248 {
1249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250
1251         return nv_common_hw_fini(adev);
1252 }
1253
1254 static int nv_common_resume(void *handle)
1255 {
1256         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1257
1258         return nv_common_hw_init(adev);
1259 }
1260
1261 static bool nv_common_is_idle(void *handle)
1262 {
1263         return true;
1264 }
1265
1266 static int nv_common_wait_for_idle(void *handle)
1267 {
1268         return 0;
1269 }
1270
1271 static int nv_common_soft_reset(void *handle)
1272 {
1273         return 0;
1274 }
1275
1276 static int nv_common_set_clockgating_state(void *handle,
1277                                            enum amd_clockgating_state state)
1278 {
1279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281         if (amdgpu_sriov_vf(adev))
1282                 return 0;
1283
1284         switch (adev->asic_type) {
1285         case CHIP_NAVI10:
1286         case CHIP_NAVI14:
1287         case CHIP_NAVI12:
1288         case CHIP_SIENNA_CICHLID:
1289         case CHIP_NAVY_FLOUNDER:
1290         case CHIP_DIMGREY_CAVEFISH:
1291                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1292                                 state == AMD_CG_STATE_GATE);
1293                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1294                                 state == AMD_CG_STATE_GATE);
1295                 adev->hdp.funcs->update_clock_gating(adev,
1296                                 state == AMD_CG_STATE_GATE);
1297                 adev->smuio.funcs->update_rom_clock_gating(adev,
1298                                 state == AMD_CG_STATE_GATE);
1299                 break;
1300         default:
1301                 break;
1302         }
1303         return 0;
1304 }
1305
1306 static int nv_common_set_powergating_state(void *handle,
1307                                            enum amd_powergating_state state)
1308 {
1309         /* TODO */
1310         return 0;
1311 }
1312
1313 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1314 {
1315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317         if (amdgpu_sriov_vf(adev))
1318                 *flags = 0;
1319
1320         adev->nbio.funcs->get_clockgating_state(adev, flags);
1321
1322         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1323
1324         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1325
1326         return;
1327 }
1328
1329 static const struct amd_ip_funcs nv_common_ip_funcs = {
1330         .name = "nv_common",
1331         .early_init = nv_common_early_init,
1332         .late_init = nv_common_late_init,
1333         .sw_init = nv_common_sw_init,
1334         .sw_fini = nv_common_sw_fini,
1335         .hw_init = nv_common_hw_init,
1336         .hw_fini = nv_common_hw_fini,
1337         .suspend = nv_common_suspend,
1338         .resume = nv_common_resume,
1339         .is_idle = nv_common_is_idle,
1340         .wait_for_idle = nv_common_wait_for_idle,
1341         .soft_reset = nv_common_soft_reset,
1342         .set_clockgating_state = nv_common_set_clockgating_state,
1343         .set_powergating_state = nv_common_set_powergating_state,
1344         .get_clockgating_state = nv_common_get_clockgating_state,
1345 };