drivers/gpu/drm/i915/display/intel_display.h

   1 /*
   2  * Copyright © 2006-2019 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DISPLAY_H_
  26 #define _INTEL_DISPLAY_H_
  27
  28 #include <drm/drm_util.h>
  29
  30 enum link_m_n_set;
  31 enum drm_scaling_filter;
  32 struct dpll;
  33 struct drm_connector;
  34 struct drm_device;
  35 struct drm_display_mode;
  36 struct drm_encoder;
  37 struct drm_file;
  38 struct drm_format_info;
  39 struct drm_framebuffer;
  40 struct drm_i915_gem_object;
  41 struct drm_i915_private;
  42 struct drm_mode_fb_cmd2;
  43 struct drm_modeset_acquire_ctx;
  44 struct drm_plane;
  45 struct drm_plane_state;
  46 struct i915_address_space;
  47 struct i915_ggtt_view;
  48 struct intel_atomic_state;
  49 struct intel_crtc;
  50 struct intel_crtc_state;
  51 struct intel_digital_port;
  52 struct intel_dp;
  53 struct intel_encoder;
  54 struct intel_initial_plane_config;
  55 struct intel_load_detect_pipe;
  56 struct intel_plane;
  57 struct intel_plane_state;
  58 struct intel_remapped_info;
  59 struct intel_rotation_info;
  60
  61 enum i915_gpio {
  62         GPIOA,
  63         GPIOB,
  64         GPIOC,
  65         GPIOD,
  66         GPIOE,
  67         GPIOF,
  68         GPIOG,
  69         GPIOH,
  70         __GPIOI_UNUSED,
  71         GPIOJ,
  72         GPIOK,
  73         GPIOL,
  74         GPIOM,
  75         GPION,
  76         GPIOO,
  77 };
  78
  79 /*
  80  * Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
  81  * rest have consecutive values and match the enum values of transcoders
  82  * with a 1:1 transcoder -> pipe mapping.
  83  */
  84 enum pipe {
  85         INVALID_PIPE = -1,
  86
  87         PIPE_A = 0,
  88         PIPE_B,
  89         PIPE_C,
  90         PIPE_D,
  91         _PIPE_EDP,
  92
  93         I915_MAX_PIPES = _PIPE_EDP
  94 };
  95
  96 #define pipe_name(p) ((p) + 'A')
  97
  98 enum transcoder {
  99         INVALID_TRANSCODER = -1,
 100         /*
 101          * The following transcoders have a 1:1 transcoder -> pipe mapping,
 102          * keep their values fixed: the code assumes that TRANSCODER_A=0, the
 103          * rest have consecutive values and match the enum values of the pipes
 104          * they map to.
 105          */
 106         TRANSCODER_A = PIPE_A,
 107         TRANSCODER_B = PIPE_B,
 108         TRANSCODER_C = PIPE_C,
 109         TRANSCODER_D = PIPE_D,
 110
 111         /*
 112          * The following transcoders can map to any pipe, their enum value
 113          * doesn't need to stay fixed.
 114          */
 115         TRANSCODER_EDP,
 116         TRANSCODER_DSI_0,
 117         TRANSCODER_DSI_1,
 118         TRANSCODER_DSI_A = TRANSCODER_DSI_0,    /* legacy DSI */
 119         TRANSCODER_DSI_C = TRANSCODER_DSI_1,    /* legacy DSI */
 120
 121         I915_MAX_TRANSCODERS
 122 };
 123
 124 static inline const char *transcoder_name(enum transcoder transcoder)
 125 {
 126         switch (transcoder) {
 127         case TRANSCODER_A:
 128                 return "A";
 129         case TRANSCODER_B:
 130                 return "B";
 131         case TRANSCODER_C:
 132                 return "C";
 133         case TRANSCODER_D:
 134                 return "D";
 135         case TRANSCODER_EDP:
 136                 return "EDP";
 137         case TRANSCODER_DSI_A:
 138                 return "DSI A";
 139         case TRANSCODER_DSI_C:
 140                 return "DSI C";
 141         default:
 142                 return "<invalid>";
 143         }
 144 }
 145
 146 static inline bool transcoder_is_dsi(enum transcoder transcoder)
 147 {
 148         return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
 149 }
 150
 151 /*
 152  * Global legacy plane identifier. Valid only for primary/sprite
 153  * planes on pre-g4x, and only for primary planes on g4x-bdw.
 154  */
 155 enum i9xx_plane_id {
 156         PLANE_A,
 157         PLANE_B,
 158         PLANE_C,
 159 };
 160
 161 #define plane_name(p) ((p) + 'A')
 162 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
 163
 164 /*
 165  * Per-pipe plane identifier.
 166  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 167  * number of planes per CRTC.  Not all platforms really have this many planes,
 168  * which means some arrays of size I915_MAX_PLANES may have unused entries
 169  * between the topmost sprite plane and the cursor plane.
 170  *
 171  * This is expected to be passed to various register macros
 172  * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 173  */
 174 enum plane_id {
 175         PLANE_PRIMARY,
 176         PLANE_SPRITE0,
 177         PLANE_SPRITE1,
 178         PLANE_SPRITE2,
 179         PLANE_SPRITE3,
 180         PLANE_SPRITE4,
 181         PLANE_SPRITE5,
 182         PLANE_CURSOR,
 183
 184         I915_MAX_PLANES,
 185 };
 186
 187 #define for_each_plane_id_on_crtc(__crtc, __p) \
 188         for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
 189                 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
 190
 191 #define for_each_dbuf_slice(__dev_priv, __slice) \
 192         for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
 193                 for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
 194
 195 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
 196         for_each_dbuf_slice((__dev_priv), (__slice)) \
 197                 for_each_if((__mask) & BIT(__slice))
 198
 199 enum port {
 200         PORT_NONE = -1,
 201
 202         PORT_A = 0,
 203         PORT_B,
 204         PORT_C,
 205         PORT_D,
 206         PORT_E,
 207         PORT_F,
 208         PORT_G,
 209         PORT_H,
 210         PORT_I,
 211
 212         /* tgl+ */
 213         PORT_TC1 = PORT_D,
 214         PORT_TC2,
 215         PORT_TC3,
 216         PORT_TC4,
 217         PORT_TC5,
 218         PORT_TC6,
 219
 220         /* XE_LPD repositions D/E offsets and bitfields */
 221         PORT_D_XELPD = PORT_TC5,
 222         PORT_E_XELPD,
 223
 224         I915_MAX_PORTS
 225 };
 226
 227 #define port_name(p) ((p) + 'A')
 228
 229 /*
 230  * Ports identifier referenced from other drivers.
 231  * Expected to remain stable over time
 232  */
 233 static inline const char *port_identifier(enum port port)
 234 {
 235         switch (port) {
 236         case PORT_A:
 237                 return "Port A";
 238         case PORT_B:
 239                 return "Port B";
 240         case PORT_C:
 241                 return "Port C";
 242         case PORT_D:
 243                 return "Port D";
 244         case PORT_E:
 245                 return "Port E";
 246         case PORT_F:
 247                 return "Port F";
 248         case PORT_G:
 249                 return "Port G";
 250         case PORT_H:
 251                 return "Port H";
 252         case PORT_I:
 253                 return "Port I";
 254         default:
 255                 return "<invalid>";
 256         }
 257 }
 258
 259 enum tc_port {
 260         TC_PORT_NONE = -1,
 261
 262         TC_PORT_1 = 0,
 263         TC_PORT_2,
 264         TC_PORT_3,
 265         TC_PORT_4,
 266         TC_PORT_5,
 267         TC_PORT_6,
 268
 269         I915_MAX_TC_PORTS
 270 };
 271
 272 enum tc_port_mode {
 273         TC_PORT_TBT_ALT,
 274         TC_PORT_DP_ALT,
 275         TC_PORT_LEGACY,
 276 };
 277
 278 enum dpio_channel {
 279         DPIO_CH0,
 280         DPIO_CH1
 281 };
 282
 283 enum dpio_phy {
 284         DPIO_PHY0,
 285         DPIO_PHY1,
 286         DPIO_PHY2,
 287 };
 288
 289 enum aux_ch {
 290         AUX_CH_A,
 291         AUX_CH_B,
 292         AUX_CH_C,
 293         AUX_CH_D,
 294         AUX_CH_E, /* ICL+ */
 295         AUX_CH_F,
 296         AUX_CH_G,
 297         AUX_CH_H,
 298         AUX_CH_I,
 299
 300         /* tgl+ */
 301         AUX_CH_USBC1 = AUX_CH_D,
 302         AUX_CH_USBC2,
 303         AUX_CH_USBC3,
 304         AUX_CH_USBC4,
 305         AUX_CH_USBC5,
 306         AUX_CH_USBC6,
 307
 308         /* XE_LPD repositions D/E offsets and bitfields */
 309         AUX_CH_D_XELPD = AUX_CH_USBC5,
 310         AUX_CH_E_XELPD,
 311 };
 312
 313 #define aux_ch_name(a) ((a) + 'A')
 314
 315 /* Used by dp and fdi links */
 316 struct intel_link_m_n {
 317         u32 tu;
 318         u32 gmch_m;
 319         u32 gmch_n;
 320         u32 link_m;
 321         u32 link_n;
 322 };
 323
 324 enum phy {
 325         PHY_NONE = -1,
 326
 327         PHY_A = 0,
 328         PHY_B,
 329         PHY_C,
 330         PHY_D,
 331         PHY_E,
 332         PHY_F,
 333         PHY_G,
 334         PHY_H,
 335         PHY_I,
 336
 337         I915_MAX_PHYS
 338 };
 339
 340 #define phy_name(a) ((a) + 'A')
 341
 342 enum phy_fia {
 343         FIA1,
 344         FIA2,
 345         FIA3,
 346 };
 347
 348 #define for_each_pipe(__dev_priv, __p) \
 349         for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
 350                 for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
 351
 352 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
 353         for_each_pipe(__dev_priv, __p) \
 354                 for_each_if((__mask) & BIT(__p))
 355
 356 #define for_each_cpu_transcoder(__dev_priv, __t) \
 357         for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
 358                 for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
 359
 360 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
 361         for_each_cpu_transcoder(__dev_priv, __t) \
 362                 for_each_if ((__mask) & BIT(__t))
 363
 364 #define for_each_sprite(__dev_priv, __p, __s)                           \
 365         for ((__s) = 0;                                                 \
 366              (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)];      \
 367              (__s)++)
 368
 369 #define for_each_port(__port) \
 370         for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
 371
 372 #define for_each_port_masked(__port, __ports_mask)                      \
 373         for_each_port(__port)                                           \
 374                 for_each_if((__ports_mask) & BIT(__port))
 375
 376 #define for_each_phy_masked(__phy, __phys_mask) \
 377         for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)       \
 378                 for_each_if((__phys_mask) & BIT(__phy))
 379
 380 #define for_each_crtc(dev, crtc) \
 381         list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
 382
 383 #define for_each_intel_plane(dev, intel_plane) \
 384         list_for_each_entry(intel_plane,                        \
 385                             &(dev)->mode_config.plane_list,     \
 386                             base.head)
 387
 388 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask)         \
 389         list_for_each_entry(intel_plane,                                \
 390                             &(dev)->mode_config.plane_list,             \
 391                             base.head)                                  \
 392                 for_each_if((plane_mask) &                              \
 393                             drm_plane_mask(&intel_plane->base))
 394
 395 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
 396         list_for_each_entry(intel_plane,                                \
 397                             &(dev)->mode_config.plane_list,             \
 398                             base.head)                                  \
 399                 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
 400
 401 #define for_each_intel_crtc(dev, intel_crtc)                            \
 402         list_for_each_entry(intel_crtc,                                 \
 403                             &(dev)->mode_config.crtc_list,              \
 404                             base.head)
 405
 406 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)            \
 407         list_for_each_entry(intel_crtc,                                 \
 408                             &(dev)->mode_config.crtc_list,              \
 409                             base.head)                                  \
 410                 for_each_if((crtc_mask) & drm_crtc_mask(&intel_crtc->base))
 411
 412 #define for_each_intel_encoder(dev, intel_encoder)              \
 413         list_for_each_entry(intel_encoder,                      \
 414                             &(dev)->mode_config.encoder_list,   \
 415                             base.head)
 416
 417 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask)   \
 418         list_for_each_entry(intel_encoder,                              \
 419                             &(dev)->mode_config.encoder_list,           \
 420                             base.head)                                  \
 421                 for_each_if((encoder_mask) &                            \
 422                             drm_encoder_mask(&intel_encoder->base))
 423
 424 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
 425         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 426                 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
 427                             intel_encoder_can_psr(intel_encoder))
 428
 429 #define for_each_intel_dp(dev, intel_encoder)                   \
 430         for_each_intel_encoder(dev, intel_encoder)              \
 431                 for_each_if(intel_encoder_is_dp(intel_encoder))
 432
 433 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
 434         for_each_intel_encoder((dev), (intel_encoder)) \
 435                 for_each_if(intel_encoder_can_psr(intel_encoder))
 436
 437 #define for_each_intel_connector_iter(intel_connector, iter) \
 438         while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
 439
 440 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 441         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 442                 for_each_if((intel_encoder)->base.crtc == (__crtc))
 443
 444 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 445         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 446                 for_each_if((intel_connector)->base.encoder == (__encoder))
 447
 448 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
 449         for ((__i) = 0; \
 450              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 451                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 452                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
 453              (__i)++) \
 454                 for_each_if(plane)
 455
 456 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
 457         for ((__i) = 0; \
 458              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 459                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 460                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 461              (__i)++) \
 462                 for_each_if(plane)
 463
 464 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
 465         for ((__i) = 0; \
 466              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 467                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 468                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 469              (__i)++) \
 470                 for_each_if(crtc)
 471
 472 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
 473         for ((__i) = 0; \
 474              (__i) < (__state)->base.dev->mode_config.num_total_plane && \
 475                      ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
 476                       (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
 477                       (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
 478              (__i)++) \
 479                 for_each_if(plane)
 480
 481 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 482         for ((__i) = 0; \
 483              (__i) < (__state)->base.dev->mode_config.num_crtc && \
 484                      ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 485                       (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 486                       (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 487              (__i)++) \
 488                 for_each_if(crtc)
 489
 490 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
 491         for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
 492              (__i) >= 0  && \
 493              ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
 494               (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
 495               (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
 496              (__i)--) \
 497                 for_each_if(crtc)
 498
 499 #define intel_atomic_crtc_state_for_each_plane_state( \
 500                   plane, plane_state, \
 501                   crtc_state) \
 502         for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
 503                                 ((crtc_state)->uapi.plane_mask)) \
 504                 for_each_if ((plane_state = \
 505                               to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
 506
 507 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
 508         for ((__i) = 0; \
 509              (__i) < (__state)->base.num_connector; \
 510              (__i)++) \
 511                 for_each_if ((__state)->base.connectors[__i].ptr && \
 512                              ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
 513                              (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
 514
 515 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
 516                                      struct intel_crtc *crtc);
 517 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
 518                            u8 active_pipes);
 519 void intel_link_compute_m_n(u16 bpp, int nlanes,
 520                             int pixel_clock, int link_clock,
 521                             struct intel_link_m_n *m_n,
 522                             bool constant_n, bool fec_enable);
 523 void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 524 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 525                               u32 pixel_format, u64 modifier);
 526 enum drm_mode_status
 527 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
 528                                 const struct drm_display_mode *mode,
 529                                 bool bigjoiner);
 530 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 531 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
 532
 533 void intel_plane_destroy(struct drm_plane *plane);
 534 void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state);
 535 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
 536 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 537 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 538 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
 539 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 540 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 541                       const char *name, u32 reg, int ref_freq);
 542 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 543                            const char *name, u32 reg);
 544 void lpt_pch_enable(const struct intel_crtc_state *crtc_state);
 545 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
 546 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
 547 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
 548 unsigned int intel_fb_xy_to_linear(int x, int y,
 549                                    const struct intel_plane_state *state,
 550                                    int plane);
 551 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
 552                                    int color_plane, unsigned int height);
 553 void intel_add_fb_offsets(int *x, int *y,
 554                           const struct intel_plane_state *state, int plane);
 555 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
 556 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
 557 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
 558 int intel_display_suspend(struct drm_device *dev);
 559 void intel_encoder_destroy(struct drm_encoder *encoder);
 560 struct drm_display_mode *
 561 intel_encoder_current_mode(struct intel_encoder *encoder);
 562 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 563 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 564 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
 565 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 566                               enum port port);
 567 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
 568                                       struct drm_file *file_priv);
 569
 570 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
 571 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 572                          struct intel_digital_port *dig_port,
 573                          unsigned int expected_mask);
 574 int intel_get_load_detect_pipe(struct drm_connector *connector,
 575                                struct intel_load_detect_pipe *old,
 576                                struct drm_modeset_acquire_ctx *ctx);
 577 void intel_release_load_detect_pipe(struct drm_connector *connector,
 578                                     struct intel_load_detect_pipe *old,
 579                                     struct drm_modeset_acquire_ctx *ctx);
 580 struct i915_vma *
 581 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, bool phys_cursor,
 582                            const struct i915_ggtt_view *view,
 583                            bool uses_fence,
 584                            unsigned long *out_flags);
 585 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
 586 struct drm_framebuffer *
 587 intel_framebuffer_create(struct drm_i915_gem_object *obj,
 588                          struct drm_mode_fb_cmd2 *mode_cmd);
 589 int intel_prepare_plane_fb(struct drm_plane *plane,
 590                            struct drm_plane_state *new_state);
 591 void intel_cleanup_plane_fb(struct drm_plane *plane,
 592                             struct drm_plane_state *old_state);
 593
 594 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 595                                     enum pipe pipe);
 596
 597 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
 598 bool intel_fuzzy_clock_check(int clock1, int clock2);
 599
 600 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
 601 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
 602 void intel_dp_get_m_n(struct intel_crtc *crtc,
 603                       struct intel_crtc_state *pipe_config);
 604 void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,
 605                       enum link_m_n_set m_n);
 606 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
 607
 608 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
 609 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
 610 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
 611 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
 612 enum intel_display_power_domain
 613 intel_aux_power_domain(struct intel_digital_port *dig_port);
 614 enum intel_display_power_domain
 615 intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
 616 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
 617                                   struct intel_crtc_state *crtc_state);
 618 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
 619
 620 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
 621 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
 622
 623 bool
 624 intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
 625                                     u64 modifier);
 626
 627 int intel_plane_pin_fb(struct intel_plane_state *plane_state);
 628 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
 629 struct intel_encoder *
 630 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 631                            const struct intel_crtc_state *crtc_state);
 632
 633 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 634                                   int color_plane);
 635 unsigned int intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane);
 636
 637 void intel_display_driver_register(struct drm_i915_private *i915);
 638 void intel_display_driver_unregister(struct drm_i915_private *i915);
 639
 640 /* modesetting */
 641 void intel_modeset_init_hw(struct drm_i915_private *i915);
 642 int intel_modeset_init_noirq(struct drm_i915_private *i915);
 643 int intel_modeset_init_nogem(struct drm_i915_private *i915);
 644 int intel_modeset_init(struct drm_i915_private *i915);
 645 void intel_modeset_driver_remove(struct drm_i915_private *i915);
 646 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
 647 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
 648 void intel_display_resume(struct drm_device *dev);
 649 void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
 650 int intel_modeset_all_pipes(struct intel_atomic_state *state);
 651
 652 /* modesetting asserts */
 653 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 654                            enum pipe pipe);
 655 void assert_pll(struct drm_i915_private *dev_priv,
 656                 enum pipe pipe, bool state);
 657 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 658 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 659 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
 660 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 661 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 662 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 663                        enum pipe pipe, bool state);
 664 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
 665 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
 666 void assert_pipe(struct drm_i915_private *dev_priv,
 667                  enum transcoder cpu_transcoder, bool state);
 668 #define assert_pipe_enabled(d, t) assert_pipe(d, t, true)
 669 #define assert_pipe_disabled(d, t) assert_pipe(d, t, false)
 670
 671 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 672  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 673  * which may not necessarily be a user visible problem.  This will either
 674  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 675  * enable distros and users to tailor their preferred amount of i915 abrt
 676  * spam.
 677  */
 678 #define I915_STATE_WARN(condition, format...) ({                        \
 679         int __ret_warn_on = !!(condition);                              \
 680         if (unlikely(__ret_warn_on))                                    \
 681                 if (!WARN(i915_modparams.verbose_state_checks, format)) \
 682                         DRM_ERROR(format);                              \
 683         unlikely(__ret_warn_on);                                        \
 684 })
 685
 686 #define I915_STATE_WARN_ON(x)                                           \
 687         I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
 688
 689 #endif