drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_VCN_H__
  25 #define __AMDGPU_VCN_H__
  26
  27 #define AMDGPU_VCN_STACK_SIZE           (128*1024)
  28 #define AMDGPU_VCN_CONTEXT_SIZE         (512*1024)
  29
  30 #define AMDGPU_VCN_FIRMWARE_OFFSET      256
  31 #define AMDGPU_VCN_MAX_ENC_RINGS        3
  32
  33 #define AMDGPU_MAX_VCN_INSTANCES        2
  34 #define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
  35
  36 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
  37 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
  38
  39 #define VCN_DEC_KMD_CMD                 0x80000000
  40 #define VCN_DEC_CMD_FENCE               0x00000000
  41 #define VCN_DEC_CMD_TRAP                0x00000001
  42 #define VCN_DEC_CMD_WRITE_REG           0x00000004
  43 #define VCN_DEC_CMD_REG_READ_COND_WAIT  0x00000006
  44 #define VCN_DEC_CMD_PACKET_START        0x0000000a
  45 #define VCN_DEC_CMD_PACKET_END          0x0000000b
  46
  47 #define VCN_DEC_SW_CMD_NO_OP            0x00000000
  48 #define VCN_DEC_SW_CMD_END              0x00000001
  49 #define VCN_DEC_SW_CMD_IB               0x00000002
  50 #define VCN_DEC_SW_CMD_FENCE            0x00000003
  51 #define VCN_DEC_SW_CMD_TRAP             0x00000004
  52 #define VCN_DEC_SW_CMD_IB_AUTO          0x00000005
  53 #define VCN_DEC_SW_CMD_SEMAPHORE        0x00000006
  54 #define VCN_DEC_SW_CMD_PREEMPT_FENCE    0x00000009
  55 #define VCN_DEC_SW_CMD_REG_WRITE        0x0000000b
  56 #define VCN_DEC_SW_CMD_REG_WAIT         0x0000000c
  57
  58 #define VCN_ENC_CMD_NO_OP               0x00000000
  59 #define VCN_ENC_CMD_END                 0x00000001
  60 #define VCN_ENC_CMD_IB                  0x00000002
  61 #define VCN_ENC_CMD_FENCE               0x00000003
  62 #define VCN_ENC_CMD_TRAP                0x00000004
  63 #define VCN_ENC_CMD_REG_WRITE           0x0000000b
  64 #define VCN_ENC_CMD_REG_WAIT            0x0000000c
  65
  66 #define VCN_VID_SOC_ADDRESS_2_0         0x1fa00
  67 #define VCN1_VID_SOC_ADDRESS_3_0        0x48200
  68 #define VCN_AON_SOC_ADDRESS_2_0         0x1f800
  69 #define VCN1_AON_SOC_ADDRESS_3_0        0x48000
  70 #define VCN_VID_IP_ADDRESS_2_0          0x0
  71 #define VCN_AON_IP_ADDRESS_2_0          0x30000
  72
  73 #define mmUVD_RBC_XX_IB_REG_CHECK                                       0x026b
  74 #define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX                              1
  75 #define mmUVD_REG_XX_MASK                                               0x026c
  76 #define mmUVD_REG_XX_MASK_BASE_IDX                                      1
  77
  78 /* 1 second timeout */
  79 #define VCN_IDLE_TIMEOUT        msecs_to_jiffies(1000)
  80
  81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel)                    \
  82         ({      WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask);                   \
  83                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL,                           \
  84                         UVD_DPG_LMA_CTL__MASK_EN_MASK |                                 \
  85                         ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg)  \
  86                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
  87                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
  88                 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA);                         \
  89         })
  90
  91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel)             \
  92         do {                                                                            \
  93                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value);                  \
  94                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask);                   \
  95                 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL,                           \
  96                         UVD_DPG_LMA_CTL__READ_WRITE_MASK |                              \
  97                         ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg)  \
  98                         << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |                   \
  99                         (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));                \
 100         } while (0)
 101
 102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg)                                                \
 103         ({                                                                                      \
 104                 uint32_t internal_reg_offset, addr;                                             \
 105                 bool video_range, video1_range, aon_range, aon1_range;                          \
 106                                                                                                 \
 107                 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);           \
 108                 addr <<= 2;                                                                     \
 109                 video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) &&              \
 110                                 ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));    \
 111                 video1_range = ((((0xFFFFF & addr) >= (VCN1_VID_SOC_ADDRESS_3_0)) &&            \
 112                                 ((0xFFFFF & addr) < ((VCN1_VID_SOC_ADDRESS_3_0 + 0x2600)))));   \
 113                 aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) &&              \
 114                                 ((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));     \
 115                 aon1_range   = ((((0xFFFFF & addr) >= (VCN1_AON_SOC_ADDRESS_3_0)) &&            \
 116                                 ((0xFFFFF & addr) < ((VCN1_AON_SOC_ADDRESS_3_0 + 0x600)))));    \
 117                 if (video_range)                                                                \
 118                         internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) +   \
 119                                 (VCN_VID_IP_ADDRESS_2_0));                                      \
 120                 else if (aon_range)                                                             \
 121                         internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) +   \
 122                                 (VCN_AON_IP_ADDRESS_2_0));                                      \
 123                 else if (video1_range)                                                          \
 124                         internal_reg_offset = ((0xFFFFF & addr) - (VCN1_VID_SOC_ADDRESS_3_0) +  \
 125                                 (VCN_VID_IP_ADDRESS_2_0));                                      \
 126                 else if (aon1_range)                                                            \
 127                         internal_reg_offset = ((0xFFFFF & addr) - (VCN1_AON_SOC_ADDRESS_3_0) +  \
 128                                 (VCN_AON_IP_ADDRESS_2_0));                                      \
 129                 else                                                                            \
 130                         internal_reg_offset = (0xFFFFF & addr);                                 \
 131                                                                                                 \
 132                 internal_reg_offset >>= 2;                                                      \
 133         })
 134
 135 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en)                                        \
 136         ({                                                                                      \
 137                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,                                  \
 138                         (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                            \
 139                         mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                            \
 140                         offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));                    \
 141                 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);                                \
 142         })
 143
 144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect)                       \
 145         do {                                                                                    \
 146                 if (!indirect) {                                                                \
 147                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value);                 \
 148                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL,                          \
 149                                 (0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |                    \
 150                                  mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |                   \
 151                                  offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));           \
 152                 } else {                                                                        \
 153                         *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = offset;                \
 154                         *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = value;                 \
 155                 }                                                                               \
 156         } while (0)
 157
 158 #define AMDGPU_VCN_FW_SHARED_FLAG_0_RB  (1 << 6)
 159 #define AMDGPU_VCN_MULTI_QUEUE_FLAG     (1 << 8)
 160 #define AMDGPU_VCN_SW_RING_FLAG         (1 << 9)
 161 #define AMDGPU_VCN_FW_LOGGING_FLAG      (1 << 10)
 162 #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
 163
 164 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER        0x00000001
 165 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER          0x00000001
 166
 167 enum fw_queue_mode {
 168         FW_QUEUE_RING_RESET = 1,
 169         FW_QUEUE_DPG_HOLD_OFF = 2,
 170 };
 171
 172 enum engine_status_constants {
 173         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
 174         UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
 175         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 = 0x2A2A8AA0,
 176         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
 177         UVD_STATUS__UVD_BUSY = 0x00000004,
 178         GB_ADDR_CONFIG_DEFAULT = 0x26010011,
 179         UVD_STATUS__IDLE = 0x2,
 180         UVD_STATUS__BUSY = 0x5,
 181         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
 182         UVD_STATUS__RBC_BUSY = 0x1,
 183         UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
 184 };
 185
 186 enum internal_dpg_state {
 187         VCN_DPG_STATE__UNPAUSE = 0,
 188         VCN_DPG_STATE__PAUSE,
 189 };
 190
 191 struct dpg_pause_state {
 192         enum internal_dpg_state fw_based;
 193         enum internal_dpg_state jpeg;
 194 };
 195
 196 struct amdgpu_vcn_reg{
 197         unsigned        data0;
 198         unsigned        data1;
 199         unsigned        cmd;
 200         unsigned        nop;
 201         unsigned        context_id;
 202         unsigned        ib_vmid;
 203         unsigned        ib_bar_low;
 204         unsigned        ib_bar_high;
 205         unsigned        ib_size;
 206         unsigned        gp_scratch8;
 207         unsigned        scratch9;
 208 };
 209
 210 struct amdgpu_vcn_fw_shared {
 211         void        *cpu_addr;
 212         uint64_t    gpu_addr;
 213         uint32_t    mem_size;
 214         uint32_t    log_offset;
 215 };
 216
 217 struct amdgpu_vcn_inst {
 218         struct amdgpu_bo        *vcpu_bo;
 219         void                    *cpu_addr;
 220         uint64_t                gpu_addr;
 221         void                    *saved_bo;
 222         struct amdgpu_ring      ring_dec;
 223         struct amdgpu_ring      ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
 224         atomic_t                sched_score;
 225         struct amdgpu_irq_src   irq;
 226         struct amdgpu_vcn_reg   external;
 227         struct amdgpu_bo        *dpg_sram_bo;
 228         struct dpg_pause_state  pause_state;
 229         void                    *dpg_sram_cpu_addr;
 230         uint64_t                dpg_sram_gpu_addr;
 231         uint32_t                *dpg_sram_curr_addr;
 232         atomic_t                dpg_enc_submission_cnt;
 233         struct amdgpu_vcn_fw_shared fw_shared;
 234 };
 235
 236 struct amdgpu_vcn {
 237         unsigned                fw_version;
 238         struct delayed_work     idle_work;
 239         const struct firmware   *fw;    /* VCN firmware */
 240         unsigned                num_enc_rings;
 241         enum amd_powergating_state cur_state;
 242         bool                    indirect_sram;
 243
 244         uint8_t num_vcn_inst;
 245         struct amdgpu_vcn_inst   inst[AMDGPU_MAX_VCN_INSTANCES];
 246         uint8_t                  vcn_config[AMDGPU_MAX_VCN_INSTANCES];
 247         struct amdgpu_vcn_reg    internal;
 248         struct mutex             vcn_pg_lock;
 249         struct mutex            vcn1_jpeg1_workaround;
 250         atomic_t                 total_submission_cnt;
 251
 252         unsigned        harvest_config;
 253         int (*pause_dpg_mode)(struct amdgpu_device *adev,
 254                 int inst_idx, struct dpg_pause_state *new_state);
 255 };
 256
 257 struct amdgpu_fw_shared_rb_ptrs_struct {
 258         /* to WA DPG R/W ptr issues.*/
 259         uint32_t  rptr;
 260         uint32_t  wptr;
 261 };
 262
 263 struct amdgpu_fw_shared_multi_queue {
 264         uint8_t decode_queue_mode;
 265         uint8_t encode_generalpurpose_queue_mode;
 266         uint8_t encode_lowlatency_queue_mode;
 267         uint8_t encode_realtime_queue_mode;
 268         uint8_t padding[4];
 269 };
 270
 271 struct amdgpu_fw_shared_sw_ring {
 272         uint8_t is_enabled;
 273         uint8_t padding[3];
 274 };
 275
 276 struct amdgpu_fw_shared_fw_logging {
 277         uint8_t is_enabled;
 278         uint32_t addr_lo;
 279         uint32_t addr_hi;
 280         uint32_t size;
 281 };
 282
 283 struct amdgpu_fw_shared_smu_interface_info {
 284         uint8_t smu_interface_type;
 285         uint8_t padding[3];
 286 };
 287
 288 struct amdgpu_fw_shared {
 289         uint32_t present_flag_0;
 290         uint8_t pad[44];
 291         struct amdgpu_fw_shared_rb_ptrs_struct rb;
 292         uint8_t pad1[1];
 293         struct amdgpu_fw_shared_multi_queue multi_queue;
 294         struct amdgpu_fw_shared_sw_ring sw_ring;
 295         struct amdgpu_fw_shared_fw_logging fw_log;
 296         struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
 297 };
 298
 299 struct amdgpu_vcn_fwlog {
 300         uint32_t rptr;
 301         uint32_t wptr;
 302         uint32_t buffer_size;
 303         uint32_t header_size;
 304         uint8_t wrapped;
 305 };
 306
 307 struct amdgpu_vcn_decode_buffer {
 308         uint32_t valid_buf_flag;
 309         uint32_t msg_buffer_address_hi;
 310         uint32_t msg_buffer_address_lo;
 311         uint32_t pad[30];
 312 };
 313
 314 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
 315 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
 316 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0
 317
 318 enum vcn_ring_type {
 319         VCN_ENCODE_RING,
 320         VCN_DECODE_RING,
 321         VCN_UNIFIED_RING,
 322 };
 323
 324 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
 325 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
 326 int amdgpu_vcn_suspend(struct amdgpu_device *adev);
 327 int amdgpu_vcn_resume(struct amdgpu_device *adev);
 328 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
 329 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring);
 330
 331 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev,
 332                                 enum vcn_ring_type type, uint32_t vcn_instance);
 333
 334 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring);
 335 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 336 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring);
 337 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 338
 339 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 340 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 341
 342 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
 343
 344 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
 345
 346 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
 347 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
 348                                    uint8_t i, struct amdgpu_vcn_inst *vcn);
 349 #endif