drivers/gpu/drm/omapdrm/omap_crtc.c

   1 /*
   2  * drivers/gpu/drm/omapdrm/omap_crtc.c
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Rob Clark <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <drm/drm_atomic.h>
  21 #include <drm/drm_atomic_helper.h>
  22 #include <drm/drm_crtc.h>
  23 #include <drm/drm_crtc_helper.h>
  24 #include <drm/drm_mode.h>
  25 #include <drm/drm_plane_helper.h>
  26
  27 #include "omap_drv.h"
  28
  29 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
  30
  31 struct omap_crtc_state {
  32         /* Must be first. */
  33         struct drm_crtc_state base;
  34         /* Shadow values for legacy userspace support. */
  35         unsigned int rotation;
  36         unsigned int zpos;
  37 };
  38
  39 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  40
  41 struct omap_crtc {
  42         struct drm_crtc base;
  43
  44         const char *name;
  45         enum omap_channel channel;
  46
  47         struct videomode vm;
  48
  49         bool ignore_digit_sync_lost;
  50
  51         bool enabled;
  52         bool pending;
  53         wait_queue_head_t pending_wait;
  54         struct drm_pending_vblank_event *event;
  55 };
  56
  57 /* -----------------------------------------------------------------------------
  58  * Helper Functions
  59  */
  60
  61 struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
  62 {
  63         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  64         return &omap_crtc->vm;
  65 }
  66
  67 enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  68 {
  69         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  70         return omap_crtc->channel;
  71 }
  72
  73 static bool omap_crtc_is_pending(struct drm_crtc *crtc)
  74 {
  75         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  76         unsigned long flags;
  77         bool pending;
  78
  79         spin_lock_irqsave(&crtc->dev->event_lock, flags);
  80         pending = omap_crtc->pending;
  81         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  82
  83         return pending;
  84 }
  85
  86 int omap_crtc_wait_pending(struct drm_crtc *crtc)
  87 {
  88         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  89
  90         /*
  91          * Timeout is set to a "sufficiently" high value, which should cover
  92          * a single frame refresh even on slower displays.
  93          */
  94         return wait_event_timeout(omap_crtc->pending_wait,
  95                                   !omap_crtc_is_pending(crtc),
  96                                   msecs_to_jiffies(250));
  97 }
  98
  99 /* -----------------------------------------------------------------------------
 100  * DSS Manager Functions
 101  */
 102
 103 /*
 104  * Manager-ops, callbacks from output when they need to configure
 105  * the upstream part of the video pipe.
 106  *
 107  * Most of these we can ignore until we add support for command-mode
 108  * panels.. for video-mode the crtc-helpers already do an adequate
 109  * job of sequencing the setup of the video pipe in the proper order
 110  */
 111
 112 /* ovl-mgr-id -> crtc */
 113 static struct omap_crtc *omap_crtcs[8];
 114 static struct omap_dss_device *omap_crtc_output[8];
 115
 116 /* we can probably ignore these until we support command-mode panels: */
 117 static int omap_crtc_dss_connect(enum omap_channel channel,
 118                 struct omap_dss_device *dst)
 119 {
 120         const struct dispc_ops *dispc_ops = dispc_get_ops();
 121
 122         if (omap_crtc_output[channel])
 123                 return -EINVAL;
 124
 125         if ((dispc_ops->mgr_get_supported_outputs(channel) & dst->id) == 0)
 126                 return -EINVAL;
 127
 128         omap_crtc_output[channel] = dst;
 129         dst->dispc_channel_connected = true;
 130
 131         return 0;
 132 }
 133
 134 static void omap_crtc_dss_disconnect(enum omap_channel channel,
 135                 struct omap_dss_device *dst)
 136 {
 137         omap_crtc_output[channel] = NULL;
 138         dst->dispc_channel_connected = false;
 139 }
 140
 141 static void omap_crtc_dss_start_update(enum omap_channel channel)
 142 {
 143 }
 144
 145 /* Called only from the encoder enable/disable and suspend/resume handlers. */
 146 static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
 147 {
 148         struct drm_device *dev = crtc->dev;
 149         struct omap_drm_private *priv = dev->dev_private;
 150         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 151         enum omap_channel channel = omap_crtc->channel;
 152         struct omap_irq_wait *wait;
 153         u32 framedone_irq, vsync_irq;
 154         int ret;
 155
 156         if (WARN_ON(omap_crtc->enabled == enable))
 157                 return;
 158
 159         if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
 160                 priv->dispc_ops->mgr_enable(channel, enable);
 161                 omap_crtc->enabled = enable;
 162                 return;
 163         }
 164
 165         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 166                 /*
 167                  * Digit output produces some sync lost interrupts during the
 168                  * first frame when enabling, so we need to ignore those.
 169                  */
 170                 omap_crtc->ignore_digit_sync_lost = true;
 171         }
 172
 173         framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel);
 174         vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel);
 175
 176         if (enable) {
 177                 wait = omap_irq_wait_init(dev, vsync_irq, 1);
 178         } else {
 179                 /*
 180                  * When we disable the digit output, we need to wait for
 181                  * FRAMEDONE to know that DISPC has finished with the output.
 182                  *
 183                  * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
 184                  * that case we need to use vsync interrupt, and wait for both
 185                  * even and odd frames.
 186                  */
 187
 188                 if (framedone_irq)
 189                         wait = omap_irq_wait_init(dev, framedone_irq, 1);
 190                 else
 191                         wait = omap_irq_wait_init(dev, vsync_irq, 2);
 192         }
 193
 194         priv->dispc_ops->mgr_enable(channel, enable);
 195         omap_crtc->enabled = enable;
 196
 197         ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
 198         if (ret) {
 199                 dev_err(dev->dev, "%s: timeout waiting for %s\n",
 200                                 omap_crtc->name, enable ? "enable" : "disable");
 201         }
 202
 203         if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
 204                 omap_crtc->ignore_digit_sync_lost = false;
 205                 /* make sure the irq handler sees the value above */
 206                 mb();
 207         }
 208 }
 209
 210
 211 static int omap_crtc_dss_enable(enum omap_channel channel)
 212 {
 213         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 214         struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
 215
 216         priv->dispc_ops->mgr_set_timings(omap_crtc->channel, &omap_crtc->vm);
 217         omap_crtc_set_enabled(&omap_crtc->base, true);
 218
 219         return 0;
 220 }
 221
 222 static void omap_crtc_dss_disable(enum omap_channel channel)
 223 {
 224         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 225
 226         omap_crtc_set_enabled(&omap_crtc->base, false);
 227 }
 228
 229 static void omap_crtc_dss_set_timings(enum omap_channel channel,
 230                 const struct videomode *vm)
 231 {
 232         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 233         DBG("%s", omap_crtc->name);
 234         omap_crtc->vm = *vm;
 235 }
 236
 237 static void omap_crtc_dss_set_lcd_config(enum omap_channel channel,
 238                 const struct dss_lcd_mgr_config *config)
 239 {
 240         struct omap_crtc *omap_crtc = omap_crtcs[channel];
 241         struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
 242
 243         DBG("%s", omap_crtc->name);
 244         priv->dispc_ops->mgr_set_lcd_config(omap_crtc->channel, config);
 245 }
 246
 247 static int omap_crtc_dss_register_framedone(
 248                 enum omap_channel channel,
 249                 void (*handler)(void *), void *data)
 250 {
 251         return 0;
 252 }
 253
 254 static void omap_crtc_dss_unregister_framedone(
 255                 enum omap_channel channel,
 256                 void (*handler)(void *), void *data)
 257 {
 258 }
 259
 260 static const struct dss_mgr_ops mgr_ops = {
 261         .connect = omap_crtc_dss_connect,
 262         .disconnect = omap_crtc_dss_disconnect,
 263         .start_update = omap_crtc_dss_start_update,
 264         .enable = omap_crtc_dss_enable,
 265         .disable = omap_crtc_dss_disable,
 266         .set_timings = omap_crtc_dss_set_timings,
 267         .set_lcd_config = omap_crtc_dss_set_lcd_config,
 268         .register_framedone_handler = omap_crtc_dss_register_framedone,
 269         .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
 270 };
 271
 272 /* -----------------------------------------------------------------------------
 273  * Setup, Flush and Page Flip
 274  */
 275
 276 void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus)
 277 {
 278         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 279
 280         if (omap_crtc->ignore_digit_sync_lost) {
 281                 irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
 282                 if (!irqstatus)
 283                         return;
 284         }
 285
 286         DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
 287 }
 288
 289 void omap_crtc_vblank_irq(struct drm_crtc *crtc)
 290 {
 291         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 292         struct drm_device *dev = omap_crtc->base.dev;
 293         struct omap_drm_private *priv = dev->dev_private;
 294         bool pending;
 295
 296         spin_lock(&crtc->dev->event_lock);
 297         /*
 298          * If the dispc is busy we're racing the flush operation. Try again on
 299          * the next vblank interrupt.
 300          */
 301         if (priv->dispc_ops->mgr_go_busy(omap_crtc->channel)) {
 302                 spin_unlock(&crtc->dev->event_lock);
 303                 return;
 304         }
 305
 306         /* Send the vblank event if one has been requested. */
 307         if (omap_crtc->event) {
 308                 drm_crtc_send_vblank_event(crtc, omap_crtc->event);
 309                 omap_crtc->event = NULL;
 310         }
 311
 312         pending = omap_crtc->pending;
 313         omap_crtc->pending = false;
 314         spin_unlock(&crtc->dev->event_lock);
 315
 316         if (pending)
 317                 drm_crtc_vblank_put(crtc);
 318
 319         /* Wake up omap_atomic_complete. */
 320         wake_up(&omap_crtc->pending_wait);
 321
 322         DBG("%s: apply done", omap_crtc->name);
 323 }
 324
 325 static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
 326 {
 327         struct omap_drm_private *priv = crtc->dev->dev_private;
 328         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 329         struct omap_overlay_manager_info info;
 330
 331         memset(&info, 0, sizeof(info));
 332
 333         info.default_color = 0x000000;
 334         info.trans_enabled = false;
 335         info.partial_alpha_enabled = false;
 336         info.cpr_enable = false;
 337
 338         priv->dispc_ops->mgr_setup(omap_crtc->channel, &info);
 339 }
 340
 341 /* -----------------------------------------------------------------------------
 342  * CRTC Functions
 343  */
 344
 345 static void omap_crtc_destroy(struct drm_crtc *crtc)
 346 {
 347         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 348
 349         DBG("%s", omap_crtc->name);
 350
 351         drm_crtc_cleanup(crtc);
 352
 353         kfree(omap_crtc);
 354 }
 355
 356 static void omap_crtc_arm_event(struct drm_crtc *crtc)
 357 {
 358         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 359
 360         WARN_ON(omap_crtc->pending);
 361         omap_crtc->pending = true;
 362
 363         if (crtc->state->event) {
 364                 omap_crtc->event = crtc->state->event;
 365                 crtc->state->event = NULL;
 366         }
 367 }
 368
 369 static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
 370                                     struct drm_crtc_state *old_state)
 371 {
 372         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 373         int ret;
 374
 375         DBG("%s", omap_crtc->name);
 376
 377         spin_lock_irq(&crtc->dev->event_lock);
 378         drm_crtc_vblank_on(crtc);
 379         ret = drm_crtc_vblank_get(crtc);
 380         WARN_ON(ret != 0);
 381
 382         omap_crtc_arm_event(crtc);
 383         spin_unlock_irq(&crtc->dev->event_lock);
 384 }
 385
 386 static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
 387                                      struct drm_crtc_state *old_state)
 388 {
 389         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 390
 391         DBG("%s", omap_crtc->name);
 392
 393         spin_lock_irq(&crtc->dev->event_lock);
 394         if (crtc->state->event) {
 395                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 396                 crtc->state->event = NULL;
 397         }
 398         spin_unlock_irq(&crtc->dev->event_lock);
 399
 400         drm_crtc_vblank_off(crtc);
 401 }
 402
 403 static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
 404 {
 405         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 406         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 407         struct omap_drm_private *priv = crtc->dev->dev_private;
 408         const u32 flags_mask = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_DE_LOW |
 409                 DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
 410                 DISPLAY_FLAGS_SYNC_POSEDGE | DISPLAY_FLAGS_SYNC_NEGEDGE;
 411         unsigned int i;
 412
 413         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 414             omap_crtc->name, mode->base.id, mode->name,
 415             mode->vrefresh, mode->clock,
 416             mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
 417             mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
 418             mode->type, mode->flags);
 419
 420         drm_display_mode_to_videomode(mode, &omap_crtc->vm);
 421
 422         /*
 423          * HACK: This fixes the vm flags.
 424          * struct drm_display_mode does not contain the VSYNC/HSYNC/DE flags
 425          * and they get lost when converting back and forth between
 426          * struct drm_display_mode and struct videomode. The hack below
 427          * goes and fetches the missing flags from the panel drivers.
 428          *
 429          * Correct solution would be to use DRM's bus-flags, but that's not
 430          * easily possible before the omapdrm's panel/encoder driver model
 431          * has been changed to the DRM model.
 432          */
 433
 434         for (i = 0; i < priv->num_encoders; ++i) {
 435                 struct drm_encoder *encoder = priv->encoders[i];
 436
 437                 if (encoder->crtc == crtc) {
 438                         struct omap_dss_device *dssdev;
 439
 440                         dssdev = omap_encoder_get_dssdev(encoder);
 441
 442                         if (dssdev) {
 443                                 struct videomode vm = {0};
 444
 445                                 dssdev->driver->get_timings(dssdev, &vm);
 446
 447                                 omap_crtc->vm.flags |= vm.flags & flags_mask;
 448                         }
 449
 450                         break;
 451                 }
 452         }
 453 }
 454
 455 static int omap_crtc_atomic_check(struct drm_crtc *crtc,
 456                                 struct drm_crtc_state *state)
 457 {
 458         struct drm_plane_state *pri_state;
 459
 460         if (state->color_mgmt_changed && state->gamma_lut) {
 461                 uint length = state->gamma_lut->length /
 462                         sizeof(struct drm_color_lut);
 463
 464                 if (length < 2)
 465                         return -EINVAL;
 466         }
 467
 468         pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
 469         if (pri_state) {
 470                 struct omap_crtc_state *omap_crtc_state =
 471                         to_omap_crtc_state(state);
 472
 473                 /* Mirror new values for zpos and rotation in omap_crtc_state */
 474                 omap_crtc_state->zpos = pri_state->zpos;
 475                 omap_crtc_state->rotation = pri_state->rotation;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
 482                                    struct drm_crtc_state *old_crtc_state)
 483 {
 484 }
 485
 486 static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
 487                                    struct drm_crtc_state *old_crtc_state)
 488 {
 489         struct omap_drm_private *priv = crtc->dev->dev_private;
 490         struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
 491         int ret;
 492
 493         if (crtc->state->color_mgmt_changed) {
 494                 struct drm_color_lut *lut = NULL;
 495                 uint length = 0;
 496
 497                 if (crtc->state->gamma_lut) {
 498                         lut = (struct drm_color_lut *)
 499                                 crtc->state->gamma_lut->data;
 500                         length = crtc->state->gamma_lut->length /
 501                                 sizeof(*lut);
 502                 }
 503                 priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length);
 504         }
 505
 506         omap_crtc_write_crtc_properties(crtc);
 507
 508         /* Only flush the CRTC if it is currently enabled. */
 509         if (!omap_crtc->enabled)
 510                 return;
 511
 512         DBG("%s: GO", omap_crtc->name);
 513
 514         ret = drm_crtc_vblank_get(crtc);
 515         WARN_ON(ret != 0);
 516
 517         spin_lock_irq(&crtc->dev->event_lock);
 518         priv->dispc_ops->mgr_go(omap_crtc->channel);
 519         omap_crtc_arm_event(crtc);
 520         spin_unlock_irq(&crtc->dev->event_lock);
 521 }
 522
 523 static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
 524                                          struct drm_crtc_state *state,
 525                                          struct drm_property *property,
 526                                          uint64_t val)
 527 {
 528         struct omap_drm_private *priv = crtc->dev->dev_private;
 529         struct drm_plane_state *plane_state;
 530
 531         /*
 532          * Delegate property set to the primary plane. Get the plane state and
 533          * set the property directly, the shadow copy will be assigned in the
 534          * omap_crtc_atomic_check callback. This way updates to plane state will
 535          * always be mirrored in the crtc state correctly.
 536          */
 537         plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
 538         if (IS_ERR(plane_state))
 539                 return PTR_ERR(plane_state);
 540
 541         if (property == crtc->primary->rotation_property)
 542                 plane_state->rotation = val;
 543         else if (property == priv->zorder_prop)
 544                 plane_state->zpos = val;
 545         else
 546                 return -EINVAL;
 547
 548         return 0;
 549 }
 550
 551 static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
 552                                          const struct drm_crtc_state *state,
 553                                          struct drm_property *property,
 554                                          uint64_t *val)
 555 {
 556         struct omap_drm_private *priv = crtc->dev->dev_private;
 557         struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
 558
 559         if (property == crtc->primary->rotation_property)
 560                 *val = omap_state->rotation;
 561         else if (property == priv->zorder_prop)
 562                 *val = omap_state->zpos;
 563         else
 564                 return -EINVAL;
 565
 566         return 0;
 567 }
 568
 569 static void omap_crtc_reset(struct drm_crtc *crtc)
 570 {
 571         if (crtc->state)
 572                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 573
 574         kfree(crtc->state);
 575         crtc->state = kzalloc(sizeof(struct omap_crtc_state), GFP_KERNEL);
 576
 577         if (crtc->state)
 578                 crtc->state->crtc = crtc;
 579 }
 580
 581 static struct drm_crtc_state *
 582 omap_crtc_duplicate_state(struct drm_crtc *crtc)
 583 {
 584         struct omap_crtc_state *state, *current_state;
 585
 586         if (WARN_ON(!crtc->state))
 587                 return NULL;
 588
 589         current_state = to_omap_crtc_state(crtc->state);
 590
 591         state = kmalloc(sizeof(*state), GFP_KERNEL);
 592         if (!state)
 593                 return NULL;
 594
 595         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 596
 597         state->zpos = current_state->zpos;
 598         state->rotation = current_state->rotation;
 599
 600         return &state->base;
 601 }
 602
 603 static const struct drm_crtc_funcs omap_crtc_funcs = {
 604         .reset = omap_crtc_reset,
 605         .set_config = drm_atomic_helper_set_config,
 606         .destroy = omap_crtc_destroy,
 607         .page_flip = drm_atomic_helper_page_flip,
 608         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 609         .atomic_duplicate_state = omap_crtc_duplicate_state,
 610         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 611         .atomic_set_property = omap_crtc_atomic_set_property,
 612         .atomic_get_property = omap_crtc_atomic_get_property,
 613         .enable_vblank = omap_irq_enable_vblank,
 614         .disable_vblank = omap_irq_disable_vblank,
 615 };
 616
 617 static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
 618         .mode_set_nofb = omap_crtc_mode_set_nofb,
 619         .atomic_check = omap_crtc_atomic_check,
 620         .atomic_begin = omap_crtc_atomic_begin,
 621         .atomic_flush = omap_crtc_atomic_flush,
 622         .atomic_enable = omap_crtc_atomic_enable,
 623         .atomic_disable = omap_crtc_atomic_disable,
 624 };
 625
 626 /* -----------------------------------------------------------------------------
 627  * Init and Cleanup
 628  */
 629
 630 static const char *channel_names[] = {
 631         [OMAP_DSS_CHANNEL_LCD] = "lcd",
 632         [OMAP_DSS_CHANNEL_DIGIT] = "tv",
 633         [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
 634         [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
 635 };
 636
 637 void omap_crtc_pre_init(void)
 638 {
 639         memset(omap_crtcs, 0, sizeof(omap_crtcs));
 640
 641         dss_install_mgr_ops(&mgr_ops);
 642 }
 643
 644 void omap_crtc_pre_uninit(void)
 645 {
 646         dss_uninstall_mgr_ops();
 647 }
 648
 649 /* initialize crtc */
 650 struct drm_crtc *omap_crtc_init(struct drm_device *dev,
 651                 struct drm_plane *plane, struct omap_dss_device *dssdev)
 652 {
 653         struct omap_drm_private *priv = dev->dev_private;
 654         struct drm_crtc *crtc = NULL;
 655         struct omap_crtc *omap_crtc;
 656         enum omap_channel channel;
 657         struct omap_dss_device *out;
 658         int ret;
 659
 660         out = omapdss_find_output_from_display(dssdev);
 661         channel = out->dispc_channel;
 662         omap_dss_put_device(out);
 663
 664         DBG("%s", channel_names[channel]);
 665
 666         /* Multiple displays on same channel is not allowed */
 667         if (WARN_ON(omap_crtcs[channel] != NULL))
 668                 return ERR_PTR(-EINVAL);
 669
 670         omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
 671         if (!omap_crtc)
 672                 return ERR_PTR(-ENOMEM);
 673
 674         crtc = &omap_crtc->base;
 675
 676         init_waitqueue_head(&omap_crtc->pending_wait);
 677
 678         omap_crtc->channel = channel;
 679         omap_crtc->name = channel_names[channel];
 680
 681         ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
 682                                         &omap_crtc_funcs, NULL);
 683         if (ret < 0) {
 684                 dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
 685                         __func__, dssdev->name);
 686                 kfree(omap_crtc);
 687                 return ERR_PTR(ret);
 688         }
 689
 690         drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
 691
 692         /* The dispc API adapts to what ever size, but the HW supports
 693          * 256 element gamma table for LCDs and 1024 element table for
 694          * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
 695          * tables so lets use that. Size of HW gamma table can be
 696          * extracted with dispc_mgr_gamma_size(). If it returns 0
 697          * gamma table is not supprted.
 698          */
 699         if (priv->dispc_ops->mgr_gamma_size(channel)) {
 700                 uint gamma_lut_size = 256;
 701
 702                 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
 703                 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
 704         }
 705
 706         omap_plane_install_properties(crtc->primary, &crtc->base);
 707
 708         omap_crtcs[channel] = omap_crtc;
 709
 710         return crtc;
 711 }