drivers/gpu/drm/bridge/ite-it6505.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5 #include <linux/bits.h>
   6 #include <linux/delay.h>
   7 #include <linux/device.h>
   8 #include <linux/err.h>
   9 #include <linux/extcon.h>
  10 #include <linux/fs.h>
  11 #include <linux/gpio/consumer.h>
  12 #include <linux/i2c.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/types.h>
  20 #include <linux/wait.h>
  21
  22 #include <crypto/hash.h>
  23
  24 #include <drm/display/drm_dp_helper.h>
  25 #include <drm/display/drm_hdcp_helper.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_print.h>
  32 #include <drm/drm_probe_helper.h>
  33
  34 #include <sound/hdmi-codec.h>
  35
  36 #define REG_IC_VER 0x04
  37
  38 #define REG_RESET_CTRL 0x05
  39 #define VIDEO_RESET BIT(0)
  40 #define AUDIO_RESET BIT(1)
  41 #define ALL_LOGIC_RESET BIT(2)
  42 #define AUX_RESET BIT(3)
  43 #define HDCP_RESET BIT(4)
  44
  45 #define INT_STATUS_01 0x06
  46 #define INT_MASK_01 0x09
  47 #define INT_HPD_CHANGE 0
  48 #define INT_RECEIVE_HPD_IRQ 1
  49 #define INT_SCDT_CHANGE 2
  50 #define INT_HDCP_FAIL 3
  51 #define INT_HDCP_DONE 4
  52 #define BIT_OFFSET(x) (((x) - INT_STATUS_01) * BITS_PER_BYTE)
  53 #define BIT_INT_HPD INT_HPD_CHANGE
  54 #define BIT_INT_HPD_IRQ INT_RECEIVE_HPD_IRQ
  55 #define BIT_INT_SCDT INT_SCDT_CHANGE
  56 #define BIT_INT_HDCP_FAIL INT_HDCP_FAIL
  57 #define BIT_INT_HDCP_DONE INT_HDCP_DONE
  58
  59 #define INT_STATUS_02 0x07
  60 #define INT_MASK_02 0x0A
  61 #define INT_AUX_CMD_FAIL 0
  62 #define INT_HDCP_KSV_CHECK 1
  63 #define INT_AUDIO_FIFO_ERROR 2
  64 #define BIT_INT_AUX_CMD_FAIL (BIT_OFFSET(0x07) + INT_AUX_CMD_FAIL)
  65 #define BIT_INT_HDCP_KSV_CHECK (BIT_OFFSET(0x07) + INT_HDCP_KSV_CHECK)
  66 #define BIT_INT_AUDIO_FIFO_ERROR (BIT_OFFSET(0x07) + INT_AUDIO_FIFO_ERROR)
  67
  68 #define INT_STATUS_03 0x08
  69 #define INT_MASK_03 0x0B
  70 #define INT_LINK_TRAIN_FAIL 4
  71 #define INT_VID_FIFO_ERROR 5
  72 #define INT_IO_LATCH_FIFO_OVERFLOW 7
  73 #define BIT_INT_LINK_TRAIN_FAIL (BIT_OFFSET(0x08) + INT_LINK_TRAIN_FAIL)
  74 #define BIT_INT_VID_FIFO_ERROR (BIT_OFFSET(0x08) + INT_VID_FIFO_ERROR)
  75 #define BIT_INT_IO_FIFO_OVERFLOW (BIT_OFFSET(0x08) + INT_IO_LATCH_FIFO_OVERFLOW)
  76
  77 #define REG_SYSTEM_STS 0x0D
  78 #define INT_STS BIT(0)
  79 #define HPD_STS BIT(1)
  80 #define VIDEO_STB BIT(2)
  81
  82 #define REG_LINK_TRAIN_STS 0x0E
  83 #define LINK_STATE_CR BIT(2)
  84 #define LINK_STATE_EQ BIT(3)
  85 #define LINK_STATE_NORP BIT(4)
  86
  87 #define REG_BANK_SEL 0x0F
  88 #define REG_CLK_CTRL0 0x10
  89 #define M_PCLK_DELAY 0x03
  90
  91 #define REG_AUX_OPT 0x11
  92 #define AUX_AUTO_RST BIT(0)
  93 #define AUX_FIX_FREQ BIT(3)
  94
  95 #define REG_DATA_CTRL0 0x12
  96 #define VIDEO_LATCH_EDGE BIT(4)
  97 #define ENABLE_PCLK_COUNTER BIT(7)
  98
  99 #define REG_PCLK_COUNTER_VALUE 0x13
 100
 101 #define REG_501_FIFO_CTRL 0x15
 102 #define RST_501_FIFO BIT(1)
 103
 104 #define REG_TRAIN_CTRL0 0x16
 105 #define FORCE_LBR BIT(0)
 106 #define LANE_COUNT_MASK 0x06
 107 #define LANE_SWAP BIT(3)
 108 #define SPREAD_AMP_5 BIT(4)
 109 #define FORCE_CR_DONE BIT(5)
 110 #define FORCE_EQ_DONE BIT(6)
 111
 112 #define REG_TRAIN_CTRL1 0x17
 113 #define AUTO_TRAIN BIT(0)
 114 #define MANUAL_TRAIN BIT(1)
 115 #define FORCE_RETRAIN BIT(2)
 116
 117 #define REG_AUX_CTRL 0x23
 118 #define CLR_EDID_FIFO BIT(0)
 119 #define AUX_USER_MODE BIT(1)
 120 #define AUX_NO_SEGMENT_WR BIT(6)
 121 #define AUX_EN_FIFO_READ BIT(7)
 122
 123 #define REG_AUX_ADR_0_7 0x24
 124 #define REG_AUX_ADR_8_15 0x25
 125 #define REG_AUX_ADR_16_19 0x26
 126 #define REG_AUX_OUT_DATA0 0x27
 127
 128 #define REG_AUX_CMD_REQ 0x2B
 129 #define AUX_BUSY BIT(5)
 130
 131 #define REG_AUX_DATA_0_7 0x2C
 132 #define REG_AUX_DATA_8_15 0x2D
 133 #define REG_AUX_DATA_16_23 0x2E
 134 #define REG_AUX_DATA_24_31 0x2F
 135
 136 #define REG_AUX_DATA_FIFO 0x2F
 137
 138 #define REG_AUX_ERROR_STS 0x9F
 139 #define M_AUX_REQ_FAIL 0x03
 140
 141 #define REG_HDCP_CTRL1 0x38
 142 #define HDCP_CP_ENABLE BIT(0)
 143
 144 #define REG_HDCP_TRIGGER 0x39
 145 #define HDCP_TRIGGER_START  BIT(0)
 146 #define HDCP_TRIGGER_CPIRQ  BIT(1)
 147 #define HDCP_TRIGGER_KSV_DONE  BIT(4)
 148 #define HDCP_TRIGGER_KSV_FAIL BIT(5)
 149
 150 #define REG_HDCP_CTRL2 0x3A
 151 #define HDCP_AN_SEL BIT(0)
 152 #define HDCP_AN_GEN BIT(1)
 153 #define HDCP_HW_HPDIRQ_ACT BIT(2)
 154 #define HDCP_EN_M0_READ BIT(5)
 155
 156 #define REG_M0_0_7 0x4C
 157 #define REG_AN_0_7 0x4C
 158 #define REG_SP_CTRL0 0x58
 159 #define REG_IP_CTRL1 0x59
 160 #define REG_IP_CTRL2 0x5A
 161
 162 #define REG_LINK_DRV 0x5C
 163 #define DRV_HS BIT(1)
 164
 165 #define REG_DRV_LN_DATA_SEL 0x5D
 166
 167 #define REG_AUX 0x5E
 168
 169 #define REG_VID_BUS_CTRL0 0x60
 170 #define IN_DDR BIT(2)
 171 #define DDR_CD (0x01 << 6)
 172
 173 #define REG_VID_BUS_CTRL1 0x61
 174 #define TX_FIFO_RESET BIT(1)
 175
 176 #define REG_INPUT_CTRL 0xA0
 177 #define INPUT_HSYNC_POL BIT(0)
 178 #define INPUT_VSYNC_POL BIT(2)
 179 #define INPUT_INTERLACED BIT(4)
 180
 181 #define REG_INPUT_HTOTAL 0xA1
 182 #define REG_INPUT_HACTIVE_START 0xA3
 183 #define REG_INPUT_HACTIVE_WIDTH 0xA5
 184 #define REG_INPUT_HFRONT_PORCH 0xA7
 185 #define REG_INPUT_HSYNC_WIDTH 0xA9
 186 #define REG_INPUT_VTOTAL 0xAB
 187 #define REG_INPUT_VACTIVE_START 0xAD
 188 #define REG_INPUT_VACTIVE_WIDTH 0xAF
 189 #define REG_INPUT_VFRONT_PORCH 0xB1
 190 #define REG_INPUT_VSYNC_WIDTH 0xB3
 191
 192 #define REG_AUDIO_SRC_CTRL 0xB8
 193 #define M_AUDIO_I2S_EN 0x0F
 194 #define EN_I2S0 BIT(0)
 195 #define EN_I2S1 BIT(1)
 196 #define EN_I2S2 BIT(2)
 197 #define EN_I2S3 BIT(3)
 198 #define AUDIO_FIFO_RESET BIT(7)
 199
 200 #define REG_AUDIO_FMT 0xB9
 201 #define REG_AUDIO_FIFO_SEL 0xBA
 202
 203 #define REG_AUDIO_CTRL0 0xBB
 204 #define AUDIO_FULL_PKT BIT(4)
 205 #define AUDIO_16B_BOUND BIT(5)
 206
 207 #define REG_AUDIO_CTRL1 0xBC
 208 #define REG_AUDIO_INPUT_FREQ 0xBE
 209
 210 #define REG_IEC958_STS0 0xBF
 211 #define REG_IEC958_STS1 0xC0
 212 #define REG_IEC958_STS2 0xC1
 213 #define REG_IEC958_STS3 0xC2
 214 #define REG_IEC958_STS4 0xC3
 215
 216 #define REG_HPD_IRQ_TIME 0xC9
 217 #define REG_AUX_DEBUG_MODE 0xCA
 218 #define REG_AUX_OPT2 0xCB
 219 #define REG_HDCP_OPT 0xCE
 220 #define REG_USER_DRV_PRE 0xCF
 221
 222 #define REG_DATA_MUTE_CTRL 0xD3
 223 #define ENABLE_ENHANCED_FRAME BIT(0)
 224 #define ENABLE_AUTO_VIDEO_FIFO_RESET BIT(1)
 225 #define EN_VID_MUTE BIT(4)
 226 #define EN_AUD_MUTE BIT(5)
 227
 228 #define REG_TIME_STMP_CTRL 0xD4
 229 #define EN_ENHANCE_VID_STMP BIT(0)
 230 #define EN_ENHANCE_AUD_STMP BIT(2)
 231 #define M_STAMP_STEP 0x30
 232 #define EN_SSC_GAT BIT(6)
 233
 234 #define REG_INFOFRAME_CTRL 0xE8
 235 #define EN_AVI_PKT BIT(0)
 236 #define EN_AUD_PKT BIT(1)
 237 #define EN_MPG_PKT BIT(2)
 238 #define EN_GEN_PKT BIT(3)
 239 #define EN_VID_TIME_STMP BIT(4)
 240 #define EN_AUD_TIME_STMP BIT(5)
 241 #define EN_VID_CTRL_PKT (EN_AVI_PKT | EN_VID_TIME_STMP)
 242 #define EN_AUD_CTRL_PKT (EN_AUD_PKT | EN_AUD_TIME_STMP)
 243
 244 #define REG_AUDIO_N_0_7 0xDE
 245 #define REG_AUDIO_N_8_15 0xDF
 246 #define REG_AUDIO_N_16_23 0xE0
 247
 248 #define REG_AVI_INFO_DB1 0xE9
 249 #define REG_AVI_INFO_DB2 0xEA
 250 #define REG_AVI_INFO_DB3 0xEB
 251 #define REG_AVI_INFO_DB4 0xEC
 252 #define REG_AVI_INFO_DB5 0xED
 253 #define REG_AVI_INFO_SUM 0xF6
 254
 255 #define REG_AUD_INFOFRAM_DB1 0xF7
 256 #define REG_AUD_INFOFRAM_DB2 0xF8
 257 #define REG_AUD_INFOFRAM_DB3 0xF9
 258 #define REG_AUD_INFOFRAM_DB4 0xFA
 259 #define REG_AUD_INFOFRAM_SUM 0xFB
 260
 261 /* the following six registers are in bank1 */
 262 #define REG_DRV_0_DB_800_MV 0x7E
 263 #define REG_PRE_0_DB_800_MV 0x7F
 264 #define REG_PRE_3P5_DB_800_MV 0x81
 265 #define REG_SSC_CTRL0 0x88
 266 #define REG_SSC_CTRL1 0x89
 267 #define REG_SSC_CTRL2 0x8A
 268
 269 #define RBR DP_LINK_BW_1_62
 270 #define HBR DP_LINK_BW_2_7
 271 #define HBR2 DP_LINK_BW_5_4
 272 #define HBR3 DP_LINK_BW_8_1
 273
 274 #define DPCD_V_1_1 0x11
 275 #define MISC_VERB 0xF0
 276 #define MISC_VERC 0x70
 277 #define I2S_INPUT_FORMAT_STANDARD 0
 278 #define I2S_INPUT_FORMAT_32BIT 1
 279 #define I2S_INPUT_LEFT_JUSTIFIED 0
 280 #define I2S_INPUT_RIGHT_JUSTIFIED 1
 281 #define I2S_DATA_1T_DELAY 0
 282 #define I2S_DATA_NO_DELAY 1
 283 #define I2S_WS_LEFT_CHANNEL 0
 284 #define I2S_WS_RIGHT_CHANNEL 1
 285 #define I2S_DATA_MSB_FIRST 0
 286 #define I2S_DATA_LSB_FIRST 1
 287 #define WORD_LENGTH_16BIT 0
 288 #define WORD_LENGTH_18BIT 1
 289 #define WORD_LENGTH_20BIT 2
 290 #define WORD_LENGTH_24BIT 3
 291 #define DEBUGFS_DIR_NAME "it6505-debugfs"
 292 #define READ_BUFFER_SIZE 400
 293
 294 /* Vendor option */
 295 #define HDCP_DESIRED 1
 296 #define MAX_LANE_COUNT 4
 297 #define MAX_LINK_RATE HBR
 298 #define AUTO_TRAIN_RETRY 3
 299 #define MAX_HDCP_DOWN_STREAM_COUNT 10
 300 #define MAX_CR_LEVEL 0x03
 301 #define MAX_EQ_LEVEL 0x03
 302 #define AUX_WAIT_TIMEOUT_MS 15
 303 #define AUX_FIFO_MAX_SIZE 32
 304 #define PIXEL_CLK_DELAY 1
 305 #define PIXEL_CLK_INVERSE 0
 306 #define ADJUST_PHASE_THRESHOLD 80000
 307 #define DPI_PIXEL_CLK_MAX 95000
 308 #define HDCP_SHA1_FIFO_LEN (MAX_HDCP_DOWN_STREAM_COUNT * 5 + 10)
 309 #define DEFAULT_PWR_ON 0
 310 #define DEFAULT_DRV_HOLD 0
 311
 312 #define AUDIO_SELECT I2S
 313 #define AUDIO_TYPE LPCM
 314 #define AUDIO_SAMPLE_RATE SAMPLE_RATE_48K
 315 #define AUDIO_CHANNEL_COUNT 2
 316 #define I2S_INPUT_FORMAT I2S_INPUT_FORMAT_32BIT
 317 #define I2S_JUSTIFIED I2S_INPUT_LEFT_JUSTIFIED
 318 #define I2S_DATA_DELAY I2S_DATA_1T_DELAY
 319 #define I2S_WS_CHANNEL I2S_WS_LEFT_CHANNEL
 320 #define I2S_DATA_SEQUENCE I2S_DATA_MSB_FIRST
 321 #define AUDIO_WORD_LENGTH WORD_LENGTH_24BIT
 322
 323 enum aux_cmd_type {
 324         CMD_AUX_NATIVE_READ = 0x0,
 325         CMD_AUX_NATIVE_WRITE = 0x5,
 326         CMD_AUX_I2C_EDID_READ = 0xB,
 327 };
 328
 329 enum aux_cmd_reply {
 330         REPLY_ACK,
 331         REPLY_NACK,
 332         REPLY_DEFER,
 333 };
 334
 335 enum link_train_status {
 336         LINK_IDLE,
 337         LINK_BUSY,
 338         LINK_OK,
 339 };
 340
 341 enum hdcp_state {
 342         HDCP_AUTH_IDLE,
 343         HDCP_AUTH_GOING,
 344         HDCP_AUTH_DONE,
 345 };
 346
 347 struct it6505_platform_data {
 348         struct regulator *pwr18;
 349         struct regulator *ovdd;
 350         struct gpio_desc *gpiod_reset;
 351 };
 352
 353 enum it6505_audio_select {
 354         I2S = 0,
 355         SPDIF,
 356 };
 357
 358 enum it6505_audio_sample_rate {
 359         SAMPLE_RATE_24K = 0x6,
 360         SAMPLE_RATE_32K = 0x3,
 361         SAMPLE_RATE_48K = 0x2,
 362         SAMPLE_RATE_96K = 0xA,
 363         SAMPLE_RATE_192K = 0xE,
 364         SAMPLE_RATE_44_1K = 0x0,
 365         SAMPLE_RATE_88_2K = 0x8,
 366         SAMPLE_RATE_176_4K = 0xC,
 367 };
 368
 369 enum it6505_audio_type {
 370         LPCM = 0,
 371         NLPCM,
 372         DSS,
 373 };
 374
 375 struct it6505_audio_data {
 376         enum it6505_audio_select select;
 377         enum it6505_audio_sample_rate sample_rate;
 378         enum it6505_audio_type type;
 379         u8 word_length;
 380         u8 channel_count;
 381         u8 i2s_input_format;
 382         u8 i2s_justified;
 383         u8 i2s_data_delay;
 384         u8 i2s_ws_channel;
 385         u8 i2s_data_sequence;
 386 };
 387
 388 struct it6505_audio_sample_rate_map {
 389         enum it6505_audio_sample_rate rate;
 390         int sample_rate_value;
 391 };
 392
 393 struct it6505_drm_dp_link {
 394         unsigned char revision;
 395         unsigned int rate;
 396         unsigned int num_lanes;
 397         unsigned long capabilities;
 398 };
 399
 400 struct debugfs_entries {
 401         char *name;
 402         const struct file_operations *fops;
 403 };
 404
 405 struct it6505 {
 406         struct drm_dp_aux aux;
 407         struct drm_bridge bridge;
 408         struct i2c_client *client;
 409         struct it6505_drm_dp_link link;
 410         struct it6505_platform_data pdata;
 411         /*
 412          * Mutex protects extcon and interrupt functions from interfering
 413          * each other.
 414          */
 415         struct mutex extcon_lock;
 416         struct mutex mode_lock; /* used to bridge_detect */
 417         struct mutex aux_lock; /* used to aux data transfers */
 418         struct regmap *regmap;
 419         struct drm_display_mode source_output_mode;
 420         struct drm_display_mode video_info;
 421         struct notifier_block event_nb;
 422         struct extcon_dev *extcon;
 423         struct work_struct extcon_wq;
 424         enum drm_connector_status connector_status;
 425         enum link_train_status link_state;
 426         struct work_struct link_works;
 427         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 428         u8 lane_count;
 429         u8 link_rate_bw_code;
 430         u8 sink_count;
 431         bool step_train;
 432         bool branch_device;
 433         bool enable_ssc;
 434         bool lane_swap_disabled;
 435         bool lane_swap;
 436         bool powered;
 437         bool hpd_state;
 438         u32 afe_setting;
 439         enum hdcp_state hdcp_status;
 440         struct delayed_work hdcp_work;
 441         struct work_struct hdcp_wait_ksv_list;
 442         struct completion wait_edid_complete;
 443         u8 auto_train_retry;
 444         bool hdcp_desired;
 445         bool is_repeater;
 446         u8 hdcp_down_stream_count;
 447         u8 bksvs[DRM_HDCP_KSV_LEN];
 448         u8 sha1_input[HDCP_SHA1_FIFO_LEN];
 449         bool enable_enhanced_frame;
 450         hdmi_codec_plugged_cb plugged_cb;
 451         struct device *codec_dev;
 452         struct delayed_work delayed_audio;
 453         struct it6505_audio_data audio;
 454         struct dentry *debugfs;
 455
 456         /* it6505 driver hold option */
 457         bool enable_drv_hold;
 458 };
 459
 460 struct it6505_step_train_para {
 461         u8 voltage_swing[MAX_LANE_COUNT];
 462         u8 pre_emphasis[MAX_LANE_COUNT];
 463 };
 464
 465 /*
 466  * Vendor option afe settings for different platforms
 467  * 0: without FPC cable
 468  * 1: with FPC cable
 469  */
 470
 471 static const u8 afe_setting_table[][3] = {
 472         {0x82, 0x00, 0x45},
 473         {0x93, 0x2A, 0x85}
 474 };
 475
 476 static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = {
 477         {SAMPLE_RATE_24K, 24000},
 478         {SAMPLE_RATE_32K, 32000},
 479         {SAMPLE_RATE_48K, 48000},
 480         {SAMPLE_RATE_96K, 96000},
 481         {SAMPLE_RATE_192K, 192000},
 482         {SAMPLE_RATE_44_1K, 44100},
 483         {SAMPLE_RATE_88_2K, 88200},
 484         {SAMPLE_RATE_176_4K, 176400},
 485 };
 486
 487 static const struct regmap_range it6505_bridge_volatile_ranges[] = {
 488         { .range_min = 0, .range_max = 0xFF },
 489 };
 490
 491 static const struct regmap_access_table it6505_bridge_volatile_table = {
 492         .yes_ranges = it6505_bridge_volatile_ranges,
 493         .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges),
 494 };
 495
 496 static const struct regmap_config it6505_regmap_config = {
 497         .reg_bits = 8,
 498         .val_bits = 8,
 499         .volatile_table = &it6505_bridge_volatile_table,
 500         .cache_type = REGCACHE_NONE,
 501 };
 502
 503 static int it6505_read(struct it6505 *it6505, unsigned int reg_addr)
 504 {
 505         unsigned int value;
 506         int err;
 507         struct device *dev = &it6505->client->dev;
 508
 509         err = regmap_read(it6505->regmap, reg_addr, &value);
 510         if (err < 0) {
 511                 dev_err(dev, "read failed reg[0x%x] err: %d", reg_addr, err);
 512                 return err;
 513         }
 514
 515         return value;
 516 }
 517
 518 static int it6505_write(struct it6505 *it6505, unsigned int reg_addr,
 519                         unsigned int reg_val)
 520 {
 521         int err;
 522         struct device *dev = &it6505->client->dev;
 523
 524         err = regmap_write(it6505->regmap, reg_addr, reg_val);
 525
 526         if (err < 0) {
 527                 dev_err(dev, "write failed reg[0x%x] = 0x%x err = %d",
 528                         reg_addr, reg_val, err);
 529                 return err;
 530         }
 531
 532         return 0;
 533 }
 534
 535 static int it6505_set_bits(struct it6505 *it6505, unsigned int reg,
 536                            unsigned int mask, unsigned int value)
 537 {
 538         int err;
 539         struct device *dev = &it6505->client->dev;
 540
 541         err = regmap_update_bits(it6505->regmap, reg, mask, value);
 542         if (err < 0) {
 543                 dev_err(dev, "write reg[0x%x] = 0x%x mask = 0x%x failed err %d",
 544                         reg, value, mask, err);
 545                 return err;
 546         }
 547
 548         return 0;
 549 }
 550
 551 static void it6505_debug_print(struct it6505 *it6505, unsigned int reg,
 552                                const char *prefix)
 553 {
 554         struct device *dev = &it6505->client->dev;
 555         int val;
 556
 557         if (likely(!(__drm_debug & DRM_UT_DRIVER)))
 558                 return;
 559
 560         val = it6505_read(it6505, reg);
 561         if (val < 0)
 562                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] read error (%d)",
 563                                      prefix, reg, val);
 564         else
 565                 DRM_DEV_DEBUG_DRIVER(dev, "%s reg[%02x] = 0x%02x", prefix, reg,
 566                                      val);
 567 }
 568
 569 static int it6505_dpcd_read(struct it6505 *it6505, unsigned long offset)
 570 {
 571         u8 value;
 572         int ret;
 573         struct device *dev = &it6505->client->dev;
 574
 575         ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);
 576         if (ret < 0) {
 577                 dev_err(dev, "DPCD read failed [0x%lx] ret: %d", offset, ret);
 578                 return ret;
 579         }
 580         return value;
 581 }
 582
 583 static int it6505_dpcd_write(struct it6505 *it6505, unsigned long offset,
 584                              u8 datain)
 585 {
 586         int ret;
 587         struct device *dev = &it6505->client->dev;
 588
 589         ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);
 590         if (ret < 0) {
 591                 dev_err(dev, "DPCD write failed [0x%lx] ret: %d", offset, ret);
 592                 return ret;
 593         }
 594         return 0;
 595 }
 596
 597 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)
 598 {
 599         int ret;
 600         struct device *dev = &it6505->client->dev;
 601
 602         ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);
 603
 604         if (ret < 0)
 605                 return ret;
 606
 607         DRM_DEV_DEBUG_DRIVER(dev, "ret = %d DPCD[0x%x] = 0x%*ph", ret, offset,
 608                              num, dpcd);
 609
 610         return 0;
 611 }
 612
 613 static void it6505_dump(struct it6505 *it6505)
 614 {
 615         unsigned int i, j;
 616         u8 regs[16];
 617         struct device *dev = &it6505->client->dev;
 618
 619         for (i = 0; i <= 0xff; i += 16) {
 620                 for (j = 0; j < 16; j++)
 621                         regs[j] = it6505_read(it6505, i + j);
 622
 623                 DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x] = %16ph", i, regs);
 624         }
 625 }
 626
 627 static bool it6505_get_sink_hpd_status(struct it6505 *it6505)
 628 {
 629         int reg_0d;
 630
 631         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
 632
 633         if (reg_0d < 0)
 634                 return false;
 635
 636         return reg_0d & HPD_STS;
 637 }
 638
 639 static int it6505_read_word(struct it6505 *it6505, unsigned int reg)
 640 {
 641         int val0, val1;
 642
 643         val0 = it6505_read(it6505, reg);
 644         if (val0 < 0)
 645                 return val0;
 646
 647         val1 = it6505_read(it6505, reg + 1);
 648         if (val1 < 0)
 649                 return val1;
 650
 651         return (val1 << 8) | val0;
 652 }
 653
 654 static void it6505_calc_video_info(struct it6505 *it6505)
 655 {
 656         struct device *dev = &it6505->client->dev;
 657         int hsync_pol, vsync_pol, interlaced;
 658         int htotal, hdes, hdew, hfph, hsyncw;
 659         int vtotal, vdes, vdew, vfph, vsyncw;
 660         int rddata, i, pclk, sum = 0;
 661
 662         usleep_range(10000, 15000);
 663         rddata = it6505_read(it6505, REG_INPUT_CTRL);
 664         hsync_pol = rddata & INPUT_HSYNC_POL;
 665         vsync_pol = (rddata & INPUT_VSYNC_POL) >> 2;
 666         interlaced = (rddata & INPUT_INTERLACED) >> 4;
 667
 668         htotal = it6505_read_word(it6505, REG_INPUT_HTOTAL) & 0x1FFF;
 669         hdes = it6505_read_word(it6505, REG_INPUT_HACTIVE_START) & 0x1FFF;
 670         hdew = it6505_read_word(it6505, REG_INPUT_HACTIVE_WIDTH) & 0x1FFF;
 671         hfph = it6505_read_word(it6505, REG_INPUT_HFRONT_PORCH) & 0x1FFF;
 672         hsyncw = it6505_read_word(it6505, REG_INPUT_HSYNC_WIDTH) & 0x1FFF;
 673
 674         vtotal = it6505_read_word(it6505, REG_INPUT_VTOTAL) & 0xFFF;
 675         vdes = it6505_read_word(it6505, REG_INPUT_VACTIVE_START) & 0xFFF;
 676         vdew = it6505_read_word(it6505, REG_INPUT_VACTIVE_WIDTH) & 0xFFF;
 677         vfph = it6505_read_word(it6505, REG_INPUT_VFRONT_PORCH) & 0xFFF;
 678         vsyncw = it6505_read_word(it6505, REG_INPUT_VSYNC_WIDTH) & 0xFFF;
 679
 680         DRM_DEV_DEBUG_DRIVER(dev, "hsync_pol:%d, vsync_pol:%d, interlaced:%d",
 681                              hsync_pol, vsync_pol, interlaced);
 682         DRM_DEV_DEBUG_DRIVER(dev, "hactive_start:%d, vactive_start:%d",
 683                              hdes, vdes);
 684
 685         for (i = 0; i < 10; i++) {
 686                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 687                                 ENABLE_PCLK_COUNTER);
 688                 usleep_range(10000, 15000);
 689                 it6505_set_bits(it6505, REG_DATA_CTRL0, ENABLE_PCLK_COUNTER,
 690                                 0x00);
 691                 rddata = it6505_read_word(it6505, REG_PCLK_COUNTER_VALUE) &
 692                          0xFFF;
 693
 694                 sum += rddata;
 695         }
 696
 697         if (sum == 0) {
 698                 DRM_DEV_DEBUG_DRIVER(dev, "calc video timing error");
 699                 return;
 700         }
 701
 702         sum /= 10;
 703         pclk = 13500 * 2048 / sum;
 704         it6505->video_info.clock = pclk;
 705         it6505->video_info.hdisplay = hdew;
 706         it6505->video_info.hsync_start = hdew + hfph;
 707         it6505->video_info.hsync_end = hdew + hfph + hsyncw;
 708         it6505->video_info.htotal = htotal;
 709         it6505->video_info.vdisplay = vdew;
 710         it6505->video_info.vsync_start = vdew + vfph;
 711         it6505->video_info.vsync_end = vdew + vfph + vsyncw;
 712         it6505->video_info.vtotal = vtotal;
 713
 714         DRM_DEV_DEBUG_DRIVER(dev, DRM_MODE_FMT,
 715                              DRM_MODE_ARG(&it6505->video_info));
 716 }
 717
 718 static int it6505_drm_dp_link_probe(struct drm_dp_aux *aux,
 719                                     struct it6505_drm_dp_link *link)
 720 {
 721         u8 values[3];
 722         int err;
 723
 724         memset(link, 0, sizeof(*link));
 725
 726         err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
 727         if (err < 0)
 728                 return err;
 729
 730         link->revision = values[0];
 731         link->rate = drm_dp_bw_code_to_link_rate(values[1]);
 732         link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
 733
 734         if (values[2] & DP_ENHANCED_FRAME_CAP)
 735                 link->capabilities = DP_ENHANCED_FRAME_CAP;
 736
 737         return 0;
 738 }
 739
 740 static int it6505_drm_dp_link_set_power(struct drm_dp_aux *aux,
 741                                         struct it6505_drm_dp_link *link,
 742                                         u8 mode)
 743 {
 744         u8 value;
 745         int err;
 746
 747         /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 748         if (link->revision < DPCD_V_1_1)
 749                 return 0;
 750
 751         err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 752         if (err < 0)
 753                 return err;
 754
 755         value &= ~DP_SET_POWER_MASK;
 756         value |= mode;
 757
 758         err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 759         if (err < 0)
 760                 return err;
 761
 762         if (mode == DP_SET_POWER_D0) {
 763                 /*
 764                  * According to the DP 1.1 specification, a "Sink Device must
 765                  * exit the power saving state within 1 ms" (Section 2.5.3.1,
 766                  * Table 5-52, "Sink Control Field" (register 0x600).
 767                  */
 768                 usleep_range(1000, 2000);
 769         }
 770
 771         return 0;
 772 }
 773
 774 static void it6505_clear_int(struct it6505 *it6505)
 775 {
 776         it6505_write(it6505, INT_STATUS_01, 0xFF);
 777         it6505_write(it6505, INT_STATUS_02, 0xFF);
 778         it6505_write(it6505, INT_STATUS_03, 0xFF);
 779 }
 780
 781 static void it6505_int_mask_enable(struct it6505 *it6505)
 782 {
 783         it6505_write(it6505, INT_MASK_01, BIT(INT_HPD_CHANGE) |
 784                      BIT(INT_RECEIVE_HPD_IRQ) | BIT(INT_SCDT_CHANGE) |
 785                      BIT(INT_HDCP_FAIL) | BIT(INT_HDCP_DONE));
 786
 787         it6505_write(it6505, INT_MASK_02, BIT(INT_AUX_CMD_FAIL) |
 788                      BIT(INT_HDCP_KSV_CHECK) | BIT(INT_AUDIO_FIFO_ERROR));
 789
 790         it6505_write(it6505, INT_MASK_03, BIT(INT_LINK_TRAIN_FAIL) |
 791                      BIT(INT_VID_FIFO_ERROR) | BIT(INT_IO_LATCH_FIFO_OVERFLOW));
 792 }
 793
 794 static void it6505_int_mask_disable(struct it6505 *it6505)
 795 {
 796         it6505_write(it6505, INT_MASK_01, 0x00);
 797         it6505_write(it6505, INT_MASK_02, 0x00);
 798         it6505_write(it6505, INT_MASK_03, 0x00);
 799 }
 800
 801 static void it6505_lane_termination_on(struct it6505 *it6505)
 802 {
 803         int regcf;
 804
 805         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 806
 807         if (regcf == MISC_VERB)
 808                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x00);
 809
 810         if (regcf == MISC_VERC) {
 811                 if (it6505->lane_swap) {
 812                         switch (it6505->lane_count) {
 813                         case 1:
 814                         case 2:
 815                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 816                                                 0x0C, 0x08);
 817                                 break;
 818                         default:
 819                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 820                                                 0x0C, 0x0C);
 821                                 break;
 822                         }
 823                 } else {
 824                         switch (it6505->lane_count) {
 825                         case 1:
 826                         case 2:
 827                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 828                                                 0x0C, 0x04);
 829                                 break;
 830                         default:
 831                                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL,
 832                                                 0x0C, 0x0C);
 833                                 break;
 834                         }
 835                 }
 836         }
 837 }
 838
 839 static void it6505_lane_termination_off(struct it6505 *it6505)
 840 {
 841         int regcf;
 842
 843         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 844
 845         if (regcf == MISC_VERB)
 846                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 847
 848         if (regcf == MISC_VERC)
 849                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x0C, 0x00);
 850 }
 851
 852 static void it6505_lane_power_on(struct it6505 *it6505)
 853 {
 854         it6505_set_bits(it6505, REG_LINK_DRV, 0xF1,
 855                         (it6505->lane_swap ?
 856                                  GENMASK(7, 8 - it6505->lane_count) :
 857                                  GENMASK(3 + it6505->lane_count, 4)) |
 858                                 0x01);
 859 }
 860
 861 static void it6505_lane_power_off(struct it6505 *it6505)
 862 {
 863         it6505_set_bits(it6505, REG_LINK_DRV, 0xF0, 0x00);
 864 }
 865
 866 static void it6505_lane_off(struct it6505 *it6505)
 867 {
 868         it6505_lane_power_off(it6505);
 869         it6505_lane_termination_off(it6505);
 870 }
 871
 872 static void it6505_aux_termination_on(struct it6505 *it6505)
 873 {
 874         int regcf;
 875
 876         regcf = it6505_read(it6505, REG_USER_DRV_PRE);
 877
 878         if (regcf == MISC_VERB)
 879                 it6505_lane_termination_on(it6505);
 880
 881         if (regcf == MISC_VERC)
 882                 it6505_set_bits(it6505, REG_DRV_LN_DATA_SEL, 0x80, 0x80);
 883 }
 884
 885 static void it6505_aux_power_on(struct it6505 *it6505)
 886 {
 887         it6505_set_bits(it6505, REG_AUX, 0x02, 0x02);
 888 }
 889
 890 static void it6505_aux_on(struct it6505 *it6505)
 891 {
 892         it6505_aux_power_on(it6505);
 893         it6505_aux_termination_on(it6505);
 894 }
 895
 896 static void it6505_aux_reset(struct it6505 *it6505)
 897 {
 898         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, AUX_RESET);
 899         it6505_set_bits(it6505, REG_RESET_CTRL, AUX_RESET, 0x00);
 900 }
 901
 902 static void it6505_reset_logic(struct it6505 *it6505)
 903 {
 904         regmap_write(it6505->regmap, REG_RESET_CTRL, ALL_LOGIC_RESET);
 905         usleep_range(1000, 1500);
 906 }
 907
 908 static bool it6505_aux_op_finished(struct it6505 *it6505)
 909 {
 910         int reg2b = it6505_read(it6505, REG_AUX_CMD_REQ);
 911
 912         if (reg2b < 0)
 913                 return false;
 914
 915         return (reg2b & AUX_BUSY) == 0;
 916 }
 917
 918 static int it6505_aux_wait(struct it6505 *it6505)
 919 {
 920         int status;
 921         unsigned long timeout;
 922         struct device *dev = &it6505->client->dev;
 923
 924         timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
 925
 926         while (!it6505_aux_op_finished(it6505)) {
 927                 if (time_after(jiffies, timeout)) {
 928                         dev_err(dev, "Timed out waiting AUX to finish");
 929                         return -ETIMEDOUT;
 930                 }
 931                 usleep_range(1000, 2000);
 932         }
 933
 934         status = it6505_read(it6505, REG_AUX_ERROR_STS);
 935         if (status < 0) {
 936                 dev_err(dev, "Failed to read AUX channel: %d", status);
 937                 return status;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static ssize_t it6505_aux_operation(struct it6505 *it6505,
 944                                     enum aux_cmd_type cmd,
 945                                     unsigned int address, u8 *buffer,
 946                                     size_t size, enum aux_cmd_reply *reply)
 947 {
 948         int i, ret;
 949         bool aux_write_check = false;
 950
 951         if (!it6505_get_sink_hpd_status(it6505))
 952                 return -EIO;
 953
 954         /* set AUX user mode */
 955         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, AUX_USER_MODE);
 956
 957 aux_op_start:
 958         if (cmd == CMD_AUX_I2C_EDID_READ) {
 959                 /* AUX EDID FIFO has max length of AUX_FIFO_MAX_SIZE bytes. */
 960                 size = min_t(size_t, size, AUX_FIFO_MAX_SIZE);
 961                 /* Enable AUX FIFO read back and clear FIFO */
 962                 it6505_set_bits(it6505, REG_AUX_CTRL,
 963                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 964                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
 965
 966                 it6505_set_bits(it6505, REG_AUX_CTRL,
 967                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
 968                                 AUX_EN_FIFO_READ);
 969         } else {
 970                 /* The DP AUX transmit buffer has 4 bytes. */
 971                 size = min_t(size_t, size, 4);
 972                 it6505_set_bits(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR,
 973                                 AUX_NO_SEGMENT_WR);
 974         }
 975
 976         /* Start Address[7:0] */
 977         it6505_write(it6505, REG_AUX_ADR_0_7, (address >> 0) & 0xFF);
 978         /* Start Address[15:8] */
 979         it6505_write(it6505, REG_AUX_ADR_8_15, (address >> 8) & 0xFF);
 980         /* WriteNum[3:0]+StartAdr[19:16] */
 981         it6505_write(it6505, REG_AUX_ADR_16_19,
 982                      ((address >> 16) & 0x0F) | ((size - 1) << 4));
 983
 984         if (cmd == CMD_AUX_NATIVE_WRITE)
 985                 regmap_bulk_write(it6505->regmap, REG_AUX_OUT_DATA0, buffer,
 986                                   size);
 987
 988         /* Aux Fire */
 989         it6505_write(it6505, REG_AUX_CMD_REQ, cmd);
 990
 991         ret = it6505_aux_wait(it6505);
 992         if (ret < 0)
 993                 goto aux_op_err;
 994
 995         ret = it6505_read(it6505, REG_AUX_ERROR_STS);
 996         if (ret < 0)
 997                 goto aux_op_err;
 998
 999         switch ((ret >> 6) & 0x3) {
1000         case 0:
1001                 *reply = REPLY_ACK;
1002                 break;
1003         case 1:
1004                 *reply = REPLY_DEFER;
1005                 ret = -EAGAIN;
1006                 goto aux_op_err;
1007         case 2:
1008                 *reply = REPLY_NACK;
1009                 ret = -EIO;
1010                 goto aux_op_err;
1011         case 3:
1012                 ret = -ETIMEDOUT;
1013                 goto aux_op_err;
1014         }
1015
1016         /* Read back Native Write data */
1017         if (cmd == CMD_AUX_NATIVE_WRITE) {
1018                 aux_write_check = true;
1019                 cmd = CMD_AUX_NATIVE_READ;
1020                 goto aux_op_start;
1021         }
1022
1023         if (cmd == CMD_AUX_I2C_EDID_READ) {
1024                 for (i = 0; i < size; i++) {
1025                         ret = it6505_read(it6505, REG_AUX_DATA_FIFO);
1026                         if (ret < 0)
1027                                 goto aux_op_err;
1028                         buffer[i] = ret;
1029                 }
1030         } else {
1031                 for (i = 0; i < size; i++) {
1032                         ret = it6505_read(it6505, REG_AUX_DATA_0_7 + i);
1033                         if (ret < 0)
1034                                 goto aux_op_err;
1035
1036                         if (aux_write_check && buffer[size - 1 - i] != ret) {
1037                                 ret = -EINVAL;
1038                                 goto aux_op_err;
1039                         }
1040
1041                         buffer[size - 1 - i] = ret;
1042                 }
1043         }
1044
1045         ret = i;
1046
1047 aux_op_err:
1048         if (cmd == CMD_AUX_I2C_EDID_READ) {
1049                 /* clear AUX FIFO */
1050                 it6505_set_bits(it6505, REG_AUX_CTRL,
1051                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO,
1052                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO);
1053                 it6505_set_bits(it6505, REG_AUX_CTRL,
1054                                 AUX_EN_FIFO_READ | CLR_EDID_FIFO, 0x00);
1055         }
1056
1057         /* Leave AUX user mode */
1058         it6505_set_bits(it6505, REG_AUX_CTRL, AUX_USER_MODE, 0);
1059
1060         return ret;
1061 }
1062
1063 static ssize_t it6505_aux_do_transfer(struct it6505 *it6505,
1064                                       enum aux_cmd_type cmd,
1065                                       unsigned int address, u8 *buffer,
1066                                       size_t size, enum aux_cmd_reply *reply)
1067 {
1068         int i, ret_size, ret = 0, request_size;
1069
1070         mutex_lock(&it6505->aux_lock);
1071         for (i = 0; i < size; i += 4) {
1072                 request_size = min((int)size - i, 4);
1073                 ret_size = it6505_aux_operation(it6505, cmd, address + i,
1074                                                 buffer + i, request_size,
1075                                                 reply);
1076                 if (ret_size < 0) {
1077                         ret = ret_size;
1078                         goto aux_op_err;
1079                 }
1080
1081                 ret += ret_size;
1082         }
1083
1084 aux_op_err:
1085         mutex_unlock(&it6505->aux_lock);
1086         return ret;
1087 }
1088
1089 static ssize_t it6505_aux_transfer(struct drm_dp_aux *aux,
1090                                    struct drm_dp_aux_msg *msg)
1091 {
1092         struct it6505 *it6505 = container_of(aux, struct it6505, aux);
1093         u8 cmd;
1094         bool is_i2c = !(msg->request & DP_AUX_NATIVE_WRITE);
1095         int ret;
1096         enum aux_cmd_reply reply;
1097
1098         /* IT6505 doesn't support arbitrary I2C read / write. */
1099         if (is_i2c)
1100                 return -EINVAL;
1101
1102         switch (msg->request) {
1103         case DP_AUX_NATIVE_READ:
1104                 cmd = CMD_AUX_NATIVE_READ;
1105                 break;
1106         case DP_AUX_NATIVE_WRITE:
1107                 cmd = CMD_AUX_NATIVE_WRITE;
1108                 break;
1109         default:
1110                 return -EINVAL;
1111         }
1112
1113         ret = it6505_aux_do_transfer(it6505, cmd, msg->address, msg->buffer,
1114                                      msg->size, &reply);
1115         if (ret < 0)
1116                 return ret;
1117
1118         switch (reply) {
1119         case REPLY_ACK:
1120                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
1121                 break;
1122         case REPLY_NACK:
1123                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
1124                 break;
1125         case REPLY_DEFER:
1126                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
1127                 break;
1128         }
1129
1130         return ret;
1131 }
1132
1133 static int it6505_get_edid_block(void *data, u8 *buf, unsigned int block,
1134                                  size_t len)
1135 {
1136         struct it6505 *it6505 = data;
1137         struct device *dev = &it6505->client->dev;
1138         enum aux_cmd_reply reply;
1139         int offset, ret, aux_retry = 100;
1140
1141         it6505_aux_reset(it6505);
1142         DRM_DEV_DEBUG_DRIVER(dev, "block number = %d", block);
1143
1144         for (offset = 0; offset < EDID_LENGTH;) {
1145                 ret = it6505_aux_do_transfer(it6505, CMD_AUX_I2C_EDID_READ,
1146                                              block * EDID_LENGTH + offset,
1147                                              buf + offset, 8, &reply);
1148
1149                 if (ret < 0 && ret != -EAGAIN)
1150                         return ret;
1151
1152                 switch (reply) {
1153                 case REPLY_ACK:
1154                         DRM_DEV_DEBUG_DRIVER(dev, "[0x%02x]: %8ph", offset,
1155                                              buf + offset);
1156                         offset += 8;
1157                         aux_retry = 100;
1158                         break;
1159                 case REPLY_NACK:
1160                         return -EIO;
1161                 case REPLY_DEFER:
1162                         msleep(20);
1163                         if (!(--aux_retry))
1164                                 return -EIO;
1165                 }
1166         }
1167
1168         return 0;
1169 }
1170
1171 static void it6505_variable_config(struct it6505 *it6505)
1172 {
1173         it6505->link_rate_bw_code = HBR;
1174         it6505->lane_count = MAX_LANE_COUNT;
1175         it6505->link_state = LINK_IDLE;
1176         it6505->hdcp_desired = HDCP_DESIRED;
1177         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
1178         it6505->audio.select = AUDIO_SELECT;
1179         it6505->audio.sample_rate = AUDIO_SAMPLE_RATE;
1180         it6505->audio.channel_count = AUDIO_CHANNEL_COUNT;
1181         it6505->audio.type = AUDIO_TYPE;
1182         it6505->audio.i2s_input_format = I2S_INPUT_FORMAT;
1183         it6505->audio.i2s_justified = I2S_JUSTIFIED;
1184         it6505->audio.i2s_data_delay = I2S_DATA_DELAY;
1185         it6505->audio.i2s_ws_channel = I2S_WS_CHANNEL;
1186         it6505->audio.i2s_data_sequence = I2S_DATA_SEQUENCE;
1187         it6505->audio.word_length = AUDIO_WORD_LENGTH;
1188         memset(it6505->sha1_input, 0, sizeof(it6505->sha1_input));
1189         memset(it6505->bksvs, 0, sizeof(it6505->bksvs));
1190 }
1191
1192 static int it6505_send_video_infoframe(struct it6505 *it6505,
1193                                        struct hdmi_avi_infoframe *frame)
1194 {
1195         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1196         int err;
1197         struct device *dev = &it6505->client->dev;
1198
1199         err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
1200         if (err < 0) {
1201                 dev_err(dev, "Failed to pack AVI infoframe: %d", err);
1202                 return err;
1203         }
1204
1205         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT, 0x00);
1206         if (err)
1207                 return err;
1208
1209         err = regmap_bulk_write(it6505->regmap, REG_AVI_INFO_DB1,
1210                                 buffer + HDMI_INFOFRAME_HEADER_SIZE,
1211                                 frame->length);
1212         if (err)
1213                 return err;
1214
1215         err = it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AVI_PKT,
1216                               EN_AVI_PKT);
1217         if (err)
1218                 return err;
1219
1220         return 0;
1221 }
1222
1223 static void it6505_get_extcon_property(struct it6505 *it6505)
1224 {
1225         int err;
1226         union extcon_property_value property;
1227         struct device *dev = &it6505->client->dev;
1228
1229         if (it6505->extcon && !it6505->lane_swap_disabled) {
1230                 err = extcon_get_property(it6505->extcon, EXTCON_DISP_DP,
1231                                           EXTCON_PROP_USB_TYPEC_POLARITY,
1232                                           &property);
1233                 if (err) {
1234                         dev_err(dev, "get property fail!");
1235                         return;
1236                 }
1237                 it6505->lane_swap = property.intval;
1238         }
1239 }
1240
1241 static void it6505_clk_phase_adjustment(struct it6505 *it6505,
1242                                         const struct drm_display_mode *mode)
1243 {
1244         int clock = mode->clock;
1245
1246         it6505_set_bits(it6505, REG_CLK_CTRL0, M_PCLK_DELAY,
1247                         clock < ADJUST_PHASE_THRESHOLD ? PIXEL_CLK_DELAY : 0);
1248         it6505_set_bits(it6505, REG_DATA_CTRL0, VIDEO_LATCH_EDGE,
1249                         PIXEL_CLK_INVERSE << 4);
1250 }
1251
1252 static void it6505_link_reset_step_train(struct it6505 *it6505)
1253 {
1254         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1255                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1256         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1257                           DP_TRAINING_PATTERN_DISABLE);
1258 }
1259
1260 static void it6505_init(struct it6505 *it6505)
1261 {
1262         it6505_write(it6505, REG_AUX_OPT, AUX_AUTO_RST | AUX_FIX_FREQ);
1263         it6505_write(it6505, REG_AUX_CTRL, AUX_NO_SEGMENT_WR);
1264         it6505_write(it6505, REG_HDCP_CTRL2, HDCP_AN_SEL | HDCP_HW_HPDIRQ_ACT);
1265         it6505_write(it6505, REG_VID_BUS_CTRL0, IN_DDR | DDR_CD);
1266         it6505_write(it6505, REG_VID_BUS_CTRL1, 0x01);
1267         it6505_write(it6505, REG_AUDIO_CTRL0, AUDIO_16B_BOUND);
1268
1269         /* chip internal setting, don't modify */
1270         it6505_write(it6505, REG_HPD_IRQ_TIME, 0xF5);
1271         it6505_write(it6505, REG_AUX_DEBUG_MODE, 0x4D);
1272         it6505_write(it6505, REG_AUX_OPT2, 0x17);
1273         it6505_write(it6505, REG_HDCP_OPT, 0x60);
1274         it6505_write(it6505, REG_DATA_MUTE_CTRL,
1275                      EN_VID_MUTE | EN_AUD_MUTE | ENABLE_AUTO_VIDEO_FIFO_RESET);
1276         it6505_write(it6505, REG_TIME_STMP_CTRL,
1277                      EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP);
1278         it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00);
1279         it6505_write(it6505, REG_BANK_SEL, 0x01);
1280         it6505_write(it6505, REG_DRV_0_DB_800_MV,
1281                      afe_setting_table[it6505->afe_setting][0]);
1282         it6505_write(it6505, REG_PRE_0_DB_800_MV,
1283                      afe_setting_table[it6505->afe_setting][1]);
1284         it6505_write(it6505, REG_PRE_3P5_DB_800_MV,
1285                      afe_setting_table[it6505->afe_setting][2]);
1286         it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1287         it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1288         it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1289         it6505_write(it6505, REG_BANK_SEL, 0x00);
1290 }
1291
1292 static void it6505_video_disable(struct it6505 *it6505)
1293 {
1294         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1295         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1296         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1297 }
1298
1299 static void it6505_video_reset(struct it6505 *it6505)
1300 {
1301         it6505_link_reset_step_train(it6505);
1302         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE);
1303         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00);
1304         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET);
1305         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO);
1306         it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00);
1307         it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00);
1308 }
1309
1310 static void it6505_update_video_parameter(struct it6505 *it6505,
1311                                           const struct drm_display_mode *mode)
1312 {
1313         it6505_clk_phase_adjustment(it6505, mode);
1314         it6505_video_disable(it6505);
1315 }
1316
1317 static bool it6505_audio_input(struct it6505 *it6505)
1318 {
1319         int reg05, regbe;
1320
1321         reg05 = it6505_read(it6505, REG_RESET_CTRL);
1322         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1323         usleep_range(3000, 4000);
1324         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1325         it6505_write(it6505, REG_RESET_CTRL, reg05);
1326
1327         return regbe != 0xFF;
1328 }
1329
1330 static void it6505_setup_audio_channel_status(struct it6505 *it6505)
1331 {
1332         enum it6505_audio_sample_rate sample_rate = it6505->audio.sample_rate;
1333         u8 audio_word_length_map[] = { 0x02, 0x04, 0x03, 0x0B };
1334
1335         /* Channel Status */
1336         it6505_write(it6505, REG_IEC958_STS0, it6505->audio.type << 1);
1337         it6505_write(it6505, REG_IEC958_STS1, 0x00);
1338         it6505_write(it6505, REG_IEC958_STS2, 0x00);
1339         it6505_write(it6505, REG_IEC958_STS3, sample_rate);
1340         it6505_write(it6505, REG_IEC958_STS4, (~sample_rate << 4) |
1341                      audio_word_length_map[it6505->audio.word_length]);
1342 }
1343
1344 static void it6505_setup_audio_format(struct it6505 *it6505)
1345 {
1346         /* I2S MODE */
1347         it6505_write(it6505, REG_AUDIO_FMT,
1348                      (it6505->audio.word_length << 5) |
1349                      (it6505->audio.i2s_data_sequence << 4) |
1350                      (it6505->audio.i2s_ws_channel << 3) |
1351                      (it6505->audio.i2s_data_delay << 2) |
1352                      (it6505->audio.i2s_justified << 1) |
1353                      it6505->audio.i2s_input_format);
1354         if (it6505->audio.select == SPDIF) {
1355                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0x00);
1356                 /* 0x30 = 128*FS */
1357                 it6505_set_bits(it6505, REG_AUX_OPT, 0xF0, 0x30);
1358         } else {
1359                 it6505_write(it6505, REG_AUDIO_FIFO_SEL, 0xE4);
1360         }
1361
1362         it6505_write(it6505, REG_AUDIO_CTRL0, 0x20);
1363         it6505_write(it6505, REG_AUDIO_CTRL1, 0x00);
1364 }
1365
1366 static void it6505_enable_audio_source(struct it6505 *it6505)
1367 {
1368         unsigned int audio_source_count;
1369
1370         audio_source_count = BIT(DIV_ROUND_UP(it6505->audio.channel_count, 2))
1371                                  - 1;
1372
1373         audio_source_count |= it6505->audio.select << 4;
1374
1375         it6505_write(it6505, REG_AUDIO_SRC_CTRL, audio_source_count);
1376 }
1377
1378 static void it6505_enable_audio_infoframe(struct it6505 *it6505)
1379 {
1380         struct device *dev = &it6505->client->dev;
1381         u8 audio_info_ca[] = { 0x00, 0x00, 0x01, 0x03, 0x07, 0x0B, 0x0F, 0x1F };
1382
1383         DRM_DEV_DEBUG_DRIVER(dev, "infoframe channel_allocation:0x%02x",
1384                              audio_info_ca[it6505->audio.channel_count - 1]);
1385
1386         it6505_write(it6505, REG_AUD_INFOFRAM_DB1, it6505->audio.channel_count
1387                      - 1);
1388         it6505_write(it6505, REG_AUD_INFOFRAM_DB2, 0x00);
1389         it6505_write(it6505, REG_AUD_INFOFRAM_DB3,
1390                      audio_info_ca[it6505->audio.channel_count - 1]);
1391         it6505_write(it6505, REG_AUD_INFOFRAM_DB4, 0x00);
1392         it6505_write(it6505, REG_AUD_INFOFRAM_SUM, 0x00);
1393
1394         /* Enable Audio InfoFrame */
1395         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT,
1396                         EN_AUD_CTRL_PKT);
1397 }
1398
1399 static void it6505_disable_audio(struct it6505 *it6505)
1400 {
1401         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, EN_AUD_MUTE);
1402         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, M_AUDIO_I2S_EN, 0x00);
1403         it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_AUD_CTRL_PKT, 0x00);
1404         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, AUDIO_RESET);
1405 }
1406
1407 static void it6505_enable_audio(struct it6505 *it6505)
1408 {
1409         struct device *dev = &it6505->client->dev;
1410         int regbe;
1411
1412         DRM_DEV_DEBUG_DRIVER(dev, "start");
1413         it6505_disable_audio(it6505);
1414
1415         it6505_setup_audio_channel_status(it6505);
1416         it6505_setup_audio_format(it6505);
1417         it6505_enable_audio_source(it6505);
1418         it6505_enable_audio_infoframe(it6505);
1419
1420         it6505_write(it6505, REG_AUDIO_N_0_7, 0x00);
1421         it6505_write(it6505, REG_AUDIO_N_8_15, 0x80);
1422         it6505_write(it6505, REG_AUDIO_N_16_23, 0x00);
1423
1424         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET,
1425                         AUDIO_FIFO_RESET);
1426         it6505_set_bits(it6505, REG_AUDIO_SRC_CTRL, AUDIO_FIFO_RESET, 0x00);
1427         it6505_set_bits(it6505, REG_RESET_CTRL, AUDIO_RESET, 0x00);
1428         regbe = it6505_read(it6505, REG_AUDIO_INPUT_FREQ);
1429         DRM_DEV_DEBUG_DRIVER(dev, "regbe:0x%02x audio input fs: %d.%d kHz",
1430                              regbe, 6750 / regbe, (6750 % regbe) * 10 / regbe);
1431         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_AUD_MUTE, 0x00);
1432 }
1433
1434 static bool it6505_use_step_train_check(struct it6505 *it6505)
1435 {
1436         if (it6505->link.revision >= 0x12)
1437                 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;
1438
1439         return true;
1440 }
1441
1442 static void it6505_parse_link_capabilities(struct it6505 *it6505)
1443 {
1444         struct device *dev = &it6505->client->dev;
1445         struct it6505_drm_dp_link *link = &it6505->link;
1446         int bcaps;
1447
1448         if (it6505->dpcd[0] == 0) {
1449                 it6505_aux_on(it6505);
1450                 it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
1451                                 ARRAY_SIZE(it6505->dpcd));
1452         }
1453
1454         DRM_DEV_DEBUG_DRIVER(dev, "DPCD Rev.: %d.%d",
1455                              link->revision >> 4, link->revision & 0x0F);
1456
1457         DRM_DEV_DEBUG_DRIVER(dev, "Sink max link rate: %d.%02d Gbps per lane",
1458                              link->rate / 100000, link->rate / 1000 % 100);
1459
1460         it6505->link_rate_bw_code = drm_dp_link_rate_to_bw_code(link->rate);
1461         DRM_DEV_DEBUG_DRIVER(dev, "link rate bw code:0x%02x",
1462                              it6505->link_rate_bw_code);
1463         it6505->link_rate_bw_code = min_t(int, it6505->link_rate_bw_code,
1464                                           MAX_LINK_RATE);
1465
1466         it6505->lane_count = link->num_lanes;
1467         DRM_DEV_DEBUG_DRIVER(dev, "Sink support %d lanes training",
1468                              it6505->lane_count);
1469         it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT);
1470
1471         it6505->branch_device = drm_dp_is_branch(it6505->dpcd);
1472         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sbranch device",
1473                              it6505->branch_device ? "" : "Not ");
1474
1475         it6505->enable_enhanced_frame = link->capabilities;
1476         DRM_DEV_DEBUG_DRIVER(dev, "Sink %sSupport Enhanced Framing",
1477                              it6505->enable_enhanced_frame ? "" : "Not ");
1478
1479         it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &
1480                                 DP_MAX_DOWNSPREAD_0_5);
1481         DRM_DEV_DEBUG_DRIVER(dev, "Maximum Down-Spread: %s, %ssupport SSC!",
1482                              it6505->enable_ssc ? "0.5" : "0",
1483                              it6505->enable_ssc ? "" : "Not ");
1484
1485         it6505->step_train = it6505_use_step_train_check(it6505);
1486         if (it6505->step_train)
1487                 DRM_DEV_DEBUG_DRIVER(dev, "auto train fail, will step train");
1488
1489         bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1490         DRM_DEV_DEBUG_DRIVER(dev, "bcaps:0x%02x", bcaps);
1491         if (bcaps & DP_BCAPS_HDCP_CAPABLE) {
1492                 it6505->is_repeater = (bcaps & DP_BCAPS_REPEATER_PRESENT);
1493                 DRM_DEV_DEBUG_DRIVER(dev, "Support HDCP! Downstream is %s!",
1494                                      it6505->is_repeater ? "repeater" :
1495                                      "receiver");
1496         } else {
1497                 DRM_DEV_DEBUG_DRIVER(dev, "Sink not support HDCP!");
1498                 it6505->hdcp_desired = false;
1499         }
1500         DRM_DEV_DEBUG_DRIVER(dev, "HDCP %s",
1501                              it6505->hdcp_desired ? "desired" : "undesired");
1502 }
1503
1504 static void it6505_setup_ssc(struct it6505 *it6505)
1505 {
1506         it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5,
1507                         it6505->enable_ssc ? SPREAD_AMP_5 : 0x00);
1508         if (it6505->enable_ssc) {
1509                 it6505_write(it6505, REG_BANK_SEL, 0x01);
1510                 it6505_write(it6505, REG_SSC_CTRL0, 0x9E);
1511                 it6505_write(it6505, REG_SSC_CTRL1, 0x1C);
1512                 it6505_write(it6505, REG_SSC_CTRL2, 0x42);
1513                 it6505_write(it6505, REG_BANK_SEL, 0x00);
1514                 it6505_write(it6505, REG_SP_CTRL0, 0x07);
1515                 it6505_write(it6505, REG_IP_CTRL1, 0x29);
1516                 it6505_write(it6505, REG_IP_CTRL2, 0x03);
1517                 /* Stamp Interrupt Step */
1518                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1519                                 0x10);
1520                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1521                                   DP_SPREAD_AMP_0_5);
1522         } else {
1523                 it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL, 0x00);
1524                 it6505_set_bits(it6505, REG_TIME_STMP_CTRL, M_STAMP_STEP,
1525                                 0x00);
1526         }
1527 }
1528
1529 static inline void it6505_link_rate_setup(struct it6505 *it6505)
1530 {
1531         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_LBR,
1532                         (it6505->link_rate_bw_code == RBR) ? FORCE_LBR : 0x00);
1533         it6505_set_bits(it6505, REG_LINK_DRV, DRV_HS,
1534                         (it6505->link_rate_bw_code == RBR) ? 0x00 : DRV_HS);
1535 }
1536
1537 static void it6505_lane_count_setup(struct it6505 *it6505)
1538 {
1539         it6505_get_extcon_property(it6505);
1540         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_SWAP,
1541                         it6505->lane_swap ? LANE_SWAP : 0x00);
1542         it6505_set_bits(it6505, REG_TRAIN_CTRL0, LANE_COUNT_MASK,
1543                         (it6505->lane_count - 1) << 1);
1544 }
1545
1546 static void it6505_link_training_setup(struct it6505 *it6505)
1547 {
1548         struct device *dev = &it6505->client->dev;
1549
1550         if (it6505->enable_enhanced_frame)
1551                 it6505_set_bits(it6505, REG_DATA_MUTE_CTRL,
1552                                 ENABLE_ENHANCED_FRAME, ENABLE_ENHANCED_FRAME);
1553
1554         it6505_link_rate_setup(it6505);
1555         it6505_lane_count_setup(it6505);
1556         it6505_setup_ssc(it6505);
1557         DRM_DEV_DEBUG_DRIVER(dev,
1558                              "%s, %d lanes, %sable ssc, %sable enhanced frame",
1559                              it6505->link_rate_bw_code != RBR ? "HBR" : "RBR",
1560                              it6505->lane_count,
1561                              it6505->enable_ssc ? "en" : "dis",
1562                              it6505->enable_enhanced_frame ? "en" : "dis");
1563 }
1564
1565 static bool it6505_link_start_auto_train(struct it6505 *it6505)
1566 {
1567         int timeout = 500, link_training_state;
1568         bool state = false;
1569
1570         mutex_lock(&it6505->aux_lock);
1571         it6505_set_bits(it6505, REG_TRAIN_CTRL0,
1572                         FORCE_CR_DONE | FORCE_EQ_DONE, 0x00);
1573         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
1574         it6505_write(it6505, REG_TRAIN_CTRL1, AUTO_TRAIN);
1575
1576         while (timeout > 0) {
1577                 usleep_range(1000, 2000);
1578                 link_training_state = it6505_read(it6505, REG_LINK_TRAIN_STS);
1579
1580                 if (link_training_state > 0 &&
1581                     (link_training_state & LINK_STATE_NORP)) {
1582                         state = true;
1583                         goto unlock;
1584                 }
1585
1586                 timeout--;
1587         }
1588 unlock:
1589         mutex_unlock(&it6505->aux_lock);
1590
1591         return state;
1592 }
1593
1594 static int it6505_drm_dp_link_configure(struct it6505 *it6505)
1595 {
1596         u8 values[2];
1597         int err;
1598         struct drm_dp_aux *aux = &it6505->aux;
1599
1600         values[0] = it6505->link_rate_bw_code;
1601         values[1] = it6505->lane_count;
1602
1603         if (it6505->enable_enhanced_frame)
1604                 values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1605
1606         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
1607         if (err < 0)
1608                 return err;
1609
1610         return 0;
1611 }
1612
1613 static bool it6505_check_voltage_swing_max(u8 lane_voltage_swing_pre_emphasis)
1614 {
1615         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_CR_LEVEL);
1616 }
1617
1618 static bool it6505_check_pre_emphasis_max(u8 lane_voltage_swing_pre_emphasis)
1619 {
1620         return ((lane_voltage_swing_pre_emphasis & 0x03) == MAX_EQ_LEVEL);
1621 }
1622
1623 static bool it6505_check_max_voltage_swing_reached(u8 *lane_voltage_swing,
1624                                                    u8 lane_count)
1625 {
1626         u8 i;
1627
1628         for (i = 0; i < lane_count; i++) {
1629                 if (lane_voltage_swing[i] & DP_TRAIN_MAX_SWING_REACHED)
1630                         return true;
1631         }
1632
1633         return false;
1634 }
1635
1636 static bool
1637 step_train_lane_voltage_para_set(struct it6505 *it6505,
1638                                  struct it6505_step_train_para
1639                                  *lane_voltage_pre_emphasis,
1640                                  u8 *lane_voltage_pre_emphasis_set)
1641 {
1642         u8 *voltage_swing = lane_voltage_pre_emphasis->voltage_swing;
1643         u8 *pre_emphasis = lane_voltage_pre_emphasis->pre_emphasis;
1644         u8 i;
1645
1646         for (i = 0; i < it6505->lane_count; i++) {
1647                 voltage_swing[i] &= 0x03;
1648                 lane_voltage_pre_emphasis_set[i] = voltage_swing[i];
1649                 if (it6505_check_voltage_swing_max(voltage_swing[i]))
1650                         lane_voltage_pre_emphasis_set[i] |=
1651                                 DP_TRAIN_MAX_SWING_REACHED;
1652
1653                 pre_emphasis[i] &= 0x03;
1654                 lane_voltage_pre_emphasis_set[i] |= pre_emphasis[i]
1655                         << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1656                 if (it6505_check_pre_emphasis_max(pre_emphasis[i]))
1657                         lane_voltage_pre_emphasis_set[i] |=
1658                                 DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1659                 it6505_dpcd_write(it6505, DP_TRAINING_LANE0_SET + i,
1660                                   lane_voltage_pre_emphasis_set[i]);
1661
1662                 if (lane_voltage_pre_emphasis_set[i] !=
1663                     it6505_dpcd_read(it6505, DP_TRAINING_LANE0_SET + i))
1664                         return false;
1665         }
1666
1667         return true;
1668 }
1669
1670 static bool
1671 it6505_step_cr_train(struct it6505 *it6505,
1672                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1673 {
1674         u8 loop_count = 0, i = 0, j;
1675         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
1676         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1677         int pre_emphasis_adjust = -1, voltage_swing_adjust = -1;
1678         const struct drm_dp_aux *aux = &it6505->aux;
1679
1680         it6505_dpcd_write(it6505, DP_DOWNSPREAD_CTRL,
1681                           it6505->enable_ssc ? DP_SPREAD_AMP_0_5 : 0x00);
1682         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1683                           DP_TRAINING_PATTERN_1);
1684
1685         while (loop_count < 5 && i < 10) {
1686                 i++;
1687                 if (!step_train_lane_voltage_para_set(it6505,
1688                                                       lane_voltage_pre_emphasis,
1689                                                       lane_level_config))
1690                         continue;
1691                 drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);
1692                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1693
1694                 if (drm_dp_clock_recovery_ok(link_status, it6505->lane_count)) {
1695                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_CR_DONE,
1696                                         FORCE_CR_DONE);
1697                         return true;
1698                 }
1699                 DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "cr not done");
1700
1701                 if (it6505_check_max_voltage_swing_reached(lane_level_config,
1702                                                            it6505->lane_count))
1703                         goto cr_train_fail;
1704
1705                 for (j = 0; j < it6505->lane_count; j++) {
1706                         lane_voltage_pre_emphasis->voltage_swing[j] =
1707                                 drm_dp_get_adjust_request_voltage(link_status,
1708                                                                   j) >>
1709                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1710                         lane_voltage_pre_emphasis->pre_emphasis[j] =
1711                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1712                                                                j) >>
1713                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1714                         if (voltage_swing_adjust ==
1715                              lane_voltage_pre_emphasis->voltage_swing[j] &&
1716                             pre_emphasis_adjust ==
1717                              lane_voltage_pre_emphasis->pre_emphasis[j]) {
1718                                 loop_count++;
1719                                 continue;
1720                         }
1721
1722                         voltage_swing_adjust =
1723                                 lane_voltage_pre_emphasis->voltage_swing[j];
1724                         pre_emphasis_adjust =
1725                                 lane_voltage_pre_emphasis->pre_emphasis[j];
1726                         loop_count = 0;
1727
1728                         if (voltage_swing_adjust + pre_emphasis_adjust >
1729                             MAX_EQ_LEVEL)
1730                                 lane_voltage_pre_emphasis->voltage_swing[j] =
1731                                         MAX_EQ_LEVEL -
1732                                         lane_voltage_pre_emphasis
1733                                                 ->pre_emphasis[j];
1734                 }
1735         }
1736
1737 cr_train_fail:
1738         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1739                           DP_TRAINING_PATTERN_DISABLE);
1740
1741         return false;
1742 }
1743
1744 static bool
1745 it6505_step_eq_train(struct it6505 *it6505,
1746                      struct it6505_step_train_para *lane_voltage_pre_emphasis)
1747 {
1748         u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };
1749         u8 lane_level_config[MAX_LANE_COUNT] = { 0 };
1750         const struct drm_dp_aux *aux = &it6505->aux;
1751
1752         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1753                           DP_TRAINING_PATTERN_2);
1754
1755         while (loop_count < 6) {
1756                 loop_count++;
1757
1758                 if (!step_train_lane_voltage_para_set(it6505,
1759                                                       lane_voltage_pre_emphasis,
1760                                                       lane_level_config))
1761                         continue;
1762
1763                 drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);
1764                 drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
1765
1766                 if (!drm_dp_clock_recovery_ok(link_status, it6505->lane_count))
1767                         goto eq_train_fail;
1768
1769                 if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
1770                         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1771                                           DP_TRAINING_PATTERN_DISABLE);
1772                         it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
1773                                         FORCE_EQ_DONE);
1774                         return true;
1775                 }
1776                 DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "eq not done");
1777
1778                 for (i = 0; i < it6505->lane_count; i++) {
1779                         lane_voltage_pre_emphasis->voltage_swing[i] =
1780                                 drm_dp_get_adjust_request_voltage(link_status,
1781                                                                   i) >>
1782                                 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1783                         lane_voltage_pre_emphasis->pre_emphasis[i] =
1784                         drm_dp_get_adjust_request_pre_emphasis(link_status,
1785                                                                i) >>
1786                                         DP_TRAIN_PRE_EMPHASIS_SHIFT;
1787
1788                         if (lane_voltage_pre_emphasis->voltage_swing[i] +
1789                                     lane_voltage_pre_emphasis->pre_emphasis[i] >
1790                             MAX_EQ_LEVEL)
1791                                 lane_voltage_pre_emphasis->voltage_swing[i] =
1792                                         0x03 - lane_voltage_pre_emphasis
1793                                                        ->pre_emphasis[i];
1794                 }
1795         }
1796
1797 eq_train_fail:
1798         it6505_dpcd_write(it6505, DP_TRAINING_PATTERN_SET,
1799                           DP_TRAINING_PATTERN_DISABLE);
1800         return false;
1801 }
1802
1803 static bool it6505_link_start_step_train(struct it6505 *it6505)
1804 {
1805         int err;
1806         struct it6505_step_train_para lane_voltage_pre_emphasis = {
1807                 .voltage_swing = { 0 },
1808                 .pre_emphasis = { 0 },
1809         };
1810
1811         DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
1812         err = it6505_drm_dp_link_configure(it6505);
1813
1814         if (err < 0)
1815                 return false;
1816         if (!it6505_step_cr_train(it6505, &lane_voltage_pre_emphasis))
1817                 return false;
1818         if (!it6505_step_eq_train(it6505, &lane_voltage_pre_emphasis))
1819                 return false;
1820         return true;
1821 }
1822
1823 static bool it6505_get_video_status(struct it6505 *it6505)
1824 {
1825         int reg_0d;
1826
1827         reg_0d = it6505_read(it6505, REG_SYSTEM_STS);
1828
1829         if (reg_0d < 0)
1830                 return false;
1831
1832         return reg_0d & VIDEO_STB;
1833 }
1834
1835 static void it6505_reset_hdcp(struct it6505 *it6505)
1836 {
1837         it6505->hdcp_status = HDCP_AUTH_IDLE;
1838         /* Disable CP_Desired */
1839         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1840         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, HDCP_RESET);
1841 }
1842
1843 static void it6505_start_hdcp(struct it6505 *it6505)
1844 {
1845         struct device *dev = &it6505->client->dev;
1846
1847         DRM_DEV_DEBUG_DRIVER(dev, "start");
1848         it6505_reset_hdcp(it6505);
1849         queue_delayed_work(system_wq, &it6505->hdcp_work,
1850                            msecs_to_jiffies(2400));
1851 }
1852
1853 static void it6505_stop_hdcp(struct it6505 *it6505)
1854 {
1855         it6505_reset_hdcp(it6505);
1856         cancel_delayed_work(&it6505->hdcp_work);
1857 }
1858
1859 static bool it6505_hdcp_is_ksv_valid(u8 *ksv)
1860 {
1861         int i, ones = 0;
1862
1863         /* KSV has 20 1's and 20 0's */
1864         for (i = 0; i < DRM_HDCP_KSV_LEN; i++)
1865                 ones += hweight8(ksv[i]);
1866         if (ones != 20)
1867                 return false;
1868         return true;
1869 }
1870
1871 static void it6505_hdcp_part1_auth(struct it6505 *it6505)
1872 {
1873         struct device *dev = &it6505->client->dev;
1874         u8 hdcp_bcaps;
1875
1876         it6505_set_bits(it6505, REG_RESET_CTRL, HDCP_RESET, 0x00);
1877         /* Disable CP_Desired */
1878         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, 0x00);
1879
1880         usleep_range(1000, 1500);
1881         hdcp_bcaps = it6505_dpcd_read(it6505, DP_AUX_HDCP_BCAPS);
1882         DRM_DEV_DEBUG_DRIVER(dev, "DPCD[0x68028]: 0x%02x",
1883                              hdcp_bcaps);
1884
1885         if (!hdcp_bcaps)
1886                 return;
1887
1888         /* clear the repeater List Chk Done and fail bit */
1889         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
1890                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
1891                         0x00);
1892
1893         /* Enable An Generator */
1894         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, HDCP_AN_GEN);
1895         /* delay1ms(10);*/
1896         usleep_range(10000, 15000);
1897         /* Stop An Generator */
1898         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_AN_GEN, 0x00);
1899
1900         it6505_set_bits(it6505, REG_HDCP_CTRL1, HDCP_CP_ENABLE, HDCP_CP_ENABLE);
1901
1902         it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_START,
1903                         HDCP_TRIGGER_START);
1904
1905         it6505->hdcp_status = HDCP_AUTH_GOING;
1906 }
1907
1908 static int it6505_sha1_digest(struct it6505 *it6505, u8 *sha1_input,
1909                               unsigned int size, u8 *output_av)
1910 {
1911         struct shash_desc *desc;
1912         struct crypto_shash *tfm;
1913         int err;
1914         struct device *dev = &it6505->client->dev;
1915
1916         tfm = crypto_alloc_shash("sha1", 0, 0);
1917         if (IS_ERR(tfm)) {
1918                 dev_err(dev, "crypto_alloc_shash sha1 failed");
1919                 return PTR_ERR(tfm);
1920         }
1921         desc = kzalloc(sizeof(*desc) + crypto_shash_descsize(tfm), GFP_KERNEL);
1922         if (!desc) {
1923                 crypto_free_shash(tfm);
1924                 return -ENOMEM;
1925         }
1926
1927         desc->tfm = tfm;
1928         err = crypto_shash_digest(desc, sha1_input, size, output_av);
1929         if (err)
1930                 dev_err(dev, "crypto_shash_digest sha1 failed");
1931
1932         crypto_free_shash(tfm);
1933         kfree(desc);
1934         return err;
1935 }
1936
1937 static int it6505_setup_sha1_input(struct it6505 *it6505, u8 *sha1_input)
1938 {
1939         struct device *dev = &it6505->client->dev;
1940         u8 binfo[2];
1941         int down_stream_count, i, err, msg_count = 0;
1942
1943         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_BINFO, binfo,
1944                               ARRAY_SIZE(binfo));
1945
1946         if (err < 0) {
1947                 dev_err(dev, "Read binfo value Fail");
1948                 return err;
1949         }
1950
1951         down_stream_count = binfo[0] & 0x7F;
1952         DRM_DEV_DEBUG_DRIVER(dev, "binfo:0x%*ph", (int)ARRAY_SIZE(binfo),
1953                              binfo);
1954
1955         if ((binfo[0] & BIT(7)) || (binfo[1] & BIT(3))) {
1956                 dev_err(dev, "HDCP max cascade device exceed");
1957                 return 0;
1958         }
1959
1960         if (!down_stream_count ||
1961             down_stream_count > MAX_HDCP_DOWN_STREAM_COUNT) {
1962                 dev_err(dev, "HDCP down stream count Error %d",
1963                         down_stream_count);
1964                 return 0;
1965         }
1966
1967         for (i = 0; i < down_stream_count; i++) {
1968                 err = it6505_get_dpcd(it6505, DP_AUX_HDCP_KSV_FIFO +
1969                                       (i % 3) * DRM_HDCP_KSV_LEN,
1970                                       sha1_input + msg_count,
1971                                       DRM_HDCP_KSV_LEN);
1972
1973                 if (err < 0)
1974                         return err;
1975
1976                 msg_count += 5;
1977         }
1978
1979         it6505->hdcp_down_stream_count = down_stream_count;
1980         sha1_input[msg_count++] = binfo[0];
1981         sha1_input[msg_count++] = binfo[1];
1982
1983         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ,
1984                         HDCP_EN_M0_READ);
1985
1986         err = regmap_bulk_read(it6505->regmap, REG_M0_0_7,
1987                                sha1_input + msg_count, 8);
1988
1989         it6505_set_bits(it6505, REG_HDCP_CTRL2, HDCP_EN_M0_READ, 0x00);
1990
1991         if (err < 0) {
1992                 dev_err(dev, " Warning, Read M value Fail");
1993                 return err;
1994         }
1995
1996         msg_count += 8;
1997
1998         return msg_count;
1999 }
2000
2001 static bool it6505_hdcp_part2_ksvlist_check(struct it6505 *it6505)
2002 {
2003         struct device *dev = &it6505->client->dev;
2004         u8 av[5][4], bv[5][4];
2005         int i, err;
2006
2007         i = it6505_setup_sha1_input(it6505, it6505->sha1_input);
2008         if (i <= 0) {
2009                 dev_err(dev, "SHA-1 Input length error %d", i);
2010                 return false;
2011         }
2012
2013         it6505_sha1_digest(it6505, it6505->sha1_input, i, (u8 *)av);
2014
2015         err = it6505_get_dpcd(it6505, DP_AUX_HDCP_V_PRIME(0), (u8 *)bv,
2016                               sizeof(bv));
2017
2018         if (err < 0) {
2019                 dev_err(dev, "Read V' value Fail");
2020                 return false;
2021         }
2022
2023         for (i = 0; i < 5; i++)
2024                 if (bv[i][3] != av[i][0] || bv[i][2] != av[i][1] ||
2025                     bv[i][1] != av[i][2] || bv[i][0] != av[i][3])
2026                         return false;
2027
2028         DRM_DEV_DEBUG_DRIVER(dev, "V' all match!!");
2029         return true;
2030 }
2031
2032 static void it6505_hdcp_wait_ksv_list(struct work_struct *work)
2033 {
2034         struct it6505 *it6505 = container_of(work, struct it6505,
2035                                              hdcp_wait_ksv_list);
2036         struct device *dev = &it6505->client->dev;
2037         unsigned int timeout = 5000;
2038         u8 bstatus = 0;
2039         bool ksv_list_check;
2040
2041         timeout /= 20;
2042         while (timeout > 0) {
2043                 if (!it6505_get_sink_hpd_status(it6505))
2044                         return;
2045
2046                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2047
2048                 if (bstatus & DP_BSTATUS_READY)
2049                         break;
2050
2051                 msleep(20);
2052                 timeout--;
2053         }
2054
2055         if (timeout == 0) {
2056                 DRM_DEV_DEBUG_DRIVER(dev, "timeout and ksv list wait failed");
2057                 goto timeout;
2058         }
2059
2060         ksv_list_check = it6505_hdcp_part2_ksvlist_check(it6505);
2061         DRM_DEV_DEBUG_DRIVER(dev, "ksv list ready, ksv list check %s",
2062                              ksv_list_check ? "pass" : "fail");
2063         if (ksv_list_check) {
2064                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2065                                 HDCP_TRIGGER_KSV_DONE, HDCP_TRIGGER_KSV_DONE);
2066                 return;
2067         }
2068 timeout:
2069         it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2070                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL,
2071                         HDCP_TRIGGER_KSV_DONE | HDCP_TRIGGER_KSV_FAIL);
2072 }
2073
2074 static void it6505_hdcp_work(struct work_struct *work)
2075 {
2076         struct it6505 *it6505 = container_of(work, struct it6505,
2077                                              hdcp_work.work);
2078         struct device *dev = &it6505->client->dev;
2079         int ret;
2080         u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };
2081
2082         DRM_DEV_DEBUG_DRIVER(dev, "start");
2083
2084         if (!it6505_get_sink_hpd_status(it6505))
2085                 return;
2086
2087         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2088         DRM_DEV_DEBUG_DRIVER(dev, "ret: %d link_status: %*ph", ret,
2089                              (int)sizeof(link_status), link_status);
2090
2091         if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
2092             !it6505_get_video_status(it6505)) {
2093                 DRM_DEV_DEBUG_DRIVER(dev, "link train not done or no video");
2094                 return;
2095         }
2096
2097         ret = it6505_get_dpcd(it6505, DP_AUX_HDCP_BKSV, it6505->bksvs,
2098                               ARRAY_SIZE(it6505->bksvs));
2099         if (ret < 0) {
2100                 dev_err(dev, "fail to get bksv  ret: %d", ret);
2101                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2102                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2103         }
2104
2105         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2106                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2107
2108         if (!it6505_hdcp_is_ksv_valid(it6505->bksvs)) {
2109                 dev_err(dev, "Display Port bksv not valid");
2110                 it6505_set_bits(it6505, REG_HDCP_TRIGGER,
2111                                 HDCP_TRIGGER_KSV_FAIL, HDCP_TRIGGER_KSV_FAIL);
2112         }
2113
2114         it6505_hdcp_part1_auth(it6505);
2115 }
2116
2117 static void it6505_show_hdcp_info(struct it6505 *it6505)
2118 {
2119         struct device *dev = &it6505->client->dev;
2120         int i;
2121         u8 *sha1 = it6505->sha1_input;
2122
2123         DRM_DEV_DEBUG_DRIVER(dev, "hdcp_status: %d is_repeater: %d",
2124                              it6505->hdcp_status, it6505->is_repeater);
2125         DRM_DEV_DEBUG_DRIVER(dev, "bksv = 0x%*ph",
2126                              (int)ARRAY_SIZE(it6505->bksvs), it6505->bksvs);
2127
2128         if (it6505->is_repeater) {
2129                 DRM_DEV_DEBUG_DRIVER(dev, "hdcp_down_stream_count: %d",
2130                                      it6505->hdcp_down_stream_count);
2131                 DRM_DEV_DEBUG_DRIVER(dev, "sha1_input: 0x%*ph",
2132                                      (int)ARRAY_SIZE(it6505->sha1_input),
2133                                      it6505->sha1_input);
2134                 for (i = 0; i < it6505->hdcp_down_stream_count; i++) {
2135                         DRM_DEV_DEBUG_DRIVER(dev, "KSV_%d = 0x%*ph", i,
2136                                              DRM_HDCP_KSV_LEN, sha1);
2137                         sha1 += DRM_HDCP_KSV_LEN;
2138                 }
2139                 DRM_DEV_DEBUG_DRIVER(dev, "binfo: 0x%2ph M0: 0x%8ph",
2140                                      sha1, sha1 + 2);
2141         }
2142 }
2143
2144 static void it6505_stop_link_train(struct it6505 *it6505)
2145 {
2146         it6505->link_state = LINK_IDLE;
2147         cancel_work_sync(&it6505->link_works);
2148         it6505_write(it6505, REG_TRAIN_CTRL1, FORCE_RETRAIN);
2149 }
2150
2151 static void it6505_link_train_ok(struct it6505 *it6505)
2152 {
2153         struct device *dev = &it6505->client->dev;
2154
2155         it6505->link_state = LINK_OK;
2156         /* disalbe mute enable avi info frame */
2157         it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, 0x00);
2158         it6505_set_bits(it6505, REG_INFOFRAME_CTRL,
2159                         EN_VID_CTRL_PKT, EN_VID_CTRL_PKT);
2160
2161         if (it6505_audio_input(it6505)) {
2162                 DRM_DEV_DEBUG_DRIVER(dev, "Enable audio!");
2163                 it6505_enable_audio(it6505);
2164         }
2165
2166         if (it6505->hdcp_desired)
2167                 it6505_start_hdcp(it6505);
2168 }
2169
2170 static void it6505_link_step_train_process(struct it6505 *it6505)
2171 {
2172         struct device *dev = &it6505->client->dev;
2173         int ret, i, step_retry = 3;
2174
2175         DRM_DEV_DEBUG_DRIVER(dev, "Start step train");
2176
2177         if (it6505->sink_count == 0) {
2178                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d, force eq",
2179                                      it6505->sink_count);
2180                 it6505_set_bits(it6505, REG_TRAIN_CTRL0, FORCE_EQ_DONE,
2181                                 FORCE_EQ_DONE);
2182                 return;
2183         }
2184
2185         if (!it6505->step_train) {
2186                 DRM_DEV_DEBUG_DRIVER(dev, "not support step train");
2187                 return;
2188         }
2189
2190         /* step training start here */
2191         for (i = 0; i < step_retry; i++) {
2192                 it6505_link_reset_step_train(it6505);
2193                 ret = it6505_link_start_step_train(it6505);
2194                 DRM_DEV_DEBUG_DRIVER(dev, "step train %s, retry:%d times",
2195                                      ret ? "pass" : "failed", i + 1);
2196                 if (ret) {
2197                         it6505_link_train_ok(it6505);
2198                         return;
2199                 }
2200         }
2201
2202         DRM_DEV_DEBUG_DRIVER(dev, "training fail");
2203         it6505->link_state = LINK_IDLE;
2204         it6505_video_reset(it6505);
2205 }
2206
2207 static void it6505_link_training_work(struct work_struct *work)
2208 {
2209         struct it6505 *it6505 = container_of(work, struct it6505, link_works);
2210         struct device *dev = &it6505->client->dev;
2211         int ret;
2212
2213         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2214                              it6505->sink_count);
2215
2216         if (!it6505_get_sink_hpd_status(it6505))
2217                 return;
2218
2219         it6505_link_training_setup(it6505);
2220         it6505_reset_hdcp(it6505);
2221         it6505_aux_reset(it6505);
2222
2223         if (it6505->auto_train_retry < 1) {
2224                 it6505_link_step_train_process(it6505);
2225                 return;
2226         }
2227
2228         ret = it6505_link_start_auto_train(it6505);
2229         DRM_DEV_DEBUG_DRIVER(dev, "auto train %s, auto_train_retry: %d",
2230                              ret ? "pass" : "failed", it6505->auto_train_retry);
2231         it6505->auto_train_retry--;
2232
2233         if (ret) {
2234                 it6505_link_train_ok(it6505);
2235                 return;
2236         }
2237
2238         it6505_dump(it6505);
2239 }
2240
2241 static void it6505_plugged_status_to_codec(struct it6505 *it6505)
2242 {
2243         enum drm_connector_status status = it6505->connector_status;
2244
2245         if (it6505->plugged_cb && it6505->codec_dev)
2246                 it6505->plugged_cb(it6505->codec_dev,
2247                                    status == connector_status_connected);
2248 }
2249
2250 static int it6505_process_hpd_irq(struct it6505 *it6505)
2251 {
2252         struct device *dev = &it6505->client->dev;
2253         int ret, dpcd_sink_count, dp_irq_vector, bstatus;
2254         u8 link_status[DP_LINK_STATUS_SIZE];
2255
2256         if (!it6505_get_sink_hpd_status(it6505)) {
2257                 DRM_DEV_DEBUG_DRIVER(dev, "HPD_IRQ HPD low");
2258                 it6505->sink_count = 0;
2259                 return 0;
2260         }
2261
2262         ret = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2263         if (ret < 0)
2264                 return ret;
2265
2266         dpcd_sink_count = DP_GET_SINK_COUNT(ret);
2267         DRM_DEV_DEBUG_DRIVER(dev, "dpcd_sink_count: %d it6505->sink_count:%d",
2268                              dpcd_sink_count, it6505->sink_count);
2269
2270         if (it6505->branch_device && dpcd_sink_count != it6505->sink_count) {
2271                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2272                 it6505->sink_count = dpcd_sink_count;
2273                 it6505_reset_logic(it6505);
2274                 it6505_int_mask_enable(it6505);
2275                 it6505_init(it6505);
2276                 return 0;
2277         }
2278
2279         dp_irq_vector = it6505_dpcd_read(it6505, DP_DEVICE_SERVICE_IRQ_VECTOR);
2280         if (dp_irq_vector < 0)
2281                 return dp_irq_vector;
2282
2283         DRM_DEV_DEBUG_DRIVER(dev, "dp_irq_vector = 0x%02x", dp_irq_vector);
2284
2285         if (dp_irq_vector & DP_CP_IRQ) {
2286                 it6505_set_bits(it6505, REG_HDCP_TRIGGER, HDCP_TRIGGER_CPIRQ,
2287                                 HDCP_TRIGGER_CPIRQ);
2288
2289                 bstatus = it6505_dpcd_read(it6505, DP_AUX_HDCP_BSTATUS);
2290                 if (bstatus < 0)
2291                         return bstatus;
2292
2293                 DRM_DEV_DEBUG_DRIVER(dev, "Bstatus = 0x%02x", bstatus);
2294         }
2295
2296         ret = drm_dp_dpcd_read_link_status(&it6505->aux, link_status);
2297         if (ret < 0) {
2298                 dev_err(dev, "Fail to read link status ret: %d", ret);
2299                 return ret;
2300         }
2301
2302         DRM_DEV_DEBUG_DRIVER(dev, "link status = 0x%*ph",
2303                              (int)ARRAY_SIZE(link_status), link_status);
2304
2305         if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
2306                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2307                 it6505_video_reset(it6505);
2308         }
2309
2310         return 0;
2311 }
2312
2313 static void it6505_irq_hpd(struct it6505 *it6505)
2314 {
2315         struct device *dev = &it6505->client->dev;
2316
2317         it6505->hpd_state = it6505_get_sink_hpd_status(it6505);
2318         DRM_DEV_DEBUG_DRIVER(dev, "hpd change interrupt, change to %s",
2319                              it6505->hpd_state ? "high" : "low");
2320
2321         if (it6505->bridge.dev)
2322                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2323         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count: %d",
2324                              it6505->sink_count);
2325
2326         if (it6505->hpd_state) {
2327                 wait_for_completion_timeout(&it6505->wait_edid_complete,
2328                                             msecs_to_jiffies(6000));
2329                 it6505_lane_termination_on(it6505);
2330                 it6505_lane_power_on(it6505);
2331
2332                 /*
2333                  * for some dongle which issue HPD_irq
2334                  * when sink count change from  0->1
2335                  * it6505 not able to receive HPD_IRQ
2336                  * if HW never go into trainig done
2337                  */
2338
2339                 if (it6505->branch_device && it6505->sink_count == 0)
2340                         schedule_work(&it6505->link_works);
2341
2342                 if (!it6505_get_video_status(it6505))
2343                         it6505_video_reset(it6505);
2344
2345                 it6505_calc_video_info(it6505);
2346         } else {
2347                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2348
2349                 if (it6505->hdcp_desired)
2350                         it6505_stop_hdcp(it6505);
2351
2352                 it6505_video_disable(it6505);
2353                 it6505_disable_audio(it6505);
2354                 it6505_stop_link_train(it6505);
2355                 it6505_lane_off(it6505);
2356                 it6505_link_reset_step_train(it6505);
2357         }
2358 }
2359
2360 static void it6505_irq_hpd_irq(struct it6505 *it6505)
2361 {
2362         struct device *dev = &it6505->client->dev;
2363
2364         DRM_DEV_DEBUG_DRIVER(dev, "hpd_irq interrupt");
2365
2366         if (it6505_process_hpd_irq(it6505) < 0)
2367                 DRM_DEV_DEBUG_DRIVER(dev, "process hpd_irq fail!");
2368 }
2369
2370 static void it6505_irq_scdt(struct it6505 *it6505)
2371 {
2372         struct device *dev = &it6505->client->dev;
2373         bool data;
2374
2375         data = it6505_get_video_status(it6505);
2376         DRM_DEV_DEBUG_DRIVER(dev, "video stable change interrupt, %s",
2377                              data ? "stable" : "unstable");
2378         it6505_calc_video_info(it6505);
2379         it6505_link_reset_step_train(it6505);
2380
2381         if (data)
2382                 schedule_work(&it6505->link_works);
2383 }
2384
2385 static void it6505_irq_hdcp_done(struct it6505 *it6505)
2386 {
2387         struct device *dev = &it6505->client->dev;
2388
2389         DRM_DEV_DEBUG_DRIVER(dev, "hdcp done interrupt");
2390         it6505->hdcp_status = HDCP_AUTH_DONE;
2391         it6505_show_hdcp_info(it6505);
2392 }
2393
2394 static void it6505_irq_hdcp_fail(struct it6505 *it6505)
2395 {
2396         struct device *dev = &it6505->client->dev;
2397
2398         DRM_DEV_DEBUG_DRIVER(dev, "hdcp fail interrupt");
2399         it6505->hdcp_status = HDCP_AUTH_IDLE;
2400         it6505_show_hdcp_info(it6505);
2401         it6505_start_hdcp(it6505);
2402 }
2403
2404 static void it6505_irq_aux_cmd_fail(struct it6505 *it6505)
2405 {
2406         struct device *dev = &it6505->client->dev;
2407
2408         DRM_DEV_DEBUG_DRIVER(dev, "AUX PC Request Fail Interrupt");
2409 }
2410
2411 static void it6505_irq_hdcp_ksv_check(struct it6505 *it6505)
2412 {
2413         struct device *dev = &it6505->client->dev;
2414
2415         DRM_DEV_DEBUG_DRIVER(dev, "HDCP event Interrupt");
2416         schedule_work(&it6505->hdcp_wait_ksv_list);
2417 }
2418
2419 static void it6505_irq_audio_fifo_error(struct it6505 *it6505)
2420 {
2421         struct device *dev = &it6505->client->dev;
2422
2423         DRM_DEV_DEBUG_DRIVER(dev, "audio fifo error Interrupt");
2424
2425         if (it6505_audio_input(it6505))
2426                 it6505_enable_audio(it6505);
2427 }
2428
2429 static void it6505_irq_link_train_fail(struct it6505 *it6505)
2430 {
2431         struct device *dev = &it6505->client->dev;
2432
2433         DRM_DEV_DEBUG_DRIVER(dev, "link training fail interrupt");
2434         schedule_work(&it6505->link_works);
2435 }
2436
2437 static void it6505_irq_video_fifo_error(struct it6505 *it6505)
2438 {
2439         struct device *dev = &it6505->client->dev;
2440
2441         DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt");
2442         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2443         flush_work(&it6505->link_works);
2444         it6505_stop_hdcp(it6505);
2445         it6505_video_reset(it6505);
2446 }
2447
2448 static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505)
2449 {
2450         struct device *dev = &it6505->client->dev;
2451
2452         DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt");
2453         it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2454         flush_work(&it6505->link_works);
2455         it6505_stop_hdcp(it6505);
2456         it6505_video_reset(it6505);
2457 }
2458
2459 static bool it6505_test_bit(unsigned int bit, const unsigned int *addr)
2460 {
2461         return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE));
2462 }
2463
2464 static irqreturn_t it6505_int_threaded_handler(int unused, void *data)
2465 {
2466         struct it6505 *it6505 = data;
2467         struct device *dev = &it6505->client->dev;
2468         static const struct {
2469                 int bit;
2470                 void (*handler)(struct it6505 *it6505);
2471         } irq_vec[] = {
2472                 { BIT_INT_HPD, it6505_irq_hpd },
2473                 { BIT_INT_HPD_IRQ, it6505_irq_hpd_irq },
2474                 { BIT_INT_SCDT, it6505_irq_scdt },
2475                 { BIT_INT_HDCP_FAIL, it6505_irq_hdcp_fail },
2476                 { BIT_INT_HDCP_DONE, it6505_irq_hdcp_done },
2477                 { BIT_INT_AUX_CMD_FAIL, it6505_irq_aux_cmd_fail },
2478                 { BIT_INT_HDCP_KSV_CHECK, it6505_irq_hdcp_ksv_check },
2479                 { BIT_INT_AUDIO_FIFO_ERROR, it6505_irq_audio_fifo_error },
2480                 { BIT_INT_LINK_TRAIN_FAIL, it6505_irq_link_train_fail },
2481                 { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error },
2482                 { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow },
2483         };
2484         int int_status[3], i;
2485
2486         msleep(100);
2487         mutex_lock(&it6505->extcon_lock);
2488
2489         if (it6505->enable_drv_hold || !it6505->powered)
2490                 goto unlock;
2491
2492         int_status[0] = it6505_read(it6505, INT_STATUS_01);
2493         int_status[1] = it6505_read(it6505, INT_STATUS_02);
2494         int_status[2] = it6505_read(it6505, INT_STATUS_03);
2495
2496         it6505_write(it6505, INT_STATUS_01, int_status[0]);
2497         it6505_write(it6505, INT_STATUS_02, int_status[1]);
2498         it6505_write(it6505, INT_STATUS_03, int_status[2]);
2499
2500         DRM_DEV_DEBUG_DRIVER(dev, "reg06 = 0x%02x", int_status[0]);
2501         DRM_DEV_DEBUG_DRIVER(dev, "reg07 = 0x%02x", int_status[1]);
2502         DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]);
2503         it6505_debug_print(it6505, REG_SYSTEM_STS, "");
2504
2505         if (it6505_test_bit(irq_vec[0].bit, (unsigned int *)int_status))
2506                 irq_vec[0].handler(it6505);
2507
2508         if (!it6505->hpd_state)
2509                 goto unlock;
2510
2511         for (i = 1; i < ARRAY_SIZE(irq_vec); i++) {
2512                 if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status))
2513                         irq_vec[i].handler(it6505);
2514         }
2515
2516 unlock:
2517         mutex_unlock(&it6505->extcon_lock);
2518
2519         return IRQ_HANDLED;
2520 }
2521
2522 static int it6505_poweron(struct it6505 *it6505)
2523 {
2524         struct device *dev = &it6505->client->dev;
2525         struct it6505_platform_data *pdata = &it6505->pdata;
2526         int err;
2527
2528         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start powered on");
2529
2530         if (it6505->powered) {
2531                 DRM_DEV_DEBUG_DRIVER(dev, "it6505 already powered on");
2532                 return 0;
2533         }
2534
2535         if (pdata->pwr18) {
2536                 err = regulator_enable(pdata->pwr18);
2537                 if (err) {
2538                         DRM_DEV_DEBUG_DRIVER(dev, "Failed to enable VDD18: %d",
2539                                              err);
2540                         return err;
2541                 }
2542         }
2543
2544         if (pdata->ovdd) {
2545                 /* time interval between IVDD and OVDD at least be 1ms */
2546                 usleep_range(1000, 2000);
2547                 err = regulator_enable(pdata->ovdd);
2548                 if (err) {
2549                         regulator_disable(pdata->pwr18);
2550                         return err;
2551                 }
2552         }
2553         /* time interval between OVDD and SYSRSTN at least be 10ms */
2554         if (pdata->gpiod_reset) {
2555                 usleep_range(10000, 20000);
2556                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2557                 usleep_range(1000, 2000);
2558                 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
2559                 usleep_range(10000, 20000);
2560         }
2561
2562         it6505_reset_logic(it6505);
2563         it6505_int_mask_enable(it6505);
2564         it6505_init(it6505);
2565         it6505_lane_off(it6505);
2566
2567         it6505->powered = true;
2568
2569         return 0;
2570 }
2571
2572 static int it6505_poweroff(struct it6505 *it6505)
2573 {
2574         struct device *dev = &it6505->client->dev;
2575         struct it6505_platform_data *pdata = &it6505->pdata;
2576         int err;
2577
2578         DRM_DEV_DEBUG_DRIVER(dev, "it6505 start power off");
2579
2580         if (!it6505->powered) {
2581                 DRM_DEV_DEBUG_DRIVER(dev, "power had been already off");
2582                 return 0;
2583         }
2584
2585         if (pdata->gpiod_reset)
2586                 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
2587
2588         if (pdata->pwr18) {
2589                 err = regulator_disable(pdata->pwr18);
2590                 if (err)
2591                         return err;
2592         }
2593
2594         if (pdata->ovdd) {
2595                 err = regulator_disable(pdata->ovdd);
2596                 if (err)
2597                         return err;
2598         }
2599
2600         it6505->powered = false;
2601         it6505->sink_count = 0;
2602
2603         return 0;
2604 }
2605
2606 static enum drm_connector_status it6505_detect(struct it6505 *it6505)
2607 {
2608         struct device *dev = &it6505->client->dev;
2609         enum drm_connector_status status = connector_status_disconnected;
2610         int dp_sink_count;
2611
2612         DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d powered:%d",
2613                              it6505->sink_count, it6505->powered);
2614
2615         mutex_lock(&it6505->mode_lock);
2616
2617         if (!it6505->powered)
2618                 goto unlock;
2619
2620         if (it6505->enable_drv_hold) {
2621                 status = it6505_get_sink_hpd_status(it6505) ?
2622                                         connector_status_connected :
2623                                         connector_status_disconnected;
2624                 goto unlock;
2625         }
2626
2627         if (it6505_get_sink_hpd_status(it6505)) {
2628                 it6505_aux_on(it6505);
2629                 it6505_drm_dp_link_probe(&it6505->aux, &it6505->link);
2630                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2631                                              DP_SET_POWER_D0);
2632                 it6505->auto_train_retry = AUTO_TRAIN_RETRY;
2633
2634                 if (it6505->dpcd[0] == 0) {
2635                         it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,
2636                                         ARRAY_SIZE(it6505->dpcd));
2637                         it6505_variable_config(it6505);
2638                         it6505_parse_link_capabilities(it6505);
2639                 }
2640
2641                 dp_sink_count = it6505_dpcd_read(it6505, DP_SINK_COUNT);
2642                 it6505->sink_count = DP_GET_SINK_COUNT(dp_sink_count);
2643                 DRM_DEV_DEBUG_DRIVER(dev, "it6505->sink_count:%d branch:%d",
2644                                      it6505->sink_count, it6505->branch_device);
2645
2646                 if (it6505->branch_device) {
2647                         status = (it6505->sink_count != 0) ?
2648                                  connector_status_connected :
2649                                  connector_status_disconnected;
2650                 } else {
2651                         status = connector_status_connected;
2652                 }
2653         } else {
2654                 it6505->sink_count = 0;
2655                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2656         }
2657
2658 unlock:
2659         if (it6505->connector_status != status) {
2660                 it6505->connector_status = status;
2661                 it6505_plugged_status_to_codec(it6505);
2662         }
2663
2664         mutex_unlock(&it6505->mode_lock);
2665
2666         return status;
2667 }
2668
2669 static int it6505_extcon_notifier(struct notifier_block *self,
2670                                   unsigned long event, void *ptr)
2671 {
2672         struct it6505 *it6505 = container_of(self, struct it6505, event_nb);
2673
2674         schedule_work(&it6505->extcon_wq);
2675         return NOTIFY_DONE;
2676 }
2677
2678 static void it6505_extcon_work(struct work_struct *work)
2679 {
2680         struct it6505 *it6505 = container_of(work, struct it6505, extcon_wq);
2681         struct device *dev = &it6505->client->dev;
2682         int state = extcon_get_state(it6505->extcon, EXTCON_DISP_DP);
2683         unsigned int pwroffretry = 0;
2684
2685         if (it6505->enable_drv_hold)
2686                 return;
2687
2688         mutex_lock(&it6505->extcon_lock);
2689
2690         DRM_DEV_DEBUG_DRIVER(dev, "EXTCON_DISP_DP = 0x%02x", state);
2691         if (state > 0) {
2692                 DRM_DEV_DEBUG_DRIVER(dev, "start to power on");
2693                 msleep(100);
2694                 it6505_poweron(it6505);
2695         } else {
2696                 DRM_DEV_DEBUG_DRIVER(dev, "start to power off");
2697                 while (it6505_poweroff(it6505) && pwroffretry++ < 5) {
2698                         DRM_DEV_DEBUG_DRIVER(dev, "power off fail %d times",
2699                                              pwroffretry);
2700                 }
2701
2702                 drm_helper_hpd_irq_event(it6505->bridge.dev);
2703                 memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
2704                 DRM_DEV_DEBUG_DRIVER(dev, "power off it6505 success!");
2705         }
2706
2707         mutex_unlock(&it6505->extcon_lock);
2708 }
2709
2710 static int it6505_use_notifier_module(struct it6505 *it6505)
2711 {
2712         int ret;
2713         struct device *dev = &it6505->client->dev;
2714
2715         it6505->event_nb.notifier_call = it6505_extcon_notifier;
2716         INIT_WORK(&it6505->extcon_wq, it6505_extcon_work);
2717         ret = devm_extcon_register_notifier(&it6505->client->dev,
2718                                             it6505->extcon, EXTCON_DISP_DP,
2719                                             &it6505->event_nb);
2720         if (ret) {
2721                 dev_err(dev, "failed to register notifier for DP");
2722                 return ret;
2723         }
2724
2725         schedule_work(&it6505->extcon_wq);
2726
2727         return 0;
2728 }
2729
2730 static void it6505_remove_notifier_module(struct it6505 *it6505)
2731 {
2732         if (it6505->extcon) {
2733                 devm_extcon_unregister_notifier(&it6505->client->dev,
2734                                                 it6505->extcon, EXTCON_DISP_DP,
2735                                                 &it6505->event_nb);
2736
2737                 flush_work(&it6505->extcon_wq);
2738         }
2739 }
2740
2741 static void __maybe_unused it6505_delayed_audio(struct work_struct *work)
2742 {
2743         struct it6505 *it6505 = container_of(work, struct it6505,
2744                                              delayed_audio.work);
2745
2746         DRM_DEV_DEBUG_DRIVER(&it6505->client->dev, "start");
2747
2748         if (!it6505->powered)
2749                 return;
2750
2751         if (!it6505->enable_drv_hold)
2752                 it6505_enable_audio(it6505);
2753 }
2754
2755 static int __maybe_unused it6505_audio_setup_hw_params(struct it6505 *it6505,
2756                                                        struct hdmi_codec_params
2757                                                        *params)
2758 {
2759         struct device *dev = &it6505->client->dev;
2760         int i = 0;
2761
2762         DRM_DEV_DEBUG_DRIVER(dev, "%s %d Hz, %d bit, %d channels\n", __func__,
2763                              params->sample_rate, params->sample_width,
2764                              params->cea.channels);
2765
2766         if (!it6505->bridge.encoder)
2767                 return -ENODEV;
2768
2769         if (params->cea.channels <= 1 || params->cea.channels > 8) {
2770                 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support",
2771                                      it6505->audio.channel_count);
2772                 return -EINVAL;
2773         }
2774
2775         it6505->audio.channel_count = params->cea.channels;
2776
2777         while (i < ARRAY_SIZE(audio_sample_rate_map) &&
2778                params->sample_rate !=
2779                        audio_sample_rate_map[i].sample_rate_value) {
2780                 i++;
2781         }
2782         if (i == ARRAY_SIZE(audio_sample_rate_map)) {
2783                 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d Hz not support",
2784                                      params->sample_rate);
2785                 return -EINVAL;
2786         }
2787         it6505->audio.sample_rate = audio_sample_rate_map[i].rate;
2788
2789         switch (params->sample_width) {
2790         case 16:
2791                 it6505->audio.word_length = WORD_LENGTH_16BIT;
2792                 break;
2793         case 18:
2794                 it6505->audio.word_length = WORD_LENGTH_18BIT;
2795                 break;
2796         case 20:
2797                 it6505->audio.word_length = WORD_LENGTH_20BIT;
2798                 break;
2799         case 24:
2800         case 32:
2801                 it6505->audio.word_length = WORD_LENGTH_24BIT;
2802                 break;
2803         default:
2804                 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support",
2805                                      params->sample_width);
2806                 return -EINVAL;
2807         }
2808
2809         return 0;
2810 }
2811
2812 static void __maybe_unused it6505_audio_shutdown(struct device *dev, void *data)
2813 {
2814         struct it6505 *it6505 = dev_get_drvdata(dev);
2815
2816         if (it6505->powered)
2817                 it6505_disable_audio(it6505);
2818 }
2819
2820 static int __maybe_unused it6505_audio_hook_plugged_cb(struct device *dev,
2821                                                        void *data,
2822                                                        hdmi_codec_plugged_cb fn,
2823                                                        struct device *codec_dev)
2824 {
2825         struct it6505 *it6505 = data;
2826
2827         it6505->plugged_cb = fn;
2828         it6505->codec_dev = codec_dev;
2829         it6505_plugged_status_to_codec(it6505);
2830
2831         return 0;
2832 }
2833
2834 static inline struct it6505 *bridge_to_it6505(struct drm_bridge *bridge)
2835 {
2836         return container_of(bridge, struct it6505, bridge);
2837 }
2838
2839 static int it6505_bridge_attach(struct drm_bridge *bridge,
2840                                 enum drm_bridge_attach_flags flags)
2841 {
2842         struct it6505 *it6505 = bridge_to_it6505(bridge);
2843         struct device *dev = &it6505->client->dev;
2844         int ret;
2845
2846         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
2847                 DRM_ERROR("DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied");
2848                 return -EINVAL;
2849         }
2850
2851         if (!bridge->encoder) {
2852                 dev_err(dev, "Parent encoder object not found");
2853                 return -ENODEV;
2854         }
2855
2856         /* Register aux channel */
2857         it6505->aux.name = "DP-AUX";
2858         it6505->aux.dev = dev;
2859         it6505->aux.drm_dev = bridge->dev;
2860         it6505->aux.transfer = it6505_aux_transfer;
2861
2862         ret = drm_dp_aux_register(&it6505->aux);
2863
2864         if (ret < 0) {
2865                 dev_err(dev, "Failed to register aux: %d", ret);
2866                 return ret;
2867         }
2868
2869         if (it6505->extcon) {
2870                 ret = it6505_use_notifier_module(it6505);
2871                 if (ret < 0) {
2872                         dev_err(dev, "use notifier module failed");
2873                         return ret;
2874                 }
2875         }
2876
2877         return 0;
2878 }
2879
2880 static void it6505_bridge_detach(struct drm_bridge *bridge)
2881 {
2882         struct it6505 *it6505 = bridge_to_it6505(bridge);
2883
2884         flush_work(&it6505->link_works);
2885         it6505_remove_notifier_module(it6505);
2886 }
2887
2888 static enum drm_mode_status
2889 it6505_bridge_mode_valid(struct drm_bridge *bridge,
2890                          const struct drm_display_info *info,
2891                          const struct drm_display_mode *mode)
2892 {
2893         struct it6505 *it6505 = bridge_to_it6505(bridge);
2894
2895         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2896                 return MODE_NO_INTERLACE;
2897
2898         if (mode->clock > DPI_PIXEL_CLK_MAX)
2899                 return MODE_CLOCK_HIGH;
2900
2901         it6505->video_info.clock = mode->clock;
2902
2903         return MODE_OK;
2904 }
2905
2906 static void it6505_bridge_atomic_enable(struct drm_bridge *bridge,
2907                                         struct drm_bridge_state *old_state)
2908 {
2909         struct it6505 *it6505 = bridge_to_it6505(bridge);
2910         struct device *dev = &it6505->client->dev;
2911         struct drm_atomic_state *state = old_state->base.state;
2912         struct hdmi_avi_infoframe frame;
2913         struct drm_crtc_state *crtc_state;
2914         struct drm_connector_state *conn_state;
2915         struct drm_display_mode *mode;
2916         struct drm_connector *connector;
2917         int ret;
2918
2919         DRM_DEV_DEBUG_DRIVER(dev, "start");
2920
2921         connector = drm_atomic_get_new_connector_for_encoder(state,
2922                                                              bridge->encoder);
2923
2924         if (WARN_ON(!connector))
2925                 return;
2926
2927         conn_state = drm_atomic_get_new_connector_state(state, connector);
2928
2929         if (WARN_ON(!conn_state))
2930                 return;
2931
2932         crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
2933
2934         if (WARN_ON(!crtc_state))
2935                 return;
2936
2937         mode = &crtc_state->adjusted_mode;
2938
2939         if (WARN_ON(!mode))
2940                 return;
2941
2942         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
2943                                                        connector,
2944                                                        mode);
2945         if (ret)
2946                 dev_err(dev, "Failed to setup AVI infoframe: %d", ret);
2947
2948         it6505_update_video_parameter(it6505, mode);
2949
2950         ret = it6505_send_video_infoframe(it6505, &frame);
2951
2952         if (ret)
2953                 dev_err(dev, "Failed to send AVI infoframe: %d", ret);
2954
2955         it6505_int_mask_enable(it6505);
2956         it6505_video_reset(it6505);
2957 }
2958
2959 static void it6505_bridge_atomic_disable(struct drm_bridge *bridge,
2960                                          struct drm_bridge_state *old_state)
2961 {
2962         struct it6505 *it6505 = bridge_to_it6505(bridge);
2963         struct device *dev = &it6505->client->dev;
2964
2965         DRM_DEV_DEBUG_DRIVER(dev, "start");
2966
2967         if (it6505->powered) {
2968                 it6505_video_disable(it6505);
2969                 it6505_drm_dp_link_set_power(&it6505->aux, &it6505->link,
2970                                              DP_SET_POWER_D3);
2971         }
2972 }
2973
2974 static enum drm_connector_status
2975 it6505_bridge_detect(struct drm_bridge *bridge)
2976 {
2977         struct it6505 *it6505 = bridge_to_it6505(bridge);
2978
2979         return it6505_detect(it6505);
2980 }
2981
2982 static struct edid *it6505_bridge_get_edid(struct drm_bridge *bridge,
2983                                            struct drm_connector *connector)
2984 {
2985         struct it6505 *it6505 = bridge_to_it6505(bridge);
2986         struct device *dev = &it6505->client->dev;
2987         struct edid *edid;
2988
2989         edid = drm_do_get_edid(connector, it6505_get_edid_block, it6505);
2990
2991         if (!edid) {
2992                 DRM_DEV_DEBUG_DRIVER(dev, "failed to get edid!");
2993                 return NULL;
2994         }
2995
2996         return edid;
2997 }
2998
2999 static const struct drm_bridge_funcs it6505_bridge_funcs = {
3000         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
3001         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
3002         .atomic_reset = drm_atomic_helper_bridge_reset,
3003         .attach = it6505_bridge_attach,
3004         .detach = it6505_bridge_detach,
3005         .mode_valid = it6505_bridge_mode_valid,
3006         .atomic_enable = it6505_bridge_atomic_enable,
3007         .atomic_disable = it6505_bridge_atomic_disable,
3008         .detect = it6505_bridge_detect,
3009         .get_edid = it6505_bridge_get_edid,
3010 };
3011
3012 static __maybe_unused int it6505_bridge_resume(struct device *dev)
3013 {
3014         struct it6505 *it6505 = dev_get_drvdata(dev);
3015
3016         return it6505_poweron(it6505);
3017 }
3018
3019 static __maybe_unused int it6505_bridge_suspend(struct device *dev)
3020 {
3021         struct it6505 *it6505 = dev_get_drvdata(dev);
3022
3023         return it6505_poweroff(it6505);
3024 }
3025
3026 static SIMPLE_DEV_PM_OPS(it6505_bridge_pm_ops, it6505_bridge_suspend,
3027                          it6505_bridge_resume);
3028
3029 static int it6505_init_pdata(struct it6505 *it6505)
3030 {
3031         struct it6505_platform_data *pdata = &it6505->pdata;
3032         struct device *dev = &it6505->client->dev;
3033
3034         /* 1.0V digital core power regulator  */
3035         pdata->pwr18 = devm_regulator_get(dev, "pwr18");
3036         if (IS_ERR(pdata->pwr18)) {
3037                 dev_err(dev, "pwr18 regulator not found");
3038                 return PTR_ERR(pdata->pwr18);
3039         }
3040
3041         pdata->ovdd = devm_regulator_get(dev, "ovdd");
3042         if (IS_ERR(pdata->ovdd)) {
3043                 dev_err(dev, "ovdd regulator not found");
3044                 return PTR_ERR(pdata->ovdd);
3045         }
3046
3047         pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
3048         if (IS_ERR(pdata->gpiod_reset)) {
3049                 dev_err(dev, "gpiod_reset gpio not found");
3050                 return PTR_ERR(pdata->gpiod_reset);
3051         }
3052
3053         return 0;
3054 }
3055
3056 static void it6505_parse_dt(struct it6505 *it6505)
3057 {
3058         struct device *dev = &it6505->client->dev;
3059         u32 *afe_setting = &it6505->afe_setting;
3060
3061         it6505->lane_swap_disabled =
3062                 device_property_read_bool(dev, "no-laneswap");
3063
3064         if (it6505->lane_swap_disabled)
3065                 it6505->lane_swap = false;
3066
3067         if (device_property_read_u32(dev, "afe-setting", afe_setting) == 0) {
3068                 if (*afe_setting >= ARRAY_SIZE(afe_setting_table)) {
3069                         dev_err(dev, "afe setting error, use default");
3070                         *afe_setting = 0;
3071                 }
3072         } else {
3073                 *afe_setting = 0;
3074         }
3075         DRM_DEV_DEBUG_DRIVER(dev, "using afe_setting: %d", *afe_setting);
3076 }
3077
3078 static ssize_t receive_timing_debugfs_show(struct file *file, char __user *buf,
3079                                            size_t len, loff_t *ppos)
3080 {
3081         struct it6505 *it6505 = file->private_data;
3082         struct drm_display_mode *vid = &it6505->video_info;
3083         u8 read_buf[READ_BUFFER_SIZE];
3084         u8 *str = read_buf, *end = read_buf + READ_BUFFER_SIZE;
3085         ssize_t ret, count;
3086
3087         if (!it6505)
3088                 return -ENODEV;
3089
3090         it6505_calc_video_info(it6505);
3091         str += scnprintf(str, end - str, "---video timing---\n");
3092         str += scnprintf(str, end - str, "PCLK:%d.%03dMHz\n",
3093                          vid->clock / 1000, vid->clock % 1000);
3094         str += scnprintf(str, end - str, "HTotal:%d\n", vid->htotal);
3095         str += scnprintf(str, end - str, "HActive:%d\n", vid->hdisplay);
3096         str += scnprintf(str, end - str, "HFrontPorch:%d\n",
3097                          vid->hsync_start - vid->hdisplay);
3098         str += scnprintf(str, end - str, "HSyncWidth:%d\n",
3099                          vid->hsync_end - vid->hsync_start);
3100         str += scnprintf(str, end - str, "HBackPorch:%d\n",
3101                          vid->htotal - vid->hsync_end);
3102         str += scnprintf(str, end - str, "VTotal:%d\n", vid->vtotal);
3103         str += scnprintf(str, end - str, "VActive:%d\n", vid->vdisplay);
3104         str += scnprintf(str, end - str, "VFrontPorch:%d\n",
3105                          vid->vsync_start - vid->vdisplay);
3106         str += scnprintf(str, end - str, "VSyncWidth:%d\n",
3107                          vid->vsync_end - vid->vsync_start);
3108         str += scnprintf(str, end - str, "VBackPorch:%d\n",
3109                          vid->vtotal - vid->vsync_end);
3110
3111         count = str - read_buf;
3112         ret = simple_read_from_buffer(buf, len, ppos, read_buf, count);
3113
3114         return ret;
3115 }
3116
3117 static int force_power_on_off_debugfs_write(void *data, u64 value)
3118 {
3119         struct it6505 *it6505 = data;
3120
3121         if (!it6505)
3122                 return -ENODEV;
3123
3124         if (value)
3125                 it6505_poweron(it6505);
3126         else
3127                 it6505_poweroff(it6505);
3128
3129         return 0;
3130 }
3131
3132 static int enable_drv_hold_debugfs_show(void *data, u64 *buf)
3133 {
3134         struct it6505 *it6505 = data;
3135
3136         if (!it6505)
3137                 return -ENODEV;
3138
3139         *buf = it6505->enable_drv_hold;
3140
3141         return 0;
3142 }
3143
3144 static int enable_drv_hold_debugfs_write(void *data, u64 drv_hold)
3145 {
3146         struct it6505 *it6505 = data;
3147
3148         if (!it6505)
3149                 return -ENODEV;
3150
3151         it6505->enable_drv_hold = drv_hold;
3152
3153         if (it6505->enable_drv_hold) {
3154                 it6505_int_mask_disable(it6505);
3155         } else {
3156                 it6505_clear_int(it6505);
3157                 it6505_int_mask_enable(it6505);
3158
3159                 if (it6505->powered) {
3160                         it6505->connector_status =
3161                                         it6505_get_sink_hpd_status(it6505) ?
3162                                         connector_status_connected :
3163                                         connector_status_disconnected;
3164                 } else {
3165                         it6505->connector_status =
3166                                         connector_status_disconnected;
3167                 }
3168         }
3169
3170         return 0;
3171 }
3172
3173 static const struct file_operations receive_timing_fops = {
3174         .owner = THIS_MODULE,
3175         .open = simple_open,
3176         .read = receive_timing_debugfs_show,
3177         .llseek = default_llseek,
3178 };
3179
3180 DEFINE_DEBUGFS_ATTRIBUTE(fops_force_power, NULL,
3181                          force_power_on_off_debugfs_write, "%llu\n");
3182
3183 DEFINE_DEBUGFS_ATTRIBUTE(fops_enable_drv_hold, enable_drv_hold_debugfs_show,
3184                          enable_drv_hold_debugfs_write, "%llu\n");
3185
3186 static const struct debugfs_entries debugfs_entry[] = {
3187         { "receive_timing", &receive_timing_fops },
3188         { "force_power_on_off", &fops_force_power },
3189         { "enable_drv_hold", &fops_enable_drv_hold },
3190         { NULL, NULL },
3191 };
3192
3193 static void debugfs_create_files(struct it6505 *it6505)
3194 {
3195         int i = 0;
3196
3197         while (debugfs_entry[i].name && debugfs_entry[i].fops) {
3198                 debugfs_create_file(debugfs_entry[i].name, 0644,
3199                                     it6505->debugfs, it6505,
3200                                     debugfs_entry[i].fops);
3201                 i++;
3202         }
3203 }
3204
3205 static void debugfs_init(struct it6505 *it6505)
3206 {
3207         struct device *dev = &it6505->client->dev;
3208
3209         it6505->debugfs = debugfs_create_dir(DEBUGFS_DIR_NAME, NULL);
3210
3211         if (IS_ERR(it6505->debugfs)) {
3212                 dev_err(dev, "failed to create debugfs root");
3213                 return;
3214         }
3215
3216         debugfs_create_files(it6505);
3217 }
3218
3219 static void it6505_debugfs_remove(struct it6505 *it6505)
3220 {
3221         debugfs_remove_recursive(it6505->debugfs);
3222 }
3223
3224 static void it6505_shutdown(struct i2c_client *client)
3225 {
3226         struct it6505 *it6505 = dev_get_drvdata(&client->dev);
3227
3228         if (it6505->powered)
3229                 it6505_lane_off(it6505);
3230 }
3231
3232 static int it6505_i2c_probe(struct i2c_client *client,
3233                             const struct i2c_device_id *id)
3234 {
3235         struct it6505 *it6505;
3236         struct device *dev = &client->dev;
3237         struct extcon_dev *extcon;
3238         int err, intp_irq;
3239
3240         it6505 = devm_kzalloc(&client->dev, sizeof(*it6505), GFP_KERNEL);
3241         if (!it6505)
3242                 return -ENOMEM;
3243
3244         mutex_init(&it6505->extcon_lock);
3245         mutex_init(&it6505->mode_lock);
3246         mutex_init(&it6505->aux_lock);
3247
3248         it6505->bridge.of_node = client->dev.of_node;
3249         it6505->connector_status = connector_status_disconnected;
3250         it6505->client = client;
3251         i2c_set_clientdata(client, it6505);
3252
3253         /* get extcon device from DTS */
3254         extcon = extcon_get_edev_by_phandle(dev, 0);
3255         if (PTR_ERR(extcon) == -EPROBE_DEFER)
3256                 return -EPROBE_DEFER;
3257         if (IS_ERR(extcon)) {
3258                 dev_err(dev, "can not get extcon device!");
3259                 return PTR_ERR(extcon);
3260         }
3261
3262         it6505->extcon = extcon;
3263
3264         it6505->regmap = devm_regmap_init_i2c(client, &it6505_regmap_config);
3265         if (IS_ERR(it6505->regmap)) {
3266                 dev_err(dev, "regmap i2c init failed");
3267                 err = PTR_ERR(it6505->regmap);
3268                 return err;
3269         }
3270
3271         err = it6505_init_pdata(it6505);
3272         if (err) {
3273                 dev_err(dev, "Failed to initialize pdata: %d", err);
3274                 return err;
3275         }
3276
3277         it6505_parse_dt(it6505);
3278
3279         intp_irq = client->irq;
3280
3281         if (!intp_irq) {
3282                 dev_err(dev, "Failed to get INTP IRQ");
3283                 err = -ENODEV;
3284                 return err;
3285         }
3286
3287         err = devm_request_threaded_irq(&client->dev, intp_irq, NULL,
3288                                         it6505_int_threaded_handler,
3289                                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
3290                                         "it6505-intp", it6505);
3291         if (err) {
3292                 dev_err(dev, "Failed to request INTP threaded IRQ: %d", err);
3293                 return err;
3294         }
3295
3296         INIT_WORK(&it6505->link_works, it6505_link_training_work);
3297         INIT_WORK(&it6505->hdcp_wait_ksv_list, it6505_hdcp_wait_ksv_list);
3298         INIT_DELAYED_WORK(&it6505->hdcp_work, it6505_hdcp_work);
3299         init_completion(&it6505->wait_edid_complete);
3300         memset(it6505->dpcd, 0, sizeof(it6505->dpcd));
3301         it6505->powered = false;
3302         it6505->enable_drv_hold = DEFAULT_DRV_HOLD;
3303
3304         if (DEFAULT_PWR_ON)
3305                 it6505_poweron(it6505);
3306
3307         DRM_DEV_DEBUG_DRIVER(dev, "it6505 device name: %s", dev_name(dev));
3308         debugfs_init(it6505);
3309
3310         it6505->bridge.funcs = &it6505_bridge_funcs;
3311         it6505->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
3312         it6505->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
3313                              DRM_BRIDGE_OP_HPD;
3314         drm_bridge_add(&it6505->bridge);
3315
3316         return 0;
3317 }
3318
3319 static int it6505_i2c_remove(struct i2c_client *client)
3320 {
3321         struct it6505 *it6505 = i2c_get_clientdata(client);
3322
3323         drm_bridge_remove(&it6505->bridge);
3324         drm_dp_aux_unregister(&it6505->aux);
3325         it6505_debugfs_remove(it6505);
3326         it6505_poweroff(it6505);
3327
3328         return 0;
3329 }
3330
3331 static const struct i2c_device_id it6505_id[] = {
3332         { "it6505", 0 },
3333         { }
3334 };
3335
3336 MODULE_DEVICE_TABLE(i2c, it6505_id);
3337
3338 static const struct of_device_id it6505_of_match[] = {
3339         { .compatible = "ite,it6505" },
3340         { }
3341 };
3342
3343 static struct i2c_driver it6505_i2c_driver = {
3344         .driver = {
3345                 .name = "it6505",
3346                 .of_match_table = it6505_of_match,
3347                 .pm = &it6505_bridge_pm_ops,
3348         },
3349         .probe = it6505_i2c_probe,
3350         .remove = it6505_i2c_remove,
3351         .shutdown = it6505_shutdown,
3352         .id_table = it6505_id,
3353 };
3354
3355 module_i2c_driver(it6505_i2c_driver);
3356
3357 MODULE_AUTHOR("Allen Chen <[email protected]>");
3358 MODULE_DESCRIPTION("IT6505 DisplayPort Transmitter driver");
3359 MODULE_LICENSE("GPL v2");