drivers/gpu/drm/arm/malidp_planes.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <[email protected]>
   5  *
   6  * ARM Mali DP plane manipulation routines.
   7  */
   8
   9 #include <linux/iommu.h>
  10 #include <linux/platform_device.h>
  11
  12 #include <drm/drm_atomic.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_blend.h>
  15 #include <drm/drm_drv.h>
  16 #include <drm/drm_fb_cma_helper.h>
  17 #include <drm/drm_fourcc.h>
  18 #include <drm/drm_framebuffer.h>
  19 #include <drm/drm_gem_cma_helper.h>
  20 #include <drm/drm_gem_framebuffer_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <drm/drm_print.h>
  23
  24 #include "malidp_hw.h"
  25 #include "malidp_drv.h"
  26
  27 /* Layer specific register offsets */
  28 #define MALIDP_LAYER_FORMAT             0x000
  29 #define   LAYER_FORMAT_MASK             0x3f
  30 #define MALIDP_LAYER_CONTROL            0x004
  31 #define   LAYER_ENABLE                  (1 << 0)
  32 #define   LAYER_FLOWCFG_MASK            7
  33 #define   LAYER_FLOWCFG(x)              (((x) & LAYER_FLOWCFG_MASK) << 1)
  34 #define     LAYER_FLOWCFG_SCALE_SE      3
  35 #define   LAYER_ROT_OFFSET              8
  36 #define   LAYER_H_FLIP                  (1 << 10)
  37 #define   LAYER_V_FLIP                  (1 << 11)
  38 #define   LAYER_ROT_MASK                (0xf << 8)
  39 #define   LAYER_COMP_MASK               (0x3 << 12)
  40 #define   LAYER_COMP_PIXEL              (0x3 << 12)
  41 #define   LAYER_COMP_PLANE              (0x2 << 12)
  42 #define   LAYER_PMUL_ENABLE             (0x1 << 14)
  43 #define   LAYER_ALPHA_OFFSET            (16)
  44 #define   LAYER_ALPHA_MASK              (0xff)
  45 #define   LAYER_ALPHA(x)                (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET)
  46 #define MALIDP_LAYER_COMPOSE            0x008
  47 #define MALIDP_LAYER_SIZE               0x00c
  48 #define   LAYER_H_VAL(x)                (((x) & 0x1fff) << 0)
  49 #define   LAYER_V_VAL(x)                (((x) & 0x1fff) << 16)
  50 #define MALIDP_LAYER_COMP_SIZE          0x010
  51 #define MALIDP_LAYER_OFFSET             0x014
  52 #define MALIDP550_LS_ENABLE             0x01c
  53 #define MALIDP550_LS_R1_IN_SIZE         0x020
  54
  55 #define MODIFIERS_COUNT_MAX             15
  56
  57 /*
  58  * This 4-entry look-up-table is used to determine the full 8-bit alpha value
  59  * for formats with 1- or 2-bit alpha channels.
  60  * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
  61  * opacity for 2-bit formats.
  62  */
  63 #define MALIDP_ALPHA_LUT 0xffaa5500
  64
  65 /* page sizes the MMU prefetcher can support */
  66 #define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES     (SZ_4K | SZ_64K)
  67 #define MALIDP_MMU_PREFETCH_FULL_PGSIZES        (SZ_1M | SZ_2M)
  68
  69 /* readahead for partial-frame prefetch */
  70 #define MALIDP_MMU_PREFETCH_READAHEAD           8
  71
  72 static void malidp_de_plane_destroy(struct drm_plane *plane)
  73 {
  74         struct malidp_plane *mp = to_malidp_plane(plane);
  75
  76         drm_plane_cleanup(plane);
  77         kfree(mp);
  78 }
  79
  80 /*
  81  * Replicate what the default ->reset hook does: free the state pointer and
  82  * allocate a new empty object. We just need enough space to store
  83  * a malidp_plane_state instead of a drm_plane_state.
  84  */
  85 static void malidp_plane_reset(struct drm_plane *plane)
  86 {
  87         struct malidp_plane_state *state = to_malidp_plane_state(plane->state);
  88
  89         if (state)
  90                 __drm_atomic_helper_plane_destroy_state(&state->base);
  91         kfree(state);
  92         plane->state = NULL;
  93         state = kzalloc(sizeof(*state), GFP_KERNEL);
  94         if (state)
  95                 __drm_atomic_helper_plane_reset(plane, &state->base);
  96 }
  97
  98 static struct
  99 drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
 100 {
 101         struct malidp_plane_state *state, *m_state;
 102
 103         if (!plane->state)
 104                 return NULL;
 105
 106         state = kmalloc(sizeof(*state), GFP_KERNEL);
 107         if (!state)
 108                 return NULL;
 109
 110         m_state = to_malidp_plane_state(plane->state);
 111         __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
 112         state->rotmem_size = m_state->rotmem_size;
 113         state->format = m_state->format;
 114         state->n_planes = m_state->n_planes;
 115
 116         state->mmu_prefetch_mode = m_state->mmu_prefetch_mode;
 117         state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize;
 118
 119         return &state->base;
 120 }
 121
 122 static void malidp_destroy_plane_state(struct drm_plane *plane,
 123                                        struct drm_plane_state *state)
 124 {
 125         struct malidp_plane_state *m_state = to_malidp_plane_state(state);
 126
 127         __drm_atomic_helper_plane_destroy_state(state);
 128         kfree(m_state);
 129 }
 130
 131 static const char * const prefetch_mode_names[] = {
 132         [MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE",
 133         [MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL",
 134         [MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL",
 135 };
 136
 137 static void malidp_plane_atomic_print_state(struct drm_printer *p,
 138                                             const struct drm_plane_state *state)
 139 {
 140         struct malidp_plane_state *ms = to_malidp_plane_state(state);
 141
 142         drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
 143         drm_printf(p, "\tformat_id=%u\n", ms->format);
 144         drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
 145         drm_printf(p, "\tmmu_prefetch_mode=%s\n",
 146                    prefetch_mode_names[ms->mmu_prefetch_mode]);
 147         drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize);
 148 }
 149
 150 bool malidp_format_mod_supported(struct drm_device *drm,
 151                                  u32 format, u64 modifier)
 152 {
 153         const struct drm_format_info *info;
 154         const u64 *modifiers;
 155         struct malidp_drm *malidp = drm->dev_private;
 156         const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
 157
 158         if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
 159                 return false;
 160
 161         /* Some pixel formats are supported without any modifier */
 162         if (modifier == DRM_FORMAT_MOD_LINEAR) {
 163                 /*
 164                  * However these pixel formats need to be supported with
 165                  * modifiers only
 166                  */
 167                 return !malidp_hw_format_is_afbc_only(format);
 168         }
 169
 170         if (!fourcc_mod_is_vendor(modifier, ARM)) {
 171                 DRM_ERROR("Unknown modifier (not Arm)\n");
 172                 return false;
 173         }
 174
 175         if (modifier &
 176             ~DRM_FORMAT_MOD_ARM_AFBC(AFBC_MOD_VALID_BITS)) {
 177                 DRM_DEBUG_KMS("Unsupported modifiers\n");
 178                 return false;
 179         }
 180
 181         modifiers = malidp_format_modifiers;
 182
 183         /* SPLIT buffers must use SPARSE layout */
 184         if (WARN_ON_ONCE((modifier & AFBC_SPLIT) && !(modifier & AFBC_SPARSE)))
 185                 return false;
 186
 187         /* CBR only applies to YUV formats, where YTR should be always 0 */
 188         if (WARN_ON_ONCE((modifier & AFBC_CBR) && (modifier & AFBC_YTR)))
 189                 return false;
 190
 191         while (*modifiers != DRM_FORMAT_MOD_INVALID) {
 192                 if (*modifiers == modifier)
 193                         break;
 194
 195                 modifiers++;
 196         }
 197
 198         /* return false, if the modifier was not found */
 199         if (*modifiers == DRM_FORMAT_MOD_INVALID) {
 200                 DRM_DEBUG_KMS("Unsupported modifier\n");
 201                 return false;
 202         }
 203
 204         info = drm_format_info(format);
 205
 206         if (info->num_planes != 1) {
 207                 DRM_DEBUG_KMS("AFBC buffers expect one plane\n");
 208                 return false;
 209         }
 210
 211         if (malidp_hw_format_is_linear_only(format) == true) {
 212                 DRM_DEBUG_KMS("Given format (0x%x) is supported is linear mode only\n",
 213                               format);
 214                 return false;
 215         }
 216
 217         /*
 218          * RGB formats need to provide YTR modifier and YUV formats should not
 219          * provide YTR modifier.
 220          */
 221         if (!(info->is_yuv) != !!(modifier & AFBC_FORMAT_MOD_YTR)) {
 222                 DRM_DEBUG_KMS("AFBC_FORMAT_MOD_YTR is %s for %s formats\n",
 223                               info->is_yuv ? "disallowed" : "mandatory",
 224                               info->is_yuv ? "YUV" : "RGB");
 225                 return false;
 226         }
 227
 228         if (modifier & AFBC_SPLIT) {
 229                 if (!info->is_yuv) {
 230                         if (info->cpp[0] <= 2) {
 231                                 DRM_DEBUG_KMS("RGB formats <= 16bpp are not supported with SPLIT\n");
 232                                 return false;
 233                         }
 234                 }
 235
 236                 if ((info->hsub != 1) || (info->vsub != 1)) {
 237                         if (!(format == DRM_FORMAT_YUV420_10BIT &&
 238                               (map->features & MALIDP_DEVICE_AFBC_YUV_420_10_SUPPORT_SPLIT))) {
 239                                 DRM_DEBUG_KMS("Formats which are sub-sampled should never be split\n");
 240                                 return false;
 241                         }
 242                 }
 243         }
 244
 245         if (modifier & AFBC_CBR) {
 246                 if ((info->hsub == 1) || (info->vsub == 1)) {
 247                         DRM_DEBUG_KMS("Formats which are not sub-sampled should not have CBR set\n");
 248                         return false;
 249                 }
 250         }
 251
 252         return true;
 253 }
 254
 255 static bool malidp_format_mod_supported_per_plane(struct drm_plane *plane,
 256                                                   u32 format, u64 modifier)
 257 {
 258         return malidp_format_mod_supported(plane->dev, format, modifier);
 259 }
 260
 261 static const struct drm_plane_funcs malidp_de_plane_funcs = {
 262         .update_plane = drm_atomic_helper_update_plane,
 263         .disable_plane = drm_atomic_helper_disable_plane,
 264         .destroy = malidp_de_plane_destroy,
 265         .reset = malidp_plane_reset,
 266         .atomic_duplicate_state = malidp_duplicate_plane_state,
 267         .atomic_destroy_state = malidp_destroy_plane_state,
 268         .atomic_print_state = malidp_plane_atomic_print_state,
 269         .format_mod_supported = malidp_format_mod_supported_per_plane,
 270 };
 271
 272 static int malidp_se_check_scaling(struct malidp_plane *mp,
 273                                    struct drm_plane_state *state)
 274 {
 275         struct drm_crtc_state *crtc_state =
 276                 drm_atomic_get_existing_crtc_state(state->state, state->crtc);
 277         struct malidp_crtc_state *mc;
 278         u32 src_w, src_h;
 279         int ret;
 280
 281         if (!crtc_state)
 282                 return -EINVAL;
 283
 284         mc = to_malidp_crtc_state(crtc_state);
 285
 286         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 287                                                   0, INT_MAX, true, true);
 288         if (ret)
 289                 return ret;
 290
 291         if (state->rotation & MALIDP_ROTATED_MASK) {
 292                 src_w = state->src_h >> 16;
 293                 src_h = state->src_w >> 16;
 294         } else {
 295                 src_w = state->src_w >> 16;
 296                 src_h = state->src_h >> 16;
 297         }
 298
 299         if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) {
 300                 /* Scaling not necessary for this plane. */
 301                 mc->scaled_planes_mask &= ~(mp->layer->id);
 302                 return 0;
 303         }
 304
 305         if (mp->layer->id & (DE_SMART | DE_GRAPHICS2))
 306                 return -EINVAL;
 307
 308         mc->scaled_planes_mask |= mp->layer->id;
 309         /* Defer scaling requirements calculation to the crtc check. */
 310         return 0;
 311 }
 312
 313 static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp)
 314 {
 315         struct iommu_domain *mmu_dom;
 316
 317         mmu_dom = iommu_get_domain_for_dev(mp->base.dev->dev);
 318         if (mmu_dom)
 319                 return mmu_dom->pgsize_bitmap;
 320
 321         return 0;
 322 }
 323
 324 /*
 325  * Check if the framebuffer is entirely made up of pages at least pgsize in
 326  * size. Only a heuristic: assumes that each scatterlist entry has been aligned
 327  * to the largest page size smaller than its length and that the MMU maps to
 328  * the largest page size possible.
 329  */
 330 static bool malidp_check_pages_threshold(struct malidp_plane_state *ms,
 331                                          u32 pgsize)
 332 {
 333         int i;
 334
 335         for (i = 0; i < ms->n_planes; i++) {
 336                 struct drm_gem_object *obj;
 337                 struct drm_gem_cma_object *cma_obj;
 338                 struct sg_table *sgt;
 339                 struct scatterlist *sgl;
 340
 341                 obj = drm_gem_fb_get_obj(ms->base.fb, i);
 342                 cma_obj = to_drm_gem_cma_obj(obj);
 343
 344                 if (cma_obj->sgt)
 345                         sgt = cma_obj->sgt;
 346                 else
 347                         sgt = obj->funcs->get_sg_table(obj);
 348
 349                 if (IS_ERR(sgt))
 350                         return false;
 351
 352                 sgl = sgt->sgl;
 353
 354                 while (sgl) {
 355                         if (sgl->length < pgsize) {
 356                                 if (!cma_obj->sgt)
 357                                         kfree(sgt);
 358                                 return false;
 359                         }
 360
 361                         sgl = sg_next(sgl);
 362                 }
 363                 if (!cma_obj->sgt)
 364                         kfree(sgt);
 365         }
 366
 367         return true;
 368 }
 369
 370 /*
 371  * Check if it is possible to enable partial-frame MMU prefetch given the
 372  * current format, AFBC state and rotation.
 373  */
 374 static bool malidp_partial_prefetch_supported(u32 format, u64 modifier,
 375                                               unsigned int rotation)
 376 {
 377         bool afbc, sparse;
 378
 379         /* rotation and horizontal flip not supported for partial prefetch */
 380         if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
 381                         DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X))
 382                 return false;
 383
 384         afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0);
 385         sparse = modifier & AFBC_FORMAT_MOD_SPARSE;
 386
 387         switch (format) {
 388         case DRM_FORMAT_ARGB2101010:
 389         case DRM_FORMAT_RGBA1010102:
 390         case DRM_FORMAT_BGRA1010102:
 391         case DRM_FORMAT_ARGB8888:
 392         case DRM_FORMAT_RGBA8888:
 393         case DRM_FORMAT_BGRA8888:
 394         case DRM_FORMAT_XRGB8888:
 395         case DRM_FORMAT_XBGR8888:
 396         case DRM_FORMAT_RGBX8888:
 397         case DRM_FORMAT_BGRX8888:
 398         case DRM_FORMAT_RGB888:
 399         case DRM_FORMAT_RGBA5551:
 400         case DRM_FORMAT_RGB565:
 401                 /* always supported */
 402                 return true;
 403
 404         case DRM_FORMAT_ABGR2101010:
 405         case DRM_FORMAT_ABGR8888:
 406         case DRM_FORMAT_ABGR1555:
 407         case DRM_FORMAT_BGR565:
 408                 /* supported, but if AFBC then must be sparse mode */
 409                 return (!afbc) || (afbc && sparse);
 410
 411         case DRM_FORMAT_BGR888:
 412                 /* supported, but not for AFBC */
 413                 return !afbc;
 414
 415         case DRM_FORMAT_YUYV:
 416         case DRM_FORMAT_UYVY:
 417         case DRM_FORMAT_NV12:
 418         case DRM_FORMAT_YUV420:
 419                 /* not supported */
 420                 return false;
 421
 422         default:
 423                 return false;
 424         }
 425 }
 426
 427 /*
 428  * Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as
 429  * long as the framebuffer is all large pages. Otherwise partial-frame prefetch
 430  * is selected as long as it is supported for the current format. The selected
 431  * page size for prefetch is returned in pgsize_bitmap.
 432  */
 433 static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode
 434                 (struct malidp_plane_state *ms, u32 *pgsize_bitmap)
 435 {
 436         u32 pgsizes;
 437
 438         /* get the full-frame prefetch page size(s) supported by the MMU */
 439         pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES;
 440
 441         while (pgsizes) {
 442                 u32 largest_pgsize = 1 << __fls(pgsizes);
 443
 444                 if (malidp_check_pages_threshold(ms, largest_pgsize)) {
 445                         *pgsize_bitmap = largest_pgsize;
 446                         return MALIDP_PREFETCH_MODE_FULL;
 447                 }
 448
 449                 pgsizes -= largest_pgsize;
 450         }
 451
 452         /* get the partial-frame prefetch page size(s) supported by the MMU */
 453         pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES;
 454
 455         if (malidp_partial_prefetch_supported(ms->base.fb->format->format,
 456                                               ms->base.fb->modifier,
 457                                               ms->base.rotation)) {
 458                 /* partial prefetch using the smallest page size */
 459                 *pgsize_bitmap = 1 << __ffs(pgsizes);
 460                 return MALIDP_PREFETCH_MODE_PARTIAL;
 461         }
 462         *pgsize_bitmap = 0;
 463         return MALIDP_PREFETCH_MODE_NONE;
 464 }
 465
 466 static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode,
 467                                          u8 readahead, u8 n_planes, u32 pgsize)
 468 {
 469         u32 mmu_ctrl = 0;
 470
 471         if (mode != MALIDP_PREFETCH_MODE_NONE) {
 472                 mmu_ctrl |= MALIDP_MMU_CTRL_EN;
 473
 474                 if (mode == MALIDP_PREFETCH_MODE_PARTIAL) {
 475                         mmu_ctrl |= MALIDP_MMU_CTRL_MODE;
 476                         mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead);
 477                 }
 478
 479                 if (pgsize == SZ_64K || pgsize == SZ_2M) {
 480                         int i;
 481
 482                         for (i = 0; i < n_planes; i++)
 483                                 mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i);
 484                 }
 485         }
 486
 487         return mmu_ctrl;
 488 }
 489
 490 static void malidp_de_prefetch_settings(struct malidp_plane *mp,
 491                                         struct malidp_plane_state *ms)
 492 {
 493         if (!mp->layer->mmu_ctrl_offset)
 494                 return;
 495
 496         /* get the page sizes supported by the MMU */
 497         ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp);
 498         ms->mmu_prefetch_mode  =
 499                 malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize);
 500 }
 501
 502 static int malidp_de_plane_check(struct drm_plane *plane,
 503                                  struct drm_atomic_state *state)
 504 {
 505         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 506                                                                                  plane);
 507         struct malidp_plane *mp = to_malidp_plane(plane);
 508         struct malidp_plane_state *ms = to_malidp_plane_state(new_plane_state);
 509         bool rotated = new_plane_state->rotation & MALIDP_ROTATED_MASK;
 510         struct drm_framebuffer *fb;
 511         u16 pixel_alpha = new_plane_state->pixel_blend_mode;
 512         int i, ret;
 513         unsigned int block_w, block_h;
 514
 515         if (!new_plane_state->crtc || WARN_ON(!new_plane_state->fb))
 516                 return 0;
 517
 518         fb = new_plane_state->fb;
 519
 520         ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map,
 521                                              mp->layer->id, fb->format->format,
 522                                              !!fb->modifier);
 523         if (ms->format == MALIDP_INVALID_FORMAT_ID)
 524                 return -EINVAL;
 525
 526         ms->n_planes = fb->format->num_planes;
 527         for (i = 0; i < ms->n_planes; i++) {
 528                 u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated);
 529
 530                 if (((fb->pitches[i] * drm_format_info_block_height(fb->format, i))
 531                                 & (alignment - 1)) && !(fb->modifier)) {
 532                         DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
 533                                       fb->pitches[i], i);
 534                         return -EINVAL;
 535                 }
 536         }
 537
 538         block_w = drm_format_info_block_width(fb->format, 0);
 539         block_h = drm_format_info_block_height(fb->format, 0);
 540         if (fb->width % block_w || fb->height % block_h) {
 541                 DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes");
 542                 return -EINVAL;
 543         }
 544         if ((new_plane_state->src_x >> 16) % block_w || (new_plane_state->src_y >> 16) % block_h) {
 545                 DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes");
 546                 return -EINVAL;
 547         }
 548
 549         if ((new_plane_state->crtc_w > mp->hwdev->max_line_size) ||
 550             (new_plane_state->crtc_h > mp->hwdev->max_line_size) ||
 551             (new_plane_state->crtc_w < mp->hwdev->min_line_size) ||
 552             (new_plane_state->crtc_h < mp->hwdev->min_line_size))
 553                 return -EINVAL;
 554
 555         /*
 556          * DP550/650 video layers can accept 3 plane formats only if
 557          * fb->pitches[1] == fb->pitches[2] since they don't have a
 558          * third plane stride register.
 559          */
 560         if (ms->n_planes == 3 &&
 561             !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) &&
 562             (new_plane_state->fb->pitches[1] != new_plane_state->fb->pitches[2]))
 563                 return -EINVAL;
 564
 565         ret = malidp_se_check_scaling(mp, new_plane_state);
 566         if (ret)
 567                 return ret;
 568
 569         /* validate the rotation constraints for each layer */
 570         if (new_plane_state->rotation != DRM_MODE_ROTATE_0) {
 571                 if (mp->layer->rot == ROTATE_NONE)
 572                         return -EINVAL;
 573                 if ((mp->layer->rot == ROTATE_COMPRESSED) && !(fb->modifier))
 574                         return -EINVAL;
 575                 /*
 576                  * packed RGB888 / BGR888 can't be rotated or flipped
 577                  * unless they are stored in a compressed way
 578                  */
 579                 if ((fb->format->format == DRM_FORMAT_RGB888 ||
 580                      fb->format->format == DRM_FORMAT_BGR888) && !(fb->modifier))
 581                         return -EINVAL;
 582         }
 583
 584         /* SMART layer does not support AFBC */
 585         if (mp->layer->id == DE_SMART && fb->modifier) {
 586                 DRM_ERROR("AFBC framebuffer not supported in SMART layer");
 587                 return -EINVAL;
 588         }
 589
 590         ms->rotmem_size = 0;
 591         if (new_plane_state->rotation & MALIDP_ROTATED_MASK) {
 592                 int val;
 593
 594                 val = mp->hwdev->hw->rotmem_required(mp->hwdev, new_plane_state->crtc_w,
 595                                                      new_plane_state->crtc_h,
 596                                                      fb->format->format,
 597                                                      !!(fb->modifier));
 598                 if (val < 0)
 599                         return val;
 600
 601                 ms->rotmem_size = val;
 602         }
 603
 604         /* HW can't support plane + pixel blending */
 605         if ((new_plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE) &&
 606             (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE) &&
 607             fb->format->has_alpha)
 608                 return -EINVAL;
 609
 610         malidp_de_prefetch_settings(mp, ms);
 611
 612         return 0;
 613 }
 614
 615 static void malidp_de_set_plane_pitches(struct malidp_plane *mp,
 616                                         int num_planes, unsigned int pitches[3])
 617 {
 618         int i;
 619         int num_strides = num_planes;
 620
 621         if (!mp->layer->stride_offset)
 622                 return;
 623
 624         if (num_planes == 3)
 625                 num_strides = (mp->hwdev->hw->features &
 626                                MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2;
 627
 628         /*
 629          * The drm convention for pitch is that it needs to cover width * cpp,
 630          * but our hardware wants the pitch/stride to cover all rows included
 631          * in a tile.
 632          */
 633         for (i = 0; i < num_strides; ++i) {
 634                 unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i);
 635
 636                 malidp_hw_write(mp->hwdev, pitches[i] * block_h,
 637                                 mp->layer->base +
 638                                 mp->layer->stride_offset + i * 4);
 639         }
 640 }
 641
 642 static const s16
 643 malidp_yuv2rgb_coeffs[][DRM_COLOR_RANGE_MAX][MALIDP_COLORADJ_NUM_COEFFS] = {
 644         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 645                 1192,    0, 1634,
 646                 1192, -401, -832,
 647                 1192, 2066,    0,
 648                   64,  512,  512
 649         },
 650         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
 651                 1024,    0, 1436,
 652                 1024, -352, -731,
 653                 1024, 1815,    0,
 654                    0,  512,  512
 655         },
 656         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 657                 1192,    0, 1836,
 658                 1192, -218, -546,
 659                 1192, 2163,    0,
 660                   64,  512,  512
 661         },
 662         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
 663                 1024,    0, 1613,
 664                 1024, -192, -479,
 665                 1024, 1900,    0,
 666                    0,  512,  512
 667         },
 668         [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 669                 1024,    0, 1476,
 670                 1024, -165, -572,
 671                 1024, 1884,    0,
 672                    0,  512,  512
 673         },
 674         [DRM_COLOR_YCBCR_BT2020][DRM_COLOR_YCBCR_FULL_RANGE] = {
 675                 1024,    0, 1510,
 676                 1024, -168, -585,
 677                 1024, 1927,    0,
 678                    0,  512,  512
 679         }
 680 };
 681
 682 static void malidp_de_set_color_encoding(struct malidp_plane *plane,
 683                                          enum drm_color_encoding enc,
 684                                          enum drm_color_range range)
 685 {
 686         unsigned int i;
 687
 688         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; i++) {
 689                 /* coefficients are signed, two's complement values */
 690                 malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i],
 691                                 plane->layer->base + plane->layer->yuv2rgb_offset +
 692                                 i * 4);
 693         }
 694 }
 695
 696 static void malidp_de_set_mmu_control(struct malidp_plane *mp,
 697                                       struct malidp_plane_state *ms)
 698 {
 699         u32 mmu_ctrl;
 700
 701         /* check hardware supports MMU prefetch */
 702         if (!mp->layer->mmu_ctrl_offset)
 703                 return;
 704
 705         mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode,
 706                                                  MALIDP_MMU_PREFETCH_READAHEAD,
 707                                                  ms->n_planes,
 708                                                  ms->mmu_prefetch_pgsize);
 709
 710         malidp_hw_write(mp->hwdev, mmu_ctrl,
 711                         mp->layer->base + mp->layer->mmu_ctrl_offset);
 712 }
 713
 714 static void malidp_set_plane_base_addr(struct drm_framebuffer *fb,
 715                                        struct malidp_plane *mp,
 716                                        int plane_index)
 717 {
 718         dma_addr_t paddr;
 719         u16 ptr;
 720         struct drm_plane *plane = &mp->base;
 721         bool afbc = fb->modifier ? true : false;
 722
 723         ptr = mp->layer->ptr + (plane_index << 4);
 724
 725         /*
 726          * drm_fb_cma_get_gem_addr() alters the physical base address of the
 727          * framebuffer as per the plane's src_x, src_y co-ordinates (ie to
 728          * take care of source cropping).
 729          * For AFBC, this is not needed as the cropping is handled by _AD_CROP_H
 730          * and _AD_CROP_V registers.
 731          */
 732         if (!afbc) {
 733                 paddr = drm_fb_cma_get_gem_addr(fb, plane->state,
 734                                                 plane_index);
 735         } else {
 736                 struct drm_gem_cma_object *obj;
 737
 738                 obj = drm_fb_cma_get_gem_obj(fb, plane_index);
 739
 740                 if (WARN_ON(!obj))
 741                         return;
 742                 paddr = obj->paddr;
 743         }
 744
 745         malidp_hw_write(mp->hwdev, lower_32_bits(paddr), ptr);
 746         malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4);
 747 }
 748
 749 static void malidp_de_set_plane_afbc(struct drm_plane *plane)
 750 {
 751         struct malidp_plane *mp;
 752         u32 src_w, src_h, val = 0, src_x, src_y;
 753         struct drm_framebuffer *fb = plane->state->fb;
 754
 755         mp = to_malidp_plane(plane);
 756
 757         /* no afbc_decoder_offset means AFBC is not supported on this plane */
 758         if (!mp->layer->afbc_decoder_offset)
 759                 return;
 760
 761         if (!fb->modifier) {
 762                 malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset);
 763                 return;
 764         }
 765
 766         /* convert src values from Q16 fixed point to integer */
 767         src_w = plane->state->src_w >> 16;
 768         src_h = plane->state->src_h >> 16;
 769         src_x = plane->state->src_x >> 16;
 770         src_y = plane->state->src_y >> 16;
 771
 772         val = ((fb->width - (src_x + src_w)) << MALIDP_AD_CROP_RIGHT_OFFSET) |
 773                    src_x;
 774         malidp_hw_write(mp->hwdev, val,
 775                         mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_H);
 776
 777         val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) |
 778                    src_y;
 779         malidp_hw_write(mp->hwdev, val,
 780                         mp->layer->afbc_decoder_offset + MALIDP_AD_CROP_V);
 781
 782         val = MALIDP_AD_EN;
 783         if (fb->modifier & AFBC_FORMAT_MOD_SPLIT)
 784                 val |= MALIDP_AD_BS;
 785         if (fb->modifier & AFBC_FORMAT_MOD_YTR)
 786                 val |= MALIDP_AD_YTR;
 787
 788         malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset);
 789 }
 790
 791 static void malidp_de_plane_update(struct drm_plane *plane,
 792                                    struct drm_atomic_state *state)
 793 {
 794         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 795                                                                            plane);
 796         struct malidp_plane *mp;
 797         struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
 798         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 799                                                                            plane);
 800         u16 pixel_alpha = new_state->pixel_blend_mode;
 801         u8 plane_alpha = new_state->alpha >> 8;
 802         u32 src_w, src_h, dest_w, dest_h, val;
 803         int i;
 804         struct drm_framebuffer *fb = plane->state->fb;
 805
 806         mp = to_malidp_plane(plane);
 807
 808         /*
 809          * For AFBC framebuffer, use the framebuffer width and height for
 810          * configuring layer input size register.
 811          */
 812         if (fb->modifier) {
 813                 src_w = fb->width;
 814                 src_h = fb->height;
 815         } else {
 816                 /* convert src values from Q16 fixed point to integer */
 817                 src_w = new_state->src_w >> 16;
 818                 src_h = new_state->src_h >> 16;
 819         }
 820
 821         dest_w = new_state->crtc_w;
 822         dest_h = new_state->crtc_h;
 823
 824         val = malidp_hw_read(mp->hwdev, mp->layer->base);
 825         val = (val & ~LAYER_FORMAT_MASK) | ms->format;
 826         malidp_hw_write(mp->hwdev, val, mp->layer->base);
 827
 828         for (i = 0; i < ms->n_planes; i++)
 829                 malidp_set_plane_base_addr(fb, mp, i);
 830
 831         malidp_de_set_mmu_control(mp, ms);
 832
 833         malidp_de_set_plane_pitches(mp, ms->n_planes,
 834                                     new_state->fb->pitches);
 835
 836         if ((plane->state->color_encoding != old_state->color_encoding) ||
 837             (plane->state->color_range != old_state->color_range))
 838                 malidp_de_set_color_encoding(mp, plane->state->color_encoding,
 839                                              plane->state->color_range);
 840
 841         malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
 842                         mp->layer->base + MALIDP_LAYER_SIZE);
 843
 844         malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
 845                         mp->layer->base + MALIDP_LAYER_COMP_SIZE);
 846
 847         malidp_hw_write(mp->hwdev, LAYER_H_VAL(new_state->crtc_x) |
 848                         LAYER_V_VAL(new_state->crtc_y),
 849                         mp->layer->base + MALIDP_LAYER_OFFSET);
 850
 851         if (mp->layer->id == DE_SMART) {
 852                 /*
 853                  * Enable the first rectangle in the SMART layer to be
 854                  * able to use it as a drm plane.
 855                  */
 856                 malidp_hw_write(mp->hwdev, 1,
 857                                 mp->layer->base + MALIDP550_LS_ENABLE);
 858                 malidp_hw_write(mp->hwdev,
 859                                 LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
 860                                 mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
 861         }
 862
 863         malidp_de_set_plane_afbc(plane);
 864
 865         /* first clear the rotation bits */
 866         val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
 867         val &= ~LAYER_ROT_MASK;
 868
 869         /* setup the rotation and axis flip bits */
 870         if (new_state->rotation & DRM_MODE_ROTATE_MASK)
 871                 val |= ilog2(plane->state->rotation & DRM_MODE_ROTATE_MASK) <<
 872                        LAYER_ROT_OFFSET;
 873         if (new_state->rotation & DRM_MODE_REFLECT_X)
 874                 val |= LAYER_H_FLIP;
 875         if (new_state->rotation & DRM_MODE_REFLECT_Y)
 876                 val |= LAYER_V_FLIP;
 877
 878         val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE | LAYER_ALPHA(0xff));
 879
 880         if (new_state->alpha != DRM_BLEND_ALPHA_OPAQUE) {
 881                 val |= LAYER_COMP_PLANE;
 882         } else if (new_state->fb->format->has_alpha) {
 883                 /* We only care about blend mode if the format has alpha */
 884                 switch (pixel_alpha) {
 885                 case DRM_MODE_BLEND_PREMULTI:
 886                         val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE;
 887                         break;
 888                 case DRM_MODE_BLEND_COVERAGE:
 889                         val |= LAYER_COMP_PIXEL;
 890                         break;
 891                 }
 892         }
 893         val |= LAYER_ALPHA(plane_alpha);
 894
 895         val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK);
 896         if (new_state->crtc) {
 897                 struct malidp_crtc_state *m =
 898                         to_malidp_crtc_state(new_state->crtc->state);
 899
 900                 if (m->scaler_config.scale_enable &&
 901                     m->scaler_config.plane_src_id == mp->layer->id)
 902                         val |= LAYER_FLOWCFG(LAYER_FLOWCFG_SCALE_SE);
 903         }
 904
 905         /* set the 'enable layer' bit */
 906         val |= LAYER_ENABLE;
 907
 908         malidp_hw_write(mp->hwdev, val,
 909                         mp->layer->base + MALIDP_LAYER_CONTROL);
 910 }
 911
 912 static void malidp_de_plane_disable(struct drm_plane *plane,
 913                                     struct drm_atomic_state *state)
 914 {
 915         struct malidp_plane *mp = to_malidp_plane(plane);
 916
 917         malidp_hw_clearbits(mp->hwdev,
 918                             LAYER_ENABLE | LAYER_FLOWCFG(LAYER_FLOWCFG_MASK),
 919                             mp->layer->base + MALIDP_LAYER_CONTROL);
 920 }
 921
 922 static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
 923         .atomic_check = malidp_de_plane_check,
 924         .atomic_update = malidp_de_plane_update,
 925         .atomic_disable = malidp_de_plane_disable,
 926 };
 927
 928 static const uint64_t linear_only_modifiers[] = {
 929         DRM_FORMAT_MOD_LINEAR,
 930         DRM_FORMAT_MOD_INVALID
 931 };
 932
 933 int malidp_de_planes_init(struct drm_device *drm)
 934 {
 935         struct malidp_drm *malidp = drm->dev_private;
 936         const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
 937         struct malidp_plane *plane = NULL;
 938         enum drm_plane_type plane_type;
 939         unsigned long crtcs = BIT(drm->mode_config.num_crtc);
 940         unsigned long flags = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
 941                               DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
 942         unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
 943                                   BIT(DRM_MODE_BLEND_PREMULTI)   |
 944                                   BIT(DRM_MODE_BLEND_COVERAGE);
 945         u32 *formats;
 946         int ret, i = 0, j = 0, n;
 947         u64 supported_modifiers[MODIFIERS_COUNT_MAX];
 948         const u64 *modifiers;
 949
 950         modifiers = malidp_format_modifiers;
 951
 952         if (!(map->features & MALIDP_DEVICE_AFBC_SUPPORT_SPLIT)) {
 953                 /*
 954                  * Since our hardware does not support SPLIT, so build the list
 955                  * of supported modifiers excluding SPLIT ones.
 956                  */
 957                 while (*modifiers != DRM_FORMAT_MOD_INVALID) {
 958                         if (!(*modifiers & AFBC_SPLIT))
 959                                 supported_modifiers[j++] = *modifiers;
 960
 961                         modifiers++;
 962                 }
 963                 supported_modifiers[j++] = DRM_FORMAT_MOD_INVALID;
 964                 modifiers = supported_modifiers;
 965         }
 966
 967         formats = kcalloc(map->n_pixel_formats, sizeof(*formats), GFP_KERNEL);
 968         if (!formats) {
 969                 ret = -ENOMEM;
 970                 goto cleanup;
 971         }
 972
 973         for (i = 0; i < map->n_layers; i++) {
 974                 u8 id = map->layers[i].id;
 975
 976                 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 977                 if (!plane) {
 978                         ret = -ENOMEM;
 979                         goto cleanup;
 980                 }
 981
 982                 /* build the list of DRM supported formats based on the map */
 983                 for (n = 0, j = 0;  j < map->n_pixel_formats; j++) {
 984                         if ((map->pixel_formats[j].layer & id) == id)
 985                                 formats[n++] = map->pixel_formats[j].format;
 986                 }
 987
 988                 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
 989                                         DRM_PLANE_TYPE_OVERLAY;
 990
 991                 /*
 992                  * All the layers except smart layer supports AFBC modifiers.
 993                  */
 994                 ret = drm_universal_plane_init(drm, &plane->base, crtcs,
 995                                 &malidp_de_plane_funcs, formats, n,
 996                                 (id == DE_SMART) ? linear_only_modifiers : modifiers,
 997                                 plane_type, NULL);
 998
 999                 if (ret < 0)
1000                         goto cleanup;
1001
1002                 drm_plane_helper_add(&plane->base,
1003                                      &malidp_de_plane_helper_funcs);
1004                 plane->hwdev = malidp->dev;
1005                 plane->layer = &map->layers[i];
1006
1007                 drm_plane_create_alpha_property(&plane->base);
1008                 drm_plane_create_blend_mode_property(&plane->base, blend_caps);
1009
1010                 if (id == DE_SMART) {
1011                         /* Skip the features which the SMART layer doesn't have. */
1012                         continue;
1013                 }
1014
1015                 drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, flags);
1016                 malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
1017                                 plane->layer->base + MALIDP_LAYER_COMPOSE);
1018
1019                 /* Attach the YUV->RGB property only to video layers */
1020                 if (id & (DE_VIDEO1 | DE_VIDEO2)) {
1021                         /* default encoding for YUV->RGB is BT601 NARROW */
1022                         enum drm_color_encoding enc = DRM_COLOR_YCBCR_BT601;
1023                         enum drm_color_range range = DRM_COLOR_YCBCR_LIMITED_RANGE;
1024
1025                         ret = drm_plane_create_color_properties(&plane->base,
1026                                         BIT(DRM_COLOR_YCBCR_BT601) | \
1027                                         BIT(DRM_COLOR_YCBCR_BT709) | \
1028                                         BIT(DRM_COLOR_YCBCR_BT2020),
1029                                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | \
1030                                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1031                                         enc, range);
1032                         if (!ret)
1033                                 /* program the HW registers */
1034                                 malidp_de_set_color_encoding(plane, enc, range);
1035                         else
1036                                 DRM_WARN("Failed to create video layer %d color properties\n", id);
1037                 }
1038         }
1039
1040         kfree(formats);
1041
1042         return 0;
1043
1044 cleanup:
1045         kfree(formats);
1046
1047         return ret;
1048 }