drivers/spi/spi-cadence.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Cadence SPI controller driver (master and slave mode)
   4  *
   5  * Copyright (C) 2008 - 2014 Xilinx, Inc.
   6  *
   7  * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/gpio/consumer.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/of_address.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/spi/spi.h>
  22
  23 /* Name of this driver */
  24 #define CDNS_SPI_NAME           "cdns-spi"
  25
  26 /* Register offset definitions */
  27 #define CDNS_SPI_CR     0x00 /* Configuration  Register, RW */
  28 #define CDNS_SPI_ISR    0x04 /* Interrupt Status Register, RO */
  29 #define CDNS_SPI_IER    0x08 /* Interrupt Enable Register, WO */
  30 #define CDNS_SPI_IDR    0x0c /* Interrupt Disable Register, WO */
  31 #define CDNS_SPI_IMR    0x10 /* Interrupt Enabled Mask Register, RO */
  32 #define CDNS_SPI_ER     0x14 /* Enable/Disable Register, RW */
  33 #define CDNS_SPI_DR     0x18 /* Delay Register, RW */
  34 #define CDNS_SPI_TXD    0x1C /* Data Transmit Register, WO */
  35 #define CDNS_SPI_RXD    0x20 /* Data Receive Register, RO */
  36 #define CDNS_SPI_SICR   0x24 /* Slave Idle Count Register, RW */
  37 #define CDNS_SPI_THLD   0x28 /* Transmit FIFO Watermark Register,RW */
  38
  39 #define SPI_AUTOSUSPEND_TIMEOUT         3000
  40 /*
  41  * SPI Configuration Register bit Masks
  42  *
  43  * This register contains various control bits that affect the operation
  44  * of the SPI controller
  45  */
  46 #define CDNS_SPI_CR_MANSTRT     0x00010000 /* Manual TX Start */
  47 #define CDNS_SPI_CR_CPHA                0x00000004 /* Clock Phase Control */
  48 #define CDNS_SPI_CR_CPOL                0x00000002 /* Clock Polarity Control */
  49 #define CDNS_SPI_CR_SSCTRL              0x00003C00 /* Slave Select Mask */
  50 #define CDNS_SPI_CR_PERI_SEL    0x00000200 /* Peripheral Select Decode */
  51 #define CDNS_SPI_CR_BAUD_DIV    0x00000038 /* Baud Rate Divisor Mask */
  52 #define CDNS_SPI_CR_MSTREN              0x00000001 /* Master Enable Mask */
  53 #define CDNS_SPI_CR_MANSTRTEN   0x00008000 /* Manual TX Enable Mask */
  54 #define CDNS_SPI_CR_SSFORCE     0x00004000 /* Manual SS Enable Mask */
  55 #define CDNS_SPI_CR_BAUD_DIV_4  0x00000008 /* Default Baud Div Mask */
  56 #define CDNS_SPI_CR_DEFAULT     (CDNS_SPI_CR_MSTREN | \
  57                                         CDNS_SPI_CR_SSCTRL | \
  58                                         CDNS_SPI_CR_SSFORCE | \
  59                                         CDNS_SPI_CR_BAUD_DIV_4)
  60
  61 /*
  62  * SPI Configuration Register - Baud rate and slave select
  63  *
  64  * These are the values used in the calculation of baud rate divisor and
  65  * setting the slave select.
  66  */
  67
  68 #define CDNS_SPI_BAUD_DIV_MAX           7 /* Baud rate divisor maximum */
  69 #define CDNS_SPI_BAUD_DIV_MIN           1 /* Baud rate divisor minimum */
  70 #define CDNS_SPI_BAUD_DIV_SHIFT         3 /* Baud rate divisor shift in CR */
  71 #define CDNS_SPI_SS_SHIFT               10 /* Slave Select field shift in CR */
  72 #define CDNS_SPI_SS0                    0x1 /* Slave Select zero */
  73 #define CDNS_SPI_NOSS                   0xF /* No Slave select */
  74
  75 /*
  76  * SPI Interrupt Registers bit Masks
  77  *
  78  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  79  * bit definitions.
  80  */
  81 #define CDNS_SPI_IXR_TXOW       0x00000004 /* SPI TX FIFO Overwater */
  82 #define CDNS_SPI_IXR_MODF       0x00000002 /* SPI Mode Fault */
  83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
  84 #define CDNS_SPI_IXR_DEFAULT    (CDNS_SPI_IXR_TXOW | \
  85                                         CDNS_SPI_IXR_MODF)
  86 #define CDNS_SPI_IXR_TXFULL     0x00000008 /* SPI TX Full */
  87 #define CDNS_SPI_IXR_ALL        0x0000007F /* SPI all interrupts */
  88
  89 /*
  90  * SPI Enable Register bit Masks
  91  *
  92  * This register is used to enable or disable the SPI controller
  93  */
  94 #define CDNS_SPI_ER_ENABLE      0x00000001 /* SPI Enable Bit Mask */
  95 #define CDNS_SPI_ER_DISABLE     0x0 /* SPI Disable Bit Mask */
  96
  97 /* Default number of chip select lines */
  98 #define CDNS_SPI_DEFAULT_NUM_CS         4
  99
 100 /**
 101  * struct cdns_spi - This definition defines spi driver instance
 102  * @regs:               Virtual address of the SPI controller registers
 103  * @ref_clk:            Pointer to the peripheral clock
 104  * @pclk:               Pointer to the APB clock
 105  * @speed_hz:           Current SPI bus clock speed in Hz
 106  * @txbuf:              Pointer to the TX buffer
 107  * @rxbuf:              Pointer to the RX buffer
 108  * @tx_bytes:           Number of bytes left to transfer
 109  * @rx_bytes:           Number of bytes requested
 110  * @dev_busy:           Device busy flag
 111  * @is_decoded_cs:      Flag for decoder property set or not
 112  * @tx_fifo_depth:      Depth of the TX FIFO
 113  */
 114 struct cdns_spi {
 115         void __iomem *regs;
 116         struct clk *ref_clk;
 117         struct clk *pclk;
 118         unsigned int clk_rate;
 119         u32 speed_hz;
 120         const u8 *txbuf;
 121         u8 *rxbuf;
 122         int tx_bytes;
 123         int rx_bytes;
 124         u8 dev_busy;
 125         u32 is_decoded_cs;
 126         unsigned int tx_fifo_depth;
 127 };
 128
 129 /* Macros for the SPI controller read/write */
 130 static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
 131 {
 132         return readl_relaxed(xspi->regs + offset);
 133 }
 134
 135 static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
 136 {
 137         writel_relaxed(val, xspi->regs + offset);
 138 }
 139
 140 /**
 141  * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
 142  * @xspi:       Pointer to the cdns_spi structure
 143  * @is_slave:   Flag to indicate slave or master mode
 144  * * On reset the SPI controller is configured to slave or  master mode.
 145  * In master mode baud rate divisor is set to 4, threshold value for TX FIFO
 146  * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
 147  *
 148  * This function initializes the SPI controller to disable and clear all the
 149  * interrupts, enable manual slave select and manual start, deselect all the
 150  * chip select lines, and enable the SPI controller.
 151  */
 152 static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_slave)
 153 {
 154         u32 ctrl_reg = 0;
 155
 156         if (!is_slave)
 157                 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
 158
 159         if (xspi->is_decoded_cs)
 160                 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
 161
 162         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 163         cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
 164
 165         /* Clear the RX FIFO */
 166         while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
 167                 cdns_spi_read(xspi, CDNS_SPI_RXD);
 168
 169         cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
 170         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 171         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 172 }
 173
 174 /**
 175  * cdns_spi_chipselect - Select or deselect the chip select line
 176  * @spi:        Pointer to the spi_device structure
 177  * @is_high:    Select(0) or deselect (1) the chip select line
 178  */
 179 static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
 180 {
 181         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 182         u32 ctrl_reg;
 183
 184         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 185
 186         if (is_high) {
 187                 /* Deselect the slave */
 188                 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
 189         } else {
 190                 /* Select the slave */
 191                 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
 192                 if (!(xspi->is_decoded_cs))
 193                         ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
 194                                      CDNS_SPI_SS_SHIFT) &
 195                                      CDNS_SPI_CR_SSCTRL;
 196                 else
 197                         ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
 198                                      CDNS_SPI_CR_SSCTRL;
 199         }
 200
 201         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 202 }
 203
 204 /**
 205  * cdns_spi_config_clock_mode - Sets clock polarity and phase
 206  * @spi:        Pointer to the spi_device structure
 207  *
 208  * Sets the requested clock polarity and phase.
 209  */
 210 static void cdns_spi_config_clock_mode(struct spi_device *spi)
 211 {
 212         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 213         u32 ctrl_reg, new_ctrl_reg;
 214
 215         new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 216         ctrl_reg = new_ctrl_reg;
 217
 218         /* Set the SPI clock phase and clock polarity */
 219         new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
 220         if (spi->mode & SPI_CPHA)
 221                 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
 222         if (spi->mode & SPI_CPOL)
 223                 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
 224
 225         if (new_ctrl_reg != ctrl_reg) {
 226                 /*
 227                  * Just writing the CR register does not seem to apply the clock
 228                  * setting changes. This is problematic when changing the clock
 229                  * polarity as it will cause the SPI slave to see spurious clock
 230                  * transitions. To workaround the issue toggle the ER register.
 231                  */
 232                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 233                 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
 234                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 235         }
 236 }
 237
 238 /**
 239  * cdns_spi_config_clock_freq - Sets clock frequency
 240  * @spi:        Pointer to the spi_device structure
 241  * @transfer:   Pointer to the spi_transfer structure which provides
 242  *              information about next transfer setup parameters
 243  *
 244  * Sets the requested clock frequency.
 245  * Note: If the requested frequency is not an exact match with what can be
 246  * obtained using the prescalar value the driver sets the clock frequency which
 247  * is lower than the requested frequency (maximum lower) for the transfer. If
 248  * the requested frequency is higher or lower than that is supported by the SPI
 249  * controller the driver will set the highest or lowest frequency supported by
 250  * controller.
 251  */
 252 static void cdns_spi_config_clock_freq(struct spi_device *spi,
 253                                        struct spi_transfer *transfer)
 254 {
 255         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 256         u32 ctrl_reg, baud_rate_val;
 257         unsigned long frequency;
 258
 259         frequency = xspi->clk_rate;
 260
 261         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 262
 263         /* Set the clock frequency */
 264         if (xspi->speed_hz != transfer->speed_hz) {
 265                 /* first valid value is 1 */
 266                 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
 267                 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
 268                        (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
 269                         baud_rate_val++;
 270
 271                 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
 272                 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
 273
 274                 xspi->speed_hz = frequency / (2 << baud_rate_val);
 275         }
 276         cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
 277 }
 278
 279 /**
 280  * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
 281  * @spi:        Pointer to the spi_device structure
 282  * @transfer:   Pointer to the spi_transfer structure which provides
 283  *              information about next transfer setup parameters
 284  *
 285  * Sets the operational mode of SPI controller for the next SPI transfer and
 286  * sets the requested clock frequency.
 287  *
 288  * Return:      Always 0
 289  */
 290 static int cdns_spi_setup_transfer(struct spi_device *spi,
 291                                    struct spi_transfer *transfer)
 292 {
 293         struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
 294
 295         cdns_spi_config_clock_freq(spi, transfer);
 296
 297         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
 298                 __func__, spi->mode, spi->bits_per_word,
 299                 xspi->speed_hz);
 300
 301         return 0;
 302 }
 303
 304 /**
 305  * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
 306  * @xspi:       Pointer to the cdns_spi structure
 307  * @ntx:        Number of bytes to pack into the TX FIFO
 308  * @nrx:        Number of bytes to drain from the RX FIFO
 309  */
 310 static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
 311 {
 312         ntx = clamp(ntx, 0, xspi->tx_bytes);
 313         nrx = clamp(nrx, 0, xspi->rx_bytes);
 314
 315         xspi->tx_bytes -= ntx;
 316         xspi->rx_bytes -= nrx;
 317
 318         while (ntx || nrx) {
 319                 /* When xspi in busy condition, bytes may send failed,
 320                  * then spi control did't work thoroughly, add one byte delay
 321                  */
 322                 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
 323                         udelay(10);
 324
 325                 if (ntx) {
 326                         if (xspi->txbuf)
 327                                 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
 328                         else
 329                                 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
 330
 331                         ntx--;
 332                 }
 333
 334                 if (nrx) {
 335                         u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
 336
 337                         if (xspi->rxbuf)
 338                                 *xspi->rxbuf++ = data;
 339
 340                         nrx--;
 341                 }
 342         }
 343 }
 344
 345 /**
 346  * cdns_spi_irq - Interrupt service routine of the SPI controller
 347  * @irq:        IRQ number
 348  * @dev_id:     Pointer to the xspi structure
 349  *
 350  * This function handles TX empty and Mode Fault interrupts only.
 351  * On TX empty interrupt this function reads the received data from RX FIFO and
 352  * fills the TX FIFO if there is any data remaining to be transferred.
 353  * On Mode Fault interrupt this function indicates that transfer is completed,
 354  * the SPI subsystem will identify the error as the remaining bytes to be
 355  * transferred is non-zero.
 356  *
 357  * Return:      IRQ_HANDLED when handled; IRQ_NONE otherwise.
 358  */
 359 static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
 360 {
 361         struct spi_controller *ctlr = dev_id;
 362         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 363         irqreturn_t status;
 364         u32 intr_status;
 365
 366         status = IRQ_NONE;
 367         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 368         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 369
 370         if (intr_status & CDNS_SPI_IXR_MODF) {
 371                 /* Indicate that transfer is completed, the SPI subsystem will
 372                  * identify the error as the remaining bytes to be
 373                  * transferred is non-zero
 374                  */
 375                 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
 376                 spi_finalize_current_transfer(ctlr);
 377                 status = IRQ_HANDLED;
 378         } else if (intr_status & CDNS_SPI_IXR_TXOW) {
 379                 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
 380                 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
 381
 382                 if (threshold > 1)
 383                         trans_cnt -= threshold;
 384
 385                 /* Set threshold to one if number of pending are
 386                  * less than half fifo
 387                  */
 388                 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
 389                         cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
 390
 391                 if (xspi->tx_bytes) {
 392                         cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
 393                 } else {
 394                         cdns_spi_process_fifo(xspi, 0, trans_cnt);
 395                         cdns_spi_write(xspi, CDNS_SPI_IDR,
 396                                        CDNS_SPI_IXR_DEFAULT);
 397                         spi_finalize_current_transfer(ctlr);
 398                 }
 399                 status = IRQ_HANDLED;
 400         }
 401
 402         return status;
 403 }
 404
 405 static int cdns_prepare_message(struct spi_controller *ctlr,
 406                                 struct spi_message *msg)
 407 {
 408         if (!spi_controller_is_slave(ctlr))
 409                 cdns_spi_config_clock_mode(msg->spi);
 410         return 0;
 411 }
 412
 413 /**
 414  * cdns_transfer_one - Initiates the SPI transfer
 415  * @ctlr:       Pointer to spi_controller structure
 416  * @spi:        Pointer to the spi_device structure
 417  * @transfer:   Pointer to the spi_transfer structure which provides
 418  *              information about next transfer parameters
 419  *
 420  * This function in master mode fills the TX FIFO, starts the SPI transfer and
 421  * returns a positive transfer count so that core will wait for completion.
 422  * This function in slave mode fills the TX FIFO and wait for transfer trigger.
 423  *
 424  * Return:      Number of bytes transferred in the last transfer
 425  */
 426 static int cdns_transfer_one(struct spi_controller *ctlr,
 427                              struct spi_device *spi,
 428                              struct spi_transfer *transfer)
 429 {
 430         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 431
 432         xspi->txbuf = transfer->tx_buf;
 433         xspi->rxbuf = transfer->rx_buf;
 434         xspi->tx_bytes = transfer->len;
 435         xspi->rx_bytes = transfer->len;
 436
 437         if (!spi_controller_is_slave(ctlr)) {
 438                 cdns_spi_setup_transfer(spi, transfer);
 439         } else {
 440                 /* Set TX empty threshold to half of FIFO depth
 441                  * only if TX bytes are more than half FIFO depth.
 442                  */
 443                 if (xspi->tx_bytes > xspi->tx_fifo_depth)
 444                         cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
 445         }
 446
 447         cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
 448         spi_transfer_delay_exec(transfer);
 449
 450         cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
 451         return transfer->len;
 452 }
 453
 454 /**
 455  * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
 456  * @ctlr:       Pointer to the spi_controller structure which provides
 457  *              information about the controller.
 458  *
 459  * This function enables SPI master controller.
 460  *
 461  * Return:      0 always
 462  */
 463 static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
 464 {
 465         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 466
 467         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
 468
 469         return 0;
 470 }
 471
 472 /**
 473  * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
 474  * @ctlr:       Pointer to the spi_controller structure which provides
 475  *              information about the controller.
 476  *
 477  * This function disables the SPI master controller when no slave selected.
 478  * This function flush out if any pending data in FIFO.
 479  *
 480  * Return:      0 always
 481  */
 482 static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
 483 {
 484         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 485         u32 ctrl_reg;
 486         unsigned int cnt = xspi->tx_fifo_depth;
 487
 488         if (spi_controller_is_slave(ctlr)) {
 489                 while (cnt--)
 490                         cdns_spi_read(xspi, CDNS_SPI_RXD);
 491         }
 492
 493         /* Disable the SPI if slave is deselected */
 494         ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
 495         ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >>  CDNS_SPI_SS_SHIFT;
 496         if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_slave(ctlr))
 497                 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 498
 499         /* Reset to default */
 500         cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
 501         return 0;
 502 }
 503
 504 /**
 505  * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
 506  * @xspi:       Pointer to the cdns_spi structure
 507  *
 508  * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
 509  * IP. The FIFO threshold register is sized so that its maximum value can be the
 510  * FIFO size - 1. This is used to detect the size of the FIFO.
 511  */
 512 static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
 513 {
 514         /* The MSBs will get truncated giving us the size of the FIFO */
 515         cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
 516         xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
 517
 518         /* Reset to default */
 519         cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
 520 }
 521
 522 /**
 523  * cdns_slave_abort - Abort slave transfer
 524  * @ctlr:       Pointer to the spi_controller structure
 525  *
 526  * This function abort slave transfer if there any transfer timeout.
 527  *
 528  * Return:      0 always
 529  */
 530 static int cdns_slave_abort(struct spi_controller *ctlr)
 531 {
 532         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 533         u32 intr_status;
 534
 535         intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
 536         cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
 537         cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
 538         spi_finalize_current_transfer(ctlr);
 539
 540         return 0;
 541 }
 542
 543 /**
 544  * cdns_spi_probe - Probe method for the SPI driver
 545  * @pdev:       Pointer to the platform_device structure
 546  *
 547  * This function initializes the driver data structures and the hardware.
 548  *
 549  * Return:      0 on success and error value on error
 550  */
 551 static int cdns_spi_probe(struct platform_device *pdev)
 552 {
 553         int ret = 0, irq;
 554         struct spi_controller *ctlr;
 555         struct cdns_spi *xspi;
 556         u32 num_cs;
 557         bool slave;
 558
 559         slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
 560         if (slave)
 561                 ctlr = spi_alloc_slave(&pdev->dev, sizeof(*xspi));
 562         else
 563                 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xspi));
 564
 565         if (!ctlr)
 566                 return -ENOMEM;
 567
 568         xspi = spi_controller_get_devdata(ctlr);
 569         ctlr->dev.of_node = pdev->dev.of_node;
 570         platform_set_drvdata(pdev, ctlr);
 571
 572         xspi->regs = devm_platform_ioremap_resource(pdev, 0);
 573         if (IS_ERR(xspi->regs)) {
 574                 ret = PTR_ERR(xspi->regs);
 575                 goto remove_ctlr;
 576         }
 577
 578         xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
 579         if (IS_ERR(xspi->pclk)) {
 580                 dev_err(&pdev->dev, "pclk clock not found.\n");
 581                 ret = PTR_ERR(xspi->pclk);
 582                 goto remove_ctlr;
 583         }
 584
 585         ret = clk_prepare_enable(xspi->pclk);
 586         if (ret) {
 587                 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
 588                 goto remove_ctlr;
 589         }
 590
 591         if (!spi_controller_is_slave(ctlr)) {
 592                 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
 593                 if (IS_ERR(xspi->ref_clk)) {
 594                         dev_err(&pdev->dev, "ref_clk clock not found.\n");
 595                         ret = PTR_ERR(xspi->ref_clk);
 596                         goto clk_dis_apb;
 597                 }
 598
 599                 ret = clk_prepare_enable(xspi->ref_clk);
 600                 if (ret) {
 601                         dev_err(&pdev->dev, "Unable to enable device clock.\n");
 602                         goto clk_dis_apb;
 603                 }
 604
 605                 pm_runtime_use_autosuspend(&pdev->dev);
 606                 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 607                 pm_runtime_get_noresume(&pdev->dev);
 608                 pm_runtime_set_active(&pdev->dev);
 609                 pm_runtime_enable(&pdev->dev);
 610
 611                 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 612                 if (ret < 0)
 613                         ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
 614                 else
 615                         ctlr->num_chipselect = num_cs;
 616
 617                 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
 618                                            &xspi->is_decoded_cs);
 619                 if (ret < 0)
 620                         xspi->is_decoded_cs = 0;
 621         }
 622
 623         cdns_spi_detect_fifo_depth(xspi);
 624
 625         /* SPI controller initializations */
 626         cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
 627
 628         irq = platform_get_irq(pdev, 0);
 629         if (irq <= 0) {
 630                 ret = -ENXIO;
 631                 goto clk_dis_all;
 632         }
 633
 634         ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
 635                                0, pdev->name, ctlr);
 636         if (ret != 0) {
 637                 ret = -ENXIO;
 638                 dev_err(&pdev->dev, "request_irq failed\n");
 639                 goto clk_dis_all;
 640         }
 641
 642         ctlr->use_gpio_descriptors = true;
 643         ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
 644         ctlr->prepare_message = cdns_prepare_message;
 645         ctlr->transfer_one = cdns_transfer_one;
 646         ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
 647         ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
 648         ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
 649
 650         if (!spi_controller_is_slave(ctlr)) {
 651                 ctlr->mode_bits |=  SPI_CS_HIGH;
 652                 ctlr->set_cs = cdns_spi_chipselect;
 653                 ctlr->auto_runtime_pm = true;
 654                 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
 655                 /* Set to default valid value */
 656                 ctlr->max_speed_hz = xspi->clk_rate / 4;
 657                 xspi->speed_hz = ctlr->max_speed_hz;
 658                 pm_runtime_mark_last_busy(&pdev->dev);
 659                 pm_runtime_put_autosuspend(&pdev->dev);
 660         } else {
 661                 ctlr->mode_bits |= SPI_NO_CS;
 662                 ctlr->slave_abort = cdns_slave_abort;
 663         }
 664         ret = spi_register_controller(ctlr);
 665         if (ret) {
 666                 dev_err(&pdev->dev, "spi_register_controller failed\n");
 667                 goto clk_dis_all;
 668         }
 669
 670         return ret;
 671
 672 clk_dis_all:
 673         if (!spi_controller_is_slave(ctlr)) {
 674                 pm_runtime_set_suspended(&pdev->dev);
 675                 pm_runtime_disable(&pdev->dev);
 676                 clk_disable_unprepare(xspi->ref_clk);
 677         }
 678 clk_dis_apb:
 679         clk_disable_unprepare(xspi->pclk);
 680 remove_ctlr:
 681         spi_controller_put(ctlr);
 682         return ret;
 683 }
 684
 685 /**
 686  * cdns_spi_remove - Remove method for the SPI driver
 687  * @pdev:       Pointer to the platform_device structure
 688  *
 689  * This function is called if a device is physically removed from the system or
 690  * if the driver module is being unloaded. It frees all resources allocated to
 691  * the device.
 692  *
 693  * Return:      0 on success and error value on error
 694  */
 695 static void cdns_spi_remove(struct platform_device *pdev)
 696 {
 697         struct spi_controller *ctlr = platform_get_drvdata(pdev);
 698         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 699
 700         cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
 701
 702         clk_disable_unprepare(xspi->ref_clk);
 703         clk_disable_unprepare(xspi->pclk);
 704         pm_runtime_set_suspended(&pdev->dev);
 705         pm_runtime_disable(&pdev->dev);
 706
 707         spi_unregister_controller(ctlr);
 708 }
 709
 710 /**
 711  * cdns_spi_suspend - Suspend method for the SPI driver
 712  * @dev:        Address of the platform_device structure
 713  *
 714  * This function disables the SPI controller and
 715  * changes the driver state to "suspend"
 716  *
 717  * Return:      0 on success and error value on error
 718  */
 719 static int __maybe_unused cdns_spi_suspend(struct device *dev)
 720 {
 721         struct spi_controller *ctlr = dev_get_drvdata(dev);
 722
 723         return spi_controller_suspend(ctlr);
 724 }
 725
 726 /**
 727  * cdns_spi_resume - Resume method for the SPI driver
 728  * @dev:        Address of the platform_device structure
 729  *
 730  * This function changes the driver state to "ready"
 731  *
 732  * Return:      0 on success and error value on error
 733  */
 734 static int __maybe_unused cdns_spi_resume(struct device *dev)
 735 {
 736         struct spi_controller *ctlr = dev_get_drvdata(dev);
 737         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 738
 739         cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
 740         return spi_controller_resume(ctlr);
 741 }
 742
 743 /**
 744  * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
 745  * @dev:        Address of the platform_device structure
 746  *
 747  * This function enables the clocks
 748  *
 749  * Return:      0 on success and error value on error
 750  */
 751 static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
 752 {
 753         struct spi_controller *ctlr = dev_get_drvdata(dev);
 754         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 755         int ret;
 756
 757         ret = clk_prepare_enable(xspi->pclk);
 758         if (ret) {
 759                 dev_err(dev, "Cannot enable APB clock.\n");
 760                 return ret;
 761         }
 762
 763         ret = clk_prepare_enable(xspi->ref_clk);
 764         if (ret) {
 765                 dev_err(dev, "Cannot enable device clock.\n");
 766                 clk_disable_unprepare(xspi->pclk);
 767                 return ret;
 768         }
 769         return 0;
 770 }
 771
 772 /**
 773  * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
 774  * @dev:        Address of the platform_device structure
 775  *
 776  * This function disables the clocks
 777  *
 778  * Return:      Always 0
 779  */
 780 static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
 781 {
 782         struct spi_controller *ctlr = dev_get_drvdata(dev);
 783         struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
 784
 785         clk_disable_unprepare(xspi->ref_clk);
 786         clk_disable_unprepare(xspi->pclk);
 787
 788         return 0;
 789 }
 790
 791 static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
 792         SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
 793                            cdns_spi_runtime_resume, NULL)
 794         SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
 795 };
 796
 797 static const struct of_device_id cdns_spi_of_match[] = {
 798         { .compatible = "xlnx,zynq-spi-r1p6" },
 799         { .compatible = "cdns,spi-r1p6" },
 800         { /* end of table */ }
 801 };
 802 MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
 803
 804 /* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
 805 static struct platform_driver cdns_spi_driver = {
 806         .probe  = cdns_spi_probe,
 807         .remove_new = cdns_spi_remove,
 808         .driver = {
 809                 .name = CDNS_SPI_NAME,
 810                 .of_match_table = cdns_spi_of_match,
 811                 .pm = &cdns_spi_dev_pm_ops,
 812         },
 813 };
 814
 815 module_platform_driver(cdns_spi_driver);
 816
 817 MODULE_AUTHOR("Xilinx, Inc.");
 818 MODULE_DESCRIPTION("Cadence SPI driver");
 819 MODULE_LICENSE("GPL");