drivers/net/ethernet/intel/igc/igc_base.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c)  2018 Intel Corporation */
   3
   4 #ifndef _IGC_BASE_H
   5 #define _IGC_BASE_H
   6
   7 /* forward declaration */
   8 void igc_rx_fifo_flush_base(struct igc_hw *hw);
   9 void igc_power_down_phy_copper_base(struct igc_hw *hw);
  10
  11 /* Transmit Descriptor - Advanced */
  12 union igc_adv_tx_desc {
  13         struct {
  14                 __le64 buffer_addr;    /* Address of descriptor's data buf */
  15                 __le32 cmd_type_len;
  16                 __le32 olinfo_status;
  17         } read;
  18         struct {
  19                 __le64 rsvd;       /* Reserved */
  20                 __le32 nxtseq_seed;
  21                 __le32 status;
  22         } wb;
  23 };
  24
  25 /* Adv Transmit Descriptor Config Masks */
  26 #define IGC_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
  27 #define IGC_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
  28 #define IGC_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
  29 #define IGC_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
  30 #define IGC_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
  31 #define IGC_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
  32 #define IGC_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
  33 #define IGC_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
  34 #define IGC_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
  35 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
  36
  37 #define IGC_RAR_ENTRIES         16
  38
  39 struct igc_adv_data_desc {
  40         __le64 buffer_addr;    /* Address of the descriptor's data buffer */
  41         union {
  42                 u32 data;
  43                 struct {
  44                         u32 datalen:16; /* Data buffer length */
  45                         u32 rsvd:4;
  46                         u32 dtyp:4;  /* Descriptor type */
  47                         u32 dcmd:8;  /* Descriptor command */
  48                 } config;
  49         } lower;
  50         union {
  51                 u32 data;
  52                 struct {
  53                         u32 status:4;  /* Descriptor status */
  54                         u32 idx:4;
  55                         u32 popts:6;  /* Packet Options */
  56                         u32 paylen:18; /* Payload length */
  57                 } options;
  58         } upper;
  59 };
  60
  61 /* Receive Descriptor - Advanced */
  62 union igc_adv_rx_desc {
  63         struct {
  64                 __le64 pkt_addr; /* Packet buffer address */
  65                 __le64 hdr_addr; /* Header buffer address */
  66         } read;
  67         struct {
  68                 struct {
  69                         union {
  70                                 __le32 data;
  71                                 struct {
  72                                         __le16 pkt_info; /*RSS type, Pkt type*/
  73                                         /* Split Header, header buffer len */
  74                                         __le16 hdr_info;
  75                                 } hs_rss;
  76                         } lo_dword;
  77                         union {
  78                                 __le32 rss; /* RSS Hash */
  79                                 struct {
  80                                         __le16 ip_id; /* IP id */
  81                                         __le16 csum; /* Packet Checksum */
  82                                 } csum_ip;
  83                         } hi_dword;
  84                 } lower;
  85                 struct {
  86                         __le32 status_error; /* ext status/error */
  87                         __le16 length; /* Packet length */
  88                         __le16 vlan; /* VLAN tag */
  89                 } upper;
  90         } wb;  /* writeback */
  91 };
  92
  93 /* Adv Transmit Descriptor Config Masks */
  94 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
  95
  96 /* Additional Transmit Descriptor Control definitions */
  97 #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
  98
  99 /* Additional Receive Descriptor Control definitions */
 100 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
 101
 102 /* SRRCTL bit definitions */
 103 #define IGC_SRRCTL_BSIZEPKT_SHIFT               10 /* Shift _right_ */
 104 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT           2  /* Shift _left_ */
 105 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF  0x02000000
 106
 107 #endif /* _IGC_BASE_H */