drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Zou Nan hai <[email protected]>
  26  *    Xiang Hai hao<[email protected]>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static int
  56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  57                        u32      invalidate_domains,
  58                        u32      flush_domains)
  59 {
  60         u32 cmd;
  61         int ret;
  62
  63         cmd = MI_FLUSH;
  64         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  65                 cmd |= MI_NO_WRITE_FLUSH;
  66
  67         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  68                 cmd |= MI_READ_FLUSH;
  69
  70         ret = intel_ring_begin(ring, 2);
  71         if (ret)
  72                 return ret;
  73
  74         intel_ring_emit(ring, cmd);
  75         intel_ring_emit(ring, MI_NOOP);
  76         intel_ring_advance(ring);
  77
  78         return 0;
  79 }
  80
  81 static int
  82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  83                        u32      invalidate_domains,
  84                        u32      flush_domains)
  85 {
  86         struct drm_device *dev = ring->dev;
  87         u32 cmd;
  88         int ret;
  89
  90         /*
  91          * read/write caches:
  92          *
  93          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  94          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  95          * also flushed at 2d versus 3d pipeline switches.
  96          *
  97          * read-only caches:
  98          *
  99          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 100          * MI_READ_FLUSH is set, and is always flushed on 965.
 101          *
 102          * I915_GEM_DOMAIN_COMMAND may not exist?
 103          *
 104          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 105          * invalidated when MI_EXE_FLUSH is set.
 106          *
 107          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 108          * invalidated with every MI_FLUSH.
 109          *
 110          * TLBs:
 111          *
 112          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 113          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 114          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 115          * are flushed at any MI_FLUSH.
 116          */
 117
 118         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 119         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 120                 cmd &= ~MI_NO_WRITE_FLUSH;
 121         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 122                 cmd |= MI_EXE_FLUSH;
 123
 124         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 125             (IS_G4X(dev) || IS_GEN5(dev)))
 126                 cmd |= MI_INVALIDATE_ISP;
 127
 128         ret = intel_ring_begin(ring, 2);
 129         if (ret)
 130                 return ret;
 131
 132         intel_ring_emit(ring, cmd);
 133         intel_ring_emit(ring, MI_NOOP);
 134         intel_ring_advance(ring);
 135
 136         return 0;
 137 }
 138
 139 /**
 140  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 141  * implementing two workarounds on gen6.  From section 1.4.7.1
 142  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 143  *
 144  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 145  * produced by non-pipelined state commands), software needs to first
 146  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 147  * 0.
 148  *
 149  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 150  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 151  *
 152  * And the workaround for these two requires this workaround first:
 153  *
 154  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 155  * BEFORE the pipe-control with a post-sync op and no write-cache
 156  * flushes.
 157  *
 158  * And this last workaround is tricky because of the requirements on
 159  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 160  * volume 2 part 1:
 161  *
 162  *     "1 of the following must also be set:
 163  *      - Render Target Cache Flush Enable ([12] of DW1)
 164  *      - Depth Cache Flush Enable ([0] of DW1)
 165  *      - Stall at Pixel Scoreboard ([1] of DW1)
 166  *      - Depth Stall ([13] of DW1)
 167  *      - Post-Sync Operation ([13] of DW1)
 168  *      - Notify Enable ([8] of DW1)"
 169  *
 170  * The cache flushes require the workaround flush that triggered this
 171  * one, so we can't use it.  Depth stall would trigger the same.
 172  * Post-sync nonzero is what triggered this second workaround, so we
 173  * can't use that one either.  Notify enable is IRQs, which aren't
 174  * really our business.  That leaves only stall at scoreboard.
 175  */
 176 static int
 177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 178 {
 179         struct pipe_control *pc = ring->private;
 180         u32 scratch_addr = pc->gtt_offset + 128;
 181         int ret;
 182
 183
 184         ret = intel_ring_begin(ring, 6);
 185         if (ret)
 186                 return ret;
 187
 188         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 189         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 190                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 191         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 192         intel_ring_emit(ring, 0); /* low dword */
 193         intel_ring_emit(ring, 0); /* high dword */
 194         intel_ring_emit(ring, MI_NOOP);
 195         intel_ring_advance(ring);
 196
 197         ret = intel_ring_begin(ring, 6);
 198         if (ret)
 199                 return ret;
 200
 201         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 202         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 203         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, 0);
 206         intel_ring_emit(ring, MI_NOOP);
 207         intel_ring_advance(ring);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 214                          u32 invalidate_domains, u32 flush_domains)
 215 {
 216         u32 flags = 0;
 217         struct pipe_control *pc = ring->private;
 218         u32 scratch_addr = pc->gtt_offset + 128;
 219         int ret;
 220
 221         /* Force SNB workarounds for PIPE_CONTROL flushes */
 222         intel_emit_post_sync_nonzero_flush(ring);
 223
 224         /* Just flush everything.  Experiments have shown that reducing the
 225          * number of bits based on the write domains has little performance
 226          * impact.
 227          */
 228         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 229         flags |= PIPE_CONTROL_TLB_INVALIDATE;
 230         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 231         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 232         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 233         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 234         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 235         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 236
 237         ret = intel_ring_begin(ring, 6);
 238         if (ret)
 239                 return ret;
 240
 241         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 242         intel_ring_emit(ring, flags);
 243         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 244         intel_ring_emit(ring, 0); /* lower dword */
 245         intel_ring_emit(ring, 0); /* uppwer dword */
 246         intel_ring_emit(ring, MI_NOOP);
 247         intel_ring_advance(ring);
 248
 249         return 0;
 250 }
 251
 252 static void ring_write_tail(struct intel_ring_buffer *ring,
 253                             u32 value)
 254 {
 255         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 256         I915_WRITE_TAIL(ring, value);
 257 }
 258
 259 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 260 {
 261         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 262         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 263                         RING_ACTHD(ring->mmio_base) : ACTHD;
 264
 265         return I915_READ(acthd_reg);
 266 }
 267
 268 static int init_ring_common(struct intel_ring_buffer *ring)
 269 {
 270         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 271         struct drm_i915_gem_object *obj = ring->obj;
 272         u32 head;
 273
 274         /* Stop the ring if it's running. */
 275         I915_WRITE_CTL(ring, 0);
 276         I915_WRITE_HEAD(ring, 0);
 277         ring->write_tail(ring, 0);
 278
 279         /* Initialize the ring. */
 280         I915_WRITE_START(ring, obj->gtt_offset);
 281         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 282
 283         /* G45 ring initialization fails to reset head to zero */
 284         if (head != 0) {
 285                 DRM_DEBUG_KMS("%s head not reset to zero "
 286                               "ctl %08x head %08x tail %08x start %08x\n",
 287                               ring->name,
 288                               I915_READ_CTL(ring),
 289                               I915_READ_HEAD(ring),
 290                               I915_READ_TAIL(ring),
 291                               I915_READ_START(ring));
 292
 293                 I915_WRITE_HEAD(ring, 0);
 294
 295                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 296                         DRM_ERROR("failed to set %s head to zero "
 297                                   "ctl %08x head %08x tail %08x start %08x\n",
 298                                   ring->name,
 299                                   I915_READ_CTL(ring),
 300                                   I915_READ_HEAD(ring),
 301                                   I915_READ_TAIL(ring),
 302                                   I915_READ_START(ring));
 303                 }
 304         }
 305
 306         I915_WRITE_CTL(ring,
 307                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 308                         | RING_VALID);
 309
 310         /* If the head is still not zero, the ring is dead */
 311         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 312                      I915_READ_START(ring) == obj->gtt_offset &&
 313                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 314                 DRM_ERROR("%s initialization failed "
 315                                 "ctl %08x head %08x tail %08x start %08x\n",
 316                                 ring->name,
 317                                 I915_READ_CTL(ring),
 318                                 I915_READ_HEAD(ring),
 319                                 I915_READ_TAIL(ring),
 320                                 I915_READ_START(ring));
 321                 return -EIO;
 322         }
 323
 324         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 325                 i915_kernel_lost_context(ring->dev);
 326         else {
 327                 ring->head = I915_READ_HEAD(ring);
 328                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 329                 ring->space = ring_space(ring);
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int
 336 init_pipe_control(struct intel_ring_buffer *ring)
 337 {
 338         struct pipe_control *pc;
 339         struct drm_i915_gem_object *obj;
 340         int ret;
 341
 342         if (ring->private)
 343                 return 0;
 344
 345         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 346         if (!pc)
 347                 return -ENOMEM;
 348
 349         obj = i915_gem_alloc_object(ring->dev, 4096);
 350         if (obj == NULL) {
 351                 DRM_ERROR("Failed to allocate seqno page\n");
 352                 ret = -ENOMEM;
 353                 goto err;
 354         }
 355
 356         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 357
 358         ret = i915_gem_object_pin(obj, 4096, true);
 359         if (ret)
 360                 goto err_unref;
 361
 362         pc->gtt_offset = obj->gtt_offset;
 363         pc->cpu_page =  kmap(obj->pages[0]);
 364         if (pc->cpu_page == NULL)
 365                 goto err_unpin;
 366
 367         pc->obj = obj;
 368         ring->private = pc;
 369         return 0;
 370
 371 err_unpin:
 372         i915_gem_object_unpin(obj);
 373 err_unref:
 374         drm_gem_object_unreference(&obj->base);
 375 err:
 376         kfree(pc);
 377         return ret;
 378 }
 379
 380 static void
 381 cleanup_pipe_control(struct intel_ring_buffer *ring)
 382 {
 383         struct pipe_control *pc = ring->private;
 384         struct drm_i915_gem_object *obj;
 385
 386         if (!ring->private)
 387                 return;
 388
 389         obj = pc->obj;
 390         kunmap(obj->pages[0]);
 391         i915_gem_object_unpin(obj);
 392         drm_gem_object_unreference(&obj->base);
 393
 394         kfree(pc);
 395         ring->private = NULL;
 396 }
 397
 398 static int init_render_ring(struct intel_ring_buffer *ring)
 399 {
 400         struct drm_device *dev = ring->dev;
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         int ret = init_ring_common(ring);
 403
 404         if (INTEL_INFO(dev)->gen > 3) {
 405                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 406                 if (IS_GEN7(dev))
 407                         I915_WRITE(GFX_MODE_GEN7,
 408                                    _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 409                                    _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 410         }
 411
 412         if (INTEL_INFO(dev)->gen >= 5) {
 413                 ret = init_pipe_control(ring);
 414                 if (ret)
 415                         return ret;
 416         }
 417
 418         if (IS_GEN6(dev)) {
 419                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 420                  * "If this bit is set, STCunit will have LRA as replacement
 421                  *  policy. [...] This bit must be reset.  LRA replacement
 422                  *  policy is not supported."
 423                  */
 424                 I915_WRITE(CACHE_MODE_0,
 425                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 426
 427                 /* This is not explicitly set for GEN6, so read the register.
 428                  * see intel_ring_mi_set_context() for why we care.
 429                  * TODO: consider explicitly setting the bit for GEN5
 430                  */
 431                 ring->itlb_before_ctx_switch =
 432                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 433         }
 434
 435         if (INTEL_INFO(dev)->gen >= 6)
 436                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 437
 438         if (IS_IVYBRIDGE(dev))
 439                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 440
 441         return ret;
 442 }
 443
 444 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 445 {
 446         if (!ring->private)
 447                 return;
 448
 449         cleanup_pipe_control(ring);
 450 }
 451
 452 static void
 453 update_mboxes(struct intel_ring_buffer *ring,
 454             u32 seqno,
 455             u32 mmio_offset)
 456 {
 457         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 458                               MI_SEMAPHORE_GLOBAL_GTT |
 459                               MI_SEMAPHORE_REGISTER |
 460                               MI_SEMAPHORE_UPDATE);
 461         intel_ring_emit(ring, seqno);
 462         intel_ring_emit(ring, mmio_offset);
 463 }
 464
 465 /**
 466  * gen6_add_request - Update the semaphore mailbox registers
 467  *
 468  * @ring - ring that is adding a request
 469  * @seqno - return seqno stuck into the ring
 470  *
 471  * Update the mailbox registers in the *other* rings with the current seqno.
 472  * This acts like a signal in the canonical semaphore.
 473  */
 474 static int
 475 gen6_add_request(struct intel_ring_buffer *ring,
 476                  u32 *seqno)
 477 {
 478         u32 mbox1_reg;
 479         u32 mbox2_reg;
 480         int ret;
 481
 482         ret = intel_ring_begin(ring, 10);
 483         if (ret)
 484                 return ret;
 485
 486         mbox1_reg = ring->signal_mbox[0];
 487         mbox2_reg = ring->signal_mbox[1];
 488
 489         *seqno = i915_gem_next_request_seqno(ring);
 490
 491         update_mboxes(ring, *seqno, mbox1_reg);
 492         update_mboxes(ring, *seqno, mbox2_reg);
 493         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 494         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 495         intel_ring_emit(ring, *seqno);
 496         intel_ring_emit(ring, MI_USER_INTERRUPT);
 497         intel_ring_advance(ring);
 498
 499         return 0;
 500 }
 501
 502 /**
 503  * intel_ring_sync - sync the waiter to the signaller on seqno
 504  *
 505  * @waiter - ring that is waiting
 506  * @signaller - ring which has, or will signal
 507  * @seqno - seqno which the waiter will block on
 508  */
 509 static int
 510 gen6_ring_sync(struct intel_ring_buffer *waiter,
 511                struct intel_ring_buffer *signaller,
 512                u32 seqno)
 513 {
 514         int ret;
 515         u32 dw1 = MI_SEMAPHORE_MBOX |
 516                   MI_SEMAPHORE_COMPARE |
 517                   MI_SEMAPHORE_REGISTER;
 518
 519         /* Throughout all of the GEM code, seqno passed implies our current
 520          * seqno is >= the last seqno executed. However for hardware the
 521          * comparison is strictly greater than.
 522          */
 523         seqno -= 1;
 524
 525         WARN_ON(signaller->semaphore_register[waiter->id] ==
 526                 MI_SEMAPHORE_SYNC_INVALID);
 527
 528         ret = intel_ring_begin(waiter, 4);
 529         if (ret)
 530                 return ret;
 531
 532         intel_ring_emit(waiter,
 533                         dw1 | signaller->semaphore_register[waiter->id]);
 534         intel_ring_emit(waiter, seqno);
 535         intel_ring_emit(waiter, 0);
 536         intel_ring_emit(waiter, MI_NOOP);
 537         intel_ring_advance(waiter);
 538
 539         return 0;
 540 }
 541
 542 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 543 do {                                                                    \
 544         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 545                  PIPE_CONTROL_DEPTH_STALL);                             \
 546         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 547         intel_ring_emit(ring__, 0);                                                     \
 548         intel_ring_emit(ring__, 0);                                                     \
 549 } while (0)
 550
 551 static int
 552 pc_render_add_request(struct intel_ring_buffer *ring,
 553                       u32 *result)
 554 {
 555         u32 seqno = i915_gem_next_request_seqno(ring);
 556         struct pipe_control *pc = ring->private;
 557         u32 scratch_addr = pc->gtt_offset + 128;
 558         int ret;
 559
 560         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 561          * incoherent with writes to memory, i.e. completely fubar,
 562          * so we need to use PIPE_NOTIFY instead.
 563          *
 564          * However, we also need to workaround the qword write
 565          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 566          * memory before requesting an interrupt.
 567          */
 568         ret = intel_ring_begin(ring, 32);
 569         if (ret)
 570                 return ret;
 571
 572         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 573                         PIPE_CONTROL_WRITE_FLUSH |
 574                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 575         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 576         intel_ring_emit(ring, seqno);
 577         intel_ring_emit(ring, 0);
 578         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 579         scratch_addr += 128; /* write to separate cachelines */
 580         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 581         scratch_addr += 128;
 582         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 583         scratch_addr += 128;
 584         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 585         scratch_addr += 128;
 586         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 587         scratch_addr += 128;
 588         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 589
 590         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 591                         PIPE_CONTROL_WRITE_FLUSH |
 592                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 593                         PIPE_CONTROL_NOTIFY);
 594         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 595         intel_ring_emit(ring, seqno);
 596         intel_ring_emit(ring, 0);
 597         intel_ring_advance(ring);
 598
 599         *result = seqno;
 600         return 0;
 601 }
 602
 603 static u32
 604 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
 605 {
 606         struct drm_device *dev = ring->dev;
 607
 608         /* Workaround to force correct ordering between irq and seqno writes on
 609          * ivb (and maybe also on snb) by reading from a CS register (like
 610          * ACTHD) before reading the status page. */
 611         if (IS_GEN6(dev) || IS_GEN7(dev))
 612                 intel_ring_get_active_head(ring);
 613         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 614 }
 615
 616 static u32
 617 ring_get_seqno(struct intel_ring_buffer *ring)
 618 {
 619         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 620 }
 621
 622 static u32
 623 pc_render_get_seqno(struct intel_ring_buffer *ring)
 624 {
 625         struct pipe_control *pc = ring->private;
 626         return pc->cpu_page[0];
 627 }
 628
 629 static bool
 630 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 631 {
 632         struct drm_device *dev = ring->dev;
 633         drm_i915_private_t *dev_priv = dev->dev_private;
 634         unsigned long flags;
 635
 636         if (!dev->irq_enabled)
 637                 return false;
 638
 639         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 640         if (ring->irq_refcount++ == 0) {
 641                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 642                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 643                 POSTING_READ(GTIMR);
 644         }
 645         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 646
 647         return true;
 648 }
 649
 650 static void
 651 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 652 {
 653         struct drm_device *dev = ring->dev;
 654         drm_i915_private_t *dev_priv = dev->dev_private;
 655         unsigned long flags;
 656
 657         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 658         if (--ring->irq_refcount == 0) {
 659                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 660                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 661                 POSTING_READ(GTIMR);
 662         }
 663         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 664 }
 665
 666 static bool
 667 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 668 {
 669         struct drm_device *dev = ring->dev;
 670         drm_i915_private_t *dev_priv = dev->dev_private;
 671         unsigned long flags;
 672
 673         if (!dev->irq_enabled)
 674                 return false;
 675
 676         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 677         if (ring->irq_refcount++ == 0) {
 678                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 679                 I915_WRITE(IMR, dev_priv->irq_mask);
 680                 POSTING_READ(IMR);
 681         }
 682         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 683
 684         return true;
 685 }
 686
 687 static void
 688 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 689 {
 690         struct drm_device *dev = ring->dev;
 691         drm_i915_private_t *dev_priv = dev->dev_private;
 692         unsigned long flags;
 693
 694         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 695         if (--ring->irq_refcount == 0) {
 696                 dev_priv->irq_mask |= ring->irq_enable_mask;
 697                 I915_WRITE(IMR, dev_priv->irq_mask);
 698                 POSTING_READ(IMR);
 699         }
 700         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 701 }
 702
 703 static bool
 704 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 705 {
 706         struct drm_device *dev = ring->dev;
 707         drm_i915_private_t *dev_priv = dev->dev_private;
 708         unsigned long flags;
 709
 710         if (!dev->irq_enabled)
 711                 return false;
 712
 713         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 714         if (ring->irq_refcount++ == 0) {
 715                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 716                 I915_WRITE16(IMR, dev_priv->irq_mask);
 717                 POSTING_READ16(IMR);
 718         }
 719         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 720
 721         return true;
 722 }
 723
 724 static void
 725 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 726 {
 727         struct drm_device *dev = ring->dev;
 728         drm_i915_private_t *dev_priv = dev->dev_private;
 729         unsigned long flags;
 730
 731         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 732         if (--ring->irq_refcount == 0) {
 733                 dev_priv->irq_mask |= ring->irq_enable_mask;
 734                 I915_WRITE16(IMR, dev_priv->irq_mask);
 735                 POSTING_READ16(IMR);
 736         }
 737         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 738 }
 739
 740 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 741 {
 742         struct drm_device *dev = ring->dev;
 743         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 744         u32 mmio = 0;
 745
 746         /* The ring status page addresses are no longer next to the rest of
 747          * the ring registers as of gen7.
 748          */
 749         if (IS_GEN7(dev)) {
 750                 switch (ring->id) {
 751                 case RCS:
 752                         mmio = RENDER_HWS_PGA_GEN7;
 753                         break;
 754                 case BCS:
 755                         mmio = BLT_HWS_PGA_GEN7;
 756                         break;
 757                 case VCS:
 758                         mmio = BSD_HWS_PGA_GEN7;
 759                         break;
 760                 }
 761         } else if (IS_GEN6(ring->dev)) {
 762                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 763         } else {
 764                 mmio = RING_HWS_PGA(ring->mmio_base);
 765         }
 766
 767         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 768         POSTING_READ(mmio);
 769 }
 770
 771 static int
 772 bsd_ring_flush(struct intel_ring_buffer *ring,
 773                u32     invalidate_domains,
 774                u32     flush_domains)
 775 {
 776         int ret;
 777
 778         ret = intel_ring_begin(ring, 2);
 779         if (ret)
 780                 return ret;
 781
 782         intel_ring_emit(ring, MI_FLUSH);
 783         intel_ring_emit(ring, MI_NOOP);
 784         intel_ring_advance(ring);
 785         return 0;
 786 }
 787
 788 static int
 789 i9xx_add_request(struct intel_ring_buffer *ring,
 790                  u32 *result)
 791 {
 792         u32 seqno;
 793         int ret;
 794
 795         ret = intel_ring_begin(ring, 4);
 796         if (ret)
 797                 return ret;
 798
 799         seqno = i915_gem_next_request_seqno(ring);
 800
 801         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 802         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 803         intel_ring_emit(ring, seqno);
 804         intel_ring_emit(ring, MI_USER_INTERRUPT);
 805         intel_ring_advance(ring);
 806
 807         *result = seqno;
 808         return 0;
 809 }
 810
 811 static bool
 812 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 813 {
 814         struct drm_device *dev = ring->dev;
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816         unsigned long flags;
 817
 818         if (!dev->irq_enabled)
 819                return false;
 820
 821         /* It looks like we need to prevent the gt from suspending while waiting
 822          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 823          * blt/bsd rings on ivb. */
 824         gen6_gt_force_wake_get(dev_priv);
 825
 826         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 827         if (ring->irq_refcount++ == 0) {
 828                 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
 829                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 830                                                 GEN6_RENDER_L3_PARITY_ERROR));
 831                 else
 832                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 833                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 834                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 835                 POSTING_READ(GTIMR);
 836         }
 837         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 838
 839         return true;
 840 }
 841
 842 static void
 843 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 844 {
 845         struct drm_device *dev = ring->dev;
 846         drm_i915_private_t *dev_priv = dev->dev_private;
 847         unsigned long flags;
 848
 849         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 850         if (--ring->irq_refcount == 0) {
 851                 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
 852                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 853                 else
 854                         I915_WRITE_IMR(ring, ~0);
 855                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 856                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 857                 POSTING_READ(GTIMR);
 858         }
 859         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 860
 861         gen6_gt_force_wake_put(dev_priv);
 862 }
 863
 864 static int
 865 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 866 {
 867         int ret;
 868
 869         ret = intel_ring_begin(ring, 2);
 870         if (ret)
 871                 return ret;
 872
 873         intel_ring_emit(ring,
 874                         MI_BATCH_BUFFER_START |
 875                         MI_BATCH_GTT |
 876                         MI_BATCH_NON_SECURE_I965);
 877         intel_ring_emit(ring, offset);
 878         intel_ring_advance(ring);
 879
 880         return 0;
 881 }
 882
 883 static int
 884 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
 885                                 u32 offset, u32 len)
 886 {
 887         int ret;
 888
 889         ret = intel_ring_begin(ring, 4);
 890         if (ret)
 891                 return ret;
 892
 893         intel_ring_emit(ring, MI_BATCH_BUFFER);
 894         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 895         intel_ring_emit(ring, offset + len - 8);
 896         intel_ring_emit(ring, 0);
 897         intel_ring_advance(ring);
 898
 899         return 0;
 900 }
 901
 902 static int
 903 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
 904                                 u32 offset, u32 len)
 905 {
 906         int ret;
 907
 908         ret = intel_ring_begin(ring, 2);
 909         if (ret)
 910                 return ret;
 911
 912         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
 913         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 914         intel_ring_advance(ring);
 915
 916         return 0;
 917 }
 918
 919 static void cleanup_status_page(struct intel_ring_buffer *ring)
 920 {
 921         struct drm_i915_gem_object *obj;
 922
 923         obj = ring->status_page.obj;
 924         if (obj == NULL)
 925                 return;
 926
 927         kunmap(obj->pages[0]);
 928         i915_gem_object_unpin(obj);
 929         drm_gem_object_unreference(&obj->base);
 930         ring->status_page.obj = NULL;
 931 }
 932
 933 static int init_status_page(struct intel_ring_buffer *ring)
 934 {
 935         struct drm_device *dev = ring->dev;
 936         struct drm_i915_gem_object *obj;
 937         int ret;
 938
 939         obj = i915_gem_alloc_object(dev, 4096);
 940         if (obj == NULL) {
 941                 DRM_ERROR("Failed to allocate status page\n");
 942                 ret = -ENOMEM;
 943                 goto err;
 944         }
 945
 946         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 947
 948         ret = i915_gem_object_pin(obj, 4096, true);
 949         if (ret != 0) {
 950                 goto err_unref;
 951         }
 952
 953         ring->status_page.gfx_addr = obj->gtt_offset;
 954         ring->status_page.page_addr = kmap(obj->pages[0]);
 955         if (ring->status_page.page_addr == NULL) {
 956                 goto err_unpin;
 957         }
 958         ring->status_page.obj = obj;
 959         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 960
 961         intel_ring_setup_status_page(ring);
 962         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 963                         ring->name, ring->status_page.gfx_addr);
 964
 965         return 0;
 966
 967 err_unpin:
 968         i915_gem_object_unpin(obj);
 969 err_unref:
 970         drm_gem_object_unreference(&obj->base);
 971 err:
 972         return ret;
 973 }
 974
 975 static int intel_init_ring_buffer(struct drm_device *dev,
 976                                   struct intel_ring_buffer *ring)
 977 {
 978         struct drm_i915_gem_object *obj;
 979         struct drm_i915_private *dev_priv = dev->dev_private;
 980         int ret;
 981
 982         ring->dev = dev;
 983         INIT_LIST_HEAD(&ring->active_list);
 984         INIT_LIST_HEAD(&ring->request_list);
 985         INIT_LIST_HEAD(&ring->gpu_write_list);
 986         ring->size = 32 * PAGE_SIZE;
 987
 988         init_waitqueue_head(&ring->irq_queue);
 989
 990         if (I915_NEED_GFX_HWS(dev)) {
 991                 ret = init_status_page(ring);
 992                 if (ret)
 993                         return ret;
 994         }
 995
 996         obj = i915_gem_alloc_object(dev, ring->size);
 997         if (obj == NULL) {
 998                 DRM_ERROR("Failed to allocate ringbuffer\n");
 999                 ret = -ENOMEM;
1000                 goto err_hws;
1001         }
1002
1003         ring->obj = obj;
1004
1005         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1006         if (ret)
1007                 goto err_unref;
1008
1009         ring->virtual_start =
1010                 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1011                            ring->size);
1012         if (ring->virtual_start == NULL) {
1013                 DRM_ERROR("Failed to map ringbuffer.\n");
1014                 ret = -EINVAL;
1015                 goto err_unpin;
1016         }
1017
1018         ret = ring->init(ring);
1019         if (ret)
1020                 goto err_unmap;
1021
1022         /* Workaround an erratum on the i830 which causes a hang if
1023          * the TAIL pointer points to within the last 2 cachelines
1024          * of the buffer.
1025          */
1026         ring->effective_size = ring->size;
1027         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1028                 ring->effective_size -= 128;
1029
1030         return 0;
1031
1032 err_unmap:
1033         iounmap(ring->virtual_start);
1034 err_unpin:
1035         i915_gem_object_unpin(obj);
1036 err_unref:
1037         drm_gem_object_unreference(&obj->base);
1038         ring->obj = NULL;
1039 err_hws:
1040         cleanup_status_page(ring);
1041         return ret;
1042 }
1043
1044 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1045 {
1046         struct drm_i915_private *dev_priv;
1047         int ret;
1048
1049         if (ring->obj == NULL)
1050                 return;
1051
1052         /* Disable the ring buffer. The ring must be idle at this point */
1053         dev_priv = ring->dev->dev_private;
1054         ret = intel_wait_ring_idle(ring);
1055         if (ret)
1056                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1057                           ring->name, ret);
1058
1059         I915_WRITE_CTL(ring, 0);
1060
1061         iounmap(ring->virtual_start);
1062
1063         i915_gem_object_unpin(ring->obj);
1064         drm_gem_object_unreference(&ring->obj->base);
1065         ring->obj = NULL;
1066
1067         if (ring->cleanup)
1068                 ring->cleanup(ring);
1069
1070         cleanup_status_page(ring);
1071 }
1072
1073 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1074 {
1075         uint32_t __iomem *virt;
1076         int rem = ring->size - ring->tail;
1077
1078         if (ring->space < rem) {
1079                 int ret = intel_wait_ring_buffer(ring, rem);
1080                 if (ret)
1081                         return ret;
1082         }
1083
1084         virt = ring->virtual_start + ring->tail;
1085         rem /= 4;
1086         while (rem--)
1087                 iowrite32(MI_NOOP, virt++);
1088
1089         ring->tail = 0;
1090         ring->space = ring_space(ring);
1091
1092         return 0;
1093 }
1094
1095 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1096 {
1097         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1098         bool was_interruptible;
1099         int ret;
1100
1101         /* XXX As we have not yet audited all the paths to check that
1102          * they are ready for ERESTARTSYS from intel_ring_begin, do not
1103          * allow us to be interruptible by a signal.
1104          */
1105         was_interruptible = dev_priv->mm.interruptible;
1106         dev_priv->mm.interruptible = false;
1107
1108         ret = i915_wait_seqno(ring, seqno);
1109
1110         dev_priv->mm.interruptible = was_interruptible;
1111         if (!ret)
1112                 i915_gem_retire_requests_ring(ring);
1113
1114         return ret;
1115 }
1116
1117 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1118 {
1119         struct drm_i915_gem_request *request;
1120         u32 seqno = 0;
1121         int ret;
1122
1123         i915_gem_retire_requests_ring(ring);
1124
1125         if (ring->last_retired_head != -1) {
1126                 ring->head = ring->last_retired_head;
1127                 ring->last_retired_head = -1;
1128                 ring->space = ring_space(ring);
1129                 if (ring->space >= n)
1130                         return 0;
1131         }
1132
1133         list_for_each_entry(request, &ring->request_list, list) {
1134                 int space;
1135
1136                 if (request->tail == -1)
1137                         continue;
1138
1139                 space = request->tail - (ring->tail + 8);
1140                 if (space < 0)
1141                         space += ring->size;
1142                 if (space >= n) {
1143                         seqno = request->seqno;
1144                         break;
1145                 }
1146
1147                 /* Consume this request in case we need more space than
1148                  * is available and so need to prevent a race between
1149                  * updating last_retired_head and direct reads of
1150                  * I915_RING_HEAD. It also provides a nice sanity check.
1151                  */
1152                 request->tail = -1;
1153         }
1154
1155         if (seqno == 0)
1156                 return -ENOSPC;
1157
1158         ret = intel_ring_wait_seqno(ring, seqno);
1159         if (ret)
1160                 return ret;
1161
1162         if (WARN_ON(ring->last_retired_head == -1))
1163                 return -ENOSPC;
1164
1165         ring->head = ring->last_retired_head;
1166         ring->last_retired_head = -1;
1167         ring->space = ring_space(ring);
1168         if (WARN_ON(ring->space < n))
1169                 return -ENOSPC;
1170
1171         return 0;
1172 }
1173
1174 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1175 {
1176         struct drm_device *dev = ring->dev;
1177         struct drm_i915_private *dev_priv = dev->dev_private;
1178         unsigned long end;
1179         int ret;
1180
1181         ret = intel_ring_wait_request(ring, n);
1182         if (ret != -ENOSPC)
1183                 return ret;
1184
1185         trace_i915_ring_wait_begin(ring);
1186         /* With GEM the hangcheck timer should kick us out of the loop,
1187          * leaving it early runs the risk of corrupting GEM state (due
1188          * to running on almost untested codepaths). But on resume
1189          * timers don't work yet, so prevent a complete hang in that
1190          * case by choosing an insanely large timeout. */
1191         end = jiffies + 60 * HZ;
1192
1193         do {
1194                 ring->head = I915_READ_HEAD(ring);
1195                 ring->space = ring_space(ring);
1196                 if (ring->space >= n) {
1197                         trace_i915_ring_wait_end(ring);
1198                         return 0;
1199                 }
1200
1201                 if (dev->primary->master) {
1202                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1203                         if (master_priv->sarea_priv)
1204                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1205                 }
1206
1207                 msleep(1);
1208                 if (atomic_read(&dev_priv->mm.wedged))
1209                         return -EAGAIN;
1210         } while (!time_after(jiffies, end));
1211         trace_i915_ring_wait_end(ring);
1212         return -EBUSY;
1213 }
1214
1215 int intel_ring_begin(struct intel_ring_buffer *ring,
1216                      int num_dwords)
1217 {
1218         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1219         int n = 4*num_dwords;
1220         int ret;
1221
1222         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1223                 return -EIO;
1224
1225         if (unlikely(ring->tail + n > ring->effective_size)) {
1226                 ret = intel_wrap_ring_buffer(ring);
1227                 if (unlikely(ret))
1228                         return ret;
1229         }
1230
1231         if (unlikely(ring->space < n)) {
1232                 ret = intel_wait_ring_buffer(ring, n);
1233                 if (unlikely(ret))
1234                         return ret;
1235         }
1236
1237         ring->space -= n;
1238         return 0;
1239 }
1240
1241 void intel_ring_advance(struct intel_ring_buffer *ring)
1242 {
1243         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1244
1245         ring->tail &= ring->size - 1;
1246         if (dev_priv->stop_rings & intel_ring_flag(ring))
1247                 return;
1248         ring->write_tail(ring, ring->tail);
1249 }
1250
1251
1252 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1253                                      u32 value)
1254 {
1255         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1256
1257        /* Every tail move must follow the sequence below */
1258         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1259                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1260                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1261         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1262
1263         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1264                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1265                 50))
1266         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1267
1268         I915_WRITE_TAIL(ring, value);
1269         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1270                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1271                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1272 }
1273
1274 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1275                            u32 invalidate, u32 flush)
1276 {
1277         uint32_t cmd;
1278         int ret;
1279
1280         ret = intel_ring_begin(ring, 4);
1281         if (ret)
1282                 return ret;
1283
1284         cmd = MI_FLUSH_DW;
1285         if (invalidate & I915_GEM_GPU_DOMAINS)
1286                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1287         intel_ring_emit(ring, cmd);
1288         intel_ring_emit(ring, 0);
1289         intel_ring_emit(ring, 0);
1290         intel_ring_emit(ring, MI_NOOP);
1291         intel_ring_advance(ring);
1292         return 0;
1293 }
1294
1295 static int
1296 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1297                               u32 offset, u32 len)
1298 {
1299         int ret;
1300
1301         ret = intel_ring_begin(ring, 2);
1302         if (ret)
1303                 return ret;
1304
1305         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1306         /* bit0-7 is the length on GEN6+ */
1307         intel_ring_emit(ring, offset);
1308         intel_ring_advance(ring);
1309
1310         return 0;
1311 }
1312
1313 /* Blitter support (SandyBridge+) */
1314
1315 static int blt_ring_flush(struct intel_ring_buffer *ring,
1316                           u32 invalidate, u32 flush)
1317 {
1318         uint32_t cmd;
1319         int ret;
1320
1321         ret = intel_ring_begin(ring, 4);
1322         if (ret)
1323                 return ret;
1324
1325         cmd = MI_FLUSH_DW;
1326         if (invalidate & I915_GEM_DOMAIN_RENDER)
1327                 cmd |= MI_INVALIDATE_TLB;
1328         intel_ring_emit(ring, cmd);
1329         intel_ring_emit(ring, 0);
1330         intel_ring_emit(ring, 0);
1331         intel_ring_emit(ring, MI_NOOP);
1332         intel_ring_advance(ring);
1333         return 0;
1334 }
1335
1336 int intel_init_render_ring_buffer(struct drm_device *dev)
1337 {
1338         drm_i915_private_t *dev_priv = dev->dev_private;
1339         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1340
1341         ring->name = "render ring";
1342         ring->id = RCS;
1343         ring->mmio_base = RENDER_RING_BASE;
1344
1345         if (INTEL_INFO(dev)->gen >= 6) {
1346                 ring->add_request = gen6_add_request;
1347                 ring->flush = gen6_render_ring_flush;
1348                 ring->irq_get = gen6_ring_get_irq;
1349                 ring->irq_put = gen6_ring_put_irq;
1350                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1351                 ring->get_seqno = gen6_ring_get_seqno;
1352                 ring->sync_to = gen6_ring_sync;
1353                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1354                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1355                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1356                 ring->signal_mbox[0] = GEN6_VRSYNC;
1357                 ring->signal_mbox[1] = GEN6_BRSYNC;
1358         } else if (IS_GEN5(dev)) {
1359                 ring->add_request = pc_render_add_request;
1360                 ring->flush = gen4_render_ring_flush;
1361                 ring->get_seqno = pc_render_get_seqno;
1362                 ring->irq_get = gen5_ring_get_irq;
1363                 ring->irq_put = gen5_ring_put_irq;
1364                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1365         } else {
1366                 ring->add_request = i9xx_add_request;
1367                 if (INTEL_INFO(dev)->gen < 4)
1368                         ring->flush = gen2_render_ring_flush;
1369                 else
1370                         ring->flush = gen4_render_ring_flush;
1371                 ring->get_seqno = ring_get_seqno;
1372                 if (IS_GEN2(dev)) {
1373                         ring->irq_get = i8xx_ring_get_irq;
1374                         ring->irq_put = i8xx_ring_put_irq;
1375                 } else {
1376                         ring->irq_get = i9xx_ring_get_irq;
1377                         ring->irq_put = i9xx_ring_put_irq;
1378                 }
1379                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1380         }
1381         ring->write_tail = ring_write_tail;
1382         if (INTEL_INFO(dev)->gen >= 6)
1383                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1384         else if (INTEL_INFO(dev)->gen >= 4)
1385                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1386         else if (IS_I830(dev) || IS_845G(dev))
1387                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1388         else
1389                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1390         ring->init = init_render_ring;
1391         ring->cleanup = render_ring_cleanup;
1392
1393
1394         if (!I915_NEED_GFX_HWS(dev)) {
1395                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1396                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1397         }
1398
1399         return intel_init_ring_buffer(dev, ring);
1400 }
1401
1402 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1403 {
1404         drm_i915_private_t *dev_priv = dev->dev_private;
1405         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1406
1407         ring->name = "render ring";
1408         ring->id = RCS;
1409         ring->mmio_base = RENDER_RING_BASE;
1410
1411         if (INTEL_INFO(dev)->gen >= 6) {
1412                 /* non-kms not supported on gen6+ */
1413                 return -ENODEV;
1414         }
1415
1416         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1417          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1418          * the special gen5 functions. */
1419         ring->add_request = i9xx_add_request;
1420         if (INTEL_INFO(dev)->gen < 4)
1421                 ring->flush = gen2_render_ring_flush;
1422         else
1423                 ring->flush = gen4_render_ring_flush;
1424         ring->get_seqno = ring_get_seqno;
1425         if (IS_GEN2(dev)) {
1426                 ring->irq_get = i8xx_ring_get_irq;
1427                 ring->irq_put = i8xx_ring_put_irq;
1428         } else {
1429                 ring->irq_get = i9xx_ring_get_irq;
1430                 ring->irq_put = i9xx_ring_put_irq;
1431         }
1432         ring->irq_enable_mask = I915_USER_INTERRUPT;
1433         ring->write_tail = ring_write_tail;
1434         if (INTEL_INFO(dev)->gen >= 4)
1435                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1436         else if (IS_I830(dev) || IS_845G(dev))
1437                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1438         else
1439                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1440         ring->init = init_render_ring;
1441         ring->cleanup = render_ring_cleanup;
1442
1443         if (!I915_NEED_GFX_HWS(dev))
1444                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1445
1446         ring->dev = dev;
1447         INIT_LIST_HEAD(&ring->active_list);
1448         INIT_LIST_HEAD(&ring->request_list);
1449         INIT_LIST_HEAD(&ring->gpu_write_list);
1450
1451         ring->size = size;
1452         ring->effective_size = ring->size;
1453         if (IS_I830(ring->dev))
1454                 ring->effective_size -= 128;
1455
1456         ring->virtual_start = ioremap_wc(start, size);
1457         if (ring->virtual_start == NULL) {
1458                 DRM_ERROR("can not ioremap virtual address for"
1459                           " ring buffer\n");
1460                 return -ENOMEM;
1461         }
1462
1463         return 0;
1464 }
1465
1466 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1467 {
1468         drm_i915_private_t *dev_priv = dev->dev_private;
1469         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1470
1471         ring->name = "bsd ring";
1472         ring->id = VCS;
1473
1474         ring->write_tail = ring_write_tail;
1475         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1476                 ring->mmio_base = GEN6_BSD_RING_BASE;
1477                 /* gen6 bsd needs a special wa for tail updates */
1478                 if (IS_GEN6(dev))
1479                         ring->write_tail = gen6_bsd_ring_write_tail;
1480                 ring->flush = gen6_ring_flush;
1481                 ring->add_request = gen6_add_request;
1482                 ring->get_seqno = gen6_ring_get_seqno;
1483                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1484                 ring->irq_get = gen6_ring_get_irq;
1485                 ring->irq_put = gen6_ring_put_irq;
1486                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1487                 ring->sync_to = gen6_ring_sync;
1488                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1489                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1490                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1491                 ring->signal_mbox[0] = GEN6_RVSYNC;
1492                 ring->signal_mbox[1] = GEN6_BVSYNC;
1493         } else {
1494                 ring->mmio_base = BSD_RING_BASE;
1495                 ring->flush = bsd_ring_flush;
1496                 ring->add_request = i9xx_add_request;
1497                 ring->get_seqno = ring_get_seqno;
1498                 if (IS_GEN5(dev)) {
1499                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1500                         ring->irq_get = gen5_ring_get_irq;
1501                         ring->irq_put = gen5_ring_put_irq;
1502                 } else {
1503                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1504                         ring->irq_get = i9xx_ring_get_irq;
1505                         ring->irq_put = i9xx_ring_put_irq;
1506                 }
1507                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1508         }
1509         ring->init = init_ring_common;
1510
1511
1512         return intel_init_ring_buffer(dev, ring);
1513 }
1514
1515 int intel_init_blt_ring_buffer(struct drm_device *dev)
1516 {
1517         drm_i915_private_t *dev_priv = dev->dev_private;
1518         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1519
1520         ring->name = "blitter ring";
1521         ring->id = BCS;
1522
1523         ring->mmio_base = BLT_RING_BASE;
1524         ring->write_tail = ring_write_tail;
1525         ring->flush = blt_ring_flush;
1526         ring->add_request = gen6_add_request;
1527         ring->get_seqno = gen6_ring_get_seqno;
1528         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1529         ring->irq_get = gen6_ring_get_irq;
1530         ring->irq_put = gen6_ring_put_irq;
1531         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1532         ring->sync_to = gen6_ring_sync;
1533         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1534         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1535         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1536         ring->signal_mbox[0] = GEN6_RBSYNC;
1537         ring->signal_mbox[1] = GEN6_VBSYNC;
1538         ring->init = init_ring_common;
1539
1540         return intel_init_ring_buffer(dev, ring);
1541 }