drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Dave Airlie <[email protected]>
  27  *      Jesse Barnes <[email protected]>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         u32 tmp;
  95         bool ret;
  96
  97         if (!intel_display_power_get_if_enabled(dev_priv,
  98                                                 encoder->power_domain))
  99                 return false;
 100
 101         ret = false;
 102
 103         tmp = I915_READ(lvds_encoder->reg);
 104
 105         if (!(tmp & LVDS_PORT_EN))
 106                 goto out;
 107
 108         if (HAS_PCH_CPT(dev_priv))
 109                 *pipe = PORT_TO_PIPE_CPT(tmp);
 110         else
 111                 *pipe = PORT_TO_PIPE(tmp);
 112
 113         ret = true;
 114
 115 out:
 116         intel_display_power_put(dev_priv, encoder->power_domain);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *pipe_config)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 126         u32 tmp, flags = 0;
 127
 128         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 129
 130         tmp = I915_READ(lvds_encoder->reg);
 131         if (tmp & LVDS_HSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NHSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PHSYNC;
 135         if (tmp & LVDS_VSYNC_POLARITY)
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137         else
 138                 flags |= DRM_MODE_FLAG_PVSYNC;
 139
 140         pipe_config->base.adjusted_mode.flags |= flags;
 141
 142         if (INTEL_GEN(dev_priv) < 5)
 143                 pipe_config->gmch_pfit.lvds_border_bits =
 144                         tmp & LVDS_BORDER_ENABLE;
 145
 146         /* gen2/3 store dither state in pfit control, needs to match */
 147         if (INTEL_GEN(dev_priv) < 4) {
 148                 tmp = I915_READ(PFIT_CONTROL);
 149
 150                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 151         }
 152
 153         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 154 }
 155
 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 157                                         struct intel_lvds_pps *pps)
 158 {
 159         u32 val;
 160
 161         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 162
 163         val = I915_READ(PP_ON_DELAYS(0));
 164         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 165                     PANEL_PORT_SELECT_SHIFT;
 166         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 167                      PANEL_POWER_UP_DELAY_SHIFT;
 168         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 169                   PANEL_LIGHT_ON_DELAY_SHIFT;
 170
 171         val = I915_READ(PP_OFF_DELAYS(0));
 172         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 173                   PANEL_POWER_DOWN_DELAY_SHIFT;
 174         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 175                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 176
 177         val = I915_READ(PP_DIVISOR(0));
 178         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 179                        PP_REFERENCE_DIVIDER_SHIFT;
 180         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 181               PANEL_POWER_CYCLE_DELAY_SHIFT;
 182         /*
 183          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 184          * too short power-cycle delay due to the asynchronous programming of
 185          * the register.
 186          */
 187         if (val)
 188                 val--;
 189         /* Convert from 100ms to 100us units */
 190         pps->t4 = val * 1000;
 191
 192         if (INTEL_INFO(dev_priv)->gen <= 4 &&
 193             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 194                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 195                               "setting defaults\n");
 196                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 197                 pps->t1_t2 = 40 * 10;
 198                 pps->t5 = 200 * 10;
 199                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 200                 pps->t3 = 35 * 10;
 201                 pps->tx = 200 * 10;
 202         }
 203
 204         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 205                          "divider %d port %d powerdown_on_reset %d\n",
 206                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 207                          pps->divider, pps->port, pps->powerdown_on_reset);
 208 }
 209
 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 211                                    struct intel_lvds_pps *pps)
 212 {
 213         u32 val;
 214
 215         val = I915_READ(PP_CONTROL(0));
 216         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 217         if (pps->powerdown_on_reset)
 218                 val |= PANEL_POWER_RESET;
 219         I915_WRITE(PP_CONTROL(0), val);
 220
 221         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 222                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 223                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 224         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 225                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 226
 227         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 228         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 229                PANEL_POWER_CYCLE_DELAY_SHIFT;
 230         I915_WRITE(PP_DIVISOR(0), val);
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 234                                   const struct intel_crtc_state *pipe_config,
 235                                   const struct drm_connector_state *conn_state)
 236 {
 237         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 240         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 241         int pipe = crtc->pipe;
 242         u32 temp;
 243
 244         if (HAS_PCH_SPLIT(dev_priv)) {
 245                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 246                 assert_shared_dpll_disabled(dev_priv,
 247                                             pipe_config->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(dev_priv, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(dev_priv)) {
 258                 temp &= ~PORT_TRANS_SEL_MASK;
 259                 temp |= PORT_TRANS_SEL_CPT(pipe);
 260         } else {
 261                 if (pipe == 1) {
 262                         temp |= LVDS_PIPEB_SELECT;
 263                 } else {
 264                         temp &= ~LVDS_PIPEB_SELECT;
 265                 }
 266         }
 267
 268         /* set the corresponsding LVDS_BORDER bit */
 269         temp &= ~LVDS_BORDER_ENABLE;
 270         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 271         /* Set the B0-B3 data pairs corresponding to whether we're going to
 272          * set the DPLLs for dual-channel mode or not.
 273          */
 274         if (lvds_encoder->is_dual_link)
 275                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 276         else
 277                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 278
 279         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 280          * appropriately here, but we need to look more thoroughly into how
 281          * panels behave in the two modes. For now, let's just maintain the
 282          * value we got from the BIOS.
 283          */
 284         temp &= ~LVDS_A3_POWER_MASK;
 285         temp |= lvds_encoder->a3_power;
 286
 287         /* Set the dithering flag on LVDS as needed, note that there is no
 288          * special lvds dither control bit on pch-split platforms, dithering is
 289          * only controlled through the PIPECONF reg. */
 290         if (IS_GEN4(dev_priv)) {
 291                 /* Bspec wording suggests that LVDS port dithering only exists
 292                  * for 18bpp panels. */
 293                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 294                         temp |= LVDS_ENABLE_DITHER;
 295                 else
 296                         temp &= ~LVDS_ENABLE_DITHER;
 297         }
 298         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 299         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 300                 temp |= LVDS_HSYNC_POLARITY;
 301         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 302                 temp |= LVDS_VSYNC_POLARITY;
 303
 304         I915_WRITE(lvds_encoder->reg, temp);
 305 }
 306
 307 /**
 308  * Sets the power state for the panel.
 309  */
 310 static void intel_enable_lvds(struct intel_encoder *encoder,
 311                               const struct intel_crtc_state *pipe_config,
 312                               const struct drm_connector_state *conn_state)
 313 {
 314         struct drm_device *dev = encoder->base.dev;
 315         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 316         struct drm_i915_private *dev_priv = to_i915(dev);
 317
 318         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 319
 320         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 321         POSTING_READ(lvds_encoder->reg);
 322         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
 323                 DRM_ERROR("timed out waiting for panel to power on\n");
 324
 325         intel_panel_enable_backlight(pipe_config, conn_state);
 326 }
 327
 328 static void intel_disable_lvds(struct intel_encoder *encoder,
 329                                const struct intel_crtc_state *old_crtc_state,
 330                                const struct drm_connector_state *old_conn_state)
 331 {
 332         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 333         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 334
 335         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 336         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 337                 DRM_ERROR("timed out waiting for panel to power off\n");
 338
 339         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 340         POSTING_READ(lvds_encoder->reg);
 341 }
 342
 343 static void gmch_disable_lvds(struct intel_encoder *encoder,
 344                               const struct intel_crtc_state *old_crtc_state,
 345                               const struct drm_connector_state *old_conn_state)
 346
 347 {
 348         intel_panel_disable_backlight(old_conn_state);
 349
 350         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 351 }
 352
 353 static void pch_disable_lvds(struct intel_encoder *encoder,
 354                              const struct intel_crtc_state *old_crtc_state,
 355                              const struct drm_connector_state *old_conn_state)
 356 {
 357         intel_panel_disable_backlight(old_conn_state);
 358 }
 359
 360 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 361                                   const struct intel_crtc_state *old_crtc_state,
 362                                   const struct drm_connector_state *old_conn_state)
 363 {
 364         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 365 }
 366
 367 static enum drm_mode_status
 368 intel_lvds_mode_valid(struct drm_connector *connector,
 369                       struct drm_display_mode *mode)
 370 {
 371         struct intel_connector *intel_connector = to_intel_connector(connector);
 372         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 373         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 374
 375         if (mode->hdisplay > fixed_mode->hdisplay)
 376                 return MODE_PANEL;
 377         if (mode->vdisplay > fixed_mode->vdisplay)
 378                 return MODE_PANEL;
 379         if (fixed_mode->clock > max_pixclk)
 380                 return MODE_CLOCK_HIGH;
 381
 382         return MODE_OK;
 383 }
 384
 385 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 386                                       struct intel_crtc_state *pipe_config,
 387                                       struct drm_connector_state *conn_state)
 388 {
 389         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 390         struct intel_lvds_encoder *lvds_encoder =
 391                 to_lvds_encoder(&intel_encoder->base);
 392         struct intel_connector *intel_connector =
 393                 &lvds_encoder->attached_connector->base;
 394         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 395         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 396         unsigned int lvds_bpp;
 397
 398         /* Should never happen!! */
 399         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 400                 DRM_ERROR("Can't support LVDS on pipe A\n");
 401                 return false;
 402         }
 403
 404         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 405                 lvds_bpp = 8*3;
 406         else
 407                 lvds_bpp = 6*3;
 408
 409         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 410                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 411                               pipe_config->pipe_bpp, lvds_bpp);
 412                 pipe_config->pipe_bpp = lvds_bpp;
 413         }
 414
 415         /*
 416          * We have timings from the BIOS for the panel, put them in
 417          * to the adjusted mode.  The CRTC will be set up for this mode,
 418          * with the panel scaling set up to source from the H/VDisplay
 419          * of the original mode.
 420          */
 421         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 422                                adjusted_mode);
 423
 424         if (HAS_PCH_SPLIT(dev_priv)) {
 425                 pipe_config->has_pch_encoder = true;
 426
 427                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 428                                         conn_state->scaling_mode);
 429         } else {
 430                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 431                                          conn_state->scaling_mode);
 432
 433         }
 434
 435         /*
 436          * XXX: It would be nice to support lower refresh rates on the
 437          * panels to reduce power consumption, and perhaps match the
 438          * user's requested refresh rate.
 439          */
 440
 441         return true;
 442 }
 443
 444 /**
 445  * Detect the LVDS connection.
 446  *
 447  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 448  * connected and closed means disconnected.  We also send hotplug events as
 449  * needed, using lid status notification from the input layer.
 450  */
 451 static enum drm_connector_status
 452 intel_lvds_detect(struct drm_connector *connector, bool force)
 453 {
 454         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 455         enum drm_connector_status status;
 456
 457         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 458                       connector->base.id, connector->name);
 459
 460         status = intel_panel_detect(dev_priv);
 461         if (status != connector_status_unknown)
 462                 return status;
 463
 464         return connector_status_connected;
 465 }
 466
 467 /**
 468  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 469  */
 470 static int intel_lvds_get_modes(struct drm_connector *connector)
 471 {
 472         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 473         struct drm_device *dev = connector->dev;
 474         struct drm_display_mode *mode;
 475
 476         /* use cached edid if we have one */
 477         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 478                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 479
 480         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 481         if (mode == NULL)
 482                 return 0;
 483
 484         drm_mode_probed_add(connector, mode);
 485         return 1;
 486 }
 487
 488 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 489 {
 490         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 491         return 1;
 492 }
 493
 494 /* The GPU hangs up on these systems if modeset is performed on LID open */
 495 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 496         {
 497                 .callback = intel_no_modeset_on_lid_dmi_callback,
 498                 .ident = "Toshiba Tecra A11",
 499                 .matches = {
 500                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 501                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 502                 },
 503         },
 504
 505         { }     /* terminating entry */
 506 };
 507
 508 /*
 509  * Lid events. Note the use of 'modeset':
 510  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 511  *    and set it to MODESET_DONE on open
 512  *  - we use it as a "only once" bit (ie we ignore
 513  *    duplicate events where it was already properly set)
 514  *  - the suspend/resume paths will set it to
 515  *    MODESET_SUSPENDED and ignore the lid open event,
 516  *    because they restore the mode ("lid open").
 517  */
 518 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 519                             void *unused)
 520 {
 521         struct intel_lvds_connector *lvds_connector =
 522                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 523         struct drm_connector *connector = &lvds_connector->base.base;
 524         struct drm_device *dev = connector->dev;
 525         struct drm_i915_private *dev_priv = to_i915(dev);
 526
 527         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 528                 return NOTIFY_OK;
 529
 530         mutex_lock(&dev_priv->modeset_restore_lock);
 531         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 532                 goto exit;
 533         /*
 534          * check and update the status of LVDS connector after receiving
 535          * the LID nofication event.
 536          */
 537         connector->status = connector->funcs->detect(connector, false);
 538
 539         /* Don't force modeset on machines where it causes a GPU lockup */
 540         if (dmi_check_system(intel_no_modeset_on_lid))
 541                 goto exit;
 542         if (!acpi_lid_open()) {
 543                 /* do modeset on next lid open event */
 544                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 545                 goto exit;
 546         }
 547
 548         if (dev_priv->modeset_restore == MODESET_DONE)
 549                 goto exit;
 550
 551         /*
 552          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 553          * We try to detect this here and undo any damage. The split for PCH
 554          * platforms is rather conservative and a bit arbitrary expect that on
 555          * those platforms VGA disabling requires actual legacy VGA I/O access,
 556          * and as part of the cleanup in the hw state restore we also redisable
 557          * the vga plane.
 558          */
 559         if (!HAS_PCH_SPLIT(dev_priv))
 560                 intel_display_resume(dev);
 561
 562         dev_priv->modeset_restore = MODESET_DONE;
 563
 564 exit:
 565         mutex_unlock(&dev_priv->modeset_restore_lock);
 566         return NOTIFY_OK;
 567 }
 568
 569 /**
 570  * intel_lvds_destroy - unregister and free LVDS structures
 571  * @connector: connector to free
 572  *
 573  * Unregister the DDC bus for this connector then free the driver private
 574  * structure.
 575  */
 576 static void intel_lvds_destroy(struct drm_connector *connector)
 577 {
 578         struct intel_lvds_connector *lvds_connector =
 579                 to_lvds_connector(connector);
 580
 581         if (lvds_connector->lid_notifier.notifier_call)
 582                 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
 583
 584         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 585                 kfree(lvds_connector->base.edid);
 586
 587         intel_panel_fini(&lvds_connector->base.panel);
 588
 589         drm_connector_cleanup(connector);
 590         kfree(connector);
 591 }
 592
 593 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 594         .get_modes = intel_lvds_get_modes,
 595         .mode_valid = intel_lvds_mode_valid,
 596         .atomic_check = intel_digital_connector_atomic_check,
 597 };
 598
 599 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 600         .detect = intel_lvds_detect,
 601         .fill_modes = drm_helper_probe_single_connector_modes,
 602         .atomic_get_property = intel_digital_connector_atomic_get_property,
 603         .atomic_set_property = intel_digital_connector_atomic_set_property,
 604         .late_register = intel_connector_register,
 605         .early_unregister = intel_connector_unregister,
 606         .destroy = intel_lvds_destroy,
 607         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 608         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 609 };
 610
 611 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 612         .destroy = intel_encoder_destroy,
 613 };
 614
 615 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 616 {
 617         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 618         return 1;
 619 }
 620
 621 /* These systems claim to have LVDS, but really don't */
 622 static const struct dmi_system_id intel_no_lvds[] = {
 623         {
 624                 .callback = intel_no_lvds_dmi_callback,
 625                 .ident = "Apple Mac Mini (Core series)",
 626                 .matches = {
 627                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 628                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 629                 },
 630         },
 631         {
 632                 .callback = intel_no_lvds_dmi_callback,
 633                 .ident = "Apple Mac Mini (Core 2 series)",
 634                 .matches = {
 635                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 636                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 637                 },
 638         },
 639         {
 640                 .callback = intel_no_lvds_dmi_callback,
 641                 .ident = "MSI IM-945GSE-A",
 642                 .matches = {
 643                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 644                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 645                 },
 646         },
 647         {
 648                 .callback = intel_no_lvds_dmi_callback,
 649                 .ident = "Dell Studio Hybrid",
 650                 .matches = {
 651                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 652                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 653                 },
 654         },
 655         {
 656                 .callback = intel_no_lvds_dmi_callback,
 657                 .ident = "Dell OptiPlex FX170",
 658                 .matches = {
 659                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 660                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 661                 },
 662         },
 663         {
 664                 .callback = intel_no_lvds_dmi_callback,
 665                 .ident = "AOpen Mini PC",
 666                 .matches = {
 667                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 668                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 669                 },
 670         },
 671         {
 672                 .callback = intel_no_lvds_dmi_callback,
 673                 .ident = "AOpen Mini PC MP915",
 674                 .matches = {
 675                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 676                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 677                 },
 678         },
 679         {
 680                 .callback = intel_no_lvds_dmi_callback,
 681                 .ident = "AOpen i915GMm-HFS",
 682                 .matches = {
 683                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 684                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 685                 },
 686         },
 687         {
 688                 .callback = intel_no_lvds_dmi_callback,
 689                 .ident = "AOpen i45GMx-I",
 690                 .matches = {
 691                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 692                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 693                 },
 694         },
 695         {
 696                 .callback = intel_no_lvds_dmi_callback,
 697                 .ident = "Aopen i945GTt-VFA",
 698                 .matches = {
 699                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 700                 },
 701         },
 702         {
 703                 .callback = intel_no_lvds_dmi_callback,
 704                 .ident = "Clientron U800",
 705                 .matches = {
 706                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 707                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 708                 },
 709         },
 710         {
 711                 .callback = intel_no_lvds_dmi_callback,
 712                 .ident = "Clientron E830",
 713                 .matches = {
 714                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 715                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 716                 },
 717         },
 718         {
 719                 .callback = intel_no_lvds_dmi_callback,
 720                 .ident = "Asus EeeBox PC EB1007",
 721                 .matches = {
 722                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 723                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 724                 },
 725         },
 726         {
 727                 .callback = intel_no_lvds_dmi_callback,
 728                 .ident = "Asus AT5NM10T-I",
 729                 .matches = {
 730                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 731                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 732                 },
 733         },
 734         {
 735                 .callback = intel_no_lvds_dmi_callback,
 736                 .ident = "Hewlett-Packard HP t5740",
 737                 .matches = {
 738                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 739                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 740                 },
 741         },
 742         {
 743                 .callback = intel_no_lvds_dmi_callback,
 744                 .ident = "Hewlett-Packard t5745",
 745                 .matches = {
 746                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 747                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 748                 },
 749         },
 750         {
 751                 .callback = intel_no_lvds_dmi_callback,
 752                 .ident = "Hewlett-Packard st5747",
 753                 .matches = {
 754                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 755                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 756                 },
 757         },
 758         {
 759                 .callback = intel_no_lvds_dmi_callback,
 760                 .ident = "MSI Wind Box DC500",
 761                 .matches = {
 762                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 763                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 764                 },
 765         },
 766         {
 767                 .callback = intel_no_lvds_dmi_callback,
 768                 .ident = "Gigabyte GA-D525TUD",
 769                 .matches = {
 770                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 771                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 772                 },
 773         },
 774         {
 775                 .callback = intel_no_lvds_dmi_callback,
 776                 .ident = "Supermicro X7SPA-H",
 777                 .matches = {
 778                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 779                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 780                 },
 781         },
 782         {
 783                 .callback = intel_no_lvds_dmi_callback,
 784                 .ident = "Fujitsu Esprimo Q900",
 785                 .matches = {
 786                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 787                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 788                 },
 789         },
 790         {
 791                 .callback = intel_no_lvds_dmi_callback,
 792                 .ident = "Intel D410PT",
 793                 .matches = {
 794                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 795                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 796                 },
 797         },
 798         {
 799                 .callback = intel_no_lvds_dmi_callback,
 800                 .ident = "Intel D425KT",
 801                 .matches = {
 802                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 803                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 804                 },
 805         },
 806         {
 807                 .callback = intel_no_lvds_dmi_callback,
 808                 .ident = "Intel D510MO",
 809                 .matches = {
 810                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 811                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 812                 },
 813         },
 814         {
 815                 .callback = intel_no_lvds_dmi_callback,
 816                 .ident = "Intel D525MW",
 817                 .matches = {
 818                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 819                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 820                 },
 821         },
 822
 823         { }     /* terminating entry */
 824 };
 825
 826 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 827 {
 828         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 829         return 1;
 830 }
 831
 832 static const struct dmi_system_id intel_dual_link_lvds[] = {
 833         {
 834                 .callback = intel_dual_link_lvds_callback,
 835                 .ident = "Apple MacBook Pro 15\" (2010)",
 836                 .matches = {
 837                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 838                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 839                 },
 840         },
 841         {
 842                 .callback = intel_dual_link_lvds_callback,
 843                 .ident = "Apple MacBook Pro 15\" (2011)",
 844                 .matches = {
 845                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 846                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 847                 },
 848         },
 849         {
 850                 .callback = intel_dual_link_lvds_callback,
 851                 .ident = "Apple MacBook Pro 15\" (2012)",
 852                 .matches = {
 853                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 854                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 855                 },
 856         },
 857         { }     /* terminating entry */
 858 };
 859
 860 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 861 {
 862         struct intel_encoder *intel_encoder;
 863
 864         for_each_intel_encoder(dev, intel_encoder)
 865                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 866                         return intel_encoder;
 867
 868         return NULL;
 869 }
 870
 871 bool intel_is_dual_link_lvds(struct drm_device *dev)
 872 {
 873         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 874
 875         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 876 }
 877
 878 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 879 {
 880         struct drm_device *dev = lvds_encoder->base.base.dev;
 881         unsigned int val;
 882         struct drm_i915_private *dev_priv = to_i915(dev);
 883
 884         /* use the module option value if specified */
 885         if (i915_modparams.lvds_channel_mode > 0)
 886                 return i915_modparams.lvds_channel_mode == 2;
 887
 888         /* single channel LVDS is limited to 112 MHz */
 889         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 890             > 112999)
 891                 return true;
 892
 893         if (dmi_check_system(intel_dual_link_lvds))
 894                 return true;
 895
 896         /* BIOS should set the proper LVDS register value at boot, but
 897          * in reality, it doesn't set the value when the lid is closed;
 898          * we need to check "the value to be set" in VBT when LVDS
 899          * register is uninitialized.
 900          */
 901         val = I915_READ(lvds_encoder->reg);
 902         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 903                 val = dev_priv->vbt.bios_lvds_val;
 904
 905         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 906 }
 907
 908 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 909 {
 910         /* With the introduction of the PCH we gained a dedicated
 911          * LVDS presence pin, use it. */
 912         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 913                 return true;
 914
 915         /* Otherwise LVDS was only attached to mobile products,
 916          * except for the inglorious 830gm */
 917         if (INTEL_GEN(dev_priv) <= 4 &&
 918             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 919                 return true;
 920
 921         return false;
 922 }
 923
 924 /**
 925  * intel_lvds_init - setup LVDS connectors on this device
 926  * @dev: drm device
 927  *
 928  * Create the connector, register the LVDS DDC bus, and try to figure out what
 929  * modes we can display on the LVDS panel (if present).
 930  */
 931 void intel_lvds_init(struct drm_i915_private *dev_priv)
 932 {
 933         struct drm_device *dev = &dev_priv->drm;
 934         struct intel_lvds_encoder *lvds_encoder;
 935         struct intel_encoder *intel_encoder;
 936         struct intel_lvds_connector *lvds_connector;
 937         struct intel_connector *intel_connector;
 938         struct drm_connector *connector;
 939         struct drm_encoder *encoder;
 940         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 941         struct drm_display_mode *fixed_mode = NULL;
 942         struct drm_display_mode *downclock_mode = NULL;
 943         struct edid *edid;
 944         i915_reg_t lvds_reg;
 945         u32 lvds;
 946         u8 pin;
 947         u32 allowed_scalers;
 948
 949         if (!intel_lvds_supported(dev_priv))
 950                 return;
 951
 952         /* Skip init on machines we know falsely report LVDS */
 953         if (dmi_check_system(intel_no_lvds))
 954                 return;
 955
 956         if (HAS_PCH_SPLIT(dev_priv))
 957                 lvds_reg = PCH_LVDS;
 958         else
 959                 lvds_reg = LVDS;
 960
 961         lvds = I915_READ(lvds_reg);
 962
 963         if (HAS_PCH_SPLIT(dev_priv)) {
 964                 if ((lvds & LVDS_DETECTED) == 0)
 965                         return;
 966                 if (dev_priv->vbt.edp.support) {
 967                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
 968                         return;
 969                 }
 970         }
 971
 972         pin = GMBUS_PIN_PANEL;
 973         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 974                 if ((lvds & LVDS_PORT_EN) == 0) {
 975                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 976                         return;
 977                 }
 978                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 979         }
 980
 981         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 982         if (!lvds_encoder)
 983                 return;
 984
 985         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
 986         if (!lvds_connector) {
 987                 kfree(lvds_encoder);
 988                 return;
 989         }
 990
 991         if (intel_connector_init(&lvds_connector->base) < 0) {
 992                 kfree(lvds_connector);
 993                 kfree(lvds_encoder);
 994                 return;
 995         }
 996
 997         lvds_encoder->attached_connector = lvds_connector;
 998
 999         intel_encoder = &lvds_encoder->base;
1000         encoder = &intel_encoder->base;
1001         intel_connector = &lvds_connector->base;
1002         connector = &intel_connector->base;
1003         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1004                            DRM_MODE_CONNECTOR_LVDS);
1005
1006         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1007                          DRM_MODE_ENCODER_LVDS, "LVDS");
1008
1009         intel_encoder->enable = intel_enable_lvds;
1010         intel_encoder->pre_enable = intel_pre_enable_lvds;
1011         intel_encoder->compute_config = intel_lvds_compute_config;
1012         if (HAS_PCH_SPLIT(dev_priv)) {
1013                 intel_encoder->disable = pch_disable_lvds;
1014                 intel_encoder->post_disable = pch_post_disable_lvds;
1015         } else {
1016                 intel_encoder->disable = gmch_disable_lvds;
1017         }
1018         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1019         intel_encoder->get_config = intel_lvds_get_config;
1020         intel_connector->get_hw_state = intel_connector_get_hw_state;
1021
1022         intel_connector_attach_encoder(intel_connector, intel_encoder);
1023
1024         intel_encoder->type = INTEL_OUTPUT_LVDS;
1025         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1026         intel_encoder->port = PORT_NONE;
1027         intel_encoder->cloneable = 0;
1028         if (HAS_PCH_SPLIT(dev_priv))
1029                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1030         else if (IS_GEN4(dev_priv))
1031                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1032         else
1033                 intel_encoder->crtc_mask = (1 << 1);
1034
1035         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1036         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1037         connector->interlace_allowed = false;
1038         connector->doublescan_allowed = false;
1039
1040         lvds_encoder->reg = lvds_reg;
1041
1042         /* create the scaling mode property */
1043         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
1044         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
1045         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1046         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
1047         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1048
1049         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1050         lvds_encoder->init_lvds_val = lvds;
1051
1052         /*
1053          * LVDS discovery:
1054          * 1) check for EDID on DDC
1055          * 2) check for VBT data
1056          * 3) check to see if LVDS is already on
1057          *    if none of the above, no panel
1058          * 4) make sure lid is open
1059          *    if closed, act like it's not there for now
1060          */
1061
1062         /*
1063          * Attempt to get the fixed panel mode from DDC.  Assume that the
1064          * preferred mode is the right one.
1065          */
1066         mutex_lock(&dev->mode_config.mutex);
1067         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1068                 edid = drm_get_edid_switcheroo(connector,
1069                                     intel_gmbus_get_adapter(dev_priv, pin));
1070         else
1071                 edid = drm_get_edid(connector,
1072                                     intel_gmbus_get_adapter(dev_priv, pin));
1073         if (edid) {
1074                 if (drm_add_edid_modes(connector, edid)) {
1075                         drm_mode_connector_update_edid_property(connector,
1076                                                                 edid);
1077                 } else {
1078                         kfree(edid);
1079                         edid = ERR_PTR(-EINVAL);
1080                 }
1081         } else {
1082                 edid = ERR_PTR(-ENOENT);
1083         }
1084         lvds_connector->base.edid = edid;
1085
1086         list_for_each_entry(scan, &connector->probed_modes, head) {
1087                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1088                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1089                         drm_mode_debug_printmodeline(scan);
1090
1091                         fixed_mode = drm_mode_duplicate(dev, scan);
1092                         if (fixed_mode)
1093                                 goto out;
1094                 }
1095         }
1096
1097         /* Failed to get EDID, what about VBT? */
1098         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1099                 DRM_DEBUG_KMS("using mode from VBT: ");
1100                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1101
1102                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1103                 if (fixed_mode) {
1104                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1105                         connector->display_info.width_mm = fixed_mode->width_mm;
1106                         connector->display_info.height_mm = fixed_mode->height_mm;
1107                         goto out;
1108                 }
1109         }
1110
1111         /*
1112          * If we didn't get EDID, try checking if the panel is already turned
1113          * on.  If so, assume that whatever is currently programmed is the
1114          * correct mode.
1115          */
1116         fixed_mode = intel_encoder_current_mode(intel_encoder);
1117         if (fixed_mode) {
1118                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1119                 drm_mode_debug_printmodeline(fixed_mode);
1120                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1121         }
1122
1123         /* If we still don't have a mode after all that, give up. */
1124         if (!fixed_mode)
1125                 goto failed;
1126
1127 out:
1128         mutex_unlock(&dev->mode_config.mutex);
1129
1130         intel_panel_init(&intel_connector->panel, fixed_mode, NULL,
1131                          downclock_mode);
1132         intel_panel_setup_backlight(connector, INVALID_PIPE);
1133
1134         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1135         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1136                       lvds_encoder->is_dual_link ? "dual" : "single");
1137
1138         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1139
1140         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1141         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1142                 DRM_DEBUG_KMS("lid notifier registration failed\n");
1143                 lvds_connector->lid_notifier.notifier_call = NULL;
1144         }
1145
1146         return;
1147
1148 failed:
1149         mutex_unlock(&dev->mode_config.mutex);
1150
1151         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1152         drm_connector_cleanup(connector);
1153         drm_encoder_cleanup(encoder);
1154         kfree(lvds_encoder);
1155         kfree(lvds_connector);
1156         return;
1157 }