drivers/gpu/drm/i915/intel_guc.c

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_guc.h"
  26 #include "intel_guc_submission.h"
  27 #include "i915_drv.h"
  28
  29 static void gen8_guc_raise_irq(struct intel_guc *guc)
  30 {
  31         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  32
  33         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  34 }
  35
  36 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  37 {
  38         GEM_BUG_ON(!guc->send_regs.base);
  39         GEM_BUG_ON(!guc->send_regs.count);
  40         GEM_BUG_ON(i >= guc->send_regs.count);
  41
  42         return _MMIO(guc->send_regs.base + 4 * i);
  43 }
  44
  45 void intel_guc_init_send_regs(struct intel_guc *guc)
  46 {
  47         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  48         enum forcewake_domains fw_domains = 0;
  49         unsigned int i;
  50
  51         guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  52         guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
  53
  54         for (i = 0; i < guc->send_regs.count; i++) {
  55                 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
  56                                         guc_send_reg(guc, i),
  57                                         FW_REG_READ | FW_REG_WRITE);
  58         }
  59         guc->send_regs.fw_domains = fw_domains;
  60 }
  61
  62 void intel_guc_init_early(struct intel_guc *guc)
  63 {
  64         intel_guc_fw_init_early(guc);
  65         intel_guc_ct_init_early(&guc->ct);
  66
  67         mutex_init(&guc->send_mutex);
  68         guc->send = intel_guc_send_nop;
  69         guc->notify = gen8_guc_raise_irq;
  70 }
  71
  72 int intel_guc_init_wq(struct intel_guc *guc)
  73 {
  74         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  75
  76         /*
  77          * GuC log buffer flush work item has to do register access to
  78          * send the ack to GuC and this work item, if not synced before
  79          * suspend, can potentially get executed after the GFX device is
  80          * suspended.
  81          * By marking the WQ as freezable, we don't have to bother about
  82          * flushing of this work item from the suspend hooks, the pending
  83          * work item if any will be either executed before the suspend
  84          * or scheduled later on resume. This way the handling of work
  85          * item can be kept same between system suspend & rpm suspend.
  86          */
  87         guc->log.runtime.flush_wq = alloc_ordered_workqueue("i915-guc_log",
  88                                                 WQ_HIGHPRI | WQ_FREEZABLE);
  89         if (!guc->log.runtime.flush_wq)
  90                 return -ENOMEM;
  91
  92         /*
  93          * Even though both sending GuC action, and adding a new workitem to
  94          * GuC workqueue are serialized (each with its own locking), since
  95          * we're using mutliple engines, it's possible that we're going to
  96          * issue a preempt request with two (or more - each for different
  97          * engine) workitems in GuC queue. In this situation, GuC may submit
  98          * all of them, which will make us very confused.
  99          * Our preemption contexts may even already be complete - before we
 100          * even had the chance to sent the preempt action to GuC!. Rather
 101          * than introducing yet another lock, we can just use ordered workqueue
 102          * to make sure we're always sending a single preemption request with a
 103          * single workitem.
 104          */
 105         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 106             USES_GUC_SUBMISSION(dev_priv)) {
 107                 guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
 108                                                           WQ_HIGHPRI);
 109                 if (!guc->preempt_wq) {
 110                         destroy_workqueue(guc->log.runtime.flush_wq);
 111                         return -ENOMEM;
 112                 }
 113         }
 114
 115         return 0;
 116 }
 117
 118 void intel_guc_fini_wq(struct intel_guc *guc)
 119 {
 120         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 121
 122         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 123             USES_GUC_SUBMISSION(dev_priv))
 124                 destroy_workqueue(guc->preempt_wq);
 125
 126         destroy_workqueue(guc->log.runtime.flush_wq);
 127 }
 128
 129 static int guc_shared_data_create(struct intel_guc *guc)
 130 {
 131         struct i915_vma *vma;
 132         void *vaddr;
 133
 134         vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
 135         if (IS_ERR(vma))
 136                 return PTR_ERR(vma);
 137
 138         vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
 139         if (IS_ERR(vaddr)) {
 140                 i915_vma_unpin_and_release(&vma);
 141                 return PTR_ERR(vaddr);
 142         }
 143
 144         guc->shared_data = vma;
 145         guc->shared_data_vaddr = vaddr;
 146
 147         return 0;
 148 }
 149
 150 static void guc_shared_data_destroy(struct intel_guc *guc)
 151 {
 152         i915_gem_object_unpin_map(guc->shared_data->obj);
 153         i915_vma_unpin_and_release(&guc->shared_data);
 154 }
 155
 156 int intel_guc_init(struct intel_guc *guc)
 157 {
 158         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 159         int ret;
 160
 161         ret = guc_shared_data_create(guc);
 162         if (ret)
 163                 return ret;
 164         GEM_BUG_ON(!guc->shared_data);
 165
 166         /* We need to notify the guc whenever we change the GGTT */
 167         i915_ggtt_enable_guc(dev_priv);
 168
 169         return 0;
 170 }
 171
 172 void intel_guc_fini(struct intel_guc *guc)
 173 {
 174         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 175
 176         i915_ggtt_disable_guc(dev_priv);
 177         guc_shared_data_destroy(guc);
 178 }
 179
 180 static u32 get_gt_type(struct drm_i915_private *dev_priv)
 181 {
 182         /* XXX: GT type based on PCI device ID? field seems unused by fw */
 183         return 0;
 184 }
 185
 186 static u32 get_core_family(struct drm_i915_private *dev_priv)
 187 {
 188         u32 gen = INTEL_GEN(dev_priv);
 189
 190         switch (gen) {
 191         case 9:
 192                 return GUC_CORE_FAMILY_GEN9;
 193
 194         default:
 195                 MISSING_CASE(gen);
 196                 return GUC_CORE_FAMILY_UNKNOWN;
 197         }
 198 }
 199
 200 /*
 201  * Initialise the GuC parameter block before starting the firmware
 202  * transfer. These parameters are read by the firmware on startup
 203  * and cannot be changed thereafter.
 204  */
 205 void intel_guc_init_params(struct intel_guc *guc)
 206 {
 207         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 208         u32 params[GUC_CTL_MAX_DWORDS];
 209         int i;
 210
 211         memset(params, 0, sizeof(params));
 212
 213         params[GUC_CTL_DEVICE_INFO] |=
 214                 (get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
 215                 (get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
 216
 217         /*
 218          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 219          * second. This ARAR is calculated by:
 220          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 221          */
 222         params[GUC_CTL_ARAT_HIGH] = 0;
 223         params[GUC_CTL_ARAT_LOW] = 100000000;
 224
 225         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 226
 227         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 228                         GUC_CTL_VCS2_ENABLED;
 229
 230         params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 231
 232         if (i915_modparams.guc_log_level >= 0) {
 233                 params[GUC_CTL_DEBUG] =
 234                         i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
 235         } else {
 236                 params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
 237         }
 238
 239         /* If GuC submission is enabled, set up additional parameters here */
 240         if (USES_GUC_SUBMISSION(dev_priv)) {
 241                 u32 ads = guc_ggtt_offset(guc->ads_vma) >> PAGE_SHIFT;
 242                 u32 pgs = guc_ggtt_offset(dev_priv->guc.stage_desc_pool);
 243                 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
 244
 245                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 246                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 247
 248                 pgs >>= PAGE_SHIFT;
 249                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 250                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 251
 252                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 253
 254                 /* Unmask this bit to enable the GuC's internal scheduler */
 255                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 256         }
 257
 258         /*
 259          * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
 260          * they are power context saved so it's ok to release forcewake
 261          * when we are done here and take it again at xfer time.
 262          */
 263         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
 264
 265         I915_WRITE(SOFT_SCRATCH(0), 0);
 266
 267         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 268                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 269
 270         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
 271 }
 272
 273 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
 274 {
 275         WARN(1, "Unexpected send: action=%#x\n", *action);
 276         return -ENODEV;
 277 }
 278
 279 /*
 280  * This function implements the MMIO based host to GuC interface.
 281  */
 282 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
 283 {
 284         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 285         u32 status;
 286         int i;
 287         int ret;
 288
 289         GEM_BUG_ON(!len);
 290         GEM_BUG_ON(len > guc->send_regs.count);
 291
 292         /* If CT is available, we expect to use MMIO only during init/fini */
 293         GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
 294                 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
 295                 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
 296
 297         mutex_lock(&guc->send_mutex);
 298         intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
 299
 300         for (i = 0; i < len; i++)
 301                 I915_WRITE(guc_send_reg(guc, i), action[i]);
 302
 303         POSTING_READ(guc_send_reg(guc, i - 1));
 304
 305         intel_guc_notify(guc);
 306
 307         /*
 308          * No GuC command should ever take longer than 10ms.
 309          * Fast commands should still complete in 10us.
 310          */
 311         ret = __intel_wait_for_register_fw(dev_priv,
 312                                            guc_send_reg(guc, 0),
 313                                            INTEL_GUC_RECV_MASK,
 314                                            INTEL_GUC_RECV_MASK,
 315                                            10, 10, &status);
 316         if (status != INTEL_GUC_STATUS_SUCCESS) {
 317                 /*
 318                  * Either the GuC explicitly returned an error (which
 319                  * we convert to -EIO here) or no response at all was
 320                  * received within the timeout limit (-ETIMEDOUT)
 321                  */
 322                 if (ret != -ETIMEDOUT)
 323                         ret = -EIO;
 324
 325                 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
 326                          " ret=%d status=0x%08X response=0x%08X\n",
 327                          action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
 328         }
 329
 330         intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 331         mutex_unlock(&guc->send_mutex);
 332
 333         return ret;
 334 }
 335
 336 int intel_guc_sample_forcewake(struct intel_guc *guc)
 337 {
 338         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 339         u32 action[2];
 340
 341         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 342         /* WaRsDisableCoarsePowerGating:skl,bxt */
 343         if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 344                 action[1] = 0;
 345         else
 346                 /* bit 0 and 1 are for Render and Media domain separately */
 347                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 348
 349         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 350 }
 351
 352 /**
 353  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 354  * @guc: intel_guc structure
 355  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 356  *
 357  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 358  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 359  * intel_huc_auth().
 360  *
 361  * Return:      non-zero code on error
 362  */
 363 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 364 {
 365         u32 action[] = {
 366                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 367                 rsa_offset
 368         };
 369
 370         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 371 }
 372
 373 /**
 374  * intel_guc_suspend() - notify GuC entering suspend state
 375  * @dev_priv:   i915 device private
 376  */
 377 int intel_guc_suspend(struct drm_i915_private *dev_priv)
 378 {
 379         struct intel_guc *guc = &dev_priv->guc;
 380         u32 data[3];
 381
 382         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 383                 return 0;
 384
 385         gen9_disable_guc_interrupts(dev_priv);
 386
 387         data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
 388         /* any value greater than GUC_POWER_D0 */
 389         data[1] = GUC_POWER_D1;
 390         data[2] = guc_ggtt_offset(guc->shared_data);
 391
 392         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 393 }
 394
 395 /**
 396  * intel_guc_reset_engine() - ask GuC to reset an engine
 397  * @guc:        intel_guc structure
 398  * @engine:     engine to be reset
 399  */
 400 int intel_guc_reset_engine(struct intel_guc *guc,
 401                            struct intel_engine_cs *engine)
 402 {
 403         u32 data[7];
 404
 405         GEM_BUG_ON(!guc->execbuf_client);
 406
 407         data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
 408         data[1] = engine->guc_id;
 409         data[2] = 0;
 410         data[3] = 0;
 411         data[4] = 0;
 412         data[5] = guc->execbuf_client->stage_id;
 413         data[6] = guc_ggtt_offset(guc->shared_data);
 414
 415         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 416 }
 417
 418 /**
 419  * intel_guc_resume() - notify GuC resuming from suspend state
 420  * @dev_priv:   i915 device private
 421  */
 422 int intel_guc_resume(struct drm_i915_private *dev_priv)
 423 {
 424         struct intel_guc *guc = &dev_priv->guc;
 425         u32 data[3];
 426
 427         if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 428                 return 0;
 429
 430         if (i915_modparams.guc_log_level >= 0)
 431                 gen9_enable_guc_interrupts(dev_priv);
 432
 433         data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
 434         data[1] = GUC_POWER_D0;
 435         data[2] = guc_ggtt_offset(guc->shared_data);
 436
 437         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 438 }
 439
 440 /**
 441  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 442  * @guc:        the guc
 443  * @size:       size of area to allocate (both virtual space and memory)
 444  *
 445  * This is a wrapper to create an object for use with the GuC. In order to
 446  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 447  * both some backing storage and a range inside the Global GTT. We must pin
 448  * it in the GGTT somewhere other than than [0, GUC_WOPCM_TOP) because that
 449  * range is reserved inside GuC.
 450  *
 451  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 452  */
 453 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 454 {
 455         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 456         struct drm_i915_gem_object *obj;
 457         struct i915_vma *vma;
 458         int ret;
 459
 460         obj = i915_gem_object_create(dev_priv, size);
 461         if (IS_ERR(obj))
 462                 return ERR_CAST(obj);
 463
 464         vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
 465         if (IS_ERR(vma))
 466                 goto err;
 467
 468         ret = i915_vma_pin(vma, 0, PAGE_SIZE,
 469                            PIN_GLOBAL | PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 470         if (ret) {
 471                 vma = ERR_PTR(ret);
 472                 goto err;
 473         }
 474
 475         return vma;
 476
 477 err:
 478         i915_gem_object_put(obj);
 479         return vma;
 480 }
 481
 482 u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
 483 {
 484         u32 wopcm_size = GUC_WOPCM_TOP;
 485
 486         /* On BXT, the top of WOPCM is reserved for RC6 context */
 487         if (IS_GEN9_LP(dev_priv))
 488                 wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
 489
 490         return wopcm_size;
 491 }