drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45 #define DP_DPRX_ESI_LEN 14
  46
  47 /* Compliance test status bits  */
  48 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  49 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52
  53 struct dp_link_dpll {
  54         int clock;
  55         struct dpll dpll;
  56 };
  57
  58 static const struct dp_link_dpll gen4_dpll[] = {
  59         { 162000,
  60                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  61         { 270000,
  62                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  63 };
  64
  65 static const struct dp_link_dpll pch_dpll[] = {
  66         { 162000,
  67                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  68         { 270000,
  69                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  70 };
  71
  72 static const struct dp_link_dpll vlv_dpll[] = {
  73         { 162000,
  74                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  75         { 270000,
  76                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  77 };
  78
  79 /*
  80  * CHV supports eDP 1.4 that have  more link rates.
  81  * Below only provides the fixed rate but exclude variable rate.
  82  */
  83 static const struct dp_link_dpll chv_dpll[] = {
  84         /*
  85          * CHV requires to program fractional division for m2.
  86          * m2 is stored in fixed point format using formula below
  87          * (m2_int << 22) | m2_fraction
  88          */
  89         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  90                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  91         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  92                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  93         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  94                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  95 };
  96
  97 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  98                                   324000, 432000, 540000 };
  99 static const int skl_rates[] = { 162000, 216000, 270000,
 100                                   324000, 432000, 540000 };
 101 static const int cnl_rates[] = { 162000, 216000, 270000,
 102                                  324000, 432000, 540000,
 103                                  648000, 810000 };
 104 static const int default_rates[] = { 162000, 270000, 540000 };
 105
 106 /**
 107  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 108  * @intel_dp: DP struct
 109  *
 110  * If a CPU or PCH DP output is attached to an eDP panel, this function
 111  * will return true, and false otherwise.
 112  */
 113 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 114 {
 115         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 116
 117         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 118 }
 119
 120 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 121 {
 122         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 123
 124         return intel_dig_port->base.base.dev;
 125 }
 126
 127 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 128 {
 129         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 130 }
 131
 132 static void intel_dp_link_down(struct intel_encoder *encoder,
 133                                const struct intel_crtc_state *old_crtc_state);
 134 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 135 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 136 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 137                                            const struct intel_crtc_state *crtc_state);
 138 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 139                                       enum pipe pipe);
 140 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 141
 142 /* update sink rates from dpcd */
 143 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 144 {
 145         int i, max_rate;
 146
 147         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 148
 149         for (i = 0; i < ARRAY_SIZE(default_rates); i++) {
 150                 if (default_rates[i] > max_rate)
 151                         break;
 152                 intel_dp->sink_rates[i] = default_rates[i];
 153         }
 154
 155         intel_dp->num_sink_rates = i;
 156 }
 157
 158 /* Theoretical max between source and sink */
 159 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 160 {
 161         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 162 }
 163
 164 /* Theoretical max between source and sink */
 165 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 166 {
 167         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 168         int source_max = intel_dig_port->max_lanes;
 169         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 170
 171         return min(source_max, sink_max);
 172 }
 173
 174 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 175 {
 176         return intel_dp->max_link_lane_count;
 177 }
 178
 179 int
 180 intel_dp_link_required(int pixel_clock, int bpp)
 181 {
 182         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 183         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 184 }
 185
 186 int
 187 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 188 {
 189         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 190          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 191          * is transmitted every LS_Clk per lane, there is no need to account for
 192          * the channel encoding that is done in the PHY layer here.
 193          */
 194
 195         return max_link_clock * max_lanes;
 196 }
 197
 198 static int
 199 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 200 {
 201         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 202         struct intel_encoder *encoder = &intel_dig_port->base;
 203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 204         int max_dotclk = dev_priv->max_dotclk_freq;
 205         int ds_max_dotclk;
 206
 207         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 208
 209         if (type != DP_DS_PORT_TYPE_VGA)
 210                 return max_dotclk;
 211
 212         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 213                                                     intel_dp->downstream_ports);
 214
 215         if (ds_max_dotclk != 0)
 216                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 217
 218         return max_dotclk;
 219 }
 220
 221 static void
 222 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 223 {
 224         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 225         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 226         enum port port = dig_port->base.port;
 227         const int *source_rates;
 228         int size;
 229         u32 voltage;
 230
 231         /* This should only be done once */
 232         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 233
 234         if (IS_GEN9_LP(dev_priv)) {
 235                 source_rates = bxt_rates;
 236                 size = ARRAY_SIZE(bxt_rates);
 237         } else if (IS_CANNONLAKE(dev_priv)) {
 238                 source_rates = cnl_rates;
 239                 size = ARRAY_SIZE(cnl_rates);
 240                 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 241                 if (port == PORT_A || port == PORT_D ||
 242                     voltage == VOLTAGE_INFO_0_85V)
 243                         size -= 2;
 244         } else if (IS_GEN9_BC(dev_priv)) {
 245                 source_rates = skl_rates;
 246                 size = ARRAY_SIZE(skl_rates);
 247         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 248                    IS_BROADWELL(dev_priv)) {
 249                 source_rates = default_rates;
 250                 size = ARRAY_SIZE(default_rates);
 251         } else {
 252                 source_rates = default_rates;
 253                 size = ARRAY_SIZE(default_rates) - 1;
 254         }
 255
 256         intel_dp->source_rates = source_rates;
 257         intel_dp->num_source_rates = size;
 258 }
 259
 260 static int intersect_rates(const int *source_rates, int source_len,
 261                            const int *sink_rates, int sink_len,
 262                            int *common_rates)
 263 {
 264         int i = 0, j = 0, k = 0;
 265
 266         while (i < source_len && j < sink_len) {
 267                 if (source_rates[i] == sink_rates[j]) {
 268                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 269                                 return k;
 270                         common_rates[k] = source_rates[i];
 271                         ++k;
 272                         ++i;
 273                         ++j;
 274                 } else if (source_rates[i] < sink_rates[j]) {
 275                         ++i;
 276                 } else {
 277                         ++j;
 278                 }
 279         }
 280         return k;
 281 }
 282
 283 /* return index of rate in rates array, or -1 if not found */
 284 static int intel_dp_rate_index(const int *rates, int len, int rate)
 285 {
 286         int i;
 287
 288         for (i = 0; i < len; i++)
 289                 if (rate == rates[i])
 290                         return i;
 291
 292         return -1;
 293 }
 294
 295 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 296 {
 297         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 298
 299         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 300                                                      intel_dp->num_source_rates,
 301                                                      intel_dp->sink_rates,
 302                                                      intel_dp->num_sink_rates,
 303                                                      intel_dp->common_rates);
 304
 305         /* Paranoia, there should always be something in common. */
 306         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 307                 intel_dp->common_rates[0] = default_rates[0];
 308                 intel_dp->num_common_rates = 1;
 309         }
 310 }
 311
 312 /* get length of common rates potentially limited by max_rate */
 313 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 314                                           int max_rate)
 315 {
 316         const int *common_rates = intel_dp->common_rates;
 317         int i, common_len = intel_dp->num_common_rates;
 318
 319         /* Limit results by potentially reduced max rate */
 320         for (i = 0; i < common_len; i++) {
 321                 if (common_rates[common_len - i - 1] <= max_rate)
 322                         return common_len - i;
 323         }
 324
 325         return 0;
 326 }
 327
 328 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 329                                        uint8_t lane_count)
 330 {
 331         /*
 332          * FIXME: we need to synchronize the current link parameters with
 333          * hardware readout. Currently fast link training doesn't work on
 334          * boot-up.
 335          */
 336         if (link_rate == 0 ||
 337             link_rate > intel_dp->max_link_rate)
 338                 return false;
 339
 340         if (lane_count == 0 ||
 341             lane_count > intel_dp_max_lane_count(intel_dp))
 342                 return false;
 343
 344         return true;
 345 }
 346
 347 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 348                                             int link_rate, uint8_t lane_count)
 349 {
 350         int index;
 351
 352         index = intel_dp_rate_index(intel_dp->common_rates,
 353                                     intel_dp->num_common_rates,
 354                                     link_rate);
 355         if (index > 0) {
 356                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 357                 intel_dp->max_link_lane_count = lane_count;
 358         } else if (lane_count > 1) {
 359                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 360                 intel_dp->max_link_lane_count = lane_count >> 1;
 361         } else {
 362                 DRM_ERROR("Link Training Unsuccessful\n");
 363                 return -1;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static enum drm_mode_status
 370 intel_dp_mode_valid(struct drm_connector *connector,
 371                     struct drm_display_mode *mode)
 372 {
 373         struct intel_dp *intel_dp = intel_attached_dp(connector);
 374         struct intel_connector *intel_connector = to_intel_connector(connector);
 375         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 376         int target_clock = mode->clock;
 377         int max_rate, mode_rate, max_lanes, max_link_clock;
 378         int max_dotclk;
 379
 380         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 381
 382         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 383                 if (mode->hdisplay > fixed_mode->hdisplay)
 384                         return MODE_PANEL;
 385
 386                 if (mode->vdisplay > fixed_mode->vdisplay)
 387                         return MODE_PANEL;
 388
 389                 target_clock = fixed_mode->clock;
 390         }
 391
 392         max_link_clock = intel_dp_max_link_rate(intel_dp);
 393         max_lanes = intel_dp_max_lane_count(intel_dp);
 394
 395         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 396         mode_rate = intel_dp_link_required(target_clock, 18);
 397
 398         if (mode_rate > max_rate || target_clock > max_dotclk)
 399                 return MODE_CLOCK_HIGH;
 400
 401         if (mode->clock < 10000)
 402                 return MODE_CLOCK_LOW;
 403
 404         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 405                 return MODE_H_ILLEGAL;
 406
 407         return MODE_OK;
 408 }
 409
 410 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 411 {
 412         int     i;
 413         uint32_t v = 0;
 414
 415         if (src_bytes > 4)
 416                 src_bytes = 4;
 417         for (i = 0; i < src_bytes; i++)
 418                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 419         return v;
 420 }
 421
 422 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 423 {
 424         int i;
 425         if (dst_bytes > 4)
 426                 dst_bytes = 4;
 427         for (i = 0; i < dst_bytes; i++)
 428                 dst[i] = src >> ((3-i) * 8);
 429 }
 430
 431 static void
 432 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 433 static void
 434 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 435                                               bool force_disable_vdd);
 436 static void
 437 intel_dp_pps_init(struct intel_dp *intel_dp);
 438
 439 static void pps_lock(struct intel_dp *intel_dp)
 440 {
 441         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 442
 443         /*
 444          * See intel_power_sequencer_reset() why we need
 445          * a power domain reference here.
 446          */
 447         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 448
 449         mutex_lock(&dev_priv->pps_mutex);
 450 }
 451
 452 static void pps_unlock(struct intel_dp *intel_dp)
 453 {
 454         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 455
 456         mutex_unlock(&dev_priv->pps_mutex);
 457
 458         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 459 }
 460
 461 static void
 462 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 463 {
 464         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 465         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 466         enum pipe pipe = intel_dp->pps_pipe;
 467         bool pll_enabled, release_cl_override = false;
 468         enum dpio_phy phy = DPIO_PHY(pipe);
 469         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 470         uint32_t DP;
 471
 472         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 473                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 474                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 475                 return;
 476
 477         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 478                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 479
 480         /* Preserve the BIOS-computed detected bit. This is
 481          * supposed to be read-only.
 482          */
 483         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 484         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 485         DP |= DP_PORT_WIDTH(1);
 486         DP |= DP_LINK_TRAIN_PAT_1;
 487
 488         if (IS_CHERRYVIEW(dev_priv))
 489                 DP |= DP_PIPE_SELECT_CHV(pipe);
 490         else if (pipe == PIPE_B)
 491                 DP |= DP_PIPEB_SELECT;
 492
 493         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 494
 495         /*
 496          * The DPLL for the pipe must be enabled for this to work.
 497          * So enable temporarily it if it's not already enabled.
 498          */
 499         if (!pll_enabled) {
 500                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 501                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 502
 503                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 504                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 505                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 506                                   pipe_name(pipe));
 507                         return;
 508                 }
 509         }
 510
 511         /*
 512          * Similar magic as in intel_dp_enable_port().
 513          * We _must_ do this port enable + disable trick
 514          * to make this power seqeuencer lock onto the port.
 515          * Otherwise even VDD force bit won't work.
 516          */
 517         I915_WRITE(intel_dp->output_reg, DP);
 518         POSTING_READ(intel_dp->output_reg);
 519
 520         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 521         POSTING_READ(intel_dp->output_reg);
 522
 523         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 524         POSTING_READ(intel_dp->output_reg);
 525
 526         if (!pll_enabled) {
 527                 vlv_force_pll_off(dev_priv, pipe);
 528
 529                 if (release_cl_override)
 530                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 531         }
 532 }
 533
 534 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 535 {
 536         struct intel_encoder *encoder;
 537         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 538
 539         /*
 540          * We don't have power sequencer currently.
 541          * Pick one that's not used by other ports.
 542          */
 543         for_each_intel_encoder(&dev_priv->drm, encoder) {
 544                 struct intel_dp *intel_dp;
 545
 546                 if (encoder->type != INTEL_OUTPUT_DP &&
 547                     encoder->type != INTEL_OUTPUT_EDP)
 548                         continue;
 549
 550                 intel_dp = enc_to_intel_dp(&encoder->base);
 551
 552                 if (encoder->type == INTEL_OUTPUT_EDP) {
 553                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 554                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 555
 556                         if (intel_dp->pps_pipe != INVALID_PIPE)
 557                                 pipes &= ~(1 << intel_dp->pps_pipe);
 558                 } else {
 559                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 560
 561                         if (intel_dp->active_pipe != INVALID_PIPE)
 562                                 pipes &= ~(1 << intel_dp->active_pipe);
 563                 }
 564         }
 565
 566         if (pipes == 0)
 567                 return INVALID_PIPE;
 568
 569         return ffs(pipes) - 1;
 570 }
 571
 572 static enum pipe
 573 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 574 {
 575         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 576         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 577         enum pipe pipe;
 578
 579         lockdep_assert_held(&dev_priv->pps_mutex);
 580
 581         /* We should never land here with regular DP ports */
 582         WARN_ON(!intel_dp_is_edp(intel_dp));
 583
 584         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 585                 intel_dp->active_pipe != intel_dp->pps_pipe);
 586
 587         if (intel_dp->pps_pipe != INVALID_PIPE)
 588                 return intel_dp->pps_pipe;
 589
 590         pipe = vlv_find_free_pps(dev_priv);
 591
 592         /*
 593          * Didn't find one. This should not happen since there
 594          * are two power sequencers and up to two eDP ports.
 595          */
 596         if (WARN_ON(pipe == INVALID_PIPE))
 597                 pipe = PIPE_A;
 598
 599         vlv_steal_power_sequencer(dev_priv, pipe);
 600         intel_dp->pps_pipe = pipe;
 601
 602         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 603                       pipe_name(intel_dp->pps_pipe),
 604                       port_name(intel_dig_port->base.port));
 605
 606         /* init power sequencer on this pipe and port */
 607         intel_dp_init_panel_power_sequencer(intel_dp);
 608         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 609
 610         /*
 611          * Even vdd force doesn't work until we've made
 612          * the power sequencer lock in on the port.
 613          */
 614         vlv_power_sequencer_kick(intel_dp);
 615
 616         return intel_dp->pps_pipe;
 617 }
 618
 619 static int
 620 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 621 {
 622         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 623         int backlight_controller = dev_priv->vbt.backlight.controller;
 624
 625         lockdep_assert_held(&dev_priv->pps_mutex);
 626
 627         /* We should never land here with regular DP ports */
 628         WARN_ON(!intel_dp_is_edp(intel_dp));
 629
 630         if (!intel_dp->pps_reset)
 631                 return backlight_controller;
 632
 633         intel_dp->pps_reset = false;
 634
 635         /*
 636          * Only the HW needs to be reprogrammed, the SW state is fixed and
 637          * has been setup during connector init.
 638          */
 639         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 640
 641         return backlight_controller;
 642 }
 643
 644 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 645                                enum pipe pipe);
 646
 647 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 648                                enum pipe pipe)
 649 {
 650         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 651 }
 652
 653 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 654                                 enum pipe pipe)
 655 {
 656         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 657 }
 658
 659 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 660                          enum pipe pipe)
 661 {
 662         return true;
 663 }
 664
 665 static enum pipe
 666 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 667                      enum port port,
 668                      vlv_pipe_check pipe_check)
 669 {
 670         enum pipe pipe;
 671
 672         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 673                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 674                         PANEL_PORT_SELECT_MASK;
 675
 676                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 677                         continue;
 678
 679                 if (!pipe_check(dev_priv, pipe))
 680                         continue;
 681
 682                 return pipe;
 683         }
 684
 685         return INVALID_PIPE;
 686 }
 687
 688 static void
 689 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 690 {
 691         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 692         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 693         enum port port = intel_dig_port->base.port;
 694
 695         lockdep_assert_held(&dev_priv->pps_mutex);
 696
 697         /* try to find a pipe with this port selected */
 698         /* first pick one where the panel is on */
 699         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 700                                                   vlv_pipe_has_pp_on);
 701         /* didn't find one? pick one where vdd is on */
 702         if (intel_dp->pps_pipe == INVALID_PIPE)
 703                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 704                                                           vlv_pipe_has_vdd_on);
 705         /* didn't find one? pick one with just the correct port */
 706         if (intel_dp->pps_pipe == INVALID_PIPE)
 707                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 708                                                           vlv_pipe_any);
 709
 710         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 711         if (intel_dp->pps_pipe == INVALID_PIPE) {
 712                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 713                               port_name(port));
 714                 return;
 715         }
 716
 717         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 718                       port_name(port), pipe_name(intel_dp->pps_pipe));
 719
 720         intel_dp_init_panel_power_sequencer(intel_dp);
 721         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 722 }
 723
 724 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 725 {
 726         struct intel_encoder *encoder;
 727
 728         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 729                     !IS_GEN9_LP(dev_priv)))
 730                 return;
 731
 732         /*
 733          * We can't grab pps_mutex here due to deadlock with power_domain
 734          * mutex when power_domain functions are called while holding pps_mutex.
 735          * That also means that in order to use pps_pipe the code needs to
 736          * hold both a power domain reference and pps_mutex, and the power domain
 737          * reference get/put must be done while _not_ holding pps_mutex.
 738          * pps_{lock,unlock}() do these steps in the correct order, so one
 739          * should use them always.
 740          */
 741
 742         for_each_intel_encoder(&dev_priv->drm, encoder) {
 743                 struct intel_dp *intel_dp;
 744
 745                 if (encoder->type != INTEL_OUTPUT_DP &&
 746                     encoder->type != INTEL_OUTPUT_EDP &&
 747                     encoder->type != INTEL_OUTPUT_DDI)
 748                         continue;
 749
 750                 intel_dp = enc_to_intel_dp(&encoder->base);
 751
 752                 /* Skip pure DVI/HDMI DDI encoders */
 753                 if (!i915_mmio_reg_valid(intel_dp->output_reg))
 754                         continue;
 755
 756                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 757
 758                 if (encoder->type != INTEL_OUTPUT_EDP)
 759                         continue;
 760
 761                 if (IS_GEN9_LP(dev_priv))
 762                         intel_dp->pps_reset = true;
 763                 else
 764                         intel_dp->pps_pipe = INVALID_PIPE;
 765         }
 766 }
 767
 768 struct pps_registers {
 769         i915_reg_t pp_ctrl;
 770         i915_reg_t pp_stat;
 771         i915_reg_t pp_on;
 772         i915_reg_t pp_off;
 773         i915_reg_t pp_div;
 774 };
 775
 776 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 777                                     struct pps_registers *regs)
 778 {
 779         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 780         int pps_idx = 0;
 781
 782         memset(regs, 0, sizeof(*regs));
 783
 784         if (IS_GEN9_LP(dev_priv))
 785                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 786         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 787                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 788
 789         regs->pp_ctrl = PP_CONTROL(pps_idx);
 790         regs->pp_stat = PP_STATUS(pps_idx);
 791         regs->pp_on = PP_ON_DELAYS(pps_idx);
 792         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 793         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
 794                 regs->pp_div = PP_DIVISOR(pps_idx);
 795 }
 796
 797 static i915_reg_t
 798 _pp_ctrl_reg(struct intel_dp *intel_dp)
 799 {
 800         struct pps_registers regs;
 801
 802         intel_pps_get_registers(intel_dp, &regs);
 803
 804         return regs.pp_ctrl;
 805 }
 806
 807 static i915_reg_t
 808 _pp_stat_reg(struct intel_dp *intel_dp)
 809 {
 810         struct pps_registers regs;
 811
 812         intel_pps_get_registers(intel_dp, &regs);
 813
 814         return regs.pp_stat;
 815 }
 816
 817 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 818    This function only applicable when panel PM state is not to be tracked */
 819 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 820                               void *unused)
 821 {
 822         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 823                                                  edp_notifier);
 824         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 825
 826         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 827                 return 0;
 828
 829         pps_lock(intel_dp);
 830
 831         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 832                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 833                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 834                 u32 pp_div;
 835
 836                 pp_ctrl_reg = PP_CONTROL(pipe);
 837                 pp_div_reg  = PP_DIVISOR(pipe);
 838                 pp_div = I915_READ(pp_div_reg);
 839                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 840
 841                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 842                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 843                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 844                 msleep(intel_dp->panel_power_cycle_delay);
 845         }
 846
 847         pps_unlock(intel_dp);
 848
 849         return 0;
 850 }
 851
 852 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 853 {
 854         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 855
 856         lockdep_assert_held(&dev_priv->pps_mutex);
 857
 858         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 859             intel_dp->pps_pipe == INVALID_PIPE)
 860                 return false;
 861
 862         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 863 }
 864
 865 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 866 {
 867         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 868
 869         lockdep_assert_held(&dev_priv->pps_mutex);
 870
 871         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 872             intel_dp->pps_pipe == INVALID_PIPE)
 873                 return false;
 874
 875         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 876 }
 877
 878 static void
 879 intel_dp_check_edp(struct intel_dp *intel_dp)
 880 {
 881         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 882
 883         if (!intel_dp_is_edp(intel_dp))
 884                 return;
 885
 886         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 887                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 888                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 889                               I915_READ(_pp_stat_reg(intel_dp)),
 890                               I915_READ(_pp_ctrl_reg(intel_dp)));
 891         }
 892 }
 893
 894 static uint32_t
 895 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 896 {
 897         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 898         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 899         uint32_t status;
 900         bool done;
 901
 902 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 903         if (has_aux_irq)
 904                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 905                                           msecs_to_jiffies_timeout(10));
 906         else
 907                 done = wait_for(C, 10) == 0;
 908         if (!done)
 909                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 910                           has_aux_irq);
 911 #undef C
 912
 913         return status;
 914 }
 915
 916 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 917 {
 918         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 919         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 920
 921         if (index)
 922                 return 0;
 923
 924         /*
 925          * The clock divider is based off the hrawclk, and would like to run at
 926          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 927          */
 928         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 929 }
 930
 931 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 932 {
 933         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 934         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 935
 936         if (index)
 937                 return 0;
 938
 939         /*
 940          * The clock divider is based off the cdclk or PCH rawclk, and would
 941          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 942          * divide by 2000 and use that
 943          */
 944         if (intel_dig_port->base.port == PORT_A)
 945                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 946         else
 947                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 948 }
 949
 950 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 951 {
 952         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 953         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 954
 955         if (intel_dig_port->base.port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 956                 /* Workaround for non-ULT HSW */
 957                 switch (index) {
 958                 case 0: return 63;
 959                 case 1: return 72;
 960                 default: return 0;
 961                 }
 962         }
 963
 964         return ilk_get_aux_clock_divider(intel_dp, index);
 965 }
 966
 967 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 968 {
 969         /*
 970          * SKL doesn't need us to program the AUX clock divider (Hardware will
 971          * derive the clock from CDCLK automatically). We still implement the
 972          * get_aux_clock_divider vfunc to plug-in into the existing code.
 973          */
 974         return index ? 0 : 1;
 975 }
 976
 977 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 978                                      bool has_aux_irq,
 979                                      int send_bytes,
 980                                      uint32_t aux_clock_divider)
 981 {
 982         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 983         struct drm_i915_private *dev_priv =
 984                         to_i915(intel_dig_port->base.base.dev);
 985         uint32_t precharge, timeout;
 986
 987         if (IS_GEN6(dev_priv))
 988                 precharge = 3;
 989         else
 990                 precharge = 5;
 991
 992         if (IS_BROADWELL(dev_priv))
 993                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 994         else
 995                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 996
 997         return DP_AUX_CH_CTL_SEND_BUSY |
 998                DP_AUX_CH_CTL_DONE |
 999                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1000                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1001                timeout |
1002                DP_AUX_CH_CTL_RECEIVE_ERROR |
1003                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1004                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1005                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1006 }
1007
1008 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1009                                       bool has_aux_irq,
1010                                       int send_bytes,
1011                                       uint32_t unused)
1012 {
1013         return DP_AUX_CH_CTL_SEND_BUSY |
1014                DP_AUX_CH_CTL_DONE |
1015                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1016                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1017                DP_AUX_CH_CTL_TIME_OUT_MAX |
1018                DP_AUX_CH_CTL_RECEIVE_ERROR |
1019                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1020                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1021                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1022 }
1023
1024 static int
1025 intel_dp_aux_ch(struct intel_dp *intel_dp,
1026                 const uint8_t *send, int send_bytes,
1027                 uint8_t *recv, int recv_size)
1028 {
1029         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1030         struct drm_i915_private *dev_priv =
1031                         to_i915(intel_dig_port->base.base.dev);
1032         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1033         uint32_t aux_clock_divider;
1034         int i, ret, recv_bytes;
1035         uint32_t status;
1036         int try, clock = 0;
1037         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1038         bool vdd;
1039
1040         pps_lock(intel_dp);
1041
1042         /*
1043          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1044          * In such cases we want to leave VDD enabled and it's up to upper layers
1045          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1046          * ourselves.
1047          */
1048         vdd = edp_panel_vdd_on(intel_dp);
1049
1050         /* dp aux is extremely sensitive to irq latency, hence request the
1051          * lowest possible wakeup latency and so prevent the cpu from going into
1052          * deep sleep states.
1053          */
1054         pm_qos_update_request(&dev_priv->pm_qos, 0);
1055
1056         intel_dp_check_edp(intel_dp);
1057
1058         /* Try to wait for any previous AUX channel activity */
1059         for (try = 0; try < 3; try++) {
1060                 status = I915_READ_NOTRACE(ch_ctl);
1061                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1062                         break;
1063                 msleep(1);
1064         }
1065
1066         if (try == 3) {
1067                 static u32 last_status = -1;
1068                 const u32 status = I915_READ(ch_ctl);
1069
1070                 if (status != last_status) {
1071                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1072                              status);
1073                         last_status = status;
1074                 }
1075
1076                 ret = -EBUSY;
1077                 goto out;
1078         }
1079
1080         /* Only 5 data registers! */
1081         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1082                 ret = -E2BIG;
1083                 goto out;
1084         }
1085
1086         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1087                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1088                                                           has_aux_irq,
1089                                                           send_bytes,
1090                                                           aux_clock_divider);
1091
1092                 /* Must try at least 3 times according to DP spec */
1093                 for (try = 0; try < 5; try++) {
1094                         /* Load the send data into the aux channel data registers */
1095                         for (i = 0; i < send_bytes; i += 4)
1096                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1097                                            intel_dp_pack_aux(send + i,
1098                                                              send_bytes - i));
1099
1100                         /* Send the command and wait for it to complete */
1101                         I915_WRITE(ch_ctl, send_ctl);
1102
1103                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1104
1105                         /* Clear done status and any errors */
1106                         I915_WRITE(ch_ctl,
1107                                    status |
1108                                    DP_AUX_CH_CTL_DONE |
1109                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1110                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1111
1112                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1113                                 continue;
1114
1115                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1116                          *   400us delay required for errors and timeouts
1117                          *   Timeout errors from the HW already meet this
1118                          *   requirement so skip to next iteration
1119                          */
1120                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1121                                 usleep_range(400, 500);
1122                                 continue;
1123                         }
1124                         if (status & DP_AUX_CH_CTL_DONE)
1125                                 goto done;
1126                 }
1127         }
1128
1129         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1130                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1131                 ret = -EBUSY;
1132                 goto out;
1133         }
1134
1135 done:
1136         /* Check for timeout or receive error.
1137          * Timeouts occur when the sink is not connected
1138          */
1139         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1140                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1141                 ret = -EIO;
1142                 goto out;
1143         }
1144
1145         /* Timeouts occur when the device isn't connected, so they're
1146          * "normal" -- don't fill the kernel log with these */
1147         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1148                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1149                 ret = -ETIMEDOUT;
1150                 goto out;
1151         }
1152
1153         /* Unload any bytes sent back from the other side */
1154         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1155                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1156
1157         /*
1158          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1159          * We have no idea of what happened so we return -EBUSY so
1160          * drm layer takes care for the necessary retries.
1161          */
1162         if (recv_bytes == 0 || recv_bytes > 20) {
1163                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1164                               recv_bytes);
1165                 /*
1166                  * FIXME: This patch was created on top of a series that
1167                  * organize the retries at drm level. There EBUSY should
1168                  * also take care for 1ms wait before retrying.
1169                  * That aux retries re-org is still needed and after that is
1170                  * merged we remove this sleep from here.
1171                  */
1172                 usleep_range(1000, 1500);
1173                 ret = -EBUSY;
1174                 goto out;
1175         }
1176
1177         if (recv_bytes > recv_size)
1178                 recv_bytes = recv_size;
1179
1180         for (i = 0; i < recv_bytes; i += 4)
1181                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1182                                     recv + i, recv_bytes - i);
1183
1184         ret = recv_bytes;
1185 out:
1186         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1187
1188         if (vdd)
1189                 edp_panel_vdd_off(intel_dp, false);
1190
1191         pps_unlock(intel_dp);
1192
1193         return ret;
1194 }
1195
1196 #define BARE_ADDRESS_SIZE       3
1197 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1198 static ssize_t
1199 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1200 {
1201         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1202         uint8_t txbuf[20], rxbuf[20];
1203         size_t txsize, rxsize;
1204         int ret;
1205
1206         txbuf[0] = (msg->request << 4) |
1207                 ((msg->address >> 16) & 0xf);
1208         txbuf[1] = (msg->address >> 8) & 0xff;
1209         txbuf[2] = msg->address & 0xff;
1210         txbuf[3] = msg->size - 1;
1211
1212         switch (msg->request & ~DP_AUX_I2C_MOT) {
1213         case DP_AUX_NATIVE_WRITE:
1214         case DP_AUX_I2C_WRITE:
1215         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1216                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1217                 rxsize = 2; /* 0 or 1 data bytes */
1218
1219                 if (WARN_ON(txsize > 20))
1220                         return -E2BIG;
1221
1222                 WARN_ON(!msg->buffer != !msg->size);
1223
1224                 if (msg->buffer)
1225                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1226
1227                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1228                 if (ret > 0) {
1229                         msg->reply = rxbuf[0] >> 4;
1230
1231                         if (ret > 1) {
1232                                 /* Number of bytes written in a short write. */
1233                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1234                         } else {
1235                                 /* Return payload size. */
1236                                 ret = msg->size;
1237                         }
1238                 }
1239                 break;
1240
1241         case DP_AUX_NATIVE_READ:
1242         case DP_AUX_I2C_READ:
1243                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1244                 rxsize = msg->size + 1;
1245
1246                 if (WARN_ON(rxsize > 20))
1247                         return -E2BIG;
1248
1249                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1250                 if (ret > 0) {
1251                         msg->reply = rxbuf[0] >> 4;
1252                         /*
1253                          * Assume happy day, and copy the data. The caller is
1254                          * expected to check msg->reply before touching it.
1255                          *
1256                          * Return payload size.
1257                          */
1258                         ret--;
1259                         memcpy(msg->buffer, rxbuf + 1, ret);
1260                 }
1261                 break;
1262
1263         default:
1264                 ret = -EINVAL;
1265                 break;
1266         }
1267
1268         return ret;
1269 }
1270
1271 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1272                                 enum port port)
1273 {
1274         const struct ddi_vbt_port_info *info =
1275                 &dev_priv->vbt.ddi_port_info[port];
1276         enum port aux_port;
1277
1278         if (!info->alternate_aux_channel) {
1279                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1280                               port_name(port), port_name(port));
1281                 return port;
1282         }
1283
1284         switch (info->alternate_aux_channel) {
1285         case DP_AUX_A:
1286                 aux_port = PORT_A;
1287                 break;
1288         case DP_AUX_B:
1289                 aux_port = PORT_B;
1290                 break;
1291         case DP_AUX_C:
1292                 aux_port = PORT_C;
1293                 break;
1294         case DP_AUX_D:
1295                 aux_port = PORT_D;
1296                 break;
1297         default:
1298                 MISSING_CASE(info->alternate_aux_channel);
1299                 aux_port = PORT_A;
1300                 break;
1301         }
1302
1303         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1304                       port_name(aux_port), port_name(port));
1305
1306         return aux_port;
1307 }
1308
1309 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1310                                   enum port port)
1311 {
1312         switch (port) {
1313         case PORT_B:
1314         case PORT_C:
1315         case PORT_D:
1316                 return DP_AUX_CH_CTL(port);
1317         default:
1318                 MISSING_CASE(port);
1319                 return DP_AUX_CH_CTL(PORT_B);
1320         }
1321 }
1322
1323 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1324                                    enum port port, int index)
1325 {
1326         switch (port) {
1327         case PORT_B:
1328         case PORT_C:
1329         case PORT_D:
1330                 return DP_AUX_CH_DATA(port, index);
1331         default:
1332                 MISSING_CASE(port);
1333                 return DP_AUX_CH_DATA(PORT_B, index);
1334         }
1335 }
1336
1337 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1338                                   enum port port)
1339 {
1340         switch (port) {
1341         case PORT_A:
1342                 return DP_AUX_CH_CTL(port);
1343         case PORT_B:
1344         case PORT_C:
1345         case PORT_D:
1346                 return PCH_DP_AUX_CH_CTL(port);
1347         default:
1348                 MISSING_CASE(port);
1349                 return DP_AUX_CH_CTL(PORT_A);
1350         }
1351 }
1352
1353 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1354                                    enum port port, int index)
1355 {
1356         switch (port) {
1357         case PORT_A:
1358                 return DP_AUX_CH_DATA(port, index);
1359         case PORT_B:
1360         case PORT_C:
1361         case PORT_D:
1362                 return PCH_DP_AUX_CH_DATA(port, index);
1363         default:
1364                 MISSING_CASE(port);
1365                 return DP_AUX_CH_DATA(PORT_A, index);
1366         }
1367 }
1368
1369 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1370                                   enum port port)
1371 {
1372         switch (port) {
1373         case PORT_A:
1374         case PORT_B:
1375         case PORT_C:
1376         case PORT_D:
1377                 return DP_AUX_CH_CTL(port);
1378         default:
1379                 MISSING_CASE(port);
1380                 return DP_AUX_CH_CTL(PORT_A);
1381         }
1382 }
1383
1384 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1385                                    enum port port, int index)
1386 {
1387         switch (port) {
1388         case PORT_A:
1389         case PORT_B:
1390         case PORT_C:
1391         case PORT_D:
1392                 return DP_AUX_CH_DATA(port, index);
1393         default:
1394                 MISSING_CASE(port);
1395                 return DP_AUX_CH_DATA(PORT_A, index);
1396         }
1397 }
1398
1399 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1400                                     enum port port)
1401 {
1402         if (INTEL_INFO(dev_priv)->gen >= 9)
1403                 return skl_aux_ctl_reg(dev_priv, port);
1404         else if (HAS_PCH_SPLIT(dev_priv))
1405                 return ilk_aux_ctl_reg(dev_priv, port);
1406         else
1407                 return g4x_aux_ctl_reg(dev_priv, port);
1408 }
1409
1410 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1411                                      enum port port, int index)
1412 {
1413         if (INTEL_INFO(dev_priv)->gen >= 9)
1414                 return skl_aux_data_reg(dev_priv, port, index);
1415         else if (HAS_PCH_SPLIT(dev_priv))
1416                 return ilk_aux_data_reg(dev_priv, port, index);
1417         else
1418                 return g4x_aux_data_reg(dev_priv, port, index);
1419 }
1420
1421 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1422 {
1423         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1424         enum port port = intel_aux_port(dev_priv,
1425                                         dp_to_dig_port(intel_dp)->base.port);
1426         int i;
1427
1428         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1429         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1430                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1431 }
1432
1433 static void
1434 intel_dp_aux_fini(struct intel_dp *intel_dp)
1435 {
1436         kfree(intel_dp->aux.name);
1437 }
1438
1439 static void
1440 intel_dp_aux_init(struct intel_dp *intel_dp)
1441 {
1442         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1443         enum port port = intel_dig_port->base.port;
1444
1445         intel_aux_reg_init(intel_dp);
1446         drm_dp_aux_init(&intel_dp->aux);
1447
1448         /* Failure to allocate our preferred name is not critical */
1449         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1450         intel_dp->aux.transfer = intel_dp_aux_transfer;
1451 }
1452
1453 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1454 {
1455         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1456
1457         return max_rate >= 540000;
1458 }
1459
1460 static void
1461 intel_dp_set_clock(struct intel_encoder *encoder,
1462                    struct intel_crtc_state *pipe_config)
1463 {
1464         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1465         const struct dp_link_dpll *divisor = NULL;
1466         int i, count = 0;
1467
1468         if (IS_G4X(dev_priv)) {
1469                 divisor = gen4_dpll;
1470                 count = ARRAY_SIZE(gen4_dpll);
1471         } else if (HAS_PCH_SPLIT(dev_priv)) {
1472                 divisor = pch_dpll;
1473                 count = ARRAY_SIZE(pch_dpll);
1474         } else if (IS_CHERRYVIEW(dev_priv)) {
1475                 divisor = chv_dpll;
1476                 count = ARRAY_SIZE(chv_dpll);
1477         } else if (IS_VALLEYVIEW(dev_priv)) {
1478                 divisor = vlv_dpll;
1479                 count = ARRAY_SIZE(vlv_dpll);
1480         }
1481
1482         if (divisor && count) {
1483                 for (i = 0; i < count; i++) {
1484                         if (pipe_config->port_clock == divisor[i].clock) {
1485                                 pipe_config->dpll = divisor[i].dpll;
1486                                 pipe_config->clock_set = true;
1487                                 break;
1488                         }
1489                 }
1490         }
1491 }
1492
1493 static void snprintf_int_array(char *str, size_t len,
1494                                const int *array, int nelem)
1495 {
1496         int i;
1497
1498         str[0] = '\0';
1499
1500         for (i = 0; i < nelem; i++) {
1501                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1502                 if (r >= len)
1503                         return;
1504                 str += r;
1505                 len -= r;
1506         }
1507 }
1508
1509 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1510 {
1511         char str[128]; /* FIXME: too big for stack? */
1512
1513         if ((drm_debug & DRM_UT_KMS) == 0)
1514                 return;
1515
1516         snprintf_int_array(str, sizeof(str),
1517                            intel_dp->source_rates, intel_dp->num_source_rates);
1518         DRM_DEBUG_KMS("source rates: %s\n", str);
1519
1520         snprintf_int_array(str, sizeof(str),
1521                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1522         DRM_DEBUG_KMS("sink rates: %s\n", str);
1523
1524         snprintf_int_array(str, sizeof(str),
1525                            intel_dp->common_rates, intel_dp->num_common_rates);
1526         DRM_DEBUG_KMS("common rates: %s\n", str);
1527 }
1528
1529 int
1530 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1531 {
1532         int len;
1533
1534         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1535         if (WARN_ON(len <= 0))
1536                 return 162000;
1537
1538         return intel_dp->common_rates[len - 1];
1539 }
1540
1541 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1542 {
1543         int i = intel_dp_rate_index(intel_dp->sink_rates,
1544                                     intel_dp->num_sink_rates, rate);
1545
1546         if (WARN_ON(i < 0))
1547                 i = 0;
1548
1549         return i;
1550 }
1551
1552 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1553                            uint8_t *link_bw, uint8_t *rate_select)
1554 {
1555         /* eDP 1.4 rate select method. */
1556         if (intel_dp->use_rate_select) {
1557                 *link_bw = 0;
1558                 *rate_select =
1559                         intel_dp_rate_select(intel_dp, port_clock);
1560         } else {
1561                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1562                 *rate_select = 0;
1563         }
1564 }
1565
1566 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1567                                 struct intel_crtc_state *pipe_config)
1568 {
1569         int bpp, bpc;
1570
1571         bpp = pipe_config->pipe_bpp;
1572         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1573
1574         if (bpc > 0)
1575                 bpp = min(bpp, 3*bpc);
1576
1577         /* For DP Compliance we override the computed bpp for the pipe */
1578         if (intel_dp->compliance.test_data.bpc != 0) {
1579                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1580                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1581                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1582                               pipe_config->pipe_bpp);
1583         }
1584         return bpp;
1585 }
1586
1587 static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1,
1588                                        struct drm_display_mode *m2)
1589 {
1590         bool bres = false;
1591
1592         if (m1 && m2)
1593                 bres = (m1->hdisplay == m2->hdisplay &&
1594                         m1->hsync_start == m2->hsync_start &&
1595                         m1->hsync_end == m2->hsync_end &&
1596                         m1->htotal == m2->htotal &&
1597                         m1->vdisplay == m2->vdisplay &&
1598                         m1->vsync_start == m2->vsync_start &&
1599                         m1->vsync_end == m2->vsync_end &&
1600                         m1->vtotal == m2->vtotal);
1601         return bres;
1602 }
1603
1604 bool
1605 intel_dp_compute_config(struct intel_encoder *encoder,
1606                         struct intel_crtc_state *pipe_config,
1607                         struct drm_connector_state *conn_state)
1608 {
1609         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1610         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1611         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1612         enum port port = encoder->port;
1613         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1614         struct intel_connector *intel_connector = intel_dp->attached_connector;
1615         struct intel_digital_connector_state *intel_conn_state =
1616                 to_intel_digital_connector_state(conn_state);
1617         int lane_count, clock;
1618         int min_lane_count = 1;
1619         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1620         /* Conveniently, the link BW constants become indices with a shift...*/
1621         int min_clock = 0;
1622         int max_clock;
1623         int bpp, mode_rate;
1624         int link_avail, link_clock;
1625         int common_len;
1626         uint8_t link_bw, rate_select;
1627         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1628                                            DP_DPCD_QUIRK_LIMITED_M_N);
1629
1630         common_len = intel_dp_common_len_rate_limit(intel_dp,
1631                                                     intel_dp->max_link_rate);
1632
1633         /* No common link rates between source and sink */
1634         WARN_ON(common_len <= 0);
1635
1636         max_clock = common_len - 1;
1637
1638         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1639                 pipe_config->has_pch_encoder = true;
1640
1641         pipe_config->has_drrs = false;
1642         if (IS_G4X(dev_priv) || port == PORT_A)
1643                 pipe_config->has_audio = false;
1644         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1645                 pipe_config->has_audio = intel_dp->has_audio;
1646         else
1647                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1648
1649         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1650                 struct drm_display_mode *panel_mode =
1651                         intel_connector->panel.alt_fixed_mode;
1652                 struct drm_display_mode *req_mode = &pipe_config->base.mode;
1653
1654                 if (!intel_edp_compare_alt_mode(req_mode, panel_mode))
1655                         panel_mode = intel_connector->panel.fixed_mode;
1656
1657                 drm_mode_debug_printmodeline(panel_mode);
1658
1659                 intel_fixed_panel_mode(panel_mode, adjusted_mode);
1660
1661                 if (INTEL_GEN(dev_priv) >= 9) {
1662                         int ret;
1663                         ret = skl_update_scaler_crtc(pipe_config);
1664                         if (ret)
1665                                 return ret;
1666                 }
1667
1668                 if (HAS_GMCH_DISPLAY(dev_priv))
1669                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1670                                                  conn_state->scaling_mode);
1671                 else
1672                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1673                                                 conn_state->scaling_mode);
1674         }
1675
1676         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1677             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1678                 return false;
1679
1680         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1681                 return false;
1682
1683         /* Use values requested by Compliance Test Request */
1684         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1685                 int index;
1686
1687                 /* Validate the compliance test data since max values
1688                  * might have changed due to link train fallback.
1689                  */
1690                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1691                                                intel_dp->compliance.test_lane_count)) {
1692                         index = intel_dp_rate_index(intel_dp->common_rates,
1693                                                     intel_dp->num_common_rates,
1694                                                     intel_dp->compliance.test_link_rate);
1695                         if (index >= 0)
1696                                 min_clock = max_clock = index;
1697                         min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1698                 }
1699         }
1700         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1701                       "max bw %d pixel clock %iKHz\n",
1702                       max_lane_count, intel_dp->common_rates[max_clock],
1703                       adjusted_mode->crtc_clock);
1704
1705         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1706          * bpc in between. */
1707         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1708         if (intel_dp_is_edp(intel_dp)) {
1709
1710                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1711                 if (intel_connector->base.display_info.bpc == 0 &&
1712                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1713                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1714                                       dev_priv->vbt.edp.bpp);
1715                         bpp = dev_priv->vbt.edp.bpp;
1716                 }
1717
1718                 /*
1719                  * Use the maximum clock and number of lanes the eDP panel
1720                  * advertizes being capable of. The panels are generally
1721                  * designed to support only a single clock and lane
1722                  * configuration, and typically these values correspond to the
1723                  * native resolution of the panel.
1724                  */
1725                 min_lane_count = max_lane_count;
1726                 min_clock = max_clock;
1727         }
1728
1729         for (; bpp >= 6*3; bpp -= 2*3) {
1730                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1731                                                    bpp);
1732
1733                 for (clock = min_clock; clock <= max_clock; clock++) {
1734                         for (lane_count = min_lane_count;
1735                                 lane_count <= max_lane_count;
1736                                 lane_count <<= 1) {
1737
1738                                 link_clock = intel_dp->common_rates[clock];
1739                                 link_avail = intel_dp_max_data_rate(link_clock,
1740                                                                     lane_count);
1741
1742                                 if (mode_rate <= link_avail) {
1743                                         goto found;
1744                                 }
1745                         }
1746                 }
1747         }
1748
1749         return false;
1750
1751 found:
1752         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1753                 /*
1754                  * See:
1755                  * CEA-861-E - 5.1 Default Encoding Parameters
1756                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1757                  */
1758                 pipe_config->limited_color_range =
1759                         bpp != 18 &&
1760                         drm_default_rgb_quant_range(adjusted_mode) ==
1761                         HDMI_QUANTIZATION_RANGE_LIMITED;
1762         } else {
1763                 pipe_config->limited_color_range =
1764                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1765         }
1766
1767         pipe_config->lane_count = lane_count;
1768
1769         pipe_config->pipe_bpp = bpp;
1770         pipe_config->port_clock = intel_dp->common_rates[clock];
1771
1772         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1773                               &link_bw, &rate_select);
1774
1775         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1776                       link_bw, rate_select, pipe_config->lane_count,
1777                       pipe_config->port_clock, bpp);
1778         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1779                       mode_rate, link_avail);
1780
1781         intel_link_compute_m_n(bpp, lane_count,
1782                                adjusted_mode->crtc_clock,
1783                                pipe_config->port_clock,
1784                                &pipe_config->dp_m_n,
1785                                reduce_m_n);
1786
1787         if (intel_connector->panel.downclock_mode != NULL &&
1788                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1789                         pipe_config->has_drrs = true;
1790                         intel_link_compute_m_n(bpp, lane_count,
1791                                 intel_connector->panel.downclock_mode->clock,
1792                                 pipe_config->port_clock,
1793                                 &pipe_config->dp_m2_n2,
1794                                 reduce_m_n);
1795         }
1796
1797         /*
1798          * DPLL0 VCO may need to be adjusted to get the correct
1799          * clock for eDP. This will affect cdclk as well.
1800          */
1801         if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1802                 int vco;
1803
1804                 switch (pipe_config->port_clock / 2) {
1805                 case 108000:
1806                 case 216000:
1807                         vco = 8640000;
1808                         break;
1809                 default:
1810                         vco = 8100000;
1811                         break;
1812                 }
1813
1814                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1815         }
1816
1817         if (!HAS_DDI(dev_priv))
1818                 intel_dp_set_clock(encoder, pipe_config);
1819
1820         intel_psr_compute_config(intel_dp, pipe_config);
1821
1822         return true;
1823 }
1824
1825 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1826                               int link_rate, uint8_t lane_count,
1827                               bool link_mst)
1828 {
1829         intel_dp->link_rate = link_rate;
1830         intel_dp->lane_count = lane_count;
1831         intel_dp->link_mst = link_mst;
1832 }
1833
1834 static void intel_dp_prepare(struct intel_encoder *encoder,
1835                              const struct intel_crtc_state *pipe_config)
1836 {
1837         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1838         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1839         enum port port = encoder->port;
1840         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1841         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1842
1843         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1844                                  pipe_config->lane_count,
1845                                  intel_crtc_has_type(pipe_config,
1846                                                      INTEL_OUTPUT_DP_MST));
1847
1848         /*
1849          * There are four kinds of DP registers:
1850          *
1851          *      IBX PCH
1852          *      SNB CPU
1853          *      IVB CPU
1854          *      CPT PCH
1855          *
1856          * IBX PCH and CPU are the same for almost everything,
1857          * except that the CPU DP PLL is configured in this
1858          * register
1859          *
1860          * CPT PCH is quite different, having many bits moved
1861          * to the TRANS_DP_CTL register instead. That
1862          * configuration happens (oddly) in ironlake_pch_enable
1863          */
1864
1865         /* Preserve the BIOS-computed detected bit. This is
1866          * supposed to be read-only.
1867          */
1868         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1869
1870         /* Handle DP bits in common between all three register formats */
1871         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1872         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1873
1874         /* Split out the IBX/CPU vs CPT settings */
1875
1876         if (IS_GEN7(dev_priv) && port == PORT_A) {
1877                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1878                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1879                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1880                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1881                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1882
1883                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1884                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1885
1886                 intel_dp->DP |= crtc->pipe << 29;
1887         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1888                 u32 trans_dp;
1889
1890                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1891
1892                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1893                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1894                         trans_dp |= TRANS_DP_ENH_FRAMING;
1895                 else
1896                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1897                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1898         } else {
1899                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1900                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1901
1902                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1903                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1904                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1905                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1906                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1907
1908                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1909                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1910
1911                 if (IS_CHERRYVIEW(dev_priv))
1912                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1913                 else if (crtc->pipe == PIPE_B)
1914                         intel_dp->DP |= DP_PIPEB_SELECT;
1915         }
1916 }
1917
1918 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1919 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1920
1921 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1922 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1923
1924 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1925 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1926
1927 static void intel_pps_verify_state(struct intel_dp *intel_dp);
1928
1929 static void wait_panel_status(struct intel_dp *intel_dp,
1930                                        u32 mask,
1931                                        u32 value)
1932 {
1933         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1934         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1935
1936         lockdep_assert_held(&dev_priv->pps_mutex);
1937
1938         intel_pps_verify_state(intel_dp);
1939
1940         pp_stat_reg = _pp_stat_reg(intel_dp);
1941         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1942
1943         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1944                         mask, value,
1945                         I915_READ(pp_stat_reg),
1946                         I915_READ(pp_ctrl_reg));
1947
1948         if (intel_wait_for_register(dev_priv,
1949                                     pp_stat_reg, mask, value,
1950                                     5000))
1951                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1952                                 I915_READ(pp_stat_reg),
1953                                 I915_READ(pp_ctrl_reg));
1954
1955         DRM_DEBUG_KMS("Wait complete\n");
1956 }
1957
1958 static void wait_panel_on(struct intel_dp *intel_dp)
1959 {
1960         DRM_DEBUG_KMS("Wait for panel power on\n");
1961         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1962 }
1963
1964 static void wait_panel_off(struct intel_dp *intel_dp)
1965 {
1966         DRM_DEBUG_KMS("Wait for panel power off time\n");
1967         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1968 }
1969
1970 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1971 {
1972         ktime_t panel_power_on_time;
1973         s64 panel_power_off_duration;
1974
1975         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1976
1977         /* take the difference of currrent time and panel power off time
1978          * and then make panel wait for t11_t12 if needed. */
1979         panel_power_on_time = ktime_get_boottime();
1980         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1981
1982         /* When we disable the VDD override bit last we have to do the manual
1983          * wait. */
1984         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1985                 wait_remaining_ms_from_jiffies(jiffies,
1986                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1987
1988         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1989 }
1990
1991 static void wait_backlight_on(struct intel_dp *intel_dp)
1992 {
1993         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1994                                        intel_dp->backlight_on_delay);
1995 }
1996
1997 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1998 {
1999         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2000                                        intel_dp->backlight_off_delay);
2001 }
2002
2003 /* Read the current pp_control value, unlocking the register if it
2004  * is locked
2005  */
2006
2007 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2008 {
2009         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2010         u32 control;
2011
2012         lockdep_assert_held(&dev_priv->pps_mutex);
2013
2014         control = I915_READ(_pp_ctrl_reg(intel_dp));
2015         if (WARN_ON(!HAS_DDI(dev_priv) &&
2016                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2017                 control &= ~PANEL_UNLOCK_MASK;
2018                 control |= PANEL_UNLOCK_REGS;
2019         }
2020         return control;
2021 }
2022
2023 /*
2024  * Must be paired with edp_panel_vdd_off().
2025  * Must hold pps_mutex around the whole on/off sequence.
2026  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2027  */
2028 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2029 {
2030         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2031         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2032         u32 pp;
2033         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2034         bool need_to_disable = !intel_dp->want_panel_vdd;
2035
2036         lockdep_assert_held(&dev_priv->pps_mutex);
2037
2038         if (!intel_dp_is_edp(intel_dp))
2039                 return false;
2040
2041         cancel_delayed_work(&intel_dp->panel_vdd_work);
2042         intel_dp->want_panel_vdd = true;
2043
2044         if (edp_have_panel_vdd(intel_dp))
2045                 return need_to_disable;
2046
2047         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2048
2049         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2050                       port_name(intel_dig_port->base.port));
2051
2052         if (!edp_have_panel_power(intel_dp))
2053                 wait_panel_power_cycle(intel_dp);
2054
2055         pp = ironlake_get_pp_control(intel_dp);
2056         pp |= EDP_FORCE_VDD;
2057
2058         pp_stat_reg = _pp_stat_reg(intel_dp);
2059         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2060
2061         I915_WRITE(pp_ctrl_reg, pp);
2062         POSTING_READ(pp_ctrl_reg);
2063         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2064                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2065         /*
2066          * If the panel wasn't on, delay before accessing aux channel
2067          */
2068         if (!edp_have_panel_power(intel_dp)) {
2069                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2070                               port_name(intel_dig_port->base.port));
2071                 msleep(intel_dp->panel_power_up_delay);
2072         }
2073
2074         return need_to_disable;
2075 }
2076
2077 /*
2078  * Must be paired with intel_edp_panel_vdd_off() or
2079  * intel_edp_panel_off().
2080  * Nested calls to these functions are not allowed since
2081  * we drop the lock. Caller must use some higher level
2082  * locking to prevent nested calls from other threads.
2083  */
2084 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2085 {
2086         bool vdd;
2087
2088         if (!intel_dp_is_edp(intel_dp))
2089                 return;
2090
2091         pps_lock(intel_dp);
2092         vdd = edp_panel_vdd_on(intel_dp);
2093         pps_unlock(intel_dp);
2094
2095         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2096              port_name(dp_to_dig_port(intel_dp)->base.port));
2097 }
2098
2099 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2100 {
2101         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2102         struct intel_digital_port *intel_dig_port =
2103                 dp_to_dig_port(intel_dp);
2104         u32 pp;
2105         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2106
2107         lockdep_assert_held(&dev_priv->pps_mutex);
2108
2109         WARN_ON(intel_dp->want_panel_vdd);
2110
2111         if (!edp_have_panel_vdd(intel_dp))
2112                 return;
2113
2114         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2115                       port_name(intel_dig_port->base.port));
2116
2117         pp = ironlake_get_pp_control(intel_dp);
2118         pp &= ~EDP_FORCE_VDD;
2119
2120         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2121         pp_stat_reg = _pp_stat_reg(intel_dp);
2122
2123         I915_WRITE(pp_ctrl_reg, pp);
2124         POSTING_READ(pp_ctrl_reg);
2125
2126         /* Make sure sequencer is idle before allowing subsequent activity */
2127         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2128         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2129
2130         if ((pp & PANEL_POWER_ON) == 0)
2131                 intel_dp->panel_power_off_time = ktime_get_boottime();
2132
2133         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2134 }
2135
2136 static void edp_panel_vdd_work(struct work_struct *__work)
2137 {
2138         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2139                                                  struct intel_dp, panel_vdd_work);
2140
2141         pps_lock(intel_dp);
2142         if (!intel_dp->want_panel_vdd)
2143                 edp_panel_vdd_off_sync(intel_dp);
2144         pps_unlock(intel_dp);
2145 }
2146
2147 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2148 {
2149         unsigned long delay;
2150
2151         /*
2152          * Queue the timer to fire a long time from now (relative to the power
2153          * down delay) to keep the panel power up across a sequence of
2154          * operations.
2155          */
2156         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2157         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2158 }
2159
2160 /*
2161  * Must be paired with edp_panel_vdd_on().
2162  * Must hold pps_mutex around the whole on/off sequence.
2163  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2164  */
2165 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2166 {
2167         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2168
2169         lockdep_assert_held(&dev_priv->pps_mutex);
2170
2171         if (!intel_dp_is_edp(intel_dp))
2172                 return;
2173
2174         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2175              port_name(dp_to_dig_port(intel_dp)->base.port));
2176
2177         intel_dp->want_panel_vdd = false;
2178
2179         if (sync)
2180                 edp_panel_vdd_off_sync(intel_dp);
2181         else
2182                 edp_panel_vdd_schedule_off(intel_dp);
2183 }
2184
2185 static void edp_panel_on(struct intel_dp *intel_dp)
2186 {
2187         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2188         u32 pp;
2189         i915_reg_t pp_ctrl_reg;
2190
2191         lockdep_assert_held(&dev_priv->pps_mutex);
2192
2193         if (!intel_dp_is_edp(intel_dp))
2194                 return;
2195
2196         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2197                       port_name(dp_to_dig_port(intel_dp)->base.port));
2198
2199         if (WARN(edp_have_panel_power(intel_dp),
2200                  "eDP port %c panel power already on\n",
2201                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2202                 return;
2203
2204         wait_panel_power_cycle(intel_dp);
2205
2206         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2207         pp = ironlake_get_pp_control(intel_dp);
2208         if (IS_GEN5(dev_priv)) {
2209                 /* ILK workaround: disable reset around power sequence */
2210                 pp &= ~PANEL_POWER_RESET;
2211                 I915_WRITE(pp_ctrl_reg, pp);
2212                 POSTING_READ(pp_ctrl_reg);
2213         }
2214
2215         pp |= PANEL_POWER_ON;
2216         if (!IS_GEN5(dev_priv))
2217                 pp |= PANEL_POWER_RESET;
2218
2219         I915_WRITE(pp_ctrl_reg, pp);
2220         POSTING_READ(pp_ctrl_reg);
2221
2222         wait_panel_on(intel_dp);
2223         intel_dp->last_power_on = jiffies;
2224
2225         if (IS_GEN5(dev_priv)) {
2226                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2227                 I915_WRITE(pp_ctrl_reg, pp);
2228                 POSTING_READ(pp_ctrl_reg);
2229         }
2230 }
2231
2232 void intel_edp_panel_on(struct intel_dp *intel_dp)
2233 {
2234         if (!intel_dp_is_edp(intel_dp))
2235                 return;
2236
2237         pps_lock(intel_dp);
2238         edp_panel_on(intel_dp);
2239         pps_unlock(intel_dp);
2240 }
2241
2242
2243 static void edp_panel_off(struct intel_dp *intel_dp)
2244 {
2245         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2246         u32 pp;
2247         i915_reg_t pp_ctrl_reg;
2248
2249         lockdep_assert_held(&dev_priv->pps_mutex);
2250
2251         if (!intel_dp_is_edp(intel_dp))
2252                 return;
2253
2254         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2255                       port_name(dp_to_dig_port(intel_dp)->base.port));
2256
2257         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2258              port_name(dp_to_dig_port(intel_dp)->base.port));
2259
2260         pp = ironlake_get_pp_control(intel_dp);
2261         /* We need to switch off panel power _and_ force vdd, for otherwise some
2262          * panels get very unhappy and cease to work. */
2263         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2264                 EDP_BLC_ENABLE);
2265
2266         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2267
2268         intel_dp->want_panel_vdd = false;
2269
2270         I915_WRITE(pp_ctrl_reg, pp);
2271         POSTING_READ(pp_ctrl_reg);
2272
2273         wait_panel_off(intel_dp);
2274         intel_dp->panel_power_off_time = ktime_get_boottime();
2275
2276         /* We got a reference when we enabled the VDD. */
2277         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2278 }
2279
2280 void intel_edp_panel_off(struct intel_dp *intel_dp)
2281 {
2282         if (!intel_dp_is_edp(intel_dp))
2283                 return;
2284
2285         pps_lock(intel_dp);
2286         edp_panel_off(intel_dp);
2287         pps_unlock(intel_dp);
2288 }
2289
2290 /* Enable backlight in the panel power control. */
2291 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2292 {
2293         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2294         u32 pp;
2295         i915_reg_t pp_ctrl_reg;
2296
2297         /*
2298          * If we enable the backlight right away following a panel power
2299          * on, we may see slight flicker as the panel syncs with the eDP
2300          * link.  So delay a bit to make sure the image is solid before
2301          * allowing it to appear.
2302          */
2303         wait_backlight_on(intel_dp);
2304
2305         pps_lock(intel_dp);
2306
2307         pp = ironlake_get_pp_control(intel_dp);
2308         pp |= EDP_BLC_ENABLE;
2309
2310         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2311
2312         I915_WRITE(pp_ctrl_reg, pp);
2313         POSTING_READ(pp_ctrl_reg);
2314
2315         pps_unlock(intel_dp);
2316 }
2317
2318 /* Enable backlight PWM and backlight PP control. */
2319 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2320                             const struct drm_connector_state *conn_state)
2321 {
2322         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2323
2324         if (!intel_dp_is_edp(intel_dp))
2325                 return;
2326
2327         DRM_DEBUG_KMS("\n");
2328
2329         intel_panel_enable_backlight(crtc_state, conn_state);
2330         _intel_edp_backlight_on(intel_dp);
2331 }
2332
2333 /* Disable backlight in the panel power control. */
2334 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2335 {
2336         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2337         u32 pp;
2338         i915_reg_t pp_ctrl_reg;
2339
2340         if (!intel_dp_is_edp(intel_dp))
2341                 return;
2342
2343         pps_lock(intel_dp);
2344
2345         pp = ironlake_get_pp_control(intel_dp);
2346         pp &= ~EDP_BLC_ENABLE;
2347
2348         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2349
2350         I915_WRITE(pp_ctrl_reg, pp);
2351         POSTING_READ(pp_ctrl_reg);
2352
2353         pps_unlock(intel_dp);
2354
2355         intel_dp->last_backlight_off = jiffies;
2356         edp_wait_backlight_off(intel_dp);
2357 }
2358
2359 /* Disable backlight PP control and backlight PWM. */
2360 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2361 {
2362         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2363
2364         if (!intel_dp_is_edp(intel_dp))
2365                 return;
2366
2367         DRM_DEBUG_KMS("\n");
2368
2369         _intel_edp_backlight_off(intel_dp);
2370         intel_panel_disable_backlight(old_conn_state);
2371 }
2372
2373 /*
2374  * Hook for controlling the panel power control backlight through the bl_power
2375  * sysfs attribute. Take care to handle multiple calls.
2376  */
2377 static void intel_edp_backlight_power(struct intel_connector *connector,
2378                                       bool enable)
2379 {
2380         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2381         bool is_enabled;
2382
2383         pps_lock(intel_dp);
2384         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2385         pps_unlock(intel_dp);
2386
2387         if (is_enabled == enable)
2388                 return;
2389
2390         DRM_DEBUG_KMS("panel power control backlight %s\n",
2391                       enable ? "enable" : "disable");
2392
2393         if (enable)
2394                 _intel_edp_backlight_on(intel_dp);
2395         else
2396                 _intel_edp_backlight_off(intel_dp);
2397 }
2398
2399 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2400 {
2401         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2402         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2403         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2404
2405         I915_STATE_WARN(cur_state != state,
2406                         "DP port %c state assertion failure (expected %s, current %s)\n",
2407                         port_name(dig_port->base.port),
2408                         onoff(state), onoff(cur_state));
2409 }
2410 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2411
2412 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2413 {
2414         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2415
2416         I915_STATE_WARN(cur_state != state,
2417                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2418                         onoff(state), onoff(cur_state));
2419 }
2420 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2421 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2422
2423 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2424                                 const struct intel_crtc_state *pipe_config)
2425 {
2426         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2427         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2428
2429         assert_pipe_disabled(dev_priv, crtc->pipe);
2430         assert_dp_port_disabled(intel_dp);
2431         assert_edp_pll_disabled(dev_priv);
2432
2433         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2434                       pipe_config->port_clock);
2435
2436         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2437
2438         if (pipe_config->port_clock == 162000)
2439                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2440         else
2441                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2442
2443         I915_WRITE(DP_A, intel_dp->DP);
2444         POSTING_READ(DP_A);
2445         udelay(500);
2446
2447         /*
2448          * [DevILK] Work around required when enabling DP PLL
2449          * while a pipe is enabled going to FDI:
2450          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2451          * 2. Program DP PLL enable
2452          */
2453         if (IS_GEN5(dev_priv))
2454                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2455
2456         intel_dp->DP |= DP_PLL_ENABLE;
2457
2458         I915_WRITE(DP_A, intel_dp->DP);
2459         POSTING_READ(DP_A);
2460         udelay(200);
2461 }
2462
2463 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2464                                  const struct intel_crtc_state *old_crtc_state)
2465 {
2466         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2467         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2468
2469         assert_pipe_disabled(dev_priv, crtc->pipe);
2470         assert_dp_port_disabled(intel_dp);
2471         assert_edp_pll_enabled(dev_priv);
2472
2473         DRM_DEBUG_KMS("disabling eDP PLL\n");
2474
2475         intel_dp->DP &= ~DP_PLL_ENABLE;
2476
2477         I915_WRITE(DP_A, intel_dp->DP);
2478         POSTING_READ(DP_A);
2479         udelay(200);
2480 }
2481
2482 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2483 {
2484         /*
2485          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2486          * be capable of signalling downstream hpd with a long pulse.
2487          * Whether or not that means D3 is safe to use is not clear,
2488          * but let's assume so until proven otherwise.
2489          *
2490          * FIXME should really check all downstream ports...
2491          */
2492         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2493                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2494                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2495 }
2496
2497 /* If the sink supports it, try to set the power state appropriately */
2498 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2499 {
2500         int ret, i;
2501
2502         /* Should have a valid DPCD by this point */
2503         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2504                 return;
2505
2506         if (mode != DRM_MODE_DPMS_ON) {
2507                 if (downstream_hpd_needs_d0(intel_dp))
2508                         return;
2509
2510                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2511                                          DP_SET_POWER_D3);
2512         } else {
2513                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2514
2515                 /*
2516                  * When turning on, we need to retry for 1ms to give the sink
2517                  * time to wake up.
2518                  */
2519                 for (i = 0; i < 3; i++) {
2520                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2521                                                  DP_SET_POWER_D0);
2522                         if (ret == 1)
2523                                 break;
2524                         msleep(1);
2525                 }
2526
2527                 if (ret == 1 && lspcon->active)
2528                         lspcon_wait_pcon_mode(lspcon);
2529         }
2530
2531         if (ret != 1)
2532                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2533                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2534 }
2535
2536 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2537                                   enum pipe *pipe)
2538 {
2539         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2540         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2541         enum port port = encoder->port;
2542         u32 tmp;
2543         bool ret;
2544
2545         if (!intel_display_power_get_if_enabled(dev_priv,
2546                                                 encoder->power_domain))
2547                 return false;
2548
2549         ret = false;
2550
2551         tmp = I915_READ(intel_dp->output_reg);
2552
2553         if (!(tmp & DP_PORT_EN))
2554                 goto out;
2555
2556         if (IS_GEN7(dev_priv) && port == PORT_A) {
2557                 *pipe = PORT_TO_PIPE_CPT(tmp);
2558         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2559                 enum pipe p;
2560
2561                 for_each_pipe(dev_priv, p) {
2562                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2563                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2564                                 *pipe = p;
2565                                 ret = true;
2566
2567                                 goto out;
2568                         }
2569                 }
2570
2571                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2572                               i915_mmio_reg_offset(intel_dp->output_reg));
2573         } else if (IS_CHERRYVIEW(dev_priv)) {
2574                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2575         } else {
2576                 *pipe = PORT_TO_PIPE(tmp);
2577         }
2578
2579         ret = true;
2580
2581 out:
2582         intel_display_power_put(dev_priv, encoder->power_domain);
2583
2584         return ret;
2585 }
2586
2587 static void intel_dp_get_config(struct intel_encoder *encoder,
2588                                 struct intel_crtc_state *pipe_config)
2589 {
2590         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2591         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2592         u32 tmp, flags = 0;
2593         enum port port = encoder->port;
2594         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2595
2596         if (encoder->type == INTEL_OUTPUT_EDP)
2597                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2598         else
2599                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2600
2601         tmp = I915_READ(intel_dp->output_reg);
2602
2603         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2604
2605         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2606                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2607
2608                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2609                         flags |= DRM_MODE_FLAG_PHSYNC;
2610                 else
2611                         flags |= DRM_MODE_FLAG_NHSYNC;
2612
2613                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2614                         flags |= DRM_MODE_FLAG_PVSYNC;
2615                 else
2616                         flags |= DRM_MODE_FLAG_NVSYNC;
2617         } else {
2618                 if (tmp & DP_SYNC_HS_HIGH)
2619                         flags |= DRM_MODE_FLAG_PHSYNC;
2620                 else
2621                         flags |= DRM_MODE_FLAG_NHSYNC;
2622
2623                 if (tmp & DP_SYNC_VS_HIGH)
2624                         flags |= DRM_MODE_FLAG_PVSYNC;
2625                 else
2626                         flags |= DRM_MODE_FLAG_NVSYNC;
2627         }
2628
2629         pipe_config->base.adjusted_mode.flags |= flags;
2630
2631         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2632                 pipe_config->limited_color_range = true;
2633
2634         pipe_config->lane_count =
2635                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2636
2637         intel_dp_get_m_n(crtc, pipe_config);
2638
2639         if (port == PORT_A) {
2640                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2641                         pipe_config->port_clock = 162000;
2642                 else
2643                         pipe_config->port_clock = 270000;
2644         }
2645
2646         pipe_config->base.adjusted_mode.crtc_clock =
2647                 intel_dotclock_calculate(pipe_config->port_clock,
2648                                          &pipe_config->dp_m_n);
2649
2650         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2651             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2652                 /*
2653                  * This is a big fat ugly hack.
2654                  *
2655                  * Some machines in UEFI boot mode provide us a VBT that has 18
2656                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2657                  * unknown we fail to light up. Yet the same BIOS boots up with
2658                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2659                  * max, not what it tells us to use.
2660                  *
2661                  * Note: This will still be broken if the eDP panel is not lit
2662                  * up by the BIOS, and thus we can't get the mode at module
2663                  * load.
2664                  */
2665                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2666                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2667                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2668         }
2669 }
2670
2671 static void intel_disable_dp(struct intel_encoder *encoder,
2672                              const struct intel_crtc_state *old_crtc_state,
2673                              const struct drm_connector_state *old_conn_state)
2674 {
2675         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2676
2677         if (old_crtc_state->has_audio)
2678                 intel_audio_codec_disable(encoder,
2679                                           old_crtc_state, old_conn_state);
2680
2681         /* Make sure the panel is off before trying to change the mode. But also
2682          * ensure that we have vdd while we switch off the panel. */
2683         intel_edp_panel_vdd_on(intel_dp);
2684         intel_edp_backlight_off(old_conn_state);
2685         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2686         intel_edp_panel_off(intel_dp);
2687 }
2688
2689 static void g4x_disable_dp(struct intel_encoder *encoder,
2690                            const struct intel_crtc_state *old_crtc_state,
2691                            const struct drm_connector_state *old_conn_state)
2692 {
2693         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2694
2695         /* disable the port before the pipe on g4x */
2696         intel_dp_link_down(encoder, old_crtc_state);
2697 }
2698
2699 static void ilk_disable_dp(struct intel_encoder *encoder,
2700                            const struct intel_crtc_state *old_crtc_state,
2701                            const struct drm_connector_state *old_conn_state)
2702 {
2703         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2704 }
2705
2706 static void vlv_disable_dp(struct intel_encoder *encoder,
2707                            const struct intel_crtc_state *old_crtc_state,
2708                            const struct drm_connector_state *old_conn_state)
2709 {
2710         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2711
2712         intel_psr_disable(intel_dp, old_crtc_state);
2713
2714         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2715 }
2716
2717 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2718                                 const struct intel_crtc_state *old_crtc_state,
2719                                 const struct drm_connector_state *old_conn_state)
2720 {
2721         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2722         enum port port = encoder->port;
2723
2724         intel_dp_link_down(encoder, old_crtc_state);
2725
2726         /* Only ilk+ has port A */
2727         if (port == PORT_A)
2728                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2729 }
2730
2731 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2732                                 const struct intel_crtc_state *old_crtc_state,
2733                                 const struct drm_connector_state *old_conn_state)
2734 {
2735         intel_dp_link_down(encoder, old_crtc_state);
2736 }
2737
2738 static void chv_post_disable_dp(struct intel_encoder *encoder,
2739                                 const struct intel_crtc_state *old_crtc_state,
2740                                 const struct drm_connector_state *old_conn_state)
2741 {
2742         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2743
2744         intel_dp_link_down(encoder, old_crtc_state);
2745
2746         mutex_lock(&dev_priv->sb_lock);
2747
2748         /* Assert data lane reset */
2749         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2750
2751         mutex_unlock(&dev_priv->sb_lock);
2752 }
2753
2754 static void
2755 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2756                          uint32_t *DP,
2757                          uint8_t dp_train_pat)
2758 {
2759         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2760         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2761         enum port port = intel_dig_port->base.port;
2762
2763         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2764                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2765                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2766
2767         if (HAS_DDI(dev_priv)) {
2768                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2769
2770                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2771                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2772                 else
2773                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2774
2775                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2776                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2777                 case DP_TRAINING_PATTERN_DISABLE:
2778                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2779
2780                         break;
2781                 case DP_TRAINING_PATTERN_1:
2782                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2783                         break;
2784                 case DP_TRAINING_PATTERN_2:
2785                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2786                         break;
2787                 case DP_TRAINING_PATTERN_3:
2788                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2789                         break;
2790                 }
2791                 I915_WRITE(DP_TP_CTL(port), temp);
2792
2793         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2794                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2795                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2796
2797                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2798                 case DP_TRAINING_PATTERN_DISABLE:
2799                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2800                         break;
2801                 case DP_TRAINING_PATTERN_1:
2802                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2803                         break;
2804                 case DP_TRAINING_PATTERN_2:
2805                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2806                         break;
2807                 case DP_TRAINING_PATTERN_3:
2808                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2809                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2810                         break;
2811                 }
2812
2813         } else {
2814                 if (IS_CHERRYVIEW(dev_priv))
2815                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2816                 else
2817                         *DP &= ~DP_LINK_TRAIN_MASK;
2818
2819                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2820                 case DP_TRAINING_PATTERN_DISABLE:
2821                         *DP |= DP_LINK_TRAIN_OFF;
2822                         break;
2823                 case DP_TRAINING_PATTERN_1:
2824                         *DP |= DP_LINK_TRAIN_PAT_1;
2825                         break;
2826                 case DP_TRAINING_PATTERN_2:
2827                         *DP |= DP_LINK_TRAIN_PAT_2;
2828                         break;
2829                 case DP_TRAINING_PATTERN_3:
2830                         if (IS_CHERRYVIEW(dev_priv)) {
2831                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2832                         } else {
2833                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2834                                 *DP |= DP_LINK_TRAIN_PAT_2;
2835                         }
2836                         break;
2837                 }
2838         }
2839 }
2840
2841 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2842                                  const struct intel_crtc_state *old_crtc_state)
2843 {
2844         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2845
2846         /* enable with pattern 1 (as per spec) */
2847
2848         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2849
2850         /*
2851          * Magic for VLV/CHV. We _must_ first set up the register
2852          * without actually enabling the port, and then do another
2853          * write to enable the port. Otherwise link training will
2854          * fail when the power sequencer is freshly used for this port.
2855          */
2856         intel_dp->DP |= DP_PORT_EN;
2857         if (old_crtc_state->has_audio)
2858                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2859
2860         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2861         POSTING_READ(intel_dp->output_reg);
2862 }
2863
2864 static void intel_enable_dp(struct intel_encoder *encoder,
2865                             const struct intel_crtc_state *pipe_config,
2866                             const struct drm_connector_state *conn_state)
2867 {
2868         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2869         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2870         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2871         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2872         enum pipe pipe = crtc->pipe;
2873
2874         if (WARN_ON(dp_reg & DP_PORT_EN))
2875                 return;
2876
2877         pps_lock(intel_dp);
2878
2879         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2880                 vlv_init_panel_power_sequencer(encoder, pipe_config);
2881
2882         intel_dp_enable_port(intel_dp, pipe_config);
2883
2884         edp_panel_vdd_on(intel_dp);
2885         edp_panel_on(intel_dp);
2886         edp_panel_vdd_off(intel_dp, true);
2887
2888         pps_unlock(intel_dp);
2889
2890         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2891                 unsigned int lane_mask = 0x0;
2892
2893                 if (IS_CHERRYVIEW(dev_priv))
2894                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2895
2896                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2897                                     lane_mask);
2898         }
2899
2900         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2901         intel_dp_start_link_train(intel_dp);
2902         intel_dp_stop_link_train(intel_dp);
2903
2904         if (pipe_config->has_audio) {
2905                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2906                                  pipe_name(pipe));
2907                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2908         }
2909 }
2910
2911 static void g4x_enable_dp(struct intel_encoder *encoder,
2912                           const struct intel_crtc_state *pipe_config,
2913                           const struct drm_connector_state *conn_state)
2914 {
2915         intel_enable_dp(encoder, pipe_config, conn_state);
2916         intel_edp_backlight_on(pipe_config, conn_state);
2917 }
2918
2919 static void vlv_enable_dp(struct intel_encoder *encoder,
2920                           const struct intel_crtc_state *pipe_config,
2921                           const struct drm_connector_state *conn_state)
2922 {
2923         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2924
2925         intel_edp_backlight_on(pipe_config, conn_state);
2926         intel_psr_enable(intel_dp, pipe_config);
2927 }
2928
2929 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2930                               const struct intel_crtc_state *pipe_config,
2931                               const struct drm_connector_state *conn_state)
2932 {
2933         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2934         enum port port = encoder->port;
2935
2936         intel_dp_prepare(encoder, pipe_config);
2937
2938         /* Only ilk+ has port A */
2939         if (port == PORT_A)
2940                 ironlake_edp_pll_on(intel_dp, pipe_config);
2941 }
2942
2943 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2944 {
2945         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2946         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2947         enum pipe pipe = intel_dp->pps_pipe;
2948         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2949
2950         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2951
2952         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2953                 return;
2954
2955         edp_panel_vdd_off_sync(intel_dp);
2956
2957         /*
2958          * VLV seems to get confused when multiple power seqeuencers
2959          * have the same port selected (even if only one has power/vdd
2960          * enabled). The failure manifests as vlv_wait_port_ready() failing
2961          * CHV on the other hand doesn't seem to mind having the same port
2962          * selected in multiple power seqeuencers, but let's clear the
2963          * port select always when logically disconnecting a power sequencer
2964          * from a port.
2965          */
2966         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2967                       pipe_name(pipe), port_name(intel_dig_port->base.port));
2968         I915_WRITE(pp_on_reg, 0);
2969         POSTING_READ(pp_on_reg);
2970
2971         intel_dp->pps_pipe = INVALID_PIPE;
2972 }
2973
2974 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
2975                                       enum pipe pipe)
2976 {
2977         struct intel_encoder *encoder;
2978
2979         lockdep_assert_held(&dev_priv->pps_mutex);
2980
2981         for_each_intel_encoder(&dev_priv->drm, encoder) {
2982                 struct intel_dp *intel_dp;
2983                 enum port port;
2984
2985                 if (encoder->type != INTEL_OUTPUT_DP &&
2986                     encoder->type != INTEL_OUTPUT_EDP)
2987                         continue;
2988
2989                 intel_dp = enc_to_intel_dp(&encoder->base);
2990                 port = dp_to_dig_port(intel_dp)->base.port;
2991
2992                 WARN(intel_dp->active_pipe == pipe,
2993                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
2994                      pipe_name(pipe), port_name(port));
2995
2996                 if (intel_dp->pps_pipe != pipe)
2997                         continue;
2998
2999                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3000                               pipe_name(pipe), port_name(port));
3001
3002                 /* make sure vdd is off before we steal it */
3003                 vlv_detach_power_sequencer(intel_dp);
3004         }
3005 }
3006
3007 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3008                                            const struct intel_crtc_state *crtc_state)
3009 {
3010         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3011         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3012         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3013
3014         lockdep_assert_held(&dev_priv->pps_mutex);
3015
3016         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3017
3018         if (intel_dp->pps_pipe != INVALID_PIPE &&
3019             intel_dp->pps_pipe != crtc->pipe) {
3020                 /*
3021                  * If another power sequencer was being used on this
3022                  * port previously make sure to turn off vdd there while
3023                  * we still have control of it.
3024                  */
3025                 vlv_detach_power_sequencer(intel_dp);
3026         }
3027
3028         /*
3029          * We may be stealing the power
3030          * sequencer from another port.
3031          */
3032         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3033
3034         intel_dp->active_pipe = crtc->pipe;
3035
3036         if (!intel_dp_is_edp(intel_dp))
3037                 return;
3038
3039         /* now it's all ours */
3040         intel_dp->pps_pipe = crtc->pipe;
3041
3042         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3043                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3044
3045         /* init power sequencer on this pipe and port */
3046         intel_dp_init_panel_power_sequencer(intel_dp);
3047         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3048 }
3049
3050 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3051                               const struct intel_crtc_state *pipe_config,
3052                               const struct drm_connector_state *conn_state)
3053 {
3054         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3055
3056         intel_enable_dp(encoder, pipe_config, conn_state);
3057 }
3058
3059 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3060                                   const struct intel_crtc_state *pipe_config,
3061                                   const struct drm_connector_state *conn_state)
3062 {
3063         intel_dp_prepare(encoder, pipe_config);
3064
3065         vlv_phy_pre_pll_enable(encoder, pipe_config);
3066 }
3067
3068 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3069                               const struct intel_crtc_state *pipe_config,
3070                               const struct drm_connector_state *conn_state)
3071 {
3072         chv_phy_pre_encoder_enable(encoder, pipe_config);
3073
3074         intel_enable_dp(encoder, pipe_config, conn_state);
3075
3076         /* Second common lane will stay alive on its own now */
3077         chv_phy_release_cl2_override(encoder);
3078 }
3079
3080 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3081                                   const struct intel_crtc_state *pipe_config,
3082                                   const struct drm_connector_state *conn_state)
3083 {
3084         intel_dp_prepare(encoder, pipe_config);
3085
3086         chv_phy_pre_pll_enable(encoder, pipe_config);
3087 }
3088
3089 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3090                                     const struct intel_crtc_state *old_crtc_state,
3091                                     const struct drm_connector_state *old_conn_state)
3092 {
3093         chv_phy_post_pll_disable(encoder, old_crtc_state);
3094 }
3095
3096 /*
3097  * Fetch AUX CH registers 0x202 - 0x207 which contain
3098  * link status information
3099  */
3100 bool
3101 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3102 {
3103         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3104                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3105 }
3106
3107 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3108 {
3109         uint8_t psr_caps = 0;
3110
3111         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3112                 return false;
3113         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3114 }
3115
3116 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3117 {
3118         uint8_t dprx = 0;
3119
3120         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3121                               &dprx) != 1)
3122                 return false;
3123         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3124 }
3125
3126 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3127 {
3128         uint8_t alpm_caps = 0;
3129
3130         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3131                               &alpm_caps) != 1)
3132                 return false;
3133         return alpm_caps & DP_ALPM_CAP;
3134 }
3135
3136 /* These are source-specific values. */
3137 uint8_t
3138 intel_dp_voltage_max(struct intel_dp *intel_dp)
3139 {
3140         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3141         enum port port = dp_to_dig_port(intel_dp)->base.port;
3142
3143         if (INTEL_GEN(dev_priv) >= 9) {
3144                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3145                 return intel_ddi_dp_voltage_max(encoder);
3146         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3147                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3148         else if (IS_GEN7(dev_priv) && port == PORT_A)
3149                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3150         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3151                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3152         else
3153                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3154 }
3155
3156 uint8_t
3157 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3158 {
3159         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3160         enum port port = dp_to_dig_port(intel_dp)->base.port;
3161
3162         if (INTEL_GEN(dev_priv) >= 9) {
3163                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3164                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3165                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3166                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3167                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3168                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3169                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3170                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3171                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3172                 default:
3173                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3174                 }
3175         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3176                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3177                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3178                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3179                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3180                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3181                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3182                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3183                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3184                 default:
3185                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3186                 }
3187         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3188                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3189                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3190                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3191                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3192                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3193                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3194                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3195                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3196                 default:
3197                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3198                 }
3199         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3200                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3201                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3202                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3203                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3204                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3205                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3206                 default:
3207                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3208                 }
3209         } else {
3210                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3211                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3212                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3213                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3214                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3215                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3216                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3217                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3218                 default:
3219                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3220                 }
3221         }
3222 }
3223
3224 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3225 {
3226         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3227         unsigned long demph_reg_value, preemph_reg_value,
3228                 uniqtranscale_reg_value;
3229         uint8_t train_set = intel_dp->train_set[0];
3230
3231         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3232         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3233                 preemph_reg_value = 0x0004000;
3234                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3235                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3236                         demph_reg_value = 0x2B405555;
3237                         uniqtranscale_reg_value = 0x552AB83A;
3238                         break;
3239                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3240                         demph_reg_value = 0x2B404040;
3241                         uniqtranscale_reg_value = 0x5548B83A;
3242                         break;
3243                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3244                         demph_reg_value = 0x2B245555;
3245                         uniqtranscale_reg_value = 0x5560B83A;
3246                         break;
3247                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3248                         demph_reg_value = 0x2B405555;
3249                         uniqtranscale_reg_value = 0x5598DA3A;
3250                         break;
3251                 default:
3252                         return 0;
3253                 }
3254                 break;
3255         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3256                 preemph_reg_value = 0x0002000;
3257                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259                         demph_reg_value = 0x2B404040;
3260                         uniqtranscale_reg_value = 0x5552B83A;
3261                         break;
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3263                         demph_reg_value = 0x2B404848;
3264                         uniqtranscale_reg_value = 0x5580B83A;
3265                         break;
3266                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3267                         demph_reg_value = 0x2B404040;
3268                         uniqtranscale_reg_value = 0x55ADDA3A;
3269                         break;
3270                 default:
3271                         return 0;
3272                 }
3273                 break;
3274         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3275                 preemph_reg_value = 0x0000000;
3276                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3277                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3278                         demph_reg_value = 0x2B305555;
3279                         uniqtranscale_reg_value = 0x5570B83A;
3280                         break;
3281                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3282                         demph_reg_value = 0x2B2B4040;
3283                         uniqtranscale_reg_value = 0x55ADDA3A;
3284                         break;
3285                 default:
3286                         return 0;
3287                 }
3288                 break;
3289         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3290                 preemph_reg_value = 0x0006000;
3291                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3292                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3293                         demph_reg_value = 0x1B405555;
3294                         uniqtranscale_reg_value = 0x55ADDA3A;
3295                         break;
3296                 default:
3297                         return 0;
3298                 }
3299                 break;
3300         default:
3301                 return 0;
3302         }
3303
3304         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3305                                  uniqtranscale_reg_value, 0);
3306
3307         return 0;
3308 }
3309
3310 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3311 {
3312         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3313         u32 deemph_reg_value, margin_reg_value;
3314         bool uniq_trans_scale = false;
3315         uint8_t train_set = intel_dp->train_set[0];
3316
3317         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3318         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3319                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3320                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3321                         deemph_reg_value = 128;
3322                         margin_reg_value = 52;
3323                         break;
3324                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3325                         deemph_reg_value = 128;
3326                         margin_reg_value = 77;
3327                         break;
3328                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3329                         deemph_reg_value = 128;
3330                         margin_reg_value = 102;
3331                         break;
3332                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3333                         deemph_reg_value = 128;
3334                         margin_reg_value = 154;
3335                         uniq_trans_scale = true;
3336                         break;
3337                 default:
3338                         return 0;
3339                 }
3340                 break;
3341         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3342                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3343                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3344                         deemph_reg_value = 85;
3345                         margin_reg_value = 78;
3346                         break;
3347                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3348                         deemph_reg_value = 85;
3349                         margin_reg_value = 116;
3350                         break;
3351                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3352                         deemph_reg_value = 85;
3353                         margin_reg_value = 154;
3354                         break;
3355                 default:
3356                         return 0;
3357                 }
3358                 break;
3359         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3360                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3361                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3362                         deemph_reg_value = 64;
3363                         margin_reg_value = 104;
3364                         break;
3365                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3366                         deemph_reg_value = 64;
3367                         margin_reg_value = 154;
3368                         break;
3369                 default:
3370                         return 0;
3371                 }
3372                 break;
3373         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3374                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3375                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3376                         deemph_reg_value = 43;
3377                         margin_reg_value = 154;
3378                         break;
3379                 default:
3380                         return 0;
3381                 }
3382                 break;
3383         default:
3384                 return 0;
3385         }
3386
3387         chv_set_phy_signal_level(encoder, deemph_reg_value,
3388                                  margin_reg_value, uniq_trans_scale);
3389
3390         return 0;
3391 }
3392
3393 static uint32_t
3394 gen4_signal_levels(uint8_t train_set)
3395 {
3396         uint32_t        signal_levels = 0;
3397
3398         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3399         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3400         default:
3401                 signal_levels |= DP_VOLTAGE_0_4;
3402                 break;
3403         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3404                 signal_levels |= DP_VOLTAGE_0_6;
3405                 break;
3406         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3407                 signal_levels |= DP_VOLTAGE_0_8;
3408                 break;
3409         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3410                 signal_levels |= DP_VOLTAGE_1_2;
3411                 break;
3412         }
3413         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3414         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3415         default:
3416                 signal_levels |= DP_PRE_EMPHASIS_0;
3417                 break;
3418         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3419                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3420                 break;
3421         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3422                 signal_levels |= DP_PRE_EMPHASIS_6;
3423                 break;
3424         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3425                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3426                 break;
3427         }
3428         return signal_levels;
3429 }
3430
3431 /* Gen6's DP voltage swing and pre-emphasis control */
3432 static uint32_t
3433 gen6_edp_signal_levels(uint8_t train_set)
3434 {
3435         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3436                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3437         switch (signal_levels) {
3438         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3439         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3440                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3441         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3442                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3443         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3444         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3445                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3446         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3447         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3448                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3449         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3450         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3451                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3452         default:
3453                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3454                               "0x%x\n", signal_levels);
3455                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3456         }
3457 }
3458
3459 /* Gen7's DP voltage swing and pre-emphasis control */
3460 static uint32_t
3461 gen7_edp_signal_levels(uint8_t train_set)
3462 {
3463         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3464                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3465         switch (signal_levels) {
3466         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3467                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3468         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3469                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3470         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3471                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3472
3473         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3474                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3475         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3476                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3477
3478         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3479                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3480         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3481                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3482
3483         default:
3484                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3485                               "0x%x\n", signal_levels);
3486                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3487         }
3488 }
3489
3490 void
3491 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3492 {
3493         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3494         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3495         enum port port = intel_dig_port->base.port;
3496         uint32_t signal_levels, mask = 0;
3497         uint8_t train_set = intel_dp->train_set[0];
3498
3499         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3500                 signal_levels = bxt_signal_levels(intel_dp);
3501         } else if (HAS_DDI(dev_priv)) {
3502                 signal_levels = ddi_signal_levels(intel_dp);
3503                 mask = DDI_BUF_EMP_MASK;
3504         } else if (IS_CHERRYVIEW(dev_priv)) {
3505                 signal_levels = chv_signal_levels(intel_dp);
3506         } else if (IS_VALLEYVIEW(dev_priv)) {
3507                 signal_levels = vlv_signal_levels(intel_dp);
3508         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3509                 signal_levels = gen7_edp_signal_levels(train_set);
3510                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3511         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3512                 signal_levels = gen6_edp_signal_levels(train_set);
3513                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3514         } else {
3515                 signal_levels = gen4_signal_levels(train_set);
3516                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3517         }
3518
3519         if (mask)
3520                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3521
3522         DRM_DEBUG_KMS("Using vswing level %d\n",
3523                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3524         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3525                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3526                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3527
3528         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3529
3530         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3531         POSTING_READ(intel_dp->output_reg);
3532 }
3533
3534 void
3535 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3536                                        uint8_t dp_train_pat)
3537 {
3538         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3539         struct drm_i915_private *dev_priv =
3540                 to_i915(intel_dig_port->base.base.dev);
3541
3542         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3543
3544         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3545         POSTING_READ(intel_dp->output_reg);
3546 }
3547
3548 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3549 {
3550         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3551         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3552         enum port port = intel_dig_port->base.port;
3553         uint32_t val;
3554
3555         if (!HAS_DDI(dev_priv))
3556                 return;
3557
3558         val = I915_READ(DP_TP_CTL(port));
3559         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3560         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3561         I915_WRITE(DP_TP_CTL(port), val);
3562
3563         /*
3564          * On PORT_A we can have only eDP in SST mode. There the only reason
3565          * we need to set idle transmission mode is to work around a HW issue
3566          * where we enable the pipe while not in idle link-training mode.
3567          * In this case there is requirement to wait for a minimum number of
3568          * idle patterns to be sent.
3569          */
3570         if (port == PORT_A)
3571                 return;
3572
3573         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3574                                     DP_TP_STATUS_IDLE_DONE,
3575                                     DP_TP_STATUS_IDLE_DONE,
3576                                     1))
3577                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3578 }
3579
3580 static void
3581 intel_dp_link_down(struct intel_encoder *encoder,
3582                    const struct intel_crtc_state *old_crtc_state)
3583 {
3584         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3585         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3586         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3587         enum port port = encoder->port;
3588         uint32_t DP = intel_dp->DP;
3589
3590         if (WARN_ON(HAS_DDI(dev_priv)))
3591                 return;
3592
3593         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3594                 return;
3595
3596         DRM_DEBUG_KMS("\n");
3597
3598         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3599             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3600                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3601                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3602         } else {
3603                 if (IS_CHERRYVIEW(dev_priv))
3604                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3605                 else
3606                         DP &= ~DP_LINK_TRAIN_MASK;
3607                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3608         }
3609         I915_WRITE(intel_dp->output_reg, DP);
3610         POSTING_READ(intel_dp->output_reg);
3611
3612         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3613         I915_WRITE(intel_dp->output_reg, DP);
3614         POSTING_READ(intel_dp->output_reg);
3615
3616         /*
3617          * HW workaround for IBX, we need to move the port
3618          * to transcoder A after disabling it to allow the
3619          * matching HDMI port to be enabled on transcoder A.
3620          */
3621         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3622                 /*
3623                  * We get CPU/PCH FIFO underruns on the other pipe when
3624                  * doing the workaround. Sweep them under the rug.
3625                  */
3626                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3627                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3628
3629                 /* always enable with pattern 1 (as per spec) */
3630                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3631                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3632                 I915_WRITE(intel_dp->output_reg, DP);
3633                 POSTING_READ(intel_dp->output_reg);
3634
3635                 DP &= ~DP_PORT_EN;
3636                 I915_WRITE(intel_dp->output_reg, DP);
3637                 POSTING_READ(intel_dp->output_reg);
3638
3639                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3640                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3641                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3642         }
3643
3644         msleep(intel_dp->panel_power_down_delay);
3645
3646         intel_dp->DP = DP;
3647
3648         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3649                 pps_lock(intel_dp);
3650                 intel_dp->active_pipe = INVALID_PIPE;
3651                 pps_unlock(intel_dp);
3652         }
3653 }
3654
3655 bool
3656 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3657 {
3658         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3659                              sizeof(intel_dp->dpcd)) < 0)
3660                 return false; /* aux transfer failed */
3661
3662         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3663
3664         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3665 }
3666
3667 static bool
3668 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3669 {
3670         struct drm_i915_private *dev_priv =
3671                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3672
3673         /* this function is meant to be called only once */
3674         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3675
3676         if (!intel_dp_read_dpcd(intel_dp))
3677                 return false;
3678
3679         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3680                          drm_dp_is_branch(intel_dp->dpcd));
3681
3682         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3683                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3684                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3685
3686         /* Check if the panel supports PSR */
3687         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3688                          intel_dp->psr_dpcd,
3689                          sizeof(intel_dp->psr_dpcd));
3690         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3691                 dev_priv->psr.sink_support = true;
3692                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3693         }
3694
3695         if (INTEL_GEN(dev_priv) >= 9 &&
3696             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3697                 uint8_t frame_sync_cap;
3698
3699                 dev_priv->psr.sink_support = true;
3700                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3701                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3702                                       &frame_sync_cap) != 1)
3703                         frame_sync_cap = 0;
3704                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3705                 /* PSR2 needs frame sync as well */
3706                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3707                 DRM_DEBUG_KMS("PSR2 %s on sink",
3708                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3709
3710                 if (dev_priv->psr.psr2_support) {
3711                         dev_priv->psr.y_cord_support =
3712                                 intel_dp_get_y_cord_status(intel_dp);
3713                         dev_priv->psr.colorimetry_support =
3714                                 intel_dp_get_colorimetry_status(intel_dp);
3715                         dev_priv->psr.alpm =
3716                                 intel_dp_get_alpm_status(intel_dp);
3717                 }
3718
3719         }
3720
3721         /*
3722          * Read the eDP display control registers.
3723          *
3724          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3725          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3726          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3727          * method). The display control registers should read zero if they're
3728          * not supported anyway.
3729          */
3730         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3731                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3732                              sizeof(intel_dp->edp_dpcd))
3733                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3734                               intel_dp->edp_dpcd);
3735
3736         /* Read the eDP 1.4+ supported link rates. */
3737         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3738                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3739                 int i;
3740
3741                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3742                                 sink_rates, sizeof(sink_rates));
3743
3744                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3745                         int val = le16_to_cpu(sink_rates[i]);
3746
3747                         if (val == 0)
3748                                 break;
3749
3750                         /* Value read multiplied by 200kHz gives the per-lane
3751                          * link rate in kHz. The source rates are, however,
3752                          * stored in terms of LS_Clk kHz. The full conversion
3753                          * back to symbols is
3754                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3755                          */
3756                         intel_dp->sink_rates[i] = (val * 200) / 10;
3757                 }
3758                 intel_dp->num_sink_rates = i;
3759         }
3760
3761         /*
3762          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3763          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3764          */
3765         if (intel_dp->num_sink_rates)
3766                 intel_dp->use_rate_select = true;
3767         else
3768                 intel_dp_set_sink_rates(intel_dp);
3769
3770         intel_dp_set_common_rates(intel_dp);
3771
3772         return true;
3773 }
3774
3775
3776 static bool
3777 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3778 {
3779         u8 sink_count;
3780
3781         if (!intel_dp_read_dpcd(intel_dp))
3782                 return false;
3783
3784         /* Don't clobber cached eDP rates. */
3785         if (!intel_dp_is_edp(intel_dp)) {
3786                 intel_dp_set_sink_rates(intel_dp);
3787                 intel_dp_set_common_rates(intel_dp);
3788         }
3789
3790         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3791                 return false;
3792
3793         /*
3794          * Sink count can change between short pulse hpd hence
3795          * a member variable in intel_dp will track any changes
3796          * between short pulse interrupts.
3797          */
3798         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3799
3800         /*
3801          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3802          * a dongle is present but no display. Unless we require to know
3803          * if a dongle is present or not, we don't need to update
3804          * downstream port information. So, an early return here saves
3805          * time from performing other operations which are not required.
3806          */
3807         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3808                 return false;
3809
3810         if (!drm_dp_is_branch(intel_dp->dpcd))
3811                 return true; /* native DP sink */
3812
3813         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3814                 return true; /* no per-port downstream info */
3815
3816         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3817                              intel_dp->downstream_ports,
3818                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3819                 return false; /* downstream port status fetch failed */
3820
3821         return true;
3822 }
3823
3824 static bool
3825 intel_dp_can_mst(struct intel_dp *intel_dp)
3826 {
3827         u8 mstm_cap;
3828
3829         if (!i915_modparams.enable_dp_mst)
3830                 return false;
3831
3832         if (!intel_dp->can_mst)
3833                 return false;
3834
3835         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3836                 return false;
3837
3838         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3839                 return false;
3840
3841         return mstm_cap & DP_MST_CAP;
3842 }
3843
3844 static void
3845 intel_dp_configure_mst(struct intel_dp *intel_dp)
3846 {
3847         if (!i915_modparams.enable_dp_mst)
3848                 return;
3849
3850         if (!intel_dp->can_mst)
3851                 return;
3852
3853         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3854
3855         if (intel_dp->is_mst)
3856                 DRM_DEBUG_KMS("Sink is MST capable\n");
3857         else
3858                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3859
3860         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3861                                         intel_dp->is_mst);
3862 }
3863
3864 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp,
3865                                   struct intel_crtc_state *crtc_state, bool disable_wa)
3866 {
3867         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3868         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3870         u8 buf;
3871         int ret = 0;
3872         int count = 0;
3873         int attempts = 10;
3874
3875         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3876                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3877                 ret = -EIO;
3878                 goto out;
3879         }
3880
3881         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3882                                buf & ~DP_TEST_SINK_START) < 0) {
3883                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3884                 ret = -EIO;
3885                 goto out;
3886         }
3887
3888         do {
3889                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3890
3891                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3892                                       DP_TEST_SINK_MISC, &buf) < 0) {
3893                         ret = -EIO;
3894                         goto out;
3895                 }
3896                 count = buf & DP_TEST_COUNT_MASK;
3897         } while (--attempts && count);
3898
3899         if (attempts == 0) {
3900                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3901                 ret = -ETIMEDOUT;
3902         }
3903
3904  out:
3905         if (disable_wa)
3906                 hsw_enable_ips(crtc_state);
3907         return ret;
3908 }
3909
3910 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp,
3911                                    struct intel_crtc_state *crtc_state)
3912 {
3913         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3914         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3915         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3916         u8 buf;
3917         int ret;
3918
3919         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3920                 return -EIO;
3921
3922         if (!(buf & DP_TEST_CRC_SUPPORTED))
3923                 return -ENOTTY;
3924
3925         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3926                 return -EIO;
3927
3928         if (buf & DP_TEST_SINK_START) {
3929                 ret = intel_dp_sink_crc_stop(intel_dp, crtc_state, false);
3930                 if (ret)
3931                         return ret;
3932         }
3933
3934         hsw_disable_ips(crtc_state);
3935
3936         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3937                                buf | DP_TEST_SINK_START) < 0) {
3938                 hsw_enable_ips(crtc_state);
3939                 return -EIO;
3940         }
3941
3942         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3943         return 0;
3944 }
3945
3946 int intel_dp_sink_crc(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, u8 *crc)
3947 {
3948         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3949         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3951         u8 buf;
3952         int count, ret;
3953         int attempts = 6;
3954
3955         ret = intel_dp_sink_crc_start(intel_dp, crtc_state);
3956         if (ret)
3957                 return ret;
3958
3959         do {
3960                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3961
3962                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3963                                       DP_TEST_SINK_MISC, &buf) < 0) {
3964                         ret = -EIO;
3965                         goto stop;
3966                 }
3967                 count = buf & DP_TEST_COUNT_MASK;
3968
3969         } while (--attempts && count == 0);
3970
3971         if (attempts == 0) {
3972                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3973                 ret = -ETIMEDOUT;
3974                 goto stop;
3975         }
3976
3977         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3978                 ret = -EIO;
3979                 goto stop;
3980         }
3981
3982 stop:
3983         intel_dp_sink_crc_stop(intel_dp, crtc_state, true);
3984         return ret;
3985 }
3986
3987 static bool
3988 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3989 {
3990         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3991                                  sink_irq_vector) == 1;
3992 }
3993
3994 static bool
3995 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3996 {
3997         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
3998                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
3999                 DP_DPRX_ESI_LEN;
4000 }
4001
4002 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4003 {
4004         int status = 0;
4005         int test_link_rate;
4006         uint8_t test_lane_count, test_link_bw;
4007         /* (DP CTS 1.2)
4008          * 4.3.1.11
4009          */
4010         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4011         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4012                                    &test_lane_count);
4013
4014         if (status <= 0) {
4015                 DRM_DEBUG_KMS("Lane count read failed\n");
4016                 return DP_TEST_NAK;
4017         }
4018         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4019
4020         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4021                                    &test_link_bw);
4022         if (status <= 0) {
4023                 DRM_DEBUG_KMS("Link Rate read failed\n");
4024                 return DP_TEST_NAK;
4025         }
4026         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4027
4028         /* Validate the requested link rate and lane count */
4029         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4030                                         test_lane_count))
4031                 return DP_TEST_NAK;
4032
4033         intel_dp->compliance.test_lane_count = test_lane_count;
4034         intel_dp->compliance.test_link_rate = test_link_rate;
4035
4036         return DP_TEST_ACK;
4037 }
4038
4039 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4040 {
4041         uint8_t test_pattern;
4042         uint8_t test_misc;
4043         __be16 h_width, v_height;
4044         int status = 0;
4045
4046         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4047         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4048                                    &test_pattern);
4049         if (status <= 0) {
4050                 DRM_DEBUG_KMS("Test pattern read failed\n");
4051                 return DP_TEST_NAK;
4052         }
4053         if (test_pattern != DP_COLOR_RAMP)
4054                 return DP_TEST_NAK;
4055
4056         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4057                                   &h_width, 2);
4058         if (status <= 0) {
4059                 DRM_DEBUG_KMS("H Width read failed\n");
4060                 return DP_TEST_NAK;
4061         }
4062
4063         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4064                                   &v_height, 2);
4065         if (status <= 0) {
4066                 DRM_DEBUG_KMS("V Height read failed\n");
4067                 return DP_TEST_NAK;
4068         }
4069
4070         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4071                                    &test_misc);
4072         if (status <= 0) {
4073                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4074                 return DP_TEST_NAK;
4075         }
4076         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4077                 return DP_TEST_NAK;
4078         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4079                 return DP_TEST_NAK;
4080         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4081         case DP_TEST_BIT_DEPTH_6:
4082                 intel_dp->compliance.test_data.bpc = 6;
4083                 break;
4084         case DP_TEST_BIT_DEPTH_8:
4085                 intel_dp->compliance.test_data.bpc = 8;
4086                 break;
4087         default:
4088                 return DP_TEST_NAK;
4089         }
4090
4091         intel_dp->compliance.test_data.video_pattern = test_pattern;
4092         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4093         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4094         /* Set test active flag here so userspace doesn't interrupt things */
4095         intel_dp->compliance.test_active = 1;
4096
4097         return DP_TEST_ACK;
4098 }
4099
4100 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4101 {
4102         uint8_t test_result = DP_TEST_ACK;
4103         struct intel_connector *intel_connector = intel_dp->attached_connector;
4104         struct drm_connector *connector = &intel_connector->base;
4105
4106         if (intel_connector->detect_edid == NULL ||
4107             connector->edid_corrupt ||
4108             intel_dp->aux.i2c_defer_count > 6) {
4109                 /* Check EDID read for NACKs, DEFERs and corruption
4110                  * (DP CTS 1.2 Core r1.1)
4111                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4112                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4113                  *    4.2.2.6 : EDID corruption detected
4114                  * Use failsafe mode for all cases
4115                  */
4116                 if (intel_dp->aux.i2c_nack_count > 0 ||
4117                         intel_dp->aux.i2c_defer_count > 0)
4118                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4119                                       intel_dp->aux.i2c_nack_count,
4120                                       intel_dp->aux.i2c_defer_count);
4121                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4122         } else {
4123                 struct edid *block = intel_connector->detect_edid;
4124
4125                 /* We have to write the checksum
4126                  * of the last block read
4127                  */
4128                 block += intel_connector->detect_edid->extensions;
4129
4130                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4131                                        block->checksum) <= 0)
4132                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4133
4134                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4135                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4136         }
4137
4138         /* Set test active flag here so userspace doesn't interrupt things */
4139         intel_dp->compliance.test_active = 1;
4140
4141         return test_result;
4142 }
4143
4144 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4145 {
4146         uint8_t test_result = DP_TEST_NAK;
4147         return test_result;
4148 }
4149
4150 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4151 {
4152         uint8_t response = DP_TEST_NAK;
4153         uint8_t request = 0;
4154         int status;
4155
4156         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4157         if (status <= 0) {
4158                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4159                 goto update_status;
4160         }
4161
4162         switch (request) {
4163         case DP_TEST_LINK_TRAINING:
4164                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4165                 response = intel_dp_autotest_link_training(intel_dp);
4166                 break;
4167         case DP_TEST_LINK_VIDEO_PATTERN:
4168                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4169                 response = intel_dp_autotest_video_pattern(intel_dp);
4170                 break;
4171         case DP_TEST_LINK_EDID_READ:
4172                 DRM_DEBUG_KMS("EDID test requested\n");
4173                 response = intel_dp_autotest_edid(intel_dp);
4174                 break;
4175         case DP_TEST_LINK_PHY_TEST_PATTERN:
4176                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4177                 response = intel_dp_autotest_phy_pattern(intel_dp);
4178                 break;
4179         default:
4180                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4181                 break;
4182         }
4183
4184         if (response & DP_TEST_ACK)
4185                 intel_dp->compliance.test_type = request;
4186
4187 update_status:
4188         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4189         if (status <= 0)
4190                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4191 }
4192
4193 static int
4194 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4195 {
4196         bool bret;
4197
4198         if (intel_dp->is_mst) {
4199                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4200                 int ret = 0;
4201                 int retry;
4202                 bool handled;
4203                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4204 go_again:
4205                 if (bret == true) {
4206
4207                         /* check link status - esi[10] = 0x200c */
4208                         if (intel_dp->active_mst_links &&
4209                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4210                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4211                                 intel_dp_start_link_train(intel_dp);
4212                                 intel_dp_stop_link_train(intel_dp);
4213                         }
4214
4215                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4216                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4217
4218                         if (handled) {
4219                                 for (retry = 0; retry < 3; retry++) {
4220                                         int wret;
4221                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4222                                                                  DP_SINK_COUNT_ESI+1,
4223                                                                  &esi[1], 3);
4224                                         if (wret == 3) {
4225                                                 break;
4226                                         }
4227                                 }
4228
4229                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4230                                 if (bret == true) {
4231                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4232                                         goto go_again;
4233                                 }
4234                         } else
4235                                 ret = 0;
4236
4237                         return ret;
4238                 } else {
4239                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4240                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4241                         intel_dp->is_mst = false;
4242                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4243                         /* send a hotplug event */
4244                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4245                 }
4246         }
4247         return -EINVAL;
4248 }
4249
4250 static void
4251 intel_dp_retrain_link(struct intel_dp *intel_dp)
4252 {
4253         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4254         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4255         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4256
4257         /* Suppress underruns caused by re-training */
4258         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4259         if (crtc->config->has_pch_encoder)
4260                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4261                                                       intel_crtc_pch_transcoder(crtc), false);
4262
4263         intel_dp_start_link_train(intel_dp);
4264         intel_dp_stop_link_train(intel_dp);
4265
4266         /* Keep underrun reporting disabled until things are stable */
4267         intel_wait_for_vblank(dev_priv, crtc->pipe);
4268
4269         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4270         if (crtc->config->has_pch_encoder)
4271                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4272                                                       intel_crtc_pch_transcoder(crtc), true);
4273 }
4274
4275 static void
4276 intel_dp_check_link_status(struct intel_dp *intel_dp)
4277 {
4278         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4279         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4280         struct drm_connector_state *conn_state =
4281                 intel_dp->attached_connector->base.state;
4282         u8 link_status[DP_LINK_STATUS_SIZE];
4283
4284         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4285
4286         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4287                 DRM_ERROR("Failed to get link status\n");
4288                 return;
4289         }
4290
4291         if (!conn_state->crtc)
4292                 return;
4293
4294         WARN_ON(!drm_modeset_is_locked(&conn_state->crtc->mutex));
4295
4296         if (!conn_state->crtc->state->active)
4297                 return;
4298
4299         if (conn_state->commit &&
4300             !try_wait_for_completion(&conn_state->commit->hw_done))
4301                 return;
4302
4303         /*
4304          * Validate the cached values of intel_dp->link_rate and
4305          * intel_dp->lane_count before attempting to retrain.
4306          */
4307         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4308                                         intel_dp->lane_count))
4309                 return;
4310
4311         /* Retrain if Channel EQ or CR not ok */
4312         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4313                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4314                               intel_encoder->base.name);
4315
4316                 intel_dp_retrain_link(intel_dp);
4317         }
4318 }
4319
4320 /*
4321  * According to DP spec
4322  * 5.1.2:
4323  *  1. Read DPCD
4324  *  2. Configure link according to Receiver Capabilities
4325  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4326  *  4. Check link status on receipt of hot-plug interrupt
4327  *
4328  * intel_dp_short_pulse -  handles short pulse interrupts
4329  * when full detection is not required.
4330  * Returns %true if short pulse is handled and full detection
4331  * is NOT required and %false otherwise.
4332  */
4333 static bool
4334 intel_dp_short_pulse(struct intel_dp *intel_dp)
4335 {
4336         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4337         u8 sink_irq_vector = 0;
4338         u8 old_sink_count = intel_dp->sink_count;
4339         bool ret;
4340
4341         /*
4342          * Clearing compliance test variables to allow capturing
4343          * of values for next automated test request.
4344          */
4345         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4346
4347         /*
4348          * Now read the DPCD to see if it's actually running
4349          * If the current value of sink count doesn't match with
4350          * the value that was stored earlier or dpcd read failed
4351          * we need to do full detection
4352          */
4353         ret = intel_dp_get_dpcd(intel_dp);
4354
4355         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4356                 /* No need to proceed if we are going to do full detect */
4357                 return false;
4358         }
4359
4360         /* Try to read the source of the interrupt */
4361         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4362             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4363             sink_irq_vector != 0) {
4364                 /* Clear interrupt source */
4365                 drm_dp_dpcd_writeb(&intel_dp->aux,
4366                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4367                                    sink_irq_vector);
4368
4369                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4370                         intel_dp_handle_test_request(intel_dp);
4371                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4372                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4373         }
4374
4375         intel_dp_check_link_status(intel_dp);
4376
4377         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4378                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4379                 /* Send a Hotplug Uevent to userspace to start modeset */
4380                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4381         }
4382
4383         return true;
4384 }
4385
4386 /* XXX this is probably wrong for multiple downstream ports */
4387 static enum drm_connector_status
4388 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4389 {
4390         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4391         uint8_t *dpcd = intel_dp->dpcd;
4392         uint8_t type;
4393
4394         if (lspcon->active)
4395                 lspcon_resume(lspcon);
4396
4397         if (!intel_dp_get_dpcd(intel_dp))
4398                 return connector_status_disconnected;
4399
4400         if (intel_dp_is_edp(intel_dp))
4401                 return connector_status_connected;
4402
4403         /* if there's no downstream port, we're done */
4404         if (!drm_dp_is_branch(dpcd))
4405                 return connector_status_connected;
4406
4407         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4408         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4409             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4410
4411                 return intel_dp->sink_count ?
4412                 connector_status_connected : connector_status_disconnected;
4413         }
4414
4415         if (intel_dp_can_mst(intel_dp))
4416                 return connector_status_connected;
4417
4418         /* If no HPD, poke DDC gently */
4419         if (drm_probe_ddc(&intel_dp->aux.ddc))
4420                 return connector_status_connected;
4421
4422         /* Well we tried, say unknown for unreliable port types */
4423         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4424                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4425                 if (type == DP_DS_PORT_TYPE_VGA ||
4426                     type == DP_DS_PORT_TYPE_NON_EDID)
4427                         return connector_status_unknown;
4428         } else {
4429                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4430                         DP_DWN_STRM_PORT_TYPE_MASK;
4431                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4432                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4433                         return connector_status_unknown;
4434         }
4435
4436         /* Anything else is out of spec, warn and ignore */
4437         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4438         return connector_status_disconnected;
4439 }
4440
4441 static enum drm_connector_status
4442 edp_detect(struct intel_dp *intel_dp)
4443 {
4444         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4445         enum drm_connector_status status;
4446
4447         status = intel_panel_detect(dev_priv);
4448         if (status == connector_status_unknown)
4449                 status = connector_status_connected;
4450
4451         return status;
4452 }
4453
4454 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4455                                        struct intel_digital_port *port)
4456 {
4457         u32 bit;
4458
4459         switch (port->base.port) {
4460         case PORT_B:
4461                 bit = SDE_PORTB_HOTPLUG;
4462                 break;
4463         case PORT_C:
4464                 bit = SDE_PORTC_HOTPLUG;
4465                 break;
4466         case PORT_D:
4467                 bit = SDE_PORTD_HOTPLUG;
4468                 break;
4469         default:
4470                 MISSING_CASE(port->base.port);
4471                 return false;
4472         }
4473
4474         return I915_READ(SDEISR) & bit;
4475 }
4476
4477 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4478                                        struct intel_digital_port *port)
4479 {
4480         u32 bit;
4481
4482         switch (port->base.port) {
4483         case PORT_B:
4484                 bit = SDE_PORTB_HOTPLUG_CPT;
4485                 break;
4486         case PORT_C:
4487                 bit = SDE_PORTC_HOTPLUG_CPT;
4488                 break;
4489         case PORT_D:
4490                 bit = SDE_PORTD_HOTPLUG_CPT;
4491                 break;
4492         default:
4493                 MISSING_CASE(port->base.port);
4494                 return false;
4495         }
4496
4497         return I915_READ(SDEISR) & bit;
4498 }
4499
4500 static bool spt_digital_port_connected(struct drm_i915_private *dev_priv,
4501                                        struct intel_digital_port *port)
4502 {
4503         u32 bit;
4504
4505         switch (port->base.port) {
4506         case PORT_A:
4507                 bit = SDE_PORTA_HOTPLUG_SPT;
4508                 break;
4509         case PORT_E:
4510                 bit = SDE_PORTE_HOTPLUG_SPT;
4511                 break;
4512         default:
4513                 return cpt_digital_port_connected(dev_priv, port);
4514         }
4515
4516         return I915_READ(SDEISR) & bit;
4517 }
4518
4519 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4520                                        struct intel_digital_port *port)
4521 {
4522         u32 bit;
4523
4524         switch (port->base.port) {
4525         case PORT_B:
4526                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4527                 break;
4528         case PORT_C:
4529                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4530                 break;
4531         case PORT_D:
4532                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4533                 break;
4534         default:
4535                 MISSING_CASE(port->base.port);
4536                 return false;
4537         }
4538
4539         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4540 }
4541
4542 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4543                                         struct intel_digital_port *port)
4544 {
4545         u32 bit;
4546
4547         switch (port->base.port) {
4548         case PORT_B:
4549                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4550                 break;
4551         case PORT_C:
4552                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4553                 break;
4554         case PORT_D:
4555                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4556                 break;
4557         default:
4558                 MISSING_CASE(port->base.port);
4559                 return false;
4560         }
4561
4562         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4563 }
4564
4565 static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv,
4566                                        struct intel_digital_port *port)
4567 {
4568         if (port->base.port == PORT_A)
4569                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4570         else
4571                 return ibx_digital_port_connected(dev_priv, port);
4572 }
4573
4574 static bool snb_digital_port_connected(struct drm_i915_private *dev_priv,
4575                                        struct intel_digital_port *port)
4576 {
4577         if (port->base.port == PORT_A)
4578                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4579         else
4580                 return cpt_digital_port_connected(dev_priv, port);
4581 }
4582
4583 static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv,
4584                                        struct intel_digital_port *port)
4585 {
4586         if (port->base.port == PORT_A)
4587                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4588         else
4589                 return cpt_digital_port_connected(dev_priv, port);
4590 }
4591
4592 static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv,
4593                                        struct intel_digital_port *port)
4594 {
4595         if (port->base.port == PORT_A)
4596                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4597         else
4598                 return cpt_digital_port_connected(dev_priv, port);
4599 }
4600
4601 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4602                                        struct intel_digital_port *intel_dig_port)
4603 {
4604         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4605         enum port port;
4606         u32 bit;
4607
4608         port = intel_hpd_pin_to_port(intel_encoder->hpd_pin);
4609         switch (port) {
4610         case PORT_A:
4611                 bit = BXT_DE_PORT_HP_DDIA;
4612                 break;
4613         case PORT_B:
4614                 bit = BXT_DE_PORT_HP_DDIB;
4615                 break;
4616         case PORT_C:
4617                 bit = BXT_DE_PORT_HP_DDIC;
4618                 break;
4619         default:
4620                 MISSING_CASE(port);
4621                 return false;
4622         }
4623
4624         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4625 }
4626
4627 /*
4628  * intel_digital_port_connected - is the specified port connected?
4629  * @dev_priv: i915 private structure
4630  * @port: the port to test
4631  *
4632  * Return %true if @port is connected, %false otherwise.
4633  */
4634 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4635                                   struct intel_digital_port *port)
4636 {
4637         if (HAS_GMCH_DISPLAY(dev_priv)) {
4638                 if (IS_GM45(dev_priv))
4639                         return gm45_digital_port_connected(dev_priv, port);
4640                 else
4641                         return g4x_digital_port_connected(dev_priv, port);
4642         }
4643
4644         if (IS_GEN5(dev_priv))
4645                 return ilk_digital_port_connected(dev_priv, port);
4646         else if (IS_GEN6(dev_priv))
4647                 return snb_digital_port_connected(dev_priv, port);
4648         else if (IS_GEN7(dev_priv))
4649                 return ivb_digital_port_connected(dev_priv, port);
4650         else if (IS_GEN8(dev_priv))
4651                 return bdw_digital_port_connected(dev_priv, port);
4652         else if (IS_GEN9_LP(dev_priv))
4653                 return bxt_digital_port_connected(dev_priv, port);
4654         else
4655                 return spt_digital_port_connected(dev_priv, port);
4656 }
4657
4658 static struct edid *
4659 intel_dp_get_edid(struct intel_dp *intel_dp)
4660 {
4661         struct intel_connector *intel_connector = intel_dp->attached_connector;
4662
4663         /* use cached edid if we have one */
4664         if (intel_connector->edid) {
4665                 /* invalid edid */
4666                 if (IS_ERR(intel_connector->edid))
4667                         return NULL;
4668
4669                 return drm_edid_duplicate(intel_connector->edid);
4670         } else
4671                 return drm_get_edid(&intel_connector->base,
4672                                     &intel_dp->aux.ddc);
4673 }
4674
4675 static void
4676 intel_dp_set_edid(struct intel_dp *intel_dp)
4677 {
4678         struct intel_connector *intel_connector = intel_dp->attached_connector;
4679         struct edid *edid;
4680
4681         intel_dp_unset_edid(intel_dp);
4682         edid = intel_dp_get_edid(intel_dp);
4683         intel_connector->detect_edid = edid;
4684
4685         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4686 }
4687
4688 static void
4689 intel_dp_unset_edid(struct intel_dp *intel_dp)
4690 {
4691         struct intel_connector *intel_connector = intel_dp->attached_connector;
4692
4693         kfree(intel_connector->detect_edid);
4694         intel_connector->detect_edid = NULL;
4695
4696         intel_dp->has_audio = false;
4697 }
4698
4699 static int
4700 intel_dp_long_pulse(struct intel_connector *connector)
4701 {
4702         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4703         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4704         enum drm_connector_status status;
4705         u8 sink_irq_vector = 0;
4706
4707         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4708
4709         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4710
4711         /* Can't disconnect eDP, but you can close the lid... */
4712         if (intel_dp_is_edp(intel_dp))
4713                 status = edp_detect(intel_dp);
4714         else if (intel_digital_port_connected(dev_priv,
4715                                               dp_to_dig_port(intel_dp)))
4716                 status = intel_dp_detect_dpcd(intel_dp);
4717         else
4718                 status = connector_status_disconnected;
4719
4720         if (status == connector_status_disconnected) {
4721                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4722
4723                 if (intel_dp->is_mst) {
4724                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4725                                       intel_dp->is_mst,
4726                                       intel_dp->mst_mgr.mst_state);
4727                         intel_dp->is_mst = false;
4728                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4729                                                         intel_dp->is_mst);
4730                 }
4731
4732                 goto out;
4733         }
4734
4735         if (intel_dp->reset_link_params) {
4736                 /* Initial max link lane count */
4737                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4738
4739                 /* Initial max link rate */
4740                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4741
4742                 intel_dp->reset_link_params = false;
4743         }
4744
4745         intel_dp_print_rates(intel_dp);
4746
4747         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4748                          drm_dp_is_branch(intel_dp->dpcd));
4749
4750         intel_dp_configure_mst(intel_dp);
4751
4752         if (intel_dp->is_mst) {
4753                 /*
4754                  * If we are in MST mode then this connector
4755                  * won't appear connected or have anything
4756                  * with EDID on it
4757                  */
4758                 status = connector_status_disconnected;
4759                 goto out;
4760         } else {
4761                 /*
4762                  * If display is now connected check links status,
4763                  * there has been known issues of link loss triggerring
4764                  * long pulse.
4765                  *
4766                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4767                  * weird HPD ping pong during modesets. So we can apparently
4768                  * end up with HPD going low during a modeset, and then
4769                  * going back up soon after. And once that happens we must
4770                  * retrain the link to get a picture. That's in case no
4771                  * userspace component reacted to intermittent HPD dip.
4772                  */
4773                 intel_dp_check_link_status(intel_dp);
4774         }
4775
4776         /*
4777          * Clearing NACK and defer counts to get their exact values
4778          * while reading EDID which are required by Compliance tests
4779          * 4.2.2.4 and 4.2.2.5
4780          */
4781         intel_dp->aux.i2c_nack_count = 0;
4782         intel_dp->aux.i2c_defer_count = 0;
4783
4784         intel_dp_set_edid(intel_dp);
4785         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4786                 status = connector_status_connected;
4787         intel_dp->detect_done = true;
4788
4789         /* Try to read the source of the interrupt */
4790         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4791             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4792             sink_irq_vector != 0) {
4793                 /* Clear interrupt source */
4794                 drm_dp_dpcd_writeb(&intel_dp->aux,
4795                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4796                                    sink_irq_vector);
4797
4798                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4799                         intel_dp_handle_test_request(intel_dp);
4800                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4801                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4802         }
4803
4804 out:
4805         if (status != connector_status_connected && !intel_dp->is_mst)
4806                 intel_dp_unset_edid(intel_dp);
4807
4808         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4809         return status;
4810 }
4811
4812 static int
4813 intel_dp_detect(struct drm_connector *connector,
4814                 struct drm_modeset_acquire_ctx *ctx,
4815                 bool force)
4816 {
4817         struct intel_dp *intel_dp = intel_attached_dp(connector);
4818         int status = connector->status;
4819
4820         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4821                       connector->base.id, connector->name);
4822
4823         /* If full detect is not performed yet, do a full detect */
4824         if (!intel_dp->detect_done) {
4825                 struct drm_crtc *crtc;
4826                 int ret;
4827
4828                 crtc = connector->state->crtc;
4829                 if (crtc) {
4830                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4831                         if (ret)
4832                                 return ret;
4833                 }
4834
4835                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4836         }
4837
4838         intel_dp->detect_done = false;
4839
4840         return status;
4841 }
4842
4843 static void
4844 intel_dp_force(struct drm_connector *connector)
4845 {
4846         struct intel_dp *intel_dp = intel_attached_dp(connector);
4847         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4848         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4849
4850         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4851                       connector->base.id, connector->name);
4852         intel_dp_unset_edid(intel_dp);
4853
4854         if (connector->status != connector_status_connected)
4855                 return;
4856
4857         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4858
4859         intel_dp_set_edid(intel_dp);
4860
4861         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4862 }
4863
4864 static int intel_dp_get_modes(struct drm_connector *connector)
4865 {
4866         struct intel_connector *intel_connector = to_intel_connector(connector);
4867         struct edid *edid;
4868
4869         edid = intel_connector->detect_edid;
4870         if (edid) {
4871                 int ret = intel_connector_update_modes(connector, edid);
4872                 if (ret)
4873                         return ret;
4874         }
4875
4876         /* if eDP has no EDID, fall back to fixed mode */
4877         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4878             intel_connector->panel.fixed_mode) {
4879                 struct drm_display_mode *mode;
4880
4881                 mode = drm_mode_duplicate(connector->dev,
4882                                           intel_connector->panel.fixed_mode);
4883                 if (mode) {
4884                         drm_mode_probed_add(connector, mode);
4885                         return 1;
4886                 }
4887         }
4888
4889         return 0;
4890 }
4891
4892 static int
4893 intel_dp_connector_register(struct drm_connector *connector)
4894 {
4895         struct intel_dp *intel_dp = intel_attached_dp(connector);
4896         int ret;
4897
4898         ret = intel_connector_register(connector);
4899         if (ret)
4900                 return ret;
4901
4902         i915_debugfs_connector_add(connector);
4903
4904         DRM_DEBUG_KMS("registering %s bus for %s\n",
4905                       intel_dp->aux.name, connector->kdev->kobj.name);
4906
4907         intel_dp->aux.dev = connector->kdev;
4908         return drm_dp_aux_register(&intel_dp->aux);
4909 }
4910
4911 static void
4912 intel_dp_connector_unregister(struct drm_connector *connector)
4913 {
4914         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4915         intel_connector_unregister(connector);
4916 }
4917
4918 static void
4919 intel_dp_connector_destroy(struct drm_connector *connector)
4920 {
4921         struct intel_connector *intel_connector = to_intel_connector(connector);
4922
4923         kfree(intel_connector->detect_edid);
4924
4925         if (!IS_ERR_OR_NULL(intel_connector->edid))
4926                 kfree(intel_connector->edid);
4927
4928         /*
4929          * Can't call intel_dp_is_edp() since the encoder may have been
4930          * destroyed already.
4931          */
4932         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4933                 intel_panel_fini(&intel_connector->panel);
4934
4935         drm_connector_cleanup(connector);
4936         kfree(connector);
4937 }
4938
4939 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4940 {
4941         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4942         struct intel_dp *intel_dp = &intel_dig_port->dp;
4943
4944         intel_dp_mst_encoder_cleanup(intel_dig_port);
4945         if (intel_dp_is_edp(intel_dp)) {
4946                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4947                 /*
4948                  * vdd might still be enabled do to the delayed vdd off.
4949                  * Make sure vdd is actually turned off here.
4950                  */
4951                 pps_lock(intel_dp);
4952                 edp_panel_vdd_off_sync(intel_dp);
4953                 pps_unlock(intel_dp);
4954
4955                 if (intel_dp->edp_notifier.notifier_call) {
4956                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4957                         intel_dp->edp_notifier.notifier_call = NULL;
4958                 }
4959         }
4960
4961         intel_dp_aux_fini(intel_dp);
4962
4963         drm_encoder_cleanup(encoder);
4964         kfree(intel_dig_port);
4965 }
4966
4967 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4968 {
4969         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4970
4971         if (!intel_dp_is_edp(intel_dp))
4972                 return;
4973
4974         /*
4975          * vdd might still be enabled do to the delayed vdd off.
4976          * Make sure vdd is actually turned off here.
4977          */
4978         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4979         pps_lock(intel_dp);
4980         edp_panel_vdd_off_sync(intel_dp);
4981         pps_unlock(intel_dp);
4982 }
4983
4984 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4985 {
4986         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4987
4988         lockdep_assert_held(&dev_priv->pps_mutex);
4989
4990         if (!edp_have_panel_vdd(intel_dp))
4991                 return;
4992
4993         /*
4994          * The VDD bit needs a power domain reference, so if the bit is
4995          * already enabled when we boot or resume, grab this reference and
4996          * schedule a vdd off, so we don't hold on to the reference
4997          * indefinitely.
4998          */
4999         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5000         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5001
5002         edp_panel_vdd_schedule_off(intel_dp);
5003 }
5004
5005 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5006 {
5007         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5008
5009         if ((intel_dp->DP & DP_PORT_EN) == 0)
5010                 return INVALID_PIPE;
5011
5012         if (IS_CHERRYVIEW(dev_priv))
5013                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5014         else
5015                 return PORT_TO_PIPE(intel_dp->DP);
5016 }
5017
5018 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5019 {
5020         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5021         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5022         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5023
5024         if (!HAS_DDI(dev_priv))
5025                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5026
5027         if (lspcon->active)
5028                 lspcon_resume(lspcon);
5029
5030         intel_dp->reset_link_params = true;
5031
5032         pps_lock(intel_dp);
5033
5034         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5035                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5036
5037         if (intel_dp_is_edp(intel_dp)) {
5038                 /* Reinit the power sequencer, in case BIOS did something with it. */
5039                 intel_dp_pps_init(intel_dp);
5040                 intel_edp_panel_vdd_sanitize(intel_dp);
5041         }
5042
5043         pps_unlock(intel_dp);
5044 }
5045
5046 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5047         .force = intel_dp_force,
5048         .fill_modes = drm_helper_probe_single_connector_modes,
5049         .atomic_get_property = intel_digital_connector_atomic_get_property,
5050         .atomic_set_property = intel_digital_connector_atomic_set_property,
5051         .late_register = intel_dp_connector_register,
5052         .early_unregister = intel_dp_connector_unregister,
5053         .destroy = intel_dp_connector_destroy,
5054         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5055         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5056 };
5057
5058 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5059         .detect_ctx = intel_dp_detect,
5060         .get_modes = intel_dp_get_modes,
5061         .mode_valid = intel_dp_mode_valid,
5062         .atomic_check = intel_digital_connector_atomic_check,
5063 };
5064
5065 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5066         .reset = intel_dp_encoder_reset,
5067         .destroy = intel_dp_encoder_destroy,
5068 };
5069
5070 enum irqreturn
5071 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5072 {
5073         struct intel_dp *intel_dp = &intel_dig_port->dp;
5074         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5075         enum irqreturn ret = IRQ_NONE;
5076
5077         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5078                 /*
5079                  * vdd off can generate a long pulse on eDP which
5080                  * would require vdd on to handle it, and thus we
5081                  * would end up in an endless cycle of
5082                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5083                  */
5084                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5085                               port_name(intel_dig_port->base.port));
5086                 return IRQ_HANDLED;
5087         }
5088
5089         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5090                       port_name(intel_dig_port->base.port),
5091                       long_hpd ? "long" : "short");
5092
5093         if (long_hpd) {
5094                 intel_dp->reset_link_params = true;
5095                 intel_dp->detect_done = false;
5096                 return IRQ_NONE;
5097         }
5098
5099         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5100
5101         if (intel_dp->is_mst) {
5102                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5103                         /*
5104                          * If we were in MST mode, and device is not
5105                          * there, get out of MST mode
5106                          */
5107                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5108                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5109                         intel_dp->is_mst = false;
5110                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5111                                                         intel_dp->is_mst);
5112                         intel_dp->detect_done = false;
5113                         goto put_power;
5114                 }
5115         }
5116
5117         if (!intel_dp->is_mst) {
5118                 struct drm_modeset_acquire_ctx ctx;
5119                 struct drm_connector *connector = &intel_dp->attached_connector->base;
5120                 struct drm_crtc *crtc;
5121                 int iret;
5122                 bool handled = false;
5123
5124                 drm_modeset_acquire_init(&ctx, 0);
5125 retry:
5126                 iret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, &ctx);
5127                 if (iret)
5128                         goto err;
5129
5130                 crtc = connector->state->crtc;
5131                 if (crtc) {
5132                         iret = drm_modeset_lock(&crtc->mutex, &ctx);
5133                         if (iret)
5134                                 goto err;
5135                 }
5136
5137                 handled = intel_dp_short_pulse(intel_dp);
5138
5139 err:
5140                 if (iret == -EDEADLK) {
5141                         drm_modeset_backoff(&ctx);
5142                         goto retry;
5143                 }
5144
5145                 drm_modeset_drop_locks(&ctx);
5146                 drm_modeset_acquire_fini(&ctx);
5147                 WARN(iret, "Acquiring modeset locks failed with %i\n", iret);
5148
5149                 if (!handled) {
5150                         intel_dp->detect_done = false;
5151                         goto put_power;
5152                 }
5153         }
5154
5155         ret = IRQ_HANDLED;
5156
5157 put_power:
5158         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5159
5160         return ret;
5161 }
5162
5163 /* check the VBT to see whether the eDP is on another port */
5164 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5165 {
5166         /*
5167          * eDP not supported on g4x. so bail out early just
5168          * for a bit extra safety in case the VBT is bonkers.
5169          */
5170         if (INTEL_GEN(dev_priv) < 5)
5171                 return false;
5172
5173         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5174                 return true;
5175
5176         return intel_bios_is_port_edp(dev_priv, port);
5177 }
5178
5179 static void
5180 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5181 {
5182         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5183         enum port port = dp_to_dig_port(intel_dp)->base.port;
5184
5185         if (!IS_G4X(dev_priv) && port != PORT_A)
5186                 intel_attach_force_audio_property(connector);
5187
5188         intel_attach_broadcast_rgb_property(connector);
5189
5190         if (intel_dp_is_edp(intel_dp)) {
5191                 u32 allowed_scalers;
5192
5193                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5194                 if (!HAS_GMCH_DISPLAY(dev_priv))
5195                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5196
5197                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5198
5199                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5200
5201         }
5202 }
5203
5204 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5205 {
5206         intel_dp->panel_power_off_time = ktime_get_boottime();
5207         intel_dp->last_power_on = jiffies;
5208         intel_dp->last_backlight_off = jiffies;
5209 }
5210
5211 static void
5212 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5213 {
5214         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5215         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5216         struct pps_registers regs;
5217
5218         intel_pps_get_registers(intel_dp, &regs);
5219
5220         /* Workaround: Need to write PP_CONTROL with the unlock key as
5221          * the very first thing. */
5222         pp_ctl = ironlake_get_pp_control(intel_dp);
5223
5224         pp_on = I915_READ(regs.pp_on);
5225         pp_off = I915_READ(regs.pp_off);
5226         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
5227                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5228                 pp_div = I915_READ(regs.pp_div);
5229         }
5230
5231         /* Pull timing values out of registers */
5232         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5233                      PANEL_POWER_UP_DELAY_SHIFT;
5234
5235         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5236                   PANEL_LIGHT_ON_DELAY_SHIFT;
5237
5238         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5239                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5240
5241         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5242                    PANEL_POWER_DOWN_DELAY_SHIFT;
5243
5244         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5245                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5246                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5247         } else {
5248                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5249                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5250         }
5251 }
5252
5253 static void
5254 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5255 {
5256         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5257                       state_name,
5258                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5259 }
5260
5261 static void
5262 intel_pps_verify_state(struct intel_dp *intel_dp)
5263 {
5264         struct edp_power_seq hw;
5265         struct edp_power_seq *sw = &intel_dp->pps_delays;
5266
5267         intel_pps_readout_hw_state(intel_dp, &hw);
5268
5269         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5270             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5271                 DRM_ERROR("PPS state mismatch\n");
5272                 intel_pps_dump_state("sw", sw);
5273                 intel_pps_dump_state("hw", &hw);
5274         }
5275 }
5276
5277 static void
5278 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5279 {
5280         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5281         struct edp_power_seq cur, vbt, spec,
5282                 *final = &intel_dp->pps_delays;
5283
5284         lockdep_assert_held(&dev_priv->pps_mutex);
5285
5286         /* already initialized? */
5287         if (final->t11_t12 != 0)
5288                 return;
5289
5290         intel_pps_readout_hw_state(intel_dp, &cur);
5291
5292         intel_pps_dump_state("cur", &cur);
5293
5294         vbt = dev_priv->vbt.edp.pps;
5295         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5296          * of 500ms appears to be too short. Ocassionally the panel
5297          * just fails to power back on. Increasing the delay to 800ms
5298          * seems sufficient to avoid this problem.
5299          */
5300         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5301                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5302                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5303                               vbt.t11_t12);
5304         }
5305         /* T11_T12 delay is special and actually in units of 100ms, but zero
5306          * based in the hw (so we need to add 100 ms). But the sw vbt
5307          * table multiplies it with 1000 to make it in units of 100usec,
5308          * too. */
5309         vbt.t11_t12 += 100 * 10;
5310
5311         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5312          * our hw here, which are all in 100usec. */
5313         spec.t1_t3 = 210 * 10;
5314         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5315         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5316         spec.t10 = 500 * 10;
5317         /* This one is special and actually in units of 100ms, but zero
5318          * based in the hw (so we need to add 100 ms). But the sw vbt
5319          * table multiplies it with 1000 to make it in units of 100usec,
5320          * too. */
5321         spec.t11_t12 = (510 + 100) * 10;
5322
5323         intel_pps_dump_state("vbt", &vbt);
5324
5325         /* Use the max of the register settings and vbt. If both are
5326          * unset, fall back to the spec limits. */
5327 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5328                                        spec.field : \
5329                                        max(cur.field, vbt.field))
5330         assign_final(t1_t3);
5331         assign_final(t8);
5332         assign_final(t9);
5333         assign_final(t10);
5334         assign_final(t11_t12);
5335 #undef assign_final
5336
5337 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5338         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5339         intel_dp->backlight_on_delay = get_delay(t8);
5340         intel_dp->backlight_off_delay = get_delay(t9);
5341         intel_dp->panel_power_down_delay = get_delay(t10);
5342         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5343 #undef get_delay
5344
5345         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5346                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5347                       intel_dp->panel_power_cycle_delay);
5348
5349         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5350                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5351
5352         /*
5353          * We override the HW backlight delays to 1 because we do manual waits
5354          * on them. For T8, even BSpec recommends doing it. For T9, if we
5355          * don't do this, we'll end up waiting for the backlight off delay
5356          * twice: once when we do the manual sleep, and once when we disable
5357          * the panel and wait for the PP_STATUS bit to become zero.
5358          */
5359         final->t8 = 1;
5360         final->t9 = 1;
5361
5362         /*
5363          * HW has only a 100msec granularity for t11_t12 so round it up
5364          * accordingly.
5365          */
5366         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5367 }
5368
5369 static void
5370 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5371                                               bool force_disable_vdd)
5372 {
5373         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5374         u32 pp_on, pp_off, pp_div, port_sel = 0;
5375         int div = dev_priv->rawclk_freq / 1000;
5376         struct pps_registers regs;
5377         enum port port = dp_to_dig_port(intel_dp)->base.port;
5378         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5379
5380         lockdep_assert_held(&dev_priv->pps_mutex);
5381
5382         intel_pps_get_registers(intel_dp, &regs);
5383
5384         /*
5385          * On some VLV machines the BIOS can leave the VDD
5386          * enabled even on power seqeuencers which aren't
5387          * hooked up to any port. This would mess up the
5388          * power domain tracking the first time we pick
5389          * one of these power sequencers for use since
5390          * edp_panel_vdd_on() would notice that the VDD was
5391          * already on and therefore wouldn't grab the power
5392          * domain reference. Disable VDD first to avoid this.
5393          * This also avoids spuriously turning the VDD on as
5394          * soon as the new power seqeuencer gets initialized.
5395          */
5396         if (force_disable_vdd) {
5397                 u32 pp = ironlake_get_pp_control(intel_dp);
5398
5399                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5400
5401                 if (pp & EDP_FORCE_VDD)
5402                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5403
5404                 pp &= ~EDP_FORCE_VDD;
5405
5406                 I915_WRITE(regs.pp_ctrl, pp);
5407         }
5408
5409         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5410                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5411         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5412                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5413         /* Compute the divisor for the pp clock, simply match the Bspec
5414          * formula. */
5415         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
5416                 pp_div = I915_READ(regs.pp_ctrl);
5417                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5418                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5419                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5420         } else {
5421                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5422                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5423                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5424         }
5425
5426         /* Haswell doesn't have any port selection bits for the panel
5427          * power sequencer any more. */
5428         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5429                 port_sel = PANEL_PORT_SELECT_VLV(port);
5430         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5431                 if (port == PORT_A)
5432                         port_sel = PANEL_PORT_SELECT_DPA;
5433                 else
5434                         port_sel = PANEL_PORT_SELECT_DPD;
5435         }
5436
5437         pp_on |= port_sel;
5438
5439         I915_WRITE(regs.pp_on, pp_on);
5440         I915_WRITE(regs.pp_off, pp_off);
5441         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
5442                 I915_WRITE(regs.pp_ctrl, pp_div);
5443         else
5444                 I915_WRITE(regs.pp_div, pp_div);
5445
5446         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5447                       I915_READ(regs.pp_on),
5448                       I915_READ(regs.pp_off),
5449                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
5450                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5451                       I915_READ(regs.pp_div));
5452 }
5453
5454 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5455 {
5456         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5457
5458         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5459                 vlv_initial_power_sequencer_setup(intel_dp);
5460         } else {
5461                 intel_dp_init_panel_power_sequencer(intel_dp);
5462                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5463         }
5464 }
5465
5466 /**
5467  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5468  * @dev_priv: i915 device
5469  * @crtc_state: a pointer to the active intel_crtc_state
5470  * @refresh_rate: RR to be programmed
5471  *
5472  * This function gets called when refresh rate (RR) has to be changed from
5473  * one frequency to another. Switches can be between high and low RR
5474  * supported by the panel or to any other RR based on media playback (in
5475  * this case, RR value needs to be passed from user space).
5476  *
5477  * The caller of this function needs to take a lock on dev_priv->drrs.
5478  */
5479 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5480                                     const struct intel_crtc_state *crtc_state,
5481                                     int refresh_rate)
5482 {
5483         struct intel_encoder *encoder;
5484         struct intel_digital_port *dig_port = NULL;
5485         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5487         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5488
5489         if (refresh_rate <= 0) {
5490                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5491                 return;
5492         }
5493
5494         if (intel_dp == NULL) {
5495                 DRM_DEBUG_KMS("DRRS not supported.\n");
5496                 return;
5497         }
5498
5499         dig_port = dp_to_dig_port(intel_dp);
5500         encoder = &dig_port->base;
5501
5502         if (!intel_crtc) {
5503                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5504                 return;
5505         }
5506
5507         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5508                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5509                 return;
5510         }
5511
5512         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5513                         refresh_rate)
5514                 index = DRRS_LOW_RR;
5515
5516         if (index == dev_priv->drrs.refresh_rate_type) {
5517                 DRM_DEBUG_KMS(
5518                         "DRRS requested for previously set RR...ignoring\n");
5519                 return;
5520         }
5521
5522         if (!crtc_state->base.active) {
5523                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5524                 return;
5525         }
5526
5527         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5528                 switch (index) {
5529                 case DRRS_HIGH_RR:
5530                         intel_dp_set_m_n(intel_crtc, M1_N1);
5531                         break;
5532                 case DRRS_LOW_RR:
5533                         intel_dp_set_m_n(intel_crtc, M2_N2);
5534                         break;
5535                 case DRRS_MAX_RR:
5536                 default:
5537                         DRM_ERROR("Unsupported refreshrate type\n");
5538                 }
5539         } else if (INTEL_GEN(dev_priv) > 6) {
5540                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5541                 u32 val;
5542
5543                 val = I915_READ(reg);
5544                 if (index > DRRS_HIGH_RR) {
5545                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5546                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5547                         else
5548                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5549                 } else {
5550                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5551                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5552                         else
5553                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5554                 }
5555                 I915_WRITE(reg, val);
5556         }
5557
5558         dev_priv->drrs.refresh_rate_type = index;
5559
5560         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5561 }
5562
5563 /**
5564  * intel_edp_drrs_enable - init drrs struct if supported
5565  * @intel_dp: DP struct
5566  * @crtc_state: A pointer to the active crtc state.
5567  *
5568  * Initializes frontbuffer_bits and drrs.dp
5569  */
5570 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5571                            const struct intel_crtc_state *crtc_state)
5572 {
5573         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5574
5575         if (!crtc_state->has_drrs) {
5576                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5577                 return;
5578         }
5579
5580         if (dev_priv->psr.enabled) {
5581                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5582                 return;
5583         }
5584
5585         mutex_lock(&dev_priv->drrs.mutex);
5586         if (WARN_ON(dev_priv->drrs.dp)) {
5587                 DRM_ERROR("DRRS already enabled\n");
5588                 goto unlock;
5589         }
5590
5591         dev_priv->drrs.busy_frontbuffer_bits = 0;
5592
5593         dev_priv->drrs.dp = intel_dp;
5594
5595 unlock:
5596         mutex_unlock(&dev_priv->drrs.mutex);
5597 }
5598
5599 /**
5600  * intel_edp_drrs_disable - Disable DRRS
5601  * @intel_dp: DP struct
5602  * @old_crtc_state: Pointer to old crtc_state.
5603  *
5604  */
5605 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5606                             const struct intel_crtc_state *old_crtc_state)
5607 {
5608         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5609
5610         if (!old_crtc_state->has_drrs)
5611                 return;
5612
5613         mutex_lock(&dev_priv->drrs.mutex);
5614         if (!dev_priv->drrs.dp) {
5615                 mutex_unlock(&dev_priv->drrs.mutex);
5616                 return;
5617         }
5618
5619         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5620                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5621                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5622
5623         dev_priv->drrs.dp = NULL;
5624         mutex_unlock(&dev_priv->drrs.mutex);
5625
5626         cancel_delayed_work_sync(&dev_priv->drrs.work);
5627 }
5628
5629 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5630 {
5631         struct drm_i915_private *dev_priv =
5632                 container_of(work, typeof(*dev_priv), drrs.work.work);
5633         struct intel_dp *intel_dp;
5634
5635         mutex_lock(&dev_priv->drrs.mutex);
5636
5637         intel_dp = dev_priv->drrs.dp;
5638
5639         if (!intel_dp)
5640                 goto unlock;
5641
5642         /*
5643          * The delayed work can race with an invalidate hence we need to
5644          * recheck.
5645          */
5646
5647         if (dev_priv->drrs.busy_frontbuffer_bits)
5648                 goto unlock;
5649
5650         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5651                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5652
5653                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5654                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5655         }
5656
5657 unlock:
5658         mutex_unlock(&dev_priv->drrs.mutex);
5659 }
5660
5661 /**
5662  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5663  * @dev_priv: i915 device
5664  * @frontbuffer_bits: frontbuffer plane tracking bits
5665  *
5666  * This function gets called everytime rendering on the given planes start.
5667  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5668  *
5669  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5670  */
5671 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5672                                unsigned int frontbuffer_bits)
5673 {
5674         struct drm_crtc *crtc;
5675         enum pipe pipe;
5676
5677         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5678                 return;
5679
5680         cancel_delayed_work(&dev_priv->drrs.work);
5681
5682         mutex_lock(&dev_priv->drrs.mutex);
5683         if (!dev_priv->drrs.dp) {
5684                 mutex_unlock(&dev_priv->drrs.mutex);
5685                 return;
5686         }
5687
5688         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5689         pipe = to_intel_crtc(crtc)->pipe;
5690
5691         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5692         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5693
5694         /* invalidate means busy screen hence upclock */
5695         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5696                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5697                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5698
5699         mutex_unlock(&dev_priv->drrs.mutex);
5700 }
5701
5702 /**
5703  * intel_edp_drrs_flush - Restart Idleness DRRS
5704  * @dev_priv: i915 device
5705  * @frontbuffer_bits: frontbuffer plane tracking bits
5706  *
5707  * This function gets called every time rendering on the given planes has
5708  * completed or flip on a crtc is completed. So DRRS should be upclocked
5709  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5710  * if no other planes are dirty.
5711  *
5712  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5713  */
5714 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5715                           unsigned int frontbuffer_bits)
5716 {
5717         struct drm_crtc *crtc;
5718         enum pipe pipe;
5719
5720         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5721                 return;
5722
5723         cancel_delayed_work(&dev_priv->drrs.work);
5724
5725         mutex_lock(&dev_priv->drrs.mutex);
5726         if (!dev_priv->drrs.dp) {
5727                 mutex_unlock(&dev_priv->drrs.mutex);
5728                 return;
5729         }
5730
5731         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5732         pipe = to_intel_crtc(crtc)->pipe;
5733
5734         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5735         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5736
5737         /* flush means busy screen hence upclock */
5738         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5739                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5740                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5741
5742         /*
5743          * flush also means no more activity hence schedule downclock, if all
5744          * other fbs are quiescent too
5745          */
5746         if (!dev_priv->drrs.busy_frontbuffer_bits)
5747                 schedule_delayed_work(&dev_priv->drrs.work,
5748                                 msecs_to_jiffies(1000));
5749         mutex_unlock(&dev_priv->drrs.mutex);
5750 }
5751
5752 /**
5753  * DOC: Display Refresh Rate Switching (DRRS)
5754  *
5755  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5756  * which enables swtching between low and high refresh rates,
5757  * dynamically, based on the usage scenario. This feature is applicable
5758  * for internal panels.
5759  *
5760  * Indication that the panel supports DRRS is given by the panel EDID, which
5761  * would list multiple refresh rates for one resolution.
5762  *
5763  * DRRS is of 2 types - static and seamless.
5764  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5765  * (may appear as a blink on screen) and is used in dock-undock scenario.
5766  * Seamless DRRS involves changing RR without any visual effect to the user
5767  * and can be used during normal system usage. This is done by programming
5768  * certain registers.
5769  *
5770  * Support for static/seamless DRRS may be indicated in the VBT based on
5771  * inputs from the panel spec.
5772  *
5773  * DRRS saves power by switching to low RR based on usage scenarios.
5774  *
5775  * The implementation is based on frontbuffer tracking implementation.  When
5776  * there is a disturbance on the screen triggered by user activity or a periodic
5777  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5778  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5779  * made.
5780  *
5781  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5782  * and intel_edp_drrs_flush() are called.
5783  *
5784  * DRRS can be further extended to support other internal panels and also
5785  * the scenario of video playback wherein RR is set based on the rate
5786  * requested by userspace.
5787  */
5788
5789 /**
5790  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5791  * @connector: eDP connector
5792  * @fixed_mode: preferred mode of panel
5793  *
5794  * This function is  called only once at driver load to initialize basic
5795  * DRRS stuff.
5796  *
5797  * Returns:
5798  * Downclock mode if panel supports it, else return NULL.
5799  * DRRS support is determined by the presence of downclock mode (apart
5800  * from VBT setting).
5801  */
5802 static struct drm_display_mode *
5803 intel_dp_drrs_init(struct intel_connector *connector,
5804                    struct drm_display_mode *fixed_mode)
5805 {
5806         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5807         struct drm_display_mode *downclock_mode = NULL;
5808
5809         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5810         mutex_init(&dev_priv->drrs.mutex);
5811
5812         if (INTEL_GEN(dev_priv) <= 6) {
5813                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5814                 return NULL;
5815         }
5816
5817         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5818                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5819                 return NULL;
5820         }
5821
5822         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
5823                                                     &connector->base);
5824
5825         if (!downclock_mode) {
5826                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5827                 return NULL;
5828         }
5829
5830         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5831
5832         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5833         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5834         return downclock_mode;
5835 }
5836
5837 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5838                                      struct intel_connector *intel_connector)
5839 {
5840         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5841         struct drm_i915_private *dev_priv = to_i915(dev);
5842         struct drm_connector *connector = &intel_connector->base;
5843         struct drm_display_mode *fixed_mode = NULL;
5844         struct drm_display_mode *alt_fixed_mode = NULL;
5845         struct drm_display_mode *downclock_mode = NULL;
5846         bool has_dpcd;
5847         struct drm_display_mode *scan;
5848         struct edid *edid;
5849         enum pipe pipe = INVALID_PIPE;
5850
5851         if (!intel_dp_is_edp(intel_dp))
5852                 return true;
5853
5854         /*
5855          * On IBX/CPT we may get here with LVDS already registered. Since the
5856          * driver uses the only internal power sequencer available for both
5857          * eDP and LVDS bail out early in this case to prevent interfering
5858          * with an already powered-on LVDS power sequencer.
5859          */
5860         if (intel_get_lvds_encoder(&dev_priv->drm)) {
5861                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5862                 DRM_INFO("LVDS was detected, not registering eDP\n");
5863
5864                 return false;
5865         }
5866
5867         pps_lock(intel_dp);
5868
5869         intel_dp_init_panel_power_timestamps(intel_dp);
5870         intel_dp_pps_init(intel_dp);
5871         intel_edp_panel_vdd_sanitize(intel_dp);
5872
5873         pps_unlock(intel_dp);
5874
5875         /* Cache DPCD and EDID for edp. */
5876         has_dpcd = intel_edp_init_dpcd(intel_dp);
5877
5878         if (!has_dpcd) {
5879                 /* if this fails, presume the device is a ghost */
5880                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5881                 goto out_vdd_off;
5882         }
5883
5884         mutex_lock(&dev->mode_config.mutex);
5885         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5886         if (edid) {
5887                 if (drm_add_edid_modes(connector, edid)) {
5888                         drm_mode_connector_update_edid_property(connector,
5889                                                                 edid);
5890                 } else {
5891                         kfree(edid);
5892                         edid = ERR_PTR(-EINVAL);
5893                 }
5894         } else {
5895                 edid = ERR_PTR(-ENOENT);
5896         }
5897         intel_connector->edid = edid;
5898
5899         /* prefer fixed mode from EDID if available, save an alt mode also */
5900         list_for_each_entry(scan, &connector->probed_modes, head) {
5901                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5902                         fixed_mode = drm_mode_duplicate(dev, scan);
5903                         downclock_mode = intel_dp_drrs_init(
5904                                                 intel_connector, fixed_mode);
5905                 } else if (!alt_fixed_mode) {
5906                         alt_fixed_mode = drm_mode_duplicate(dev, scan);
5907                 }
5908         }
5909
5910         /* fallback to VBT if available for eDP */
5911         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5912                 fixed_mode = drm_mode_duplicate(dev,
5913                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5914                 if (fixed_mode) {
5915                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5916                         connector->display_info.width_mm = fixed_mode->width_mm;
5917                         connector->display_info.height_mm = fixed_mode->height_mm;
5918                 }
5919         }
5920         mutex_unlock(&dev->mode_config.mutex);
5921
5922         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5923                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5924                 register_reboot_notifier(&intel_dp->edp_notifier);
5925
5926                 /*
5927                  * Figure out the current pipe for the initial backlight setup.
5928                  * If the current pipe isn't valid, try the PPS pipe, and if that
5929                  * fails just assume pipe A.
5930                  */
5931                 pipe = vlv_active_pipe(intel_dp);
5932
5933                 if (pipe != PIPE_A && pipe != PIPE_B)
5934                         pipe = intel_dp->pps_pipe;
5935
5936                 if (pipe != PIPE_A && pipe != PIPE_B)
5937                         pipe = PIPE_A;
5938
5939                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5940                               pipe_name(pipe));
5941         }
5942
5943         intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
5944                          downclock_mode);
5945         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5946         intel_panel_setup_backlight(connector, pipe);
5947
5948         return true;
5949
5950 out_vdd_off:
5951         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5952         /*
5953          * vdd might still be enabled do to the delayed vdd off.
5954          * Make sure vdd is actually turned off here.
5955          */
5956         pps_lock(intel_dp);
5957         edp_panel_vdd_off_sync(intel_dp);
5958         pps_unlock(intel_dp);
5959
5960         return false;
5961 }
5962
5963 /* Set up the hotplug pin and aux power domain. */
5964 static void
5965 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5966 {
5967         struct intel_encoder *encoder = &intel_dig_port->base;
5968         struct intel_dp *intel_dp = &intel_dig_port->dp;
5969
5970         encoder->hpd_pin = intel_hpd_pin(encoder->port);
5971
5972         switch (encoder->port) {
5973         case PORT_A:
5974                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5975                 break;
5976         case PORT_B:
5977                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5978                 break;
5979         case PORT_C:
5980                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5981                 break;
5982         case PORT_D:
5983                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5984                 break;
5985         case PORT_E:
5986                 /* FIXME: Check VBT for actual wiring of PORT E */
5987                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5988                 break;
5989         default:
5990                 MISSING_CASE(encoder->port);
5991         }
5992 }
5993
5994 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5995 {
5996         struct intel_connector *intel_connector;
5997         struct drm_connector *connector;
5998
5999         intel_connector = container_of(work, typeof(*intel_connector),
6000                                        modeset_retry_work);
6001         connector = &intel_connector->base;
6002         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6003                       connector->name);
6004
6005         /* Grab the locks before changing connector property*/
6006         mutex_lock(&connector->dev->mode_config.mutex);
6007         /* Set connector link status to BAD and send a Uevent to notify
6008          * userspace to do a modeset.
6009          */
6010         drm_mode_connector_set_link_status_property(connector,
6011                                                     DRM_MODE_LINK_STATUS_BAD);
6012         mutex_unlock(&connector->dev->mode_config.mutex);
6013         /* Send Hotplug uevent so userspace can reprobe */
6014         drm_kms_helper_hotplug_event(connector->dev);
6015 }
6016
6017 bool
6018 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6019                         struct intel_connector *intel_connector)
6020 {
6021         struct drm_connector *connector = &intel_connector->base;
6022         struct intel_dp *intel_dp = &intel_dig_port->dp;
6023         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6024         struct drm_device *dev = intel_encoder->base.dev;
6025         struct drm_i915_private *dev_priv = to_i915(dev);
6026         enum port port = intel_encoder->port;
6027         int type;
6028
6029         /* Initialize the work for modeset in case of link train failure */
6030         INIT_WORK(&intel_connector->modeset_retry_work,
6031                   intel_dp_modeset_retry_work_fn);
6032
6033         if (WARN(intel_dig_port->max_lanes < 1,
6034                  "Not enough lanes (%d) for DP on port %c\n",
6035                  intel_dig_port->max_lanes, port_name(port)))
6036                 return false;
6037
6038         intel_dp_set_source_rates(intel_dp);
6039
6040         intel_dp->reset_link_params = true;
6041         intel_dp->pps_pipe = INVALID_PIPE;
6042         intel_dp->active_pipe = INVALID_PIPE;
6043
6044         /* intel_dp vfuncs */
6045         if (INTEL_GEN(dev_priv) >= 9)
6046                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6047         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6048                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6049         else if (HAS_PCH_SPLIT(dev_priv))
6050                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6051         else
6052                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6053
6054         if (INTEL_GEN(dev_priv) >= 9)
6055                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6056         else
6057                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6058
6059         if (HAS_DDI(dev_priv))
6060                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6061
6062         /* Preserve the current hw state. */
6063         intel_dp->DP = I915_READ(intel_dp->output_reg);
6064         intel_dp->attached_connector = intel_connector;
6065
6066         if (intel_dp_is_port_edp(dev_priv, port))
6067                 type = DRM_MODE_CONNECTOR_eDP;
6068         else
6069                 type = DRM_MODE_CONNECTOR_DisplayPort;
6070
6071         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6072                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6073
6074         /*
6075          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6076          * for DP the encoder type can be set by the caller to
6077          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6078          */
6079         if (type == DRM_MODE_CONNECTOR_eDP)
6080                 intel_encoder->type = INTEL_OUTPUT_EDP;
6081
6082         /* eDP only on port B and/or C on vlv/chv */
6083         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6084                     intel_dp_is_edp(intel_dp) &&
6085                     port != PORT_B && port != PORT_C))
6086                 return false;
6087
6088         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6089                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6090                         port_name(port));
6091
6092         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6093         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6094
6095         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
6096                 connector->interlace_allowed = true;
6097         connector->doublescan_allowed = 0;
6098
6099         intel_dp_init_connector_port_info(intel_dig_port);
6100
6101         intel_dp_aux_init(intel_dp);
6102
6103         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6104                           edp_panel_vdd_work);
6105
6106         intel_connector_attach_encoder(intel_connector, intel_encoder);
6107
6108         if (HAS_DDI(dev_priv))
6109                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6110         else
6111                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6112
6113         /* init MST on ports that can support it */
6114         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
6115             (port == PORT_B || port == PORT_C || port == PORT_D))
6116                 intel_dp_mst_encoder_init(intel_dig_port,
6117                                           intel_connector->base.base.id);
6118
6119         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6120                 intel_dp_aux_fini(intel_dp);
6121                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6122                 goto fail;
6123         }
6124
6125         intel_dp_add_properties(intel_dp, connector);
6126
6127         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6128          * 0xd.  Failure to do so will result in spurious interrupts being
6129          * generated on the port when a cable is not attached.
6130          */
6131         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6132                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6133                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6134         }
6135
6136         return true;
6137
6138 fail:
6139         drm_connector_cleanup(connector);
6140
6141         return false;
6142 }
6143
6144 bool intel_dp_init(struct drm_i915_private *dev_priv,
6145                    i915_reg_t output_reg,
6146                    enum port port)
6147 {
6148         struct intel_digital_port *intel_dig_port;
6149         struct intel_encoder *intel_encoder;
6150         struct drm_encoder *encoder;
6151         struct intel_connector *intel_connector;
6152
6153         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6154         if (!intel_dig_port)
6155                 return false;
6156
6157         intel_connector = intel_connector_alloc();
6158         if (!intel_connector)
6159                 goto err_connector_alloc;
6160
6161         intel_encoder = &intel_dig_port->base;
6162         encoder = &intel_encoder->base;
6163
6164         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6165                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6166                              "DP %c", port_name(port)))
6167                 goto err_encoder_init;
6168
6169         intel_encoder->compute_config = intel_dp_compute_config;
6170         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6171         intel_encoder->get_config = intel_dp_get_config;
6172         intel_encoder->suspend = intel_dp_encoder_suspend;
6173         if (IS_CHERRYVIEW(dev_priv)) {
6174                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6175                 intel_encoder->pre_enable = chv_pre_enable_dp;
6176                 intel_encoder->enable = vlv_enable_dp;
6177                 intel_encoder->disable = vlv_disable_dp;
6178                 intel_encoder->post_disable = chv_post_disable_dp;
6179                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6180         } else if (IS_VALLEYVIEW(dev_priv)) {
6181                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6182                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6183                 intel_encoder->enable = vlv_enable_dp;
6184                 intel_encoder->disable = vlv_disable_dp;
6185                 intel_encoder->post_disable = vlv_post_disable_dp;
6186         } else if (INTEL_GEN(dev_priv) >= 5) {
6187                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6188                 intel_encoder->enable = g4x_enable_dp;
6189                 intel_encoder->disable = ilk_disable_dp;
6190                 intel_encoder->post_disable = ilk_post_disable_dp;
6191         } else {
6192                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6193                 intel_encoder->enable = g4x_enable_dp;
6194                 intel_encoder->disable = g4x_disable_dp;
6195         }
6196
6197         intel_dig_port->dp.output_reg = output_reg;
6198         intel_dig_port->max_lanes = 4;
6199
6200         intel_encoder->type = INTEL_OUTPUT_DP;
6201         intel_encoder->power_domain = intel_port_to_power_domain(port);
6202         if (IS_CHERRYVIEW(dev_priv)) {
6203                 if (port == PORT_D)
6204                         intel_encoder->crtc_mask = 1 << 2;
6205                 else
6206                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6207         } else {
6208                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6209         }
6210         intel_encoder->cloneable = 0;
6211         intel_encoder->port = port;
6212
6213         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6214         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6215
6216         if (port != PORT_A)
6217                 intel_infoframe_init(intel_dig_port);
6218
6219         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6220                 goto err_init_connector;
6221
6222         return true;
6223
6224 err_init_connector:
6225         drm_encoder_cleanup(encoder);
6226 err_encoder_init:
6227         kfree(intel_connector);
6228 err_connector_alloc:
6229         kfree(intel_dig_port);
6230         return false;
6231 }
6232
6233 void intel_dp_mst_suspend(struct drm_device *dev)
6234 {
6235         struct drm_i915_private *dev_priv = to_i915(dev);
6236         int i;
6237
6238         /* disable MST */
6239         for (i = 0; i < I915_MAX_PORTS; i++) {
6240                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6241
6242                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6243                         continue;
6244
6245                 if (intel_dig_port->dp.is_mst)
6246                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6247         }
6248 }
6249
6250 void intel_dp_mst_resume(struct drm_device *dev)
6251 {
6252         struct drm_i915_private *dev_priv = to_i915(dev);
6253         int i;
6254
6255         for (i = 0; i < I915_MAX_PORTS; i++) {
6256                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6257                 int ret;
6258
6259                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6260                         continue;
6261
6262                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6263                 if (ret)
6264                         intel_dp_check_mst_status(&intel_dig_port->dp);
6265         }
6266 }