drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26
  27 #include "intel_device_info.h"
  28 #include "i915_drv.h"
  29
  30 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  31 static const char * const platform_names[] = {
  32         PLATFORM_NAME(I830),
  33         PLATFORM_NAME(I845G),
  34         PLATFORM_NAME(I85X),
  35         PLATFORM_NAME(I865G),
  36         PLATFORM_NAME(I915G),
  37         PLATFORM_NAME(I915GM),
  38         PLATFORM_NAME(I945G),
  39         PLATFORM_NAME(I945GM),
  40         PLATFORM_NAME(G33),
  41         PLATFORM_NAME(PINEVIEW),
  42         PLATFORM_NAME(I965G),
  43         PLATFORM_NAME(I965GM),
  44         PLATFORM_NAME(G45),
  45         PLATFORM_NAME(GM45),
  46         PLATFORM_NAME(IRONLAKE),
  47         PLATFORM_NAME(SANDYBRIDGE),
  48         PLATFORM_NAME(IVYBRIDGE),
  49         PLATFORM_NAME(VALLEYVIEW),
  50         PLATFORM_NAME(HASWELL),
  51         PLATFORM_NAME(BROADWELL),
  52         PLATFORM_NAME(CHERRYVIEW),
  53         PLATFORM_NAME(SKYLAKE),
  54         PLATFORM_NAME(BROXTON),
  55         PLATFORM_NAME(KABYLAKE),
  56         PLATFORM_NAME(GEMINILAKE),
  57         PLATFORM_NAME(COFFEELAKE),
  58         PLATFORM_NAME(CANNONLAKE),
  59 };
  60 #undef PLATFORM_NAME
  61
  62 const char *intel_platform_name(enum intel_platform platform)
  63 {
  64         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  65
  66         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  67                          platform_names[platform] == NULL))
  68                 return "<unknown>";
  69
  70         return platform_names[platform];
  71 }
  72
  73 void intel_device_info_dump_flags(const struct intel_device_info *info,
  74                                   struct drm_printer *p)
  75 {
  76 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
  77         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  78 #undef PRINT_FLAG
  79 }
  80
  81 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
  82 {
  83         drm_printf(p, "slice mask: %04x\n", sseu->slice_mask);
  84         drm_printf(p, "slice total: %u\n", hweight8(sseu->slice_mask));
  85         drm_printf(p, "subslice total: %u\n", sseu_subslice_total(sseu));
  86         drm_printf(p, "subslice mask %04x\n", sseu->subslice_mask);
  87         drm_printf(p, "subslice per slice: %u\n",
  88                    hweight8(sseu->subslice_mask));
  89         drm_printf(p, "EU total: %u\n", sseu->eu_total);
  90         drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
  91         drm_printf(p, "has slice power gating: %s\n",
  92                    yesno(sseu->has_slice_pg));
  93         drm_printf(p, "has subslice power gating: %s\n",
  94                    yesno(sseu->has_subslice_pg));
  95         drm_printf(p, "has EU power gating: %s\n", yesno(sseu->has_eu_pg));
  96 }
  97
  98 void intel_device_info_dump_runtime(const struct intel_device_info *info,
  99                                     struct drm_printer *p)
 100 {
 101         sseu_dump(&info->sseu, p);
 102
 103         drm_printf(p, "CS timestamp frequency: %u kHz\n",
 104                    info->cs_timestamp_frequency_khz);
 105 }
 106
 107 void intel_device_info_dump(const struct intel_device_info *info,
 108                             struct drm_printer *p)
 109 {
 110         struct drm_i915_private *dev_priv =
 111                 container_of(info, struct drm_i915_private, info);
 112
 113         drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
 114                    INTEL_DEVID(dev_priv),
 115                    INTEL_REVID(dev_priv),
 116                    intel_platform_name(info->platform),
 117                    info->gen);
 118
 119         intel_device_info_dump_flags(info, p);
 120 }
 121
 122 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 123 {
 124         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 125         const u32 fuse2 = I915_READ(GEN8_FUSE2);
 126
 127         sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
 128                             GEN10_F2_S_ENA_SHIFT;
 129         sseu->subslice_mask = (1 << 4) - 1;
 130         sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
 131                                  GEN10_F2_SS_DIS_SHIFT);
 132
 133         sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
 134         sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
 135         sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
 136         sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
 137                                      GEN10_EU_DIS_SS_MASK));
 138
 139         /*
 140          * CNL is expected to always have a uniform distribution
 141          * of EU across subslices with the exception that any one
 142          * EU in any one subslice may be fused off for die
 143          * recovery.
 144          */
 145         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 146                                 DIV_ROUND_UP(sseu->eu_total,
 147                                              sseu_subslice_total(sseu)) : 0;
 148
 149         /* No restrictions on Power Gating */
 150         sseu->has_slice_pg = 1;
 151         sseu->has_subslice_pg = 1;
 152         sseu->has_eu_pg = 1;
 153 }
 154
 155 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 156 {
 157         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 158         u32 fuse, eu_dis;
 159
 160         fuse = I915_READ(CHV_FUSE_GT);
 161
 162         sseu->slice_mask = BIT(0);
 163
 164         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 165                 sseu->subslice_mask |= BIT(0);
 166                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 167                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 168                 sseu->eu_total += 8 - hweight32(eu_dis);
 169         }
 170
 171         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 172                 sseu->subslice_mask |= BIT(1);
 173                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 174                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 175                 sseu->eu_total += 8 - hweight32(eu_dis);
 176         }
 177
 178         /*
 179          * CHV expected to always have a uniform distribution of EU
 180          * across subslices.
 181         */
 182         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 183                                 sseu->eu_total / sseu_subslice_total(sseu) :
 184                                 0;
 185         /*
 186          * CHV supports subslice power gating on devices with more than
 187          * one subslice, and supports EU power gating on devices with
 188          * more than one EU pair per subslice.
 189         */
 190         sseu->has_slice_pg = 0;
 191         sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1;
 192         sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
 193 }
 194
 195 static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
 196 {
 197         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 198         struct sseu_dev_info *sseu = &info->sseu;
 199         int s_max = 3, ss_max = 4, eu_max = 8;
 200         int s, ss;
 201         u32 fuse2, eu_disable;
 202         u8 eu_mask = 0xff;
 203
 204         fuse2 = I915_READ(GEN8_FUSE2);
 205         sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 206
 207         /*
 208          * The subslice disable field is global, i.e. it applies
 209          * to each of the enabled slices.
 210         */
 211         sseu->subslice_mask = (1 << ss_max) - 1;
 212         sseu->subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
 213                                  GEN9_F2_SS_DIS_SHIFT);
 214
 215         /*
 216          * Iterate through enabled slices and subslices to
 217          * count the total enabled EU.
 218         */
 219         for (s = 0; s < s_max; s++) {
 220                 if (!(sseu->slice_mask & BIT(s)))
 221                         /* skip disabled slice */
 222                         continue;
 223
 224                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 225                 for (ss = 0; ss < ss_max; ss++) {
 226                         int eu_per_ss;
 227
 228                         if (!(sseu->subslice_mask & BIT(ss)))
 229                                 /* skip disabled subslice */
 230                                 continue;
 231
 232                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 233                                                       eu_mask);
 234
 235                         /*
 236                          * Record which subslice(s) has(have) 7 EUs. we
 237                          * can tune the hash used to spread work among
 238                          * subslices if they are unbalanced.
 239                          */
 240                         if (eu_per_ss == 7)
 241                                 sseu->subslice_7eu[s] |= BIT(ss);
 242
 243                         sseu->eu_total += eu_per_ss;
 244                 }
 245         }
 246
 247         /*
 248          * SKL is expected to always have a uniform distribution
 249          * of EU across subslices with the exception that any one
 250          * EU in any one subslice may be fused off for die
 251          * recovery. BXT is expected to be perfectly uniform in EU
 252          * distribution.
 253         */
 254         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 255                                 DIV_ROUND_UP(sseu->eu_total,
 256                                              sseu_subslice_total(sseu)) : 0;
 257         /*
 258          * SKL+ supports slice power gating on devices with more than
 259          * one slice, and supports EU power gating on devices with
 260          * more than one EU pair per subslice. BXT+ supports subslice
 261          * power gating on devices with more than one subslice, and
 262          * supports EU power gating on devices with more than one EU
 263          * pair per subslice.
 264         */
 265         sseu->has_slice_pg =
 266                 !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1;
 267         sseu->has_subslice_pg =
 268                 IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
 269         sseu->has_eu_pg = sseu->eu_per_subslice > 2;
 270
 271         if (IS_GEN9_LP(dev_priv)) {
 272 #define IS_SS_DISABLED(ss)      (!(sseu->subslice_mask & BIT(ss)))
 273                 info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
 274
 275                 sseu->min_eu_in_pool = 0;
 276                 if (info->has_pooled_eu) {
 277                         if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0))
 278                                 sseu->min_eu_in_pool = 3;
 279                         else if (IS_SS_DISABLED(1))
 280                                 sseu->min_eu_in_pool = 6;
 281                         else
 282                                 sseu->min_eu_in_pool = 9;
 283                 }
 284 #undef IS_SS_DISABLED
 285         }
 286 }
 287
 288 static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
 289 {
 290         struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
 291         const int s_max = 3, ss_max = 3, eu_max = 8;
 292         int s, ss;
 293         u32 fuse2, eu_disable[3]; /* s_max */
 294
 295         fuse2 = I915_READ(GEN8_FUSE2);
 296         sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 297         /*
 298          * The subslice disable field is global, i.e. it applies
 299          * to each of the enabled slices.
 300          */
 301         sseu->subslice_mask = GENMASK(ss_max - 1, 0);
 302         sseu->subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >>
 303                                  GEN8_F2_SS_DIS_SHIFT);
 304
 305         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 306         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 307                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 308                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 309         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 310                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 311                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 312
 313         /*
 314          * Iterate through enabled slices and subslices to
 315          * count the total enabled EU.
 316          */
 317         for (s = 0; s < s_max; s++) {
 318                 if (!(sseu->slice_mask & BIT(s)))
 319                         /* skip disabled slice */
 320                         continue;
 321
 322                 for (ss = 0; ss < ss_max; ss++) {
 323                         u32 n_disabled;
 324
 325                         if (!(sseu->subslice_mask & BIT(ss)))
 326                                 /* skip disabled subslice */
 327                                 continue;
 328
 329                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 330
 331                         /*
 332                          * Record which subslices have 7 EUs.
 333                          */
 334                         if (eu_max - n_disabled == 7)
 335                                 sseu->subslice_7eu[s] |= 1 << ss;
 336
 337                         sseu->eu_total += eu_max - n_disabled;
 338                 }
 339         }
 340
 341         /*
 342          * BDW is expected to always have a uniform distribution of EU across
 343          * subslices with the exception that any one EU in any one subslice may
 344          * be fused off for die recovery.
 345          */
 346         sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
 347                                 DIV_ROUND_UP(sseu->eu_total,
 348                                              sseu_subslice_total(sseu)) : 0;
 349
 350         /*
 351          * BDW supports slice power gating on devices with more than
 352          * one slice.
 353          */
 354         sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1;
 355         sseu->has_subslice_pg = 0;
 356         sseu->has_eu_pg = 0;
 357 }
 358
 359 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 360 {
 361         u32 ts_override = I915_READ(GEN9_TIMESTAMP_OVERRIDE);
 362         u32 base_freq, frac_freq;
 363
 364         base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
 365                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
 366         base_freq *= 1000;
 367
 368         frac_freq = ((ts_override &
 369                       GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
 370                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
 371         frac_freq = 1000 / (frac_freq + 1);
 372
 373         return base_freq + frac_freq;
 374 }
 375
 376 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 377 {
 378         u32 f12_5_mhz = 12500;
 379         u32 f19_2_mhz = 19200;
 380         u32 f24_mhz = 24000;
 381
 382         if (INTEL_GEN(dev_priv) <= 4) {
 383                 /* PRMs say:
 384                  *
 385                  *     "The value in this register increments once every 16
 386                  *      hclks." (through the “Clocking Configuration”
 387                  *      (“CLKCFG”) MCHBAR register)
 388                  */
 389                 return dev_priv->rawclk_freq / 16;
 390         } else if (INTEL_GEN(dev_priv) <= 8) {
 391                 /* PRMs say:
 392                  *
 393                  *     "The PCU TSC counts 10ns increments; this timestamp
 394                  *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
 395                  *      rolling over every 1.5 hours).
 396                  */
 397                 return f12_5_mhz;
 398         } else if (INTEL_GEN(dev_priv) <= 9) {
 399                 u32 ctc_reg = I915_READ(CTC_MODE);
 400                 u32 freq = 0;
 401
 402                 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
 403                         freq = read_reference_ts_freq(dev_priv);
 404                 } else {
 405                         freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
 406
 407                         /* Now figure out how the command stream's timestamp
 408                          * register increments from this frequency (it might
 409                          * increment only every few clock cycle).
 410                          */
 411                         freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
 412                                       CTC_SHIFT_PARAMETER_SHIFT);
 413                 }
 414
 415                 return freq;
 416         } else if (INTEL_GEN(dev_priv) <= 10) {
 417                 u32 ctc_reg = I915_READ(CTC_MODE);
 418                 u32 freq = 0;
 419                 u32 rpm_config_reg = 0;
 420
 421                 /* First figure out the reference frequency. There are 2 ways
 422                  * we can compute the frequency, either through the
 423                  * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
 424                  * tells us which one we should use.
 425                  */
 426                 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
 427                         freq = read_reference_ts_freq(dev_priv);
 428                 } else {
 429                         u32 crystal_clock;
 430
 431                         rpm_config_reg = I915_READ(RPM_CONFIG0);
 432                         crystal_clock = (rpm_config_reg &
 433                                          GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
 434                                 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
 435                         switch (crystal_clock) {
 436                         case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
 437                                 freq = f19_2_mhz;
 438                                 break;
 439                         case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
 440                                 freq = f24_mhz;
 441                                 break;
 442                         }
 443
 444                         /* Now figure out how the command stream's timestamp
 445                          * register increments from this frequency (it might
 446                          * increment only every few clock cycle).
 447                          */
 448                         freq >>= 3 - ((rpm_config_reg &
 449                                        GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
 450                                       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
 451                 }
 452
 453                 return freq;
 454         }
 455
 456         MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
 457         return 0;
 458 }
 459
 460 /**
 461  * intel_device_info_runtime_init - initialize runtime info
 462  * @info: intel device info struct
 463  *
 464  * Determine various intel_device_info fields at runtime.
 465  *
 466  * Use it when either:
 467  *   - it's judged too laborious to fill n static structures with the limit
 468  *     when a simple if statement does the job,
 469  *   - run-time checks (eg read fuse/strap registers) are needed.
 470  *
 471  * This function needs to be called:
 472  *   - after the MMIO has been setup as we are reading registers,
 473  *   - after the PCH has been detected,
 474  *   - before the first usage of the fields it can tweak.
 475  */
 476 void intel_device_info_runtime_init(struct intel_device_info *info)
 477 {
 478         struct drm_i915_private *dev_priv =
 479                 container_of(info, struct drm_i915_private, info);
 480         enum pipe pipe;
 481
 482         if (INTEL_GEN(dev_priv) >= 10) {
 483                 for_each_pipe(dev_priv, pipe)
 484                         info->num_scalers[pipe] = 2;
 485         } else if (INTEL_GEN(dev_priv) == 9) {
 486                 info->num_scalers[PIPE_A] = 2;
 487                 info->num_scalers[PIPE_B] = 2;
 488                 info->num_scalers[PIPE_C] = 1;
 489         }
 490
 491         /*
 492          * Skylake and Broxton currently don't expose the topmost plane as its
 493          * use is exclusive with the legacy cursor and we only want to expose
 494          * one of those, not both. Until we can safely expose the topmost plane
 495          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 496          * we don't expose the topmost plane at all to prevent ABI breakage
 497          * down the line.
 498          */
 499         if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv))
 500                 for_each_pipe(dev_priv, pipe)
 501                         info->num_sprites[pipe] = 3;
 502         else if (IS_BROXTON(dev_priv)) {
 503                 info->num_sprites[PIPE_A] = 2;
 504                 info->num_sprites[PIPE_B] = 2;
 505                 info->num_sprites[PIPE_C] = 1;
 506         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 507                 for_each_pipe(dev_priv, pipe)
 508                         info->num_sprites[pipe] = 2;
 509         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 510                 for_each_pipe(dev_priv, pipe)
 511                         info->num_sprites[pipe] = 1;
 512         }
 513
 514         if (i915_modparams.disable_display) {
 515                 DRM_INFO("Display disabled (module parameter)\n");
 516                 info->num_pipes = 0;
 517         } else if (info->num_pipes > 0 &&
 518                    (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
 519                    HAS_PCH_SPLIT(dev_priv)) {
 520                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 521                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 522
 523                 /*
 524                  * SFUSE_STRAP is supposed to have a bit signalling the display
 525                  * is fused off. Unfortunately it seems that, at least in
 526                  * certain cases, fused off display means that PCH display
 527                  * reads don't land anywhere. In that case, we read 0s.
 528                  *
 529                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 530                  * should be set when taking over after the firmware.
 531                  */
 532                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 533                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 534                     (HAS_PCH_CPT(dev_priv) &&
 535                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 536                         DRM_INFO("Display fused off, disabling\n");
 537                         info->num_pipes = 0;
 538                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 539                         DRM_INFO("PipeC fused off\n");
 540                         info->num_pipes -= 1;
 541                 }
 542         } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
 543                 u32 dfsm = I915_READ(SKL_DFSM);
 544                 u8 disabled_mask = 0;
 545                 bool invalid;
 546                 int num_bits;
 547
 548                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
 549                         disabled_mask |= BIT(PIPE_A);
 550                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
 551                         disabled_mask |= BIT(PIPE_B);
 552                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 553                         disabled_mask |= BIT(PIPE_C);
 554
 555                 num_bits = hweight8(disabled_mask);
 556
 557                 switch (disabled_mask) {
 558                 case BIT(PIPE_A):
 559                 case BIT(PIPE_B):
 560                 case BIT(PIPE_A) | BIT(PIPE_B):
 561                 case BIT(PIPE_A) | BIT(PIPE_C):
 562                         invalid = true;
 563                         break;
 564                 default:
 565                         invalid = false;
 566                 }
 567
 568                 if (num_bits > info->num_pipes || invalid)
 569                         DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
 570                                   disabled_mask);
 571                 else
 572                         info->num_pipes -= num_bits;
 573         }
 574
 575         /* Initialize slice/subslice/EU info */
 576         if (IS_CHERRYVIEW(dev_priv))
 577                 cherryview_sseu_info_init(dev_priv);
 578         else if (IS_BROADWELL(dev_priv))
 579                 broadwell_sseu_info_init(dev_priv);
 580         else if (INTEL_GEN(dev_priv) == 9)
 581                 gen9_sseu_info_init(dev_priv);
 582         else if (INTEL_GEN(dev_priv) >= 10)
 583                 gen10_sseu_info_init(dev_priv);
 584
 585         /* Initialize command stream timestamp frequency */
 586         info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 587 }