drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "gfx_v10_0_cleaner_shader.h"
  49 #include "nbio_v2_3.h"
  50
  51 /*
  52  * Navi10 has two graphic rings to share each graphic pipe.
  53  * 1. Primary ring
  54  * 2. Async ring
  55  */
  56 #define GFX10_NUM_GFX_RINGS_NV1X        1
  57 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      2
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  66 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  67 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  68 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  69
  70 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  71 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  72
  73 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  74 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  76 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  77
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  79 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  81 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  83 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  85 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  87 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  89 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  91 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  93 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  95 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  97 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  99 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 101 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 102 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 104 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 105
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish                0x0105
 107 #define mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish_BASE_IDX       1
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish                0x0106
 109 #define mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish_BASE_IDX       1
 110
 111 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 112 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 113 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 114 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 115
 116 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 117 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 118 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 119 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 120
 121 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 122 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 123 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 124 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 125 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 126 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 127 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 128 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 129 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 130 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 131 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 132 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 133 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 134 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 135 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 136 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 137 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 138 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 139 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 140
 141 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 142 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 143 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 144 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 145 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 146 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 147 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 148 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 149 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 150 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 151 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 152 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 153
 154 #define mmCPG_PSP_DEBUG                         0x5c10
 155 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 156 #define mmCPC_PSP_DEBUG                         0x5c11
 157 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 158 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 159 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 160
 161 //CC_GC_SA_UNIT_DISABLE
 162 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 163 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 164 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 165 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 166 //GC_USER_SA_UNIT_DISABLE
 167 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 168 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 169 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 170 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 171 //PA_SC_ENHANCE_3
 172 #define mmPA_SC_ENHANCE_3                       0x1085
 173 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 174 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 175 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 176
 177 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 178 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 179
 180 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 181 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 182 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 183 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 184
 185 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 186 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 187
 188 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 189 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 190
 191 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 192 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 193 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 194 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 195 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 196 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 197
 198 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 203 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 204 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 205 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 206 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 207 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 208 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 209
 210 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 211 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 212 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 213 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 214 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 215 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 216
 217 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 218 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 219 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 220 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 221 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 222 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 223
 224 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 225 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 226 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 227 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 228 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 229 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 230
 231 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 232 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 233 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 234 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 235 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 236 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 237
 238 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 239 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 240 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 241 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 242 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 243 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 244
 245 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 246 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 247 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 248 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 249 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 250 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 251
 252 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 253 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 254 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 255 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 256 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 257 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 258
 259 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 260 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 261 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 262 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 263 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 264 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 265
 266 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 271 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 272
 273 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 274 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 275 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 276 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 277 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 278 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 279
 280 static const struct amdgpu_hwip_reg_entry gc_reg_list_10_1[] = {
 281         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS),
 282         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS2),
 283         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS3),
 284         SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT1),
 285         SOC15_REG_ENTRY_STR(GC, 0, mmCP_STALLED_STAT2),
 286         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STALLED_STAT1),
 287         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STALLED_STAT1),
 288         SOC15_REG_ENTRY_STR(GC, 0, mmCP_BUSY_STAT),
 289         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT),
 290         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT),
 291         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_BUSY_STAT2),
 292         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_BUSY_STAT2),
 293         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPF_STATUS),
 294         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_ERROR),
 295         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HPD_STATUS0),
 296         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_BASE),
 297         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_RPTR),
 298         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR),
 299         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_BASE),
 300         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_RPTR),
 301         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
 302         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_BASE),
 303         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_RPTR),
 304         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB1_WPTR),
 305         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_BASE),
 306         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
 307         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
 308         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_CMD_BUFSZ),
 309         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_CMD_BUFSZ),
 310         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_CMD_BUFSZ),
 311         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_CMD_BUFSZ),
 312         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_LO),
 313         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BASE_HI),
 314         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB1_BUFSZ),
 315         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_LO),
 316         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BASE_HI),
 317         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_IB2_BUFSZ),
 318         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_LO),
 319         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BASE_HI),
 320         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB1_BUFSZ),
 321         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_LO),
 322         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BASE_HI),
 323         SOC15_REG_ENTRY_STR(GC, 0, mmCP_IB2_BUFSZ),
 324         SOC15_REG_ENTRY_STR(GC, 0, mmCPF_UTCL1_STATUS),
 325         SOC15_REG_ENTRY_STR(GC, 0, mmCPC_UTCL1_STATUS),
 326         SOC15_REG_ENTRY_STR(GC, 0, mmCPG_UTCL1_STATUS),
 327         SOC15_REG_ENTRY_STR(GC, 0, mmGDS_PROTECTION_FAULT),
 328         SOC15_REG_ENTRY_STR(GC, 0, mmGDS_VM_PROTECTION_FAULT),
 329         SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS),
 330         SOC15_REG_ENTRY_STR(GC, 0, mmIA_UTCL1_STATUS_2),
 331         SOC15_REG_ENTRY_STR(GC, 0, mmPA_CL_CNTL_STATUS),
 332         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_UTCL1_STATUS),
 333         SOC15_REG_ENTRY_STR(GC, 0, mmRMI_UTCL1_STATUS),
 334         SOC15_REG_ENTRY_STR(GC, 0, mmSQC_DCACHE_UTCL0_STATUS),
 335         SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL0_STATUS),
 336         SOC15_REG_ENTRY_STR(GC, 0, mmSQG_UTCL0_STATUS),
 337         SOC15_REG_ENTRY_STR(GC, 0, mmTCP_UTCL0_STATUS),
 338         SOC15_REG_ENTRY_STR(GC, 0, mmWD_UTCL1_STATUS),
 339         SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL),
 340         SOC15_REG_ENTRY_STR(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS),
 341         SOC15_REG_ENTRY_STR(GC, 0, mmCP_DEBUG),
 342         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_CNTL),
 343         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_CNTL),
 344         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_INSTR_PNTR),
 345         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC1_INSTR_PNTR),
 346         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC2_INSTR_PNTR),
 347         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
 348         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_INSTR_PNTR),
 349         SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_INSTR_PNTR),
 350         SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_INSTR_PNTR),
 351         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CPC_STATUS),
 352         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_STAT),
 353         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_COMMAND),
 354         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_MESSAGE),
 355         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_1),
 356         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_2),
 357         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_3),
 358         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_ARGUMENT_4),
 359         SOC15_REG_ENTRY_STR(GC, 0, mmSMU_RLC_RESPONSE),
 360         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SAFE_MODE),
 361         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SMU_SAFE_MODE),
 362         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_GPM_STAT_2),
 363         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_SPP_STATUS),
 364         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS),
 365         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_INT_STAT),
 366         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_GENERAL_6),
 367         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_A),
 368         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_B),
 369         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR),
 370         SOC15_REG_ENTRY_STR(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST),
 371         /* cp header registers */
 372         SOC15_REG_ENTRY_STR(GC, 0, mmCP_CE_HEADER_DUMP),
 373         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME1_HEADER_DUMP),
 374         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MEC_ME2_HEADER_DUMP),
 375         SOC15_REG_ENTRY_STR(GC, 0, mmCP_PFP_HEADER_DUMP),
 376         SOC15_REG_ENTRY_STR(GC, 0, mmCP_ME_HEADER_DUMP),
 377         SOC15_REG_ENTRY_STR(GC, 0, mmCP_MES_HEADER_DUMP),
 378         /* SE status registers */
 379         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE0),
 380         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE1),
 381         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE2),
 382         SOC15_REG_ENTRY_STR(GC, 0, mmGRBM_STATUS_SE3)
 383 };
 384
 385 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_10[] = {
 386         /* compute registers */
 387         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_VMID),
 388         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PERSISTENT_STATE),
 389         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PIPE_PRIORITY),
 390         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUEUE_PRIORITY),
 391         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_QUANTUM),
 392         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE),
 393         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_BASE_HI),
 394         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_RPTR),
 395         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
 396         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
 397         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL),
 398         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_CONTROL),
 399         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR),
 400         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_BASE_ADDR_HI),
 401         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_RPTR),
 402         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_IB_CONTROL),
 403         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_REQUEST),
 404         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR),
 405         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI),
 406         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_CONTROL),
 407         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_RPTR),
 408         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR),
 409         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_EVENTS),
 410         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_LO),
 411         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_BASE_ADDR_HI),
 412         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_CONTROL),
 413         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_OFFSET),
 414         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CNTL_STACK_SIZE),
 415         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_WG_STATE_OFFSET),
 416         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_CTX_SAVE_SIZE),
 417         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_GDS_RESOURCE_STATE),
 418         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ERROR),
 419         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_EOP_WPTR_MEM),
 420         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_LO),
 421         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_PQ_WPTR_HI),
 422         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
 423         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
 424         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_SUSPEND_WG_STATE_OFFSET),
 425         SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_DEQUEUE_STATUS)
 426 };
 427
 428 static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_10[] = {
 429         /* gfx queue registers */
 430         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_ACTIVE),
 431         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY),
 432         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE),
 433         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_BASE_HI),
 434         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_OFFSET),
 435         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CSMD_RPTR),
 436         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR),
 437         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_WPTR_HI),
 438         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_DEQUEUE_REQUEST),
 439         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_MAPPED),
 440         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_QUE_MGR_CONTROL),
 441         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),
 442         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_STATUS0),
 443         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO),
 444         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI),
 445         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_OFFSET),
 446         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_CSMD_RPTR),
 447         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR),
 448         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_CE_WPTR_HI),
 449         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR),
 450         SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_MQD_BASE_ADDR_HI),
 451         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO),
 452         SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI)
 453 };
 454
 455 static const struct soc15_reg_golden golden_settings_gc_10_1[] = {
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 496 };
 497
 498 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = {
 499         /* Pending on emulation bring up */
 500 };
 501
 502 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = {
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1555 };
1556
1557 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = {
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1596 };
1597
1598 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = {
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1641 };
1642
1643 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = {
1644         /* Pending on emulation bring up */
1645 };
1646
1647 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = {
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2268 };
2269
2270 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = {
2271         /* Pending on emulation bring up */
2272 };
2273
2274 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = {
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3327 };
3328
3329 static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3373 };
3374
3375 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
3376         /* Pending on emulation bring up */
3377 };
3378
3379 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3421
3422         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3424 };
3425
3426 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3451
3452         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3454 };
3455
3456 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3477 };
3478
3479 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
3480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3516 };
3517
3518 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3551 };
3552
3553 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3588 };
3589
3590 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
3591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3613 };
3614
3615 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3638 };
3639
3640 #define DEFAULT_SH_MEM_CONFIG \
3641         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3642          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3643          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3644          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3645
3646 /* TODO: pending on golden setting value of gb address config */
3647 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3648
3649 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3650 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3651 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3652 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3653 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3654 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3655                                  struct amdgpu_cu_info *cu_info);
3656 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3657 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3658                                    u32 sh_num, u32 instance, int xcc_id);
3659 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3660
3661 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3662 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3663 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3664 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3665 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3666 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3667 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3668 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3669 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3670 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3671 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3672                                            uint16_t pasid, uint32_t flush_type,
3673                                            bool all_hub, uint8_t dst_sel);
3674 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
3675                                                unsigned int vmid);
3676
3677 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3678                                           enum amd_powergating_state state);
3679 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3680 {
3681         struct amdgpu_device *adev = kiq_ring->adev;
3682         u64 shader_mc_addr;
3683
3684         /* Cleaner shader MC address */
3685         shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8;
3686
3687         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3688         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3689                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3690         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3691         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3692         amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */
3693         amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */
3694         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3695         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3696 }
3697
3698 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3699                                  struct amdgpu_ring *ring)
3700 {
3701         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3702         uint64_t wptr_addr = ring->wptr_gpu_addr;
3703         uint32_t eng_sel = 0;
3704
3705         switch (ring->funcs->type) {
3706         case AMDGPU_RING_TYPE_COMPUTE:
3707                 eng_sel = 0;
3708                 break;
3709         case AMDGPU_RING_TYPE_GFX:
3710                 eng_sel = 4;
3711                 break;
3712         case AMDGPU_RING_TYPE_MES:
3713                 eng_sel = 5;
3714                 break;
3715         default:
3716                 WARN_ON(1);
3717         }
3718
3719         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3720         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3721         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3722                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3723                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3724                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3725                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3726                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3727                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3728                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3729                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3730                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3731         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3732         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3733         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3734         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3735         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3736 }
3737
3738 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3739                                    struct amdgpu_ring *ring,
3740                                    enum amdgpu_unmap_queues_action action,
3741                                    u64 gpu_addr, u64 seq)
3742 {
3743         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3744
3745         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3746         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3747                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3748                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3749                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3750                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3751         amdgpu_ring_write(kiq_ring,
3752                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3753
3754         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3755                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3756                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3757                 amdgpu_ring_write(kiq_ring, seq);
3758         } else {
3759                 amdgpu_ring_write(kiq_ring, 0);
3760                 amdgpu_ring_write(kiq_ring, 0);
3761                 amdgpu_ring_write(kiq_ring, 0);
3762         }
3763 }
3764
3765 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3766                                    struct amdgpu_ring *ring,
3767                                    u64 addr,
3768                                    u64 seq)
3769 {
3770         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3771
3772         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3773         amdgpu_ring_write(kiq_ring,
3774                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3775                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3776                           PACKET3_QUERY_STATUS_COMMAND(2));
3777         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3778                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3779                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3780         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3781         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3782         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3783         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3784 }
3785
3786 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3787                                 uint16_t pasid, uint32_t flush_type,
3788                                 bool all_hub)
3789 {
3790         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3791 }
3792
3793 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3794         .kiq_set_resources = gfx10_kiq_set_resources,
3795         .kiq_map_queues = gfx10_kiq_map_queues,
3796         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3797         .kiq_query_status = gfx10_kiq_query_status,
3798         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3799         .set_resources_size = 8,
3800         .map_queues_size = 7,
3801         .unmap_queues_size = 6,
3802         .query_status_size = 7,
3803         .invalidate_tlbs_size = 2,
3804 };
3805
3806 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3807 {
3808         adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3809 }
3810
3811 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3812 {
3813         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3814         case IP_VERSION(10, 1, 10):
3815                 soc15_program_register_sequence(adev,
3816                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3817                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3818                 break;
3819         case IP_VERSION(10, 1, 1):
3820                 soc15_program_register_sequence(adev,
3821                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3822                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3823                 break;
3824         case IP_VERSION(10, 1, 2):
3825                 soc15_program_register_sequence(adev,
3826                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3827                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3828                 break;
3829         default:
3830                 break;
3831         }
3832 }
3833
3834 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3835 {
3836         if (amdgpu_sriov_vf(adev))
3837                 return;
3838
3839         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
3840         case IP_VERSION(10, 1, 10):
3841                 soc15_program_register_sequence(adev,
3842                                                 golden_settings_gc_10_1,
3843                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3844                 soc15_program_register_sequence(adev,
3845                                                 golden_settings_gc_10_0_nv10,
3846                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3847                 break;
3848         case IP_VERSION(10, 1, 1):
3849                 soc15_program_register_sequence(adev,
3850                                                 golden_settings_gc_10_1_1,
3851                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3852                 soc15_program_register_sequence(adev,
3853                                                 golden_settings_gc_10_1_nv14,
3854                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3855                 break;
3856         case IP_VERSION(10, 1, 2):
3857                 soc15_program_register_sequence(adev,
3858                                                 golden_settings_gc_10_1_2,
3859                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3860                 soc15_program_register_sequence(adev,
3861                                                 golden_settings_gc_10_1_2_nv12,
3862                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3863                 break;
3864         case IP_VERSION(10, 3, 0):
3865                 soc15_program_register_sequence(adev,
3866                                                 golden_settings_gc_10_3,
3867                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3868                 soc15_program_register_sequence(adev,
3869                                                 golden_settings_gc_10_3_sienna_cichlid,
3870                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3871                 break;
3872         case IP_VERSION(10, 3, 2):
3873                 soc15_program_register_sequence(adev,
3874                                                 golden_settings_gc_10_3_2,
3875                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3876                 break;
3877         case IP_VERSION(10, 3, 1):
3878                 soc15_program_register_sequence(adev,
3879                                                 golden_settings_gc_10_3_vangogh,
3880                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3881                 break;
3882         case IP_VERSION(10, 3, 3):
3883                 soc15_program_register_sequence(adev,
3884                                                 golden_settings_gc_10_3_3,
3885                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3886                 break;
3887         case IP_VERSION(10, 3, 4):
3888                 soc15_program_register_sequence(adev,
3889                                                 golden_settings_gc_10_3_4,
3890                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3891                 break;
3892         case IP_VERSION(10, 3, 5):
3893                 soc15_program_register_sequence(adev,
3894                                                 golden_settings_gc_10_3_5,
3895                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3896                 break;
3897         case IP_VERSION(10, 1, 3):
3898         case IP_VERSION(10, 1, 4):
3899                 soc15_program_register_sequence(adev,
3900                                                 golden_settings_gc_10_0_cyan_skillfish,
3901                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3902                 break;
3903         case IP_VERSION(10, 3, 6):
3904                 soc15_program_register_sequence(adev,
3905                                                 golden_settings_gc_10_3_6,
3906                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3907                 break;
3908         case IP_VERSION(10, 3, 7):
3909                 soc15_program_register_sequence(adev,
3910                                                 golden_settings_gc_10_3_7,
3911                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3912                 break;
3913         default:
3914                 break;
3915         }
3916         gfx_v10_0_init_spm_golden_registers(adev);
3917 }
3918
3919 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3920                                        bool wc, uint32_t reg, uint32_t val)
3921 {
3922         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3923         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3924                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3925         amdgpu_ring_write(ring, reg);
3926         amdgpu_ring_write(ring, 0);
3927         amdgpu_ring_write(ring, val);
3928 }
3929
3930 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3931                                   int mem_space, int opt, uint32_t addr0,
3932                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3933                                   uint32_t inv)
3934 {
3935         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3936         amdgpu_ring_write(ring,
3937                           /* memory (1) or register (0) */
3938                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3939                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3940                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3941                            WAIT_REG_MEM_ENGINE(eng_sel)));
3942
3943         if (mem_space)
3944                 BUG_ON(addr0 & 0x3); /* Dword align */
3945         amdgpu_ring_write(ring, addr0);
3946         amdgpu_ring_write(ring, addr1);
3947         amdgpu_ring_write(ring, ref);
3948         amdgpu_ring_write(ring, mask);
3949         amdgpu_ring_write(ring, inv); /* poll interval */
3950 }
3951
3952 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3953 {
3954         struct amdgpu_device *adev = ring->adev;
3955         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3956         uint32_t tmp = 0;
3957         unsigned int i;
3958         int r;
3959
3960         WREG32(scratch, 0xCAFEDEAD);
3961         r = amdgpu_ring_alloc(ring, 3);
3962         if (r) {
3963                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3964                           ring->idx, r);
3965                 return r;
3966         }
3967
3968         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3969         amdgpu_ring_write(ring, scratch -
3970                           PACKET3_SET_UCONFIG_REG_START);
3971         amdgpu_ring_write(ring, 0xDEADBEEF);
3972         amdgpu_ring_commit(ring);
3973
3974         for (i = 0; i < adev->usec_timeout; i++) {
3975                 tmp = RREG32(scratch);
3976                 if (tmp == 0xDEADBEEF)
3977                         break;
3978                 if (amdgpu_emu_mode == 1)
3979                         msleep(1);
3980                 else
3981                         udelay(1);
3982         }
3983
3984         if (i >= adev->usec_timeout)
3985                 r = -ETIMEDOUT;
3986
3987         return r;
3988 }
3989
3990 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3991 {
3992         struct amdgpu_device *adev = ring->adev;
3993         struct amdgpu_ib ib;
3994         struct dma_fence *f = NULL;
3995         unsigned int index;
3996         uint64_t gpu_addr;
3997         volatile uint32_t *cpu_ptr;
3998         long r;
3999
4000         memset(&ib, 0, sizeof(ib));
4001
4002         r = amdgpu_device_wb_get(adev, &index);
4003         if (r)
4004                 return r;
4005
4006         gpu_addr = adev->wb.gpu_addr + (index * 4);
4007         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
4008         cpu_ptr = &adev->wb.wb[index];
4009
4010         r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
4011         if (r) {
4012                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
4013                 goto err1;
4014         }
4015
4016         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
4017         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
4018         ib.ptr[2] = lower_32_bits(gpu_addr);
4019         ib.ptr[3] = upper_32_bits(gpu_addr);
4020         ib.ptr[4] = 0xDEADBEEF;
4021         ib.length_dw = 5;
4022
4023         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
4024         if (r)
4025                 goto err2;
4026
4027         r = dma_fence_wait_timeout(f, false, timeout);
4028         if (r == 0) {
4029                 r = -ETIMEDOUT;
4030                 goto err2;
4031         } else if (r < 0) {
4032                 goto err2;
4033         }
4034
4035         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
4036                 r = 0;
4037         else
4038                 r = -EINVAL;
4039 err2:
4040         amdgpu_ib_free(&ib, NULL);
4041         dma_fence_put(f);
4042 err1:
4043         amdgpu_device_wb_free(adev, index);
4044         return r;
4045 }
4046
4047 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
4048 {
4049         amdgpu_ucode_release(&adev->gfx.pfp_fw);
4050         amdgpu_ucode_release(&adev->gfx.me_fw);
4051         amdgpu_ucode_release(&adev->gfx.ce_fw);
4052         amdgpu_ucode_release(&adev->gfx.rlc_fw);
4053         amdgpu_ucode_release(&adev->gfx.mec_fw);
4054         amdgpu_ucode_release(&adev->gfx.mec2_fw);
4055
4056         kfree(adev->gfx.rlc.register_list_format);
4057 }
4058
4059 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
4060 {
4061         adev->gfx.cp_fw_write_wait = false;
4062
4063         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4064         case IP_VERSION(10, 1, 10):
4065         case IP_VERSION(10, 1, 2):
4066         case IP_VERSION(10, 1, 1):
4067         case IP_VERSION(10, 1, 3):
4068         case IP_VERSION(10, 1, 4):
4069                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
4070                     (adev->gfx.me_feature_version >= 27) &&
4071                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
4072                     (adev->gfx.pfp_feature_version >= 27) &&
4073                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
4074                     (adev->gfx.mec_feature_version >= 27))
4075                         adev->gfx.cp_fw_write_wait = true;
4076                 break;
4077         case IP_VERSION(10, 3, 0):
4078         case IP_VERSION(10, 3, 2):
4079         case IP_VERSION(10, 3, 1):
4080         case IP_VERSION(10, 3, 4):
4081         case IP_VERSION(10, 3, 5):
4082         case IP_VERSION(10, 3, 6):
4083         case IP_VERSION(10, 3, 3):
4084         case IP_VERSION(10, 3, 7):
4085                 adev->gfx.cp_fw_write_wait = true;
4086                 break;
4087         default:
4088                 break;
4089         }
4090
4091         if (!adev->gfx.cp_fw_write_wait)
4092                 DRM_WARN_ONCE("CP firmware version too old, please update!");
4093 }
4094
4095 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
4096 {
4097         bool ret = false;
4098
4099         switch (adev->pdev->revision) {
4100         case 0xc2:
4101         case 0xc3:
4102                 ret = true;
4103                 break;
4104         default:
4105                 ret = false;
4106                 break;
4107         }
4108
4109         return ret;
4110 }
4111
4112 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4113 {
4114         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4115         case IP_VERSION(10, 1, 10):
4116                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4117                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4118                 break;
4119         default:
4120                 break;
4121         }
4122 }
4123
4124 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4125 {
4126         char fw_name[53];
4127         char ucode_prefix[30];
4128         const char *wks = "";
4129         int err;
4130         const struct rlc_firmware_header_v2_0 *rlc_hdr;
4131         uint16_t version_major;
4132         uint16_t version_minor;
4133
4134         DRM_DEBUG("\n");
4135
4136         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) &&
4137             (!(adev->pdev->device == 0x7340 && adev->pdev->revision != 0x00)))
4138                 wks = "_wks";
4139         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
4140
4141         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
4142                                    AMDGPU_UCODE_REQUIRED,
4143                                    "amdgpu/%s_pfp%s.bin", ucode_prefix, wks);
4144         if (err)
4145                 goto out;
4146         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4147
4148         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
4149                                    AMDGPU_UCODE_REQUIRED,
4150                                    "amdgpu/%s_me%s.bin", ucode_prefix, wks);
4151         if (err)
4152                 goto out;
4153         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4154
4155         err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
4156                                    AMDGPU_UCODE_REQUIRED,
4157                                    "amdgpu/%s_ce%s.bin", ucode_prefix, wks);
4158         if (err)
4159                 goto out;
4160         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4161
4162         if (!amdgpu_sriov_vf(adev)) {
4163                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
4164                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4165                 if (err)
4166                         goto out;
4167
4168                 /* don't validate this firmware. There are apparently firmwares
4169                  * in the wild with incorrect size in the header
4170                  */
4171                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4172                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4173                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4174                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4175                 if (err)
4176                         goto out;
4177         }
4178
4179         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,
4180                                    AMDGPU_UCODE_REQUIRED,
4181                                    "amdgpu/%s_mec%s.bin", ucode_prefix, wks);
4182         if (err)
4183                 goto out;
4184         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4185         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4186
4187         err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw,
4188                                    AMDGPU_UCODE_REQUIRED,
4189                                    "amdgpu/%s_mec2%s.bin", ucode_prefix, wks);
4190         if (!err) {
4191                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4192                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4193         } else {
4194                 err = 0;
4195                 adev->gfx.mec2_fw = NULL;
4196         }
4197
4198         gfx_v10_0_check_fw_write_wait(adev);
4199 out:
4200         if (err) {
4201                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4202                 amdgpu_ucode_release(&adev->gfx.me_fw);
4203                 amdgpu_ucode_release(&adev->gfx.ce_fw);
4204                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4205                 amdgpu_ucode_release(&adev->gfx.mec_fw);
4206                 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4207         }
4208
4209         gfx_v10_0_check_gfxoff_flag(adev);
4210
4211         return err;
4212 }
4213
4214 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4215 {
4216         u32 count = 0;
4217         const struct cs_section_def *sect = NULL;
4218         const struct cs_extent_def *ext = NULL;
4219
4220         /* begin clear state */
4221         count += 2;
4222         /* context control state */
4223         count += 3;
4224
4225         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4226                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4227                         if (sect->id == SECT_CONTEXT)
4228                                 count += 2 + ext->reg_count;
4229                         else
4230                                 return 0;
4231                 }
4232         }
4233
4234         /* set PA_SC_TILE_STEERING_OVERRIDE */
4235         count += 3;
4236         /* end clear state */
4237         count += 2;
4238         /* clear state */
4239         count += 2;
4240
4241         return count;
4242 }
4243
4244 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4245                                     volatile u32 *buffer)
4246 {
4247         u32 count = 0, i;
4248         const struct cs_section_def *sect = NULL;
4249         const struct cs_extent_def *ext = NULL;
4250         int ctx_reg_offset;
4251
4252         if (adev->gfx.rlc.cs_data == NULL)
4253                 return;
4254         if (buffer == NULL)
4255                 return;
4256
4257         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4258         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4259
4260         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4261         buffer[count++] = cpu_to_le32(0x80000000);
4262         buffer[count++] = cpu_to_le32(0x80000000);
4263
4264         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4265                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4266                         if (sect->id == SECT_CONTEXT) {
4267                                 buffer[count++] =
4268                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4269                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4270                                                 PACKET3_SET_CONTEXT_REG_START);
4271                                 for (i = 0; i < ext->reg_count; i++)
4272                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4273                         } else {
4274                                 return;
4275                         }
4276                 }
4277         }
4278
4279         ctx_reg_offset =
4280                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4281         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4282         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4283         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4284
4285         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4286         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4287
4288         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4289         buffer[count++] = cpu_to_le32(0);
4290 }
4291
4292 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4293 {
4294         /* clear state block */
4295         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4296                         &adev->gfx.rlc.clear_state_gpu_addr,
4297                         (void **)&adev->gfx.rlc.cs_ptr);
4298
4299         /* jump table block */
4300         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4301                         &adev->gfx.rlc.cp_table_gpu_addr,
4302                         (void **)&adev->gfx.rlc.cp_table_ptr);
4303 }
4304
4305 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4306 {
4307         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4308
4309         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4310         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4311         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4312         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4313         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4314         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4315         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4316         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4317         case IP_VERSION(10, 3, 0):
4318                 reg_access_ctrl->spare_int =
4319                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4320                 break;
4321         default:
4322                 reg_access_ctrl->spare_int =
4323                         SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4324                 break;
4325         }
4326         adev->gfx.rlc.rlcg_reg_access_supported = true;
4327 }
4328
4329 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4330 {
4331         const struct cs_section_def *cs_data;
4332         int r;
4333
4334         adev->gfx.rlc.cs_data = gfx10_cs_data;
4335
4336         cs_data = adev->gfx.rlc.cs_data;
4337
4338         if (cs_data) {
4339                 /* init clear state block */
4340                 r = amdgpu_gfx_rlc_init_csb(adev);
4341                 if (r)
4342                         return r;
4343         }
4344
4345         return 0;
4346 }
4347
4348 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4349 {
4350         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4351         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4352 }
4353
4354 static void gfx_v10_0_me_init(struct amdgpu_device *adev)
4355 {
4356         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4357
4358         amdgpu_gfx_graphics_queue_acquire(adev);
4359 }
4360
4361 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4362 {
4363         int r;
4364         u32 *hpd;
4365         const __le32 *fw_data = NULL;
4366         unsigned int fw_size;
4367         u32 *fw = NULL;
4368         size_t mec_hpd_size;
4369
4370         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4371
4372         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4373
4374         /* take ownership of the relevant compute queues */
4375         amdgpu_gfx_compute_queue_acquire(adev);
4376         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4377
4378         if (mec_hpd_size) {
4379                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4380                                               AMDGPU_GEM_DOMAIN_GTT,
4381                                               &adev->gfx.mec.hpd_eop_obj,
4382                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4383                                               (void **)&hpd);
4384                 if (r) {
4385                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4386                         gfx_v10_0_mec_fini(adev);
4387                         return r;
4388                 }
4389
4390                 memset(hpd, 0, mec_hpd_size);
4391
4392                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4393                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4394         }
4395
4396         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4397                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4398
4399                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4400                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4401                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4402
4403                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4404                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4405                                               &adev->gfx.mec.mec_fw_obj,
4406                                               &adev->gfx.mec.mec_fw_gpu_addr,
4407                                               (void **)&fw);
4408                 if (r) {
4409                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4410                         gfx_v10_0_mec_fini(adev);
4411                         return r;
4412                 }
4413
4414                 memcpy(fw, fw_data, fw_size);
4415
4416                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4417                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4418         }
4419
4420         return 0;
4421 }
4422
4423 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4424 {
4425         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4426                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4427                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4428         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4429 }
4430
4431 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4432                            uint32_t thread, uint32_t regno,
4433                            uint32_t num, uint32_t *out)
4434 {
4435         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4436                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4437                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4438                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4439                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4440         while (num--)
4441                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4442 }
4443
4444 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4445 {
4446         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4447          * field when performing a select_se_sh so it should be
4448          * zero here
4449          */
4450         WARN_ON(simd != 0);
4451
4452         /* type 2 wave data */
4453         dst[(*no_fields)++] = 2;
4454         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4455         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4456         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4457         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4458         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4459         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4460         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4461         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4462         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4463         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4464         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4465         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4466         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4467         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4468         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4469         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4470 }
4471
4472 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4473                                      uint32_t wave, uint32_t start,
4474                                      uint32_t size, uint32_t *dst)
4475 {
4476         WARN_ON(simd != 0);
4477
4478         wave_read_regs(
4479                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4480                 dst);
4481 }
4482
4483 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
4484                                       uint32_t wave, uint32_t thread,
4485                                       uint32_t start, uint32_t size,
4486                                       uint32_t *dst)
4487 {
4488         wave_read_regs(
4489                 adev, wave, thread,
4490                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4491 }
4492
4493 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4494                                        u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
4495 {
4496         nv_grbm_select(adev, me, pipe, q, vm);
4497 }
4498
4499 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4500                                           bool enable)
4501 {
4502         uint32_t data, def;
4503
4504         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4505
4506         if (enable)
4507                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4508         else
4509                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4510
4511         if (data != def)
4512                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4513 }
4514
4515 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4516         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4517         .select_se_sh = &gfx_v10_0_select_se_sh,
4518         .read_wave_data = &gfx_v10_0_read_wave_data,
4519         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4520         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4521         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4522         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4523         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4524 };
4525
4526 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4527 {
4528         u32 gb_addr_config;
4529
4530         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4531         case IP_VERSION(10, 1, 10):
4532         case IP_VERSION(10, 1, 1):
4533         case IP_VERSION(10, 1, 2):
4534                 adev->gfx.config.max_hw_contexts = 8;
4535                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4536                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4537                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4538                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4539                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4540                 break;
4541         case IP_VERSION(10, 3, 0):
4542         case IP_VERSION(10, 3, 2):
4543         case IP_VERSION(10, 3, 1):
4544         case IP_VERSION(10, 3, 4):
4545         case IP_VERSION(10, 3, 5):
4546         case IP_VERSION(10, 3, 6):
4547         case IP_VERSION(10, 3, 3):
4548         case IP_VERSION(10, 3, 7):
4549                 adev->gfx.config.max_hw_contexts = 8;
4550                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4551                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4552                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4553                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4554                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4555                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4556                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4557                 break;
4558         case IP_VERSION(10, 1, 3):
4559         case IP_VERSION(10, 1, 4):
4560                 adev->gfx.config.max_hw_contexts = 8;
4561                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4562                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4563                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4564                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4565                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4566                 break;
4567         default:
4568                 BUG();
4569                 break;
4570         }
4571
4572         adev->gfx.config.gb_addr_config = gb_addr_config;
4573
4574         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4575                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4576                                       GB_ADDR_CONFIG, NUM_PIPES);
4577
4578         adev->gfx.config.max_tile_pipes =
4579                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4580
4581         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4582                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4583                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4584         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4585                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4586                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4587         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4588                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4589                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4590         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4591                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4592                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4593 }
4594
4595 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4596                                    int me, int pipe, int queue)
4597 {
4598         struct amdgpu_ring *ring;
4599         unsigned int irq_type;
4600         unsigned int hw_prio;
4601
4602         ring = &adev->gfx.gfx_ring[ring_id];
4603
4604         ring->me = me;
4605         ring->pipe = pipe;
4606         ring->queue = queue;
4607
4608         ring->ring_obj = NULL;
4609         ring->use_doorbell = true;
4610
4611         if (!ring_id)
4612                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4613         else
4614                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4615         ring->vm_hub = AMDGPU_GFXHUB(0);
4616         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4617
4618         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4619         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4620                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4621         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4622                                 hw_prio, NULL);
4623 }
4624
4625 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4626                                        int mec, int pipe, int queue)
4627 {
4628         unsigned int irq_type;
4629         struct amdgpu_ring *ring;
4630         unsigned int hw_prio;
4631
4632         ring = &adev->gfx.compute_ring[ring_id];
4633
4634         /* mec0 is me1 */
4635         ring->me = mec + 1;
4636         ring->pipe = pipe;
4637         ring->queue = queue;
4638
4639         ring->ring_obj = NULL;
4640         ring->use_doorbell = true;
4641         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4642         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4643                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4644         ring->vm_hub = AMDGPU_GFXHUB(0);
4645         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4646
4647         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4648                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4649                 + ring->pipe;
4650         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4651                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4652         /* type-2 packets are deprecated on MEC, use type-3 instead */
4653         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4654                              hw_prio, NULL);
4655 }
4656
4657 static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
4658 {
4659         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
4660         uint32_t *ptr;
4661         uint32_t inst;
4662
4663         ptr = kcalloc(reg_count, sizeof(uint32_t), GFP_KERNEL);
4664         if (!ptr) {
4665                 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n");
4666                 adev->gfx.ip_dump_core = NULL;
4667         } else {
4668                 adev->gfx.ip_dump_core = ptr;
4669         }
4670
4671         /* Allocate memory for compute queue registers for all the instances */
4672         reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
4673         inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec *
4674                 adev->gfx.mec.num_queue_per_pipe;
4675
4676         ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4677         if (!ptr) {
4678                 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n");
4679                 adev->gfx.ip_dump_compute_queues = NULL;
4680         } else {
4681                 adev->gfx.ip_dump_compute_queues = ptr;
4682         }
4683
4684         /* Allocate memory for gfx queue registers for all the instances */
4685         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
4686         inst = adev->gfx.me.num_me * adev->gfx.me.num_pipe_per_me *
4687                 adev->gfx.me.num_queue_per_pipe;
4688
4689         ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
4690         if (!ptr) {
4691                 DRM_ERROR("Failed to allocate memory for GFX Queues IP Dump\n");
4692                 adev->gfx.ip_dump_gfx_queues = NULL;
4693         } else {
4694                 adev->gfx.ip_dump_gfx_queues = ptr;
4695         }
4696 }
4697
4698 static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
4699 {
4700         int i, j, k, r, ring_id = 0;
4701         int xcc_id = 0;
4702         struct amdgpu_device *adev = ip_block->adev;
4703
4704         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4705         case IP_VERSION(10, 1, 10):
4706         case IP_VERSION(10, 1, 1):
4707         case IP_VERSION(10, 1, 2):
4708         case IP_VERSION(10, 1, 3):
4709         case IP_VERSION(10, 1, 4):
4710                 adev->gfx.me.num_me = 1;
4711                 adev->gfx.me.num_pipe_per_me = 1;
4712                 adev->gfx.me.num_queue_per_pipe = 1;
4713                 adev->gfx.mec.num_mec = 2;
4714                 adev->gfx.mec.num_pipe_per_mec = 4;
4715                 adev->gfx.mec.num_queue_per_pipe = 8;
4716                 break;
4717         case IP_VERSION(10, 3, 0):
4718         case IP_VERSION(10, 3, 2):
4719         case IP_VERSION(10, 3, 1):
4720         case IP_VERSION(10, 3, 4):
4721         case IP_VERSION(10, 3, 5):
4722         case IP_VERSION(10, 3, 6):
4723         case IP_VERSION(10, 3, 3):
4724         case IP_VERSION(10, 3, 7):
4725                 adev->gfx.me.num_me = 1;
4726                 adev->gfx.me.num_pipe_per_me = 2;
4727                 adev->gfx.me.num_queue_per_pipe = 1;
4728                 adev->gfx.mec.num_mec = 2;
4729                 adev->gfx.mec.num_pipe_per_mec = 4;
4730                 adev->gfx.mec.num_queue_per_pipe = 4;
4731                 break;
4732         default:
4733                 adev->gfx.me.num_me = 1;
4734                 adev->gfx.me.num_pipe_per_me = 1;
4735                 adev->gfx.me.num_queue_per_pipe = 1;
4736                 adev->gfx.mec.num_mec = 1;
4737                 adev->gfx.mec.num_pipe_per_mec = 4;
4738                 adev->gfx.mec.num_queue_per_pipe = 8;
4739                 break;
4740         }
4741         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4742         case IP_VERSION(10, 3, 0):
4743         case IP_VERSION(10, 3, 2):
4744         case IP_VERSION(10, 3, 4):
4745         case IP_VERSION(10, 3, 5):
4746                 adev->gfx.cleaner_shader_ptr = gfx_10_3_0_cleaner_shader_hex;
4747                 adev->gfx.cleaner_shader_size = sizeof(gfx_10_3_0_cleaner_shader_hex);
4748                 if (adev->gfx.me_fw_version >= 64 &&
4749                     adev->gfx.pfp_fw_version >= 100 &&
4750                     adev->gfx.mec_fw_version >= 122) {
4751                         adev->gfx.enable_cleaner_shader = true;
4752                         r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size);
4753                         if (r) {
4754                                 adev->gfx.enable_cleaner_shader = false;
4755                                 dev_err(adev->dev, "Failed to initialize cleaner shader\n");
4756                         }
4757                 }
4758                 break;
4759         default:
4760                 adev->gfx.enable_cleaner_shader = false;
4761                 break;
4762         }
4763
4764         /* KIQ event */
4765         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4766                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4767                               &adev->gfx.kiq[0].irq);
4768         if (r)
4769                 return r;
4770
4771         /* EOP Event */
4772         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4773                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4774                               &adev->gfx.eop_irq);
4775         if (r)
4776                 return r;
4777
4778         /* Bad opcode Event */
4779         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4780                               GFX_10_1__SRCID__CP_BAD_OPCODE_ERROR,
4781                               &adev->gfx.bad_op_irq);
4782         if (r)
4783                 return r;
4784
4785         /* Privileged reg */
4786         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4787                               &adev->gfx.priv_reg_irq);
4788         if (r)
4789                 return r;
4790
4791         /* Privileged inst */
4792         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4793                               &adev->gfx.priv_inst_irq);
4794         if (r)
4795                 return r;
4796
4797         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4798
4799         gfx_v10_0_me_init(adev);
4800
4801         if (adev->gfx.rlc.funcs) {
4802                 if (adev->gfx.rlc.funcs->init) {
4803                         r = adev->gfx.rlc.funcs->init(adev);
4804                         if (r) {
4805                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4806                                 return r;
4807                         }
4808                 }
4809         }
4810
4811         r = gfx_v10_0_mec_init(adev);
4812         if (r) {
4813                 DRM_ERROR("Failed to init MEC BOs!\n");
4814                 return r;
4815         }
4816
4817         /* set up the gfx ring */
4818         for (i = 0; i < adev->gfx.me.num_me; i++) {
4819                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4820                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4821                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4822                                         continue;
4823
4824                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4825                                                             i, k, j);
4826                                 if (r)
4827                                         return r;
4828                                 ring_id++;
4829                         }
4830                 }
4831         }
4832
4833         ring_id = 0;
4834         /* set up the compute queues - allocate horizontally across pipes */
4835         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4836                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4837                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4838                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4839                                                                      k, j))
4840                                         continue;
4841
4842                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4843                                                                 i, k, j);
4844                                 if (r)
4845                                         return r;
4846
4847                                 ring_id++;
4848                         }
4849                 }
4850         }
4851         /* TODO: Add queue reset mask when FW fully supports it */
4852         adev->gfx.gfx_supported_reset =
4853                 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]);
4854         adev->gfx.compute_supported_reset =
4855                 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]);
4856
4857         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE, 0);
4858         if (r) {
4859                 DRM_ERROR("Failed to init KIQ BOs!\n");
4860                 return r;
4861         }
4862
4863         r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
4864         if (r)
4865                 return r;
4866
4867         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd), 0);
4868         if (r)
4869                 return r;
4870
4871         /* allocate visible FB for rlc auto-loading fw */
4872         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4873                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4874                 if (r)
4875                         return r;
4876         }
4877
4878         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4879
4880         gfx_v10_0_gpu_early_init(adev);
4881
4882         gfx_v10_0_alloc_ip_dump(adev);
4883
4884         r = amdgpu_gfx_sysfs_init(adev);
4885         if (r)
4886                 return r;
4887
4888         return 0;
4889 }
4890
4891 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4892 {
4893         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4894                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4895                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4896 }
4897
4898 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4899 {
4900         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4901                               &adev->gfx.ce.ce_fw_gpu_addr,
4902                               (void **)&adev->gfx.ce.ce_fw_ptr);
4903 }
4904
4905 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4906 {
4907         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4908                               &adev->gfx.me.me_fw_gpu_addr,
4909                               (void **)&adev->gfx.me.me_fw_ptr);
4910 }
4911
4912 static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
4913 {
4914         int i;
4915         struct amdgpu_device *adev = ip_block->adev;
4916
4917         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4918                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4919         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4920                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4921
4922         amdgpu_gfx_mqd_sw_fini(adev, 0);
4923
4924         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4925         amdgpu_gfx_kiq_fini(adev, 0);
4926
4927         amdgpu_gfx_cleaner_shader_sw_fini(adev);
4928
4929         gfx_v10_0_pfp_fini(adev);
4930         gfx_v10_0_ce_fini(adev);
4931         gfx_v10_0_me_fini(adev);
4932         gfx_v10_0_rlc_fini(adev);
4933         gfx_v10_0_mec_fini(adev);
4934
4935         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4936                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4937
4938         gfx_v10_0_free_microcode(adev);
4939         amdgpu_gfx_sysfs_fini(adev);
4940
4941         kfree(adev->gfx.ip_dump_core);
4942         kfree(adev->gfx.ip_dump_compute_queues);
4943         kfree(adev->gfx.ip_dump_gfx_queues);
4944
4945         return 0;
4946 }
4947
4948 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4949                                    u32 sh_num, u32 instance, int xcc_id)
4950 {
4951         u32 data;
4952
4953         if (instance == 0xffffffff)
4954                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4955                                      INSTANCE_BROADCAST_WRITES, 1);
4956         else
4957                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4958                                      instance);
4959
4960         if (se_num == 0xffffffff)
4961                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4962                                      1);
4963         else
4964                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4965
4966         if (sh_num == 0xffffffff)
4967                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4968                                      1);
4969         else
4970                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4971
4972         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4973 }
4974
4975 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4976 {
4977         u32 data, mask;
4978
4979         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4980         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4981
4982         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4983         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4984
4985         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4986                                          adev->gfx.config.max_sh_per_se);
4987
4988         return (~data) & mask;
4989 }
4990
4991 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4992 {
4993         int i, j;
4994         u32 data;
4995         u32 active_rbs = 0;
4996         u32 bitmap;
4997         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4998                                         adev->gfx.config.max_sh_per_se;
4999
5000         mutex_lock(&adev->grbm_idx_mutex);
5001         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5002                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5003                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
5004                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
5005                               IP_VERSION(10, 3, 0)) ||
5006                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5007                               IP_VERSION(10, 3, 3)) ||
5008                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
5009                               IP_VERSION(10, 3, 6))) &&
5010                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5011                                 continue;
5012                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5013                         data = gfx_v10_0_get_rb_active_bitmap(adev);
5014                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5015                                                rb_bitmap_width_per_sh);
5016                 }
5017         }
5018         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5019         mutex_unlock(&adev->grbm_idx_mutex);
5020
5021         adev->gfx.config.backend_enable_mask = active_rbs;
5022         adev->gfx.config.num_rbs = hweight32(active_rbs);
5023 }
5024
5025 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5026 {
5027         uint32_t num_sc;
5028         uint32_t enabled_rb_per_sh;
5029         uint32_t active_rb_bitmap;
5030         uint32_t num_rb_per_sc;
5031         uint32_t num_packer_per_sc;
5032         uint32_t pa_sc_tile_steering_override;
5033
5034         /* for ASICs that integrates GFX v10.3
5035          * pa_sc_tile_steering_override should be set to 0
5036          */
5037         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0))
5038                 return 0;
5039
5040         /* init num_sc */
5041         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5042                         adev->gfx.config.num_sc_per_sh;
5043         /* init num_rb_per_sc */
5044         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5045         enabled_rb_per_sh = hweight32(active_rb_bitmap);
5046         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5047         /* init num_packer_per_sc */
5048         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5049
5050         pa_sc_tile_steering_override = 0;
5051         pa_sc_tile_steering_override |=
5052                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5053                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5054         pa_sc_tile_steering_override |=
5055                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5056                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5057         pa_sc_tile_steering_override |=
5058                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5059                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5060
5061         return pa_sc_tile_steering_override;
5062 }
5063
5064 #define DEFAULT_SH_MEM_BASES    (0x6000)
5065
5066 static void gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev,
5067                                 uint32_t first_vmid,
5068                                 uint32_t last_vmid)
5069 {
5070         uint32_t data;
5071         uint32_t trap_config_vmid_mask = 0;
5072         int i;
5073
5074         /* Calculate trap config vmid mask */
5075         for (i = first_vmid; i < last_vmid; i++)
5076                 trap_config_vmid_mask |= (1 << i);
5077
5078         data = REG_SET_FIELD(0, SPI_GDBG_TRAP_CONFIG,
5079                         VMID_SEL, trap_config_vmid_mask);
5080         data = REG_SET_FIELD(data, SPI_GDBG_TRAP_CONFIG,
5081                         TRAP_EN, 1);
5082         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data);
5083         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0);
5084
5085         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0);
5086         WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0);
5087 }
5088
5089 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5090 {
5091         int i;
5092         uint32_t sh_mem_bases;
5093
5094         /*
5095          * Configure apertures:
5096          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5097          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5098          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5099          */
5100         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5101
5102         mutex_lock(&adev->srbm_mutex);
5103         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5104                 nv_grbm_select(adev, 0, 0, 0, i);
5105                 /* CP and shaders */
5106                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5107                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5108         }
5109         nv_grbm_select(adev, 0, 0, 0, 0);
5110         mutex_unlock(&adev->srbm_mutex);
5111
5112         /*
5113          * Initialize all compute VMIDs to have no GDS, GWS, or OA
5114          * access. These should be enabled by FW for target VMIDs.
5115          */
5116         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5117                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5118                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5119                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5120                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5121         }
5122
5123         gfx_v10_0_debug_trap_config_init(adev, adev->vm_manager.first_kfd_vmid,
5124                                         AMDGPU_NUM_VMID);
5125 }
5126
5127 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5128 {
5129         int vmid;
5130
5131         /*
5132          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5133          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5134          * the driver can enable them for graphics. VMID0 should maintain
5135          * access so that HWS firmware can save/restore entries.
5136          */
5137         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5138                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5139                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5140                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5141                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5142         }
5143 }
5144
5145
5146 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5147 {
5148         int i, j, k;
5149         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5150         u32 tmp, wgp_active_bitmap = 0;
5151         u32 gcrd_targets_disable_tcp = 0;
5152         u32 utcl_invreq_disable = 0;
5153         /*
5154          * GCRD_TARGETS_DISABLE field contains
5155          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5156          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5157          */
5158         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5159                 2 * max_wgp_per_sh + /* TCP */
5160                 max_wgp_per_sh + /* SQC */
5161                 4); /* GL1C */
5162         /*
5163          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5164          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5165          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5166          */
5167         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5168                 2 * max_wgp_per_sh + /* TCP */
5169                 2 * max_wgp_per_sh + /* SQC */
5170                 4 + /* RMI */
5171                 1); /* SQG */
5172
5173         mutex_lock(&adev->grbm_idx_mutex);
5174         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5175                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5176                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
5177                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5178                         /*
5179                          * Set corresponding TCP bits for the inactive WGPs in
5180                          * GCRD_SA_TARGETS_DISABLE
5181                          */
5182                         gcrd_targets_disable_tcp = 0;
5183                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5184                         utcl_invreq_disable = 0;
5185
5186                         for (k = 0; k < max_wgp_per_sh; k++) {
5187                                 if (!(wgp_active_bitmap & (1 << k))) {
5188                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5189                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5190                                         utcl_invreq_disable |= (3 << (2 * k)) |
5191                                                 (3 << (2 * (max_wgp_per_sh + k)));
5192                                 }
5193                         }
5194
5195                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5196                         /* only override TCP & SQC bits */
5197                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5198                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5199                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5200
5201                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5202                         /* only override TCP & SQC bits */
5203                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5204                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5205                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5206                 }
5207         }
5208
5209         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
5210         mutex_unlock(&adev->grbm_idx_mutex);
5211 }
5212
5213 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5214 {
5215         /* TCCs are global (not instanced). */
5216         uint32_t tcc_disable;
5217
5218         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0)) {
5219                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5220                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5221         } else {
5222                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5223                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5224         }
5225
5226         adev->gfx.config.tcc_disabled_mask =
5227                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5228                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5229 }
5230
5231 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5232 {
5233         u32 tmp;
5234         int i;
5235
5236         if (!amdgpu_sriov_vf(adev))
5237                 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5238
5239         gfx_v10_0_setup_rb(adev);
5240         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5241         gfx_v10_0_get_tcc_info(adev);
5242         adev->gfx.config.pa_sc_tile_steering_override =
5243                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5244
5245         /* XXX SH_MEM regs */
5246         /* where to put LDS, scratch, GPUVM in FSA64 space */
5247         mutex_lock(&adev->srbm_mutex);
5248         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
5249                 nv_grbm_select(adev, 0, 0, 0, i);
5250                 /* CP and shaders */
5251                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5252                 if (i != 0) {
5253                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5254                                 (adev->gmc.private_aperture_start >> 48));
5255                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5256                                 (adev->gmc.shared_aperture_start >> 48));
5257                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5258                 }
5259         }
5260         nv_grbm_select(adev, 0, 0, 0, 0);
5261
5262         mutex_unlock(&adev->srbm_mutex);
5263
5264         gfx_v10_0_init_compute_vmid(adev);
5265         gfx_v10_0_init_gds_vmid(adev);
5266
5267 }
5268
5269 static u32 gfx_v10_0_get_cpg_int_cntl(struct amdgpu_device *adev,
5270                                       int me, int pipe)
5271 {
5272         if (me != 0)
5273                 return 0;
5274
5275         switch (pipe) {
5276         case 0:
5277                 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
5278         case 1:
5279                 return SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
5280         default:
5281                 return 0;
5282         }
5283 }
5284
5285 static u32 gfx_v10_0_get_cpc_int_cntl(struct amdgpu_device *adev,
5286                                       int me, int pipe)
5287 {
5288         /*
5289          * amdgpu controls only the first MEC. That's why this function only
5290          * handles the setting of interrupts for this specific MEC. All other
5291          * pipes' interrupts are set by amdkfd.
5292          */
5293         if (me != 1)
5294                 return 0;
5295
5296         switch (pipe) {
5297         case 0:
5298                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5299         case 1:
5300                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
5301         case 2:
5302                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
5303         case 3:
5304                 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
5305         default:
5306                 return 0;
5307         }
5308 }
5309
5310 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5311                                                bool enable)
5312 {
5313         u32 tmp, cp_int_cntl_reg;
5314         int i, j;
5315
5316         if (amdgpu_sriov_vf(adev))
5317                 return;
5318
5319         for (i = 0; i < adev->gfx.me.num_me; i++) {
5320                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
5321                         cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
5322
5323                         if (cp_int_cntl_reg) {
5324                                 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5325                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5326                                                     enable ? 1 : 0);
5327                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5328                                                     enable ? 1 : 0);
5329                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5330                                                     enable ? 1 : 0);
5331                                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5332                                                     enable ? 1 : 0);
5333                                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
5334                         }
5335                 }
5336         }
5337 }
5338
5339 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5340 {
5341         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5342
5343         /* csib */
5344         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
5345                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5346                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5347                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5348                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5349                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5350         } else {
5351                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5352                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5353                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5354                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5355                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5356         }
5357         return 0;
5358 }
5359
5360 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5361 {
5362         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5363
5364         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5365         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5366 }
5367
5368 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5369 {
5370         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5371         udelay(50);
5372         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5373         udelay(50);
5374 }
5375
5376 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5377                                              bool enable)
5378 {
5379         uint32_t rlc_pg_cntl;
5380
5381         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5382
5383         if (!enable) {
5384                 /* RLC_PG_CNTL[23] = 0 (default)
5385                  * RLC will wait for handshake acks with SMU
5386                  * GFXOFF will be enabled
5387                  * RLC_PG_CNTL[23] = 1
5388                  * RLC will not issue any message to SMU
5389                  * hence no handshake between SMU & RLC
5390                  * GFXOFF will be disabled
5391                  */
5392                 rlc_pg_cntl |= 0x800000;
5393         } else
5394                 rlc_pg_cntl &= ~0x800000;
5395         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5396 }
5397
5398 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5399 {
5400         /*
5401          * TODO: enable rlc & smu handshake until smu
5402          * and gfxoff feature works as expected
5403          */
5404         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5405                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5406
5407         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5408         udelay(50);
5409 }
5410
5411 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5412 {
5413         uint32_t tmp;
5414
5415         /* enable Save Restore Machine */
5416         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5417         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5418         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5419         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5420 }
5421
5422 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5423 {
5424         const struct rlc_firmware_header_v2_0 *hdr;
5425         const __le32 *fw_data;
5426         unsigned int i, fw_size;
5427
5428         if (!adev->gfx.rlc_fw)
5429                 return -EINVAL;
5430
5431         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5432         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5433
5434         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5435                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5436         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5437
5438         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5439                      RLCG_UCODE_LOADING_START_ADDRESS);
5440
5441         for (i = 0; i < fw_size; i++)
5442                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5443                              le32_to_cpup(fw_data++));
5444
5445         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5446
5447         return 0;
5448 }
5449
5450 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5451 {
5452         int r;
5453
5454         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5455                 adev->psp.autoload_supported) {
5456
5457                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5458                 if (r)
5459                         return r;
5460
5461                 gfx_v10_0_init_csb(adev);
5462
5463                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5464
5465                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5466                         gfx_v10_0_rlc_enable_srm(adev);
5467         } else {
5468                 if (amdgpu_sriov_vf(adev)) {
5469                         gfx_v10_0_init_csb(adev);
5470                         return 0;
5471                 }
5472
5473                 adev->gfx.rlc.funcs->stop(adev);
5474
5475                 /* disable CG */
5476                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5477
5478                 /* disable PG */
5479                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5480
5481                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5482                         /* legacy rlc firmware loading */
5483                         r = gfx_v10_0_rlc_load_microcode(adev);
5484                         if (r)
5485                                 return r;
5486                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5487                         /* rlc backdoor autoload firmware */
5488                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5489                         if (r)
5490                                 return r;
5491                 }
5492
5493                 gfx_v10_0_init_csb(adev);
5494
5495                 gfx_v10_0_update_spm_vmid_internal(adev, 0xf);
5496
5497                 adev->gfx.rlc.funcs->start(adev);
5498
5499                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5500                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5501                         if (r)
5502                                 return r;
5503                 }
5504         }
5505
5506         return 0;
5507 }
5508
5509 static struct {
5510         FIRMWARE_ID     id;
5511         unsigned int    offset;
5512         unsigned int    size;
5513 } rlc_autoload_info[FIRMWARE_ID_MAX];
5514
5515 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5516 {
5517         int ret;
5518         RLC_TABLE_OF_CONTENT *rlc_toc;
5519
5520         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5521                                         AMDGPU_GEM_DOMAIN_GTT,
5522                                         &adev->gfx.rlc.rlc_toc_bo,
5523                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5524                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5525         if (ret) {
5526                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5527                 return ret;
5528         }
5529
5530         /* Copy toc from psp sos fw to rlc toc buffer */
5531         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5532
5533         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5534         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5535                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5536                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5537                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5538                         /* Offset needs 4KB alignment */
5539                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5540                 }
5541
5542                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5543                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5544                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5545
5546                 rlc_toc++;
5547         }
5548
5549         return 0;
5550 }
5551
5552 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5553 {
5554         uint32_t total_size = 0;
5555         FIRMWARE_ID id;
5556         int ret;
5557
5558         ret = gfx_v10_0_parse_rlc_toc(adev);
5559         if (ret) {
5560                 dev_err(adev->dev, "failed to parse rlc toc\n");
5561                 return 0;
5562         }
5563
5564         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5565                 total_size += rlc_autoload_info[id].size;
5566
5567         /* In case the offset in rlc toc ucode is aligned */
5568         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5569                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5570                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5571
5572         return total_size;
5573 }
5574
5575 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5576 {
5577         int r;
5578         uint32_t total_size;
5579
5580         total_size = gfx_v10_0_calc_toc_total_size(adev);
5581
5582         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5583                                       AMDGPU_GEM_DOMAIN_GTT,
5584                                       &adev->gfx.rlc.rlc_autoload_bo,
5585                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5586                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5587         if (r) {
5588                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5589                 return r;
5590         }
5591
5592         return 0;
5593 }
5594
5595 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5596 {
5597         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5598                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5599                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5600         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5601                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5602                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5603 }
5604
5605 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5606                                                        FIRMWARE_ID id,
5607                                                        const void *fw_data,
5608                                                        uint32_t fw_size)
5609 {
5610         uint32_t toc_offset;
5611         uint32_t toc_fw_size;
5612         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5613
5614         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5615                 return;
5616
5617         toc_offset = rlc_autoload_info[id].offset;
5618         toc_fw_size = rlc_autoload_info[id].size;
5619
5620         if (fw_size == 0)
5621                 fw_size = toc_fw_size;
5622
5623         if (fw_size > toc_fw_size)
5624                 fw_size = toc_fw_size;
5625
5626         memcpy(ptr + toc_offset, fw_data, fw_size);
5627
5628         if (fw_size < toc_fw_size)
5629                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5630 }
5631
5632 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5633 {
5634         void *data;
5635         uint32_t size;
5636
5637         data = adev->gfx.rlc.rlc_toc_buf;
5638         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5639
5640         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5641                                                    FIRMWARE_ID_RLC_TOC,
5642                                                    data, size);
5643 }
5644
5645 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5646 {
5647         const __le32 *fw_data;
5648         uint32_t fw_size;
5649         const struct gfx_firmware_header_v1_0 *cp_hdr;
5650         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5651
5652         /* pfp ucode */
5653         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5654                 adev->gfx.pfp_fw->data;
5655         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5656                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5657         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5658         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5659                                                    FIRMWARE_ID_CP_PFP,
5660                                                    fw_data, fw_size);
5661
5662         /* ce ucode */
5663         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5664                 adev->gfx.ce_fw->data;
5665         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5666                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5667         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5668         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5669                                                    FIRMWARE_ID_CP_CE,
5670                                                    fw_data, fw_size);
5671
5672         /* me ucode */
5673         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5674                 adev->gfx.me_fw->data;
5675         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5676                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5677         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5678         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5679                                                    FIRMWARE_ID_CP_ME,
5680                                                    fw_data, fw_size);
5681
5682         /* rlc ucode */
5683         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5684                 adev->gfx.rlc_fw->data;
5685         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5686                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5687         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5688         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5689                                                    FIRMWARE_ID_RLC_G_UCODE,
5690                                                    fw_data, fw_size);
5691
5692         /* mec1 ucode */
5693         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5694                 adev->gfx.mec_fw->data;
5695         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5696                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5697         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5698                 cp_hdr->jt_size * 4;
5699         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5700                                                    FIRMWARE_ID_CP_MEC,
5701                                                    fw_data, fw_size);
5702         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5703 }
5704
5705 /* Temporarily put sdma part here */
5706 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5707 {
5708         const __le32 *fw_data;
5709         uint32_t fw_size;
5710         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5711         int i;
5712
5713         for (i = 0; i < adev->sdma.num_instances; i++) {
5714                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5715                         adev->sdma.instance[i].fw->data;
5716                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5717                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5718                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5719
5720                 if (i == 0) {
5721                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5722                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5723                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5724                                 FIRMWARE_ID_SDMA0_JT,
5725                                 (uint32_t *)fw_data +
5726                                 sdma_hdr->jt_offset,
5727                                 sdma_hdr->jt_size * 4);
5728                 } else if (i == 1) {
5729                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5730                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5731                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5732                                 FIRMWARE_ID_SDMA1_JT,
5733                                 (uint32_t *)fw_data +
5734                                 sdma_hdr->jt_offset,
5735                                 sdma_hdr->jt_size * 4);
5736                 }
5737         }
5738 }
5739
5740 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5741 {
5742         uint32_t rlc_g_offset, rlc_g_size, tmp;
5743         uint64_t gpu_addr;
5744
5745         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5746         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5747         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5748
5749         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5750         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5751         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5752
5753         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5754         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5755         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5756
5757         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5758         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5759                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5760                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5761                 return -EINVAL;
5762         }
5763
5764         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5765         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5766                 DRM_ERROR("RLC ROM should halt itself\n");
5767                 return -EINVAL;
5768         }
5769
5770         return 0;
5771 }
5772
5773 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5774 {
5775         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5776         uint32_t tmp;
5777         int i;
5778         uint64_t addr;
5779
5780         /* Trigger an invalidation of the L1 instruction caches */
5781         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5782         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5783         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5784
5785         /* Wait for invalidation complete */
5786         for (i = 0; i < usec_timeout; i++) {
5787                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5788                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5789                         INVALIDATE_CACHE_COMPLETE))
5790                         break;
5791                 udelay(1);
5792         }
5793
5794         if (i >= usec_timeout) {
5795                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5796                 return -EINVAL;
5797         }
5798
5799         /* Program me ucode address into intruction cache address register */
5800         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5801                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5802         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5803                         lower_32_bits(addr) & 0xFFFFF000);
5804         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5805                         upper_32_bits(addr));
5806
5807         return 0;
5808 }
5809
5810 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5811 {
5812         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5813         uint32_t tmp;
5814         int i;
5815         uint64_t addr;
5816
5817         /* Trigger an invalidation of the L1 instruction caches */
5818         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5819         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5820         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5821
5822         /* Wait for invalidation complete */
5823         for (i = 0; i < usec_timeout; i++) {
5824                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5825                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5826                         INVALIDATE_CACHE_COMPLETE))
5827                         break;
5828                 udelay(1);
5829         }
5830
5831         if (i >= usec_timeout) {
5832                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5833                 return -EINVAL;
5834         }
5835
5836         /* Program ce ucode address into intruction cache address register */
5837         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5838                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5839         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5840                         lower_32_bits(addr) & 0xFFFFF000);
5841         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5842                         upper_32_bits(addr));
5843
5844         return 0;
5845 }
5846
5847 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5848 {
5849         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5850         uint32_t tmp;
5851         int i;
5852         uint64_t addr;
5853
5854         /* Trigger an invalidation of the L1 instruction caches */
5855         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5856         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5857         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5858
5859         /* Wait for invalidation complete */
5860         for (i = 0; i < usec_timeout; i++) {
5861                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5862                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5863                         INVALIDATE_CACHE_COMPLETE))
5864                         break;
5865                 udelay(1);
5866         }
5867
5868         if (i >= usec_timeout) {
5869                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5870                 return -EINVAL;
5871         }
5872
5873         /* Program pfp ucode address into intruction cache address register */
5874         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5875                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5876         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5877                         lower_32_bits(addr) & 0xFFFFF000);
5878         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5879                         upper_32_bits(addr));
5880
5881         return 0;
5882 }
5883
5884 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5885 {
5886         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5887         uint32_t tmp;
5888         int i;
5889         uint64_t addr;
5890
5891         /* Trigger an invalidation of the L1 instruction caches */
5892         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5893         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5894         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5895
5896         /* Wait for invalidation complete */
5897         for (i = 0; i < usec_timeout; i++) {
5898                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5899                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5900                         INVALIDATE_CACHE_COMPLETE))
5901                         break;
5902                 udelay(1);
5903         }
5904
5905         if (i >= usec_timeout) {
5906                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5907                 return -EINVAL;
5908         }
5909
5910         /* Program mec1 ucode address into intruction cache address register */
5911         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5912                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5913         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5914                         lower_32_bits(addr) & 0xFFFFF000);
5915         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5916                         upper_32_bits(addr));
5917
5918         return 0;
5919 }
5920
5921 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5922 {
5923         uint32_t cp_status;
5924         uint32_t bootload_status;
5925         int i, r;
5926
5927         for (i = 0; i < adev->usec_timeout; i++) {
5928                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5929                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5930                 if ((cp_status == 0) &&
5931                     (REG_GET_FIELD(bootload_status,
5932                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5933                         break;
5934                 }
5935                 udelay(1);
5936         }
5937
5938         if (i >= adev->usec_timeout) {
5939                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5940                 return -ETIMEDOUT;
5941         }
5942
5943         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5944                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5945                 if (r)
5946                         return r;
5947
5948                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5949                 if (r)
5950                         return r;
5951
5952                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5953                 if (r)
5954                         return r;
5955
5956                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5957                 if (r)
5958                         return r;
5959         }
5960
5961         return 0;
5962 }
5963
5964 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5965 {
5966         int i;
5967         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5968
5969         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5970         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5971         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5972
5973         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
5974                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5975         else
5976                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5977
5978         if (amdgpu_in_reset(adev) && !enable)
5979                 return 0;
5980
5981         for (i = 0; i < adev->usec_timeout; i++) {
5982                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5983                         break;
5984                 udelay(1);
5985         }
5986
5987         if (i >= adev->usec_timeout)
5988                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5989
5990         return 0;
5991 }
5992
5993 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5994 {
5995         int r;
5996         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5997         const __le32 *fw_data;
5998         unsigned int i, fw_size;
5999         uint32_t tmp;
6000         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6001
6002         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6003                 adev->gfx.pfp_fw->data;
6004
6005         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6006
6007         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6008                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6009         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6010
6011         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6012                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6013                                       &adev->gfx.pfp.pfp_fw_obj,
6014                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
6015                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
6016         if (r) {
6017                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6018                 gfx_v10_0_pfp_fini(adev);
6019                 return r;
6020         }
6021
6022         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6023
6024         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6025         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6026
6027         /* Trigger an invalidation of the L1 instruction caches */
6028         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6029         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6030         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6031
6032         /* Wait for invalidation complete */
6033         for (i = 0; i < usec_timeout; i++) {
6034                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6035                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6036                         INVALIDATE_CACHE_COMPLETE))
6037                         break;
6038                 udelay(1);
6039         }
6040
6041         if (i >= usec_timeout) {
6042                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6043                 return -EINVAL;
6044         }
6045
6046         if (amdgpu_emu_mode == 1)
6047                 adev->hdp.funcs->flush_hdp(adev, NULL);
6048
6049         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6050         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6051         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6052         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6053         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6054         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6055         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6056                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6057         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6058                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6059
6060         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6061
6062         for (i = 0; i < pfp_hdr->jt_size; i++)
6063                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6064                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6065
6066         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6067
6068         return 0;
6069 }
6070
6071 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6072 {
6073         int r;
6074         const struct gfx_firmware_header_v1_0 *ce_hdr;
6075         const __le32 *fw_data;
6076         unsigned int i, fw_size;
6077         uint32_t tmp;
6078         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6079
6080         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6081                 adev->gfx.ce_fw->data;
6082
6083         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6084
6085         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6086                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6087         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6088
6089         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6090                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6091                                       &adev->gfx.ce.ce_fw_obj,
6092                                       &adev->gfx.ce.ce_fw_gpu_addr,
6093                                       (void **)&adev->gfx.ce.ce_fw_ptr);
6094         if (r) {
6095                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6096                 gfx_v10_0_ce_fini(adev);
6097                 return r;
6098         }
6099
6100         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6101
6102         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6103         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6104
6105         /* Trigger an invalidation of the L1 instruction caches */
6106         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6107         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6108         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6109
6110         /* Wait for invalidation complete */
6111         for (i = 0; i < usec_timeout; i++) {
6112                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6113                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6114                         INVALIDATE_CACHE_COMPLETE))
6115                         break;
6116                 udelay(1);
6117         }
6118
6119         if (i >= usec_timeout) {
6120                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6121                 return -EINVAL;
6122         }
6123
6124         if (amdgpu_emu_mode == 1)
6125                 adev->hdp.funcs->flush_hdp(adev, NULL);
6126
6127         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6128         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6129         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6130         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6131         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6132         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6133                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6134         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6135                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6136
6137         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6138
6139         for (i = 0; i < ce_hdr->jt_size; i++)
6140                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6141                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6142
6143         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6144
6145         return 0;
6146 }
6147
6148 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6149 {
6150         int r;
6151         const struct gfx_firmware_header_v1_0 *me_hdr;
6152         const __le32 *fw_data;
6153         unsigned int i, fw_size;
6154         uint32_t tmp;
6155         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6156
6157         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6158                 adev->gfx.me_fw->data;
6159
6160         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6161
6162         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6163                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6164         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6165
6166         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6167                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6168                                       &adev->gfx.me.me_fw_obj,
6169                                       &adev->gfx.me.me_fw_gpu_addr,
6170                                       (void **)&adev->gfx.me.me_fw_ptr);
6171         if (r) {
6172                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6173                 gfx_v10_0_me_fini(adev);
6174                 return r;
6175         }
6176
6177         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6178
6179         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6180         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6181
6182         /* Trigger an invalidation of the L1 instruction caches */
6183         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6184         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6185         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6186
6187         /* Wait for invalidation complete */
6188         for (i = 0; i < usec_timeout; i++) {
6189                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6190                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6191                         INVALIDATE_CACHE_COMPLETE))
6192                         break;
6193                 udelay(1);
6194         }
6195
6196         if (i >= usec_timeout) {
6197                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6198                 return -EINVAL;
6199         }
6200
6201         if (amdgpu_emu_mode == 1)
6202                 adev->hdp.funcs->flush_hdp(adev, NULL);
6203
6204         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6205         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6206         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6207         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6208         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6209         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6210                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6211         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6212                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6213
6214         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6215
6216         for (i = 0; i < me_hdr->jt_size; i++)
6217                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6218                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6219
6220         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6221
6222         return 0;
6223 }
6224
6225 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6226 {
6227         int r;
6228
6229         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6230                 return -EINVAL;
6231
6232         gfx_v10_0_cp_gfx_enable(adev, false);
6233
6234         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6235         if (r) {
6236                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6237                 return r;
6238         }
6239
6240         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6241         if (r) {
6242                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6243                 return r;
6244         }
6245
6246         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6247         if (r) {
6248                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6249                 return r;
6250         }
6251
6252         return 0;
6253 }
6254
6255 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6256 {
6257         struct amdgpu_ring *ring;
6258         const struct cs_section_def *sect = NULL;
6259         const struct cs_extent_def *ext = NULL;
6260         int r, i;
6261         int ctx_reg_offset;
6262
6263         /* init the CP */
6264         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6265                      adev->gfx.config.max_hw_contexts - 1);
6266         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6267
6268         gfx_v10_0_cp_gfx_enable(adev, true);
6269
6270         ring = &adev->gfx.gfx_ring[0];
6271         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6272         if (r) {
6273                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6274                 return r;
6275         }
6276
6277         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6278         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6279
6280         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6281         amdgpu_ring_write(ring, 0x80000000);
6282         amdgpu_ring_write(ring, 0x80000000);
6283
6284         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6285                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6286                         if (sect->id == SECT_CONTEXT) {
6287                                 amdgpu_ring_write(ring,
6288                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6289                                                           ext->reg_count));
6290                                 amdgpu_ring_write(ring, ext->reg_index -
6291                                                   PACKET3_SET_CONTEXT_REG_START);
6292                                 for (i = 0; i < ext->reg_count; i++)
6293                                         amdgpu_ring_write(ring, ext->extent[i]);
6294                         }
6295                 }
6296         }
6297
6298         ctx_reg_offset =
6299                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6300         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6301         amdgpu_ring_write(ring, ctx_reg_offset);
6302         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6303
6304         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6305         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6306
6307         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6308         amdgpu_ring_write(ring, 0);
6309
6310         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6311         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6312         amdgpu_ring_write(ring, 0x8000);
6313         amdgpu_ring_write(ring, 0x8000);
6314
6315         amdgpu_ring_commit(ring);
6316
6317         /* submit cs packet to copy state 0 to next available state */
6318         if (adev->gfx.num_gfx_rings > 1) {
6319                 /* maximum supported gfx ring is 2 */
6320                 ring = &adev->gfx.gfx_ring[1];
6321                 r = amdgpu_ring_alloc(ring, 2);
6322                 if (r) {
6323                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6324                         return r;
6325                 }
6326
6327                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6328                 amdgpu_ring_write(ring, 0);
6329
6330                 amdgpu_ring_commit(ring);
6331         }
6332         return 0;
6333 }
6334
6335 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6336                                          CP_PIPE_ID pipe)
6337 {
6338         u32 tmp;
6339
6340         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6341         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6342
6343         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6344 }
6345
6346 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6347                                           struct amdgpu_ring *ring)
6348 {
6349         u32 tmp;
6350
6351         if (!amdgpu_async_gfx_ring) {
6352                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6353                 if (ring->use_doorbell) {
6354                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6355                                                 DOORBELL_OFFSET, ring->doorbell_index);
6356                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6357                                                 DOORBELL_EN, 1);
6358                 } else {
6359                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6360                                                 DOORBELL_EN, 0);
6361                 }
6362                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6363         }
6364         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6365         case IP_VERSION(10, 3, 0):
6366         case IP_VERSION(10, 3, 2):
6367         case IP_VERSION(10, 3, 1):
6368         case IP_VERSION(10, 3, 4):
6369         case IP_VERSION(10, 3, 5):
6370         case IP_VERSION(10, 3, 6):
6371         case IP_VERSION(10, 3, 3):
6372         case IP_VERSION(10, 3, 7):
6373                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6374                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6375                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6376
6377                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6378                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6379                 break;
6380         default:
6381                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6382                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6383                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6384
6385                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6386                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6387                 break;
6388         }
6389 }
6390
6391 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6392 {
6393         struct amdgpu_ring *ring;
6394         u32 tmp;
6395         u32 rb_bufsz;
6396         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6397
6398         /* Set the write pointer delay */
6399         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6400
6401         /* set the RB to use vmid 0 */
6402         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6403
6404         /* Init gfx ring 0 for pipe 0 */
6405         mutex_lock(&adev->srbm_mutex);
6406         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6407
6408         /* Set ring buffer size */
6409         ring = &adev->gfx.gfx_ring[0];
6410         rb_bufsz = order_base_2(ring->ring_size / 8);
6411         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6412         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6413 #ifdef __BIG_ENDIAN
6414         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6415 #endif
6416         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6417
6418         /* Initialize the ring buffer's write pointers */
6419         ring->wptr = 0;
6420         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6421         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6422
6423         /* set the wb address whether it's enabled or not */
6424         rptr_addr = ring->rptr_gpu_addr;
6425         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6426         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6427                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6428
6429         wptr_gpu_addr = ring->wptr_gpu_addr;
6430         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6431                      lower_32_bits(wptr_gpu_addr));
6432         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6433                      upper_32_bits(wptr_gpu_addr));
6434
6435         mdelay(1);
6436         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6437
6438         rb_addr = ring->gpu_addr >> 8;
6439         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6440         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6441
6442         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6443
6444         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6445         mutex_unlock(&adev->srbm_mutex);
6446
6447         /* Init gfx ring 1 for pipe 1 */
6448         if (adev->gfx.num_gfx_rings > 1) {
6449                 mutex_lock(&adev->srbm_mutex);
6450                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6451                 /* maximum supported gfx ring is 2 */
6452                 ring = &adev->gfx.gfx_ring[1];
6453                 rb_bufsz = order_base_2(ring->ring_size / 8);
6454                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6455                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6456                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6457                 /* Initialize the ring buffer's write pointers */
6458                 ring->wptr = 0;
6459                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6460                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6461                 /* Set the wb address whether it's enabled or not */
6462                 rptr_addr = ring->rptr_gpu_addr;
6463                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6464                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6465                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6466                 wptr_gpu_addr = ring->wptr_gpu_addr;
6467                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6468                              lower_32_bits(wptr_gpu_addr));
6469                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6470                              upper_32_bits(wptr_gpu_addr));
6471
6472                 mdelay(1);
6473                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6474
6475                 rb_addr = ring->gpu_addr >> 8;
6476                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6477                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6478                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6479
6480                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6481                 mutex_unlock(&adev->srbm_mutex);
6482         }
6483         /* Switch to pipe 0 */
6484         mutex_lock(&adev->srbm_mutex);
6485         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6486         mutex_unlock(&adev->srbm_mutex);
6487
6488         /* start the ring */
6489         gfx_v10_0_cp_gfx_start(adev);
6490
6491         return 0;
6492 }
6493
6494 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6495 {
6496         if (enable) {
6497                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6498                 case IP_VERSION(10, 3, 0):
6499                 case IP_VERSION(10, 3, 2):
6500                 case IP_VERSION(10, 3, 1):
6501                 case IP_VERSION(10, 3, 4):
6502                 case IP_VERSION(10, 3, 5):
6503                 case IP_VERSION(10, 3, 6):
6504                 case IP_VERSION(10, 3, 3):
6505                 case IP_VERSION(10, 3, 7):
6506                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6507                         break;
6508                 default:
6509                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6510                         break;
6511                 }
6512         } else {
6513                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6514                 case IP_VERSION(10, 3, 0):
6515                 case IP_VERSION(10, 3, 2):
6516                 case IP_VERSION(10, 3, 1):
6517                 case IP_VERSION(10, 3, 4):
6518                 case IP_VERSION(10, 3, 5):
6519                 case IP_VERSION(10, 3, 6):
6520                 case IP_VERSION(10, 3, 3):
6521                 case IP_VERSION(10, 3, 7):
6522                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6523                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6524                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6525                         break;
6526                 default:
6527                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6528                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6529                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6530                         break;
6531                 }
6532                 adev->gfx.kiq[0].ring.sched.ready = false;
6533         }
6534         udelay(50);
6535 }
6536
6537 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6538 {
6539         const struct gfx_firmware_header_v1_0 *mec_hdr;
6540         const __le32 *fw_data;
6541         unsigned int i;
6542         u32 tmp;
6543         u32 usec_timeout = 50000; /* Wait for 50 ms */
6544
6545         if (!adev->gfx.mec_fw)
6546                 return -EINVAL;
6547
6548         gfx_v10_0_cp_compute_enable(adev, false);
6549
6550         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6551         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6552
6553         fw_data = (const __le32 *)
6554                 (adev->gfx.mec_fw->data +
6555                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6556
6557         /* Trigger an invalidation of the L1 instruction caches */
6558         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6559         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6560         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6561
6562         /* Wait for invalidation complete */
6563         for (i = 0; i < usec_timeout; i++) {
6564                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6565                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6566                                        INVALIDATE_CACHE_COMPLETE))
6567                         break;
6568                 udelay(1);
6569         }
6570
6571         if (i >= usec_timeout) {
6572                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6573                 return -EINVAL;
6574         }
6575
6576         if (amdgpu_emu_mode == 1)
6577                 adev->hdp.funcs->flush_hdp(adev, NULL);
6578
6579         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6580         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6581         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6582         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6583         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6584
6585         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6586                      0xFFFFF000);
6587         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6588                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6589
6590         /* MEC1 */
6591         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6592
6593         for (i = 0; i < mec_hdr->jt_size; i++)
6594                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6595                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6596
6597         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6598
6599         /*
6600          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6601          * different microcode than MEC1.
6602          */
6603
6604         return 0;
6605 }
6606
6607 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6608 {
6609         uint32_t tmp;
6610         struct amdgpu_device *adev = ring->adev;
6611
6612         /* tell RLC which is KIQ queue */
6613         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
6614         case IP_VERSION(10, 3, 0):
6615         case IP_VERSION(10, 3, 2):
6616         case IP_VERSION(10, 3, 1):
6617         case IP_VERSION(10, 3, 4):
6618         case IP_VERSION(10, 3, 5):
6619         case IP_VERSION(10, 3, 6):
6620         case IP_VERSION(10, 3, 3):
6621         case IP_VERSION(10, 3, 7):
6622                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6623                 tmp &= 0xffffff00;
6624                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6625                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp | 0x80);
6626                 break;
6627         default:
6628                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6629                 tmp &= 0xffffff00;
6630                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6631                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp | 0x80);
6632                 break;
6633         }
6634 }
6635
6636 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6637                                            struct v10_gfx_mqd *mqd,
6638                                            struct amdgpu_mqd_prop *prop)
6639 {
6640         bool priority = 0;
6641         u32 tmp;
6642
6643         /* set up default queue priority level
6644          * 0x0 = low priority, 0x1 = high priority
6645          */
6646         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6647                 priority = 1;
6648
6649         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6650         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6651         mqd->cp_gfx_hqd_queue_priority = tmp;
6652 }
6653
6654 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6655                                   struct amdgpu_mqd_prop *prop)
6656 {
6657         struct v10_gfx_mqd *mqd = m;
6658         uint64_t hqd_gpu_addr, wb_gpu_addr;
6659         uint32_t tmp;
6660         uint32_t rb_bufsz;
6661
6662         /* set up gfx hqd wptr */
6663         mqd->cp_gfx_hqd_wptr = 0;
6664         mqd->cp_gfx_hqd_wptr_hi = 0;
6665
6666         /* set the pointer to the MQD */
6667         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6668         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6669
6670         /* set up mqd control */
6671         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6672         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6673         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6674         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6675         mqd->cp_gfx_mqd_control = tmp;
6676
6677         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6678         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6679         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6680         mqd->cp_gfx_hqd_vmid = 0;
6681
6682         /* set up gfx queue priority */
6683         gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6684
6685         /* set up time quantum */
6686         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6687         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6688         mqd->cp_gfx_hqd_quantum = tmp;
6689
6690         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6691         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6692         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6693         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6694
6695         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6696         wb_gpu_addr = prop->rptr_gpu_addr;
6697         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6698         mqd->cp_gfx_hqd_rptr_addr_hi =
6699                 upper_32_bits(wb_gpu_addr) & 0xffff;
6700
6701         /* set up rb_wptr_poll addr */
6702         wb_gpu_addr = prop->wptr_gpu_addr;
6703         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6704         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6705
6706         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6707         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6708         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6709         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6710         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6711 #ifdef __BIG_ENDIAN
6712         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6713 #endif
6714         mqd->cp_gfx_hqd_cntl = tmp;
6715
6716         /* set up cp_doorbell_control */
6717         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6718         if (prop->use_doorbell) {
6719                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6720                                     DOORBELL_OFFSET, prop->doorbell_index);
6721                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6722                                     DOORBELL_EN, 1);
6723         } else
6724                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6725                                     DOORBELL_EN, 0);
6726         mqd->cp_rb_doorbell_control = tmp;
6727
6728         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6729         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6730
6731         /* active the queue */
6732         mqd->cp_gfx_hqd_active = 1;
6733
6734         return 0;
6735 }
6736
6737 static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset)
6738 {
6739         struct amdgpu_device *adev = ring->adev;
6740         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6741         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6742
6743         if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) {
6744                 memset((void *)mqd, 0, sizeof(*mqd));
6745                 mutex_lock(&adev->srbm_mutex);
6746                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6747                 amdgpu_ring_init_mqd(ring);
6748
6749                 /*
6750                  * if there are 2 gfx rings, set the lower doorbell
6751                  * range of the first ring, otherwise the range of
6752                  * the second ring will override the first ring
6753                  */
6754                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6755                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6756
6757                 nv_grbm_select(adev, 0, 0, 0, 0);
6758                 mutex_unlock(&adev->srbm_mutex);
6759                 if (adev->gfx.me.mqd_backup[mqd_idx])
6760                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6761         } else {
6762                 mutex_lock(&adev->srbm_mutex);
6763                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6764                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6765                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6766
6767                 nv_grbm_select(adev, 0, 0, 0, 0);
6768                 mutex_unlock(&adev->srbm_mutex);
6769                 /* restore mqd with the backup copy */
6770                 if (adev->gfx.me.mqd_backup[mqd_idx])
6771                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6772                 /* reset the ring */
6773                 ring->wptr = 0;
6774                 *ring->wptr_cpu_addr = 0;
6775                 amdgpu_ring_clear_ring(ring);
6776         }
6777
6778         return 0;
6779 }
6780
6781 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6782 {
6783         int r, i;
6784         struct amdgpu_ring *ring;
6785
6786         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6787                 ring = &adev->gfx.gfx_ring[i];
6788
6789                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6790                 if (unlikely(r != 0))
6791                         return r;
6792
6793                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6794                 if (!r) {
6795                         r = gfx_v10_0_kgq_init_queue(ring, false);
6796                         amdgpu_bo_kunmap(ring->mqd_obj);
6797                         ring->mqd_ptr = NULL;
6798                 }
6799                 amdgpu_bo_unreserve(ring->mqd_obj);
6800                 if (r)
6801                         return r;
6802         }
6803
6804         r = amdgpu_gfx_enable_kgq(adev, 0);
6805         if (r)
6806                 return r;
6807
6808         return gfx_v10_0_cp_gfx_start(adev);
6809 }
6810
6811 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6812                                       struct amdgpu_mqd_prop *prop)
6813 {
6814         struct v10_compute_mqd *mqd = m;
6815         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6816         uint32_t tmp;
6817
6818         mqd->header = 0xC0310800;
6819         mqd->compute_pipelinestat_enable = 0x00000001;
6820         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6821         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6822         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6823         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6824         mqd->compute_misc_reserved = 0x00000003;
6825
6826         eop_base_addr = prop->eop_gpu_addr >> 8;
6827         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6828         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6829
6830         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6831         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6832         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6833                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6834
6835         mqd->cp_hqd_eop_control = tmp;
6836
6837         /* enable doorbell? */
6838         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6839
6840         if (prop->use_doorbell) {
6841                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6842                                     DOORBELL_OFFSET, prop->doorbell_index);
6843                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6844                                     DOORBELL_EN, 1);
6845                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6846                                     DOORBELL_SOURCE, 0);
6847                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6848                                     DOORBELL_HIT, 0);
6849         } else {
6850                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6851                                     DOORBELL_EN, 0);
6852         }
6853
6854         mqd->cp_hqd_pq_doorbell_control = tmp;
6855
6856         /* disable the queue if it's active */
6857         mqd->cp_hqd_dequeue_request = 0;
6858         mqd->cp_hqd_pq_rptr = 0;
6859         mqd->cp_hqd_pq_wptr_lo = 0;
6860         mqd->cp_hqd_pq_wptr_hi = 0;
6861
6862         /* set the pointer to the MQD */
6863         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6864         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6865
6866         /* set MQD vmid to 0 */
6867         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6868         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6869         mqd->cp_mqd_control = tmp;
6870
6871         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6872         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6873         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6874         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6875
6876         /* set up the HQD, this is similar to CP_RB0_CNTL */
6877         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6878         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6879                             (order_base_2(prop->queue_size / 4) - 1));
6880         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6881                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6882 #ifdef __BIG_ENDIAN
6883         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6884 #endif
6885         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
6886         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,
6887                             prop->allow_tunneling);
6888         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6889         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6890         mqd->cp_hqd_pq_control = tmp;
6891
6892         /* set the wb address whether it's enabled or not */
6893         wb_gpu_addr = prop->rptr_gpu_addr;
6894         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6895         mqd->cp_hqd_pq_rptr_report_addr_hi =
6896                 upper_32_bits(wb_gpu_addr) & 0xffff;
6897
6898         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6899         wb_gpu_addr = prop->wptr_gpu_addr;
6900         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6901         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6902
6903         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6904         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6905
6906         /* set the vmid for the queue */
6907         mqd->cp_hqd_vmid = 0;
6908
6909         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6910         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6911         mqd->cp_hqd_persistent_state = tmp;
6912
6913         /* set MIN_IB_AVAIL_SIZE */
6914         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6915         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6916         mqd->cp_hqd_ib_control = tmp;
6917
6918         /* set static priority for a compute queue/ring */
6919         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6920         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6921
6922         mqd->cp_hqd_active = prop->hqd_active;
6923
6924         return 0;
6925 }
6926
6927 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6928 {
6929         struct amdgpu_device *adev = ring->adev;
6930         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6931         int j;
6932
6933         /* inactivate the queue */
6934         if (amdgpu_sriov_vf(adev))
6935                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6936
6937         /* disable wptr polling */
6938         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6939
6940         /* disable the queue if it's active */
6941         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6942                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6943                 for (j = 0; j < adev->usec_timeout; j++) {
6944                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6945                                 break;
6946                         udelay(1);
6947                 }
6948                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6949                        mqd->cp_hqd_dequeue_request);
6950                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6951                        mqd->cp_hqd_pq_rptr);
6952                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6953                        mqd->cp_hqd_pq_wptr_lo);
6954                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6955                        mqd->cp_hqd_pq_wptr_hi);
6956         }
6957
6958         /* disable doorbells */
6959         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6960
6961         /* write the EOP addr */
6962         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6963                mqd->cp_hqd_eop_base_addr_lo);
6964         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6965                mqd->cp_hqd_eop_base_addr_hi);
6966
6967         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6968         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6969                mqd->cp_hqd_eop_control);
6970
6971         /* set the pointer to the MQD */
6972         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6973                mqd->cp_mqd_base_addr_lo);
6974         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6975                mqd->cp_mqd_base_addr_hi);
6976
6977         /* set MQD vmid to 0 */
6978         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6979                mqd->cp_mqd_control);
6980
6981         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6982         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6983                mqd->cp_hqd_pq_base_lo);
6984         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6985                mqd->cp_hqd_pq_base_hi);
6986
6987         /* set up the HQD, this is similar to CP_RB0_CNTL */
6988         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6989                mqd->cp_hqd_pq_control);
6990
6991         /* set the wb address whether it's enabled or not */
6992         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6993                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6994         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6995                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6996
6997         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6998         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6999                mqd->cp_hqd_pq_wptr_poll_addr_lo);
7000         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7001                mqd->cp_hqd_pq_wptr_poll_addr_hi);
7002
7003         /* enable the doorbell if requested */
7004         if (ring->use_doorbell) {
7005                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7006                         (adev->doorbell_index.kiq * 2) << 2);
7007                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7008                         (adev->doorbell_index.userqueue_end * 2) << 2);
7009         }
7010
7011         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7012                mqd->cp_hqd_pq_doorbell_control);
7013
7014         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7015         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7016                mqd->cp_hqd_pq_wptr_lo);
7017         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7018                mqd->cp_hqd_pq_wptr_hi);
7019
7020         /* set the vmid for the queue */
7021         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7022
7023         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7024                mqd->cp_hqd_persistent_state);
7025
7026         /* activate the queue */
7027         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7028                mqd->cp_hqd_active);
7029
7030         if (ring->use_doorbell)
7031                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7032
7033         return 0;
7034 }
7035
7036 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7037 {
7038         struct amdgpu_device *adev = ring->adev;
7039         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7040
7041         gfx_v10_0_kiq_setting(ring);
7042
7043         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7044                 /* reset MQD to a clean status */
7045                 if (adev->gfx.kiq[0].mqd_backup)
7046                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
7047
7048                 /* reset ring buffer */
7049                 ring->wptr = 0;
7050                 amdgpu_ring_clear_ring(ring);
7051
7052                 mutex_lock(&adev->srbm_mutex);
7053                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7054                 gfx_v10_0_kiq_init_register(ring);
7055                 nv_grbm_select(adev, 0, 0, 0, 0);
7056                 mutex_unlock(&adev->srbm_mutex);
7057         } else {
7058                 memset((void *)mqd, 0, sizeof(*mqd));
7059                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
7060                         amdgpu_ring_clear_ring(ring);
7061                 mutex_lock(&adev->srbm_mutex);
7062                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7063                 amdgpu_ring_init_mqd(ring);
7064                 gfx_v10_0_kiq_init_register(ring);
7065                 nv_grbm_select(adev, 0, 0, 0, 0);
7066                 mutex_unlock(&adev->srbm_mutex);
7067
7068                 if (adev->gfx.kiq[0].mqd_backup)
7069                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
7070         }
7071
7072         return 0;
7073 }
7074
7075 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore)
7076 {
7077         struct amdgpu_device *adev = ring->adev;
7078         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7079         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7080
7081         if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) {
7082                 memset((void *)mqd, 0, sizeof(*mqd));
7083                 mutex_lock(&adev->srbm_mutex);
7084                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7085                 amdgpu_ring_init_mqd(ring);
7086                 nv_grbm_select(adev, 0, 0, 0, 0);
7087                 mutex_unlock(&adev->srbm_mutex);
7088
7089                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7090                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7091         } else {
7092                 /* restore MQD to a clean status */
7093                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7094                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7095                 /* reset ring buffer */
7096                 ring->wptr = 0;
7097                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7098                 amdgpu_ring_clear_ring(ring);
7099         }
7100
7101         return 0;
7102 }
7103
7104 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7105 {
7106         struct amdgpu_ring *ring;
7107         int r;
7108
7109         ring = &adev->gfx.kiq[0].ring;
7110
7111         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7112         if (unlikely(r != 0))
7113                 return r;
7114
7115         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7116         if (unlikely(r != 0)) {
7117                 amdgpu_bo_unreserve(ring->mqd_obj);
7118                 return r;
7119         }
7120
7121         gfx_v10_0_kiq_init_queue(ring);
7122         amdgpu_bo_kunmap(ring->mqd_obj);
7123         ring->mqd_ptr = NULL;
7124         amdgpu_bo_unreserve(ring->mqd_obj);
7125         return 0;
7126 }
7127
7128 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7129 {
7130         struct amdgpu_ring *ring = NULL;
7131         int r = 0, i;
7132
7133         gfx_v10_0_cp_compute_enable(adev, true);
7134
7135         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7136                 ring = &adev->gfx.compute_ring[i];
7137
7138                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7139                 if (unlikely(r != 0))
7140                         goto done;
7141                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7142                 if (!r) {
7143                         r = gfx_v10_0_kcq_init_queue(ring, false);
7144                         amdgpu_bo_kunmap(ring->mqd_obj);
7145                         ring->mqd_ptr = NULL;
7146                 }
7147                 amdgpu_bo_unreserve(ring->mqd_obj);
7148                 if (r)
7149                         goto done;
7150         }
7151
7152         r = amdgpu_gfx_enable_kcq(adev, 0);
7153 done:
7154         return r;
7155 }
7156
7157 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7158 {
7159         int r, i;
7160         struct amdgpu_ring *ring;
7161
7162         if (!(adev->flags & AMD_IS_APU))
7163                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7164
7165         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7166                 /* legacy firmware loading */
7167                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7168                 if (r)
7169                         return r;
7170
7171                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7172                 if (r)
7173                         return r;
7174         }
7175
7176         r = gfx_v10_0_kiq_resume(adev);
7177         if (r)
7178                 return r;
7179
7180         r = gfx_v10_0_kcq_resume(adev);
7181         if (r)
7182                 return r;
7183
7184         if (!amdgpu_async_gfx_ring) {
7185                 r = gfx_v10_0_cp_gfx_resume(adev);
7186                 if (r)
7187                         return r;
7188         } else {
7189                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7190                 if (r)
7191                         return r;
7192         }
7193
7194         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7195                 ring = &adev->gfx.gfx_ring[i];
7196                 r = amdgpu_ring_test_helper(ring);
7197                 if (r)
7198                         return r;
7199         }
7200
7201         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7202                 ring = &adev->gfx.compute_ring[i];
7203                 r = amdgpu_ring_test_helper(ring);
7204                 if (r)
7205                         return r;
7206         }
7207
7208         return 0;
7209 }
7210
7211 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7212 {
7213         gfx_v10_0_cp_gfx_enable(adev, enable);
7214         gfx_v10_0_cp_compute_enable(adev, enable);
7215 }
7216
7217 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7218 {
7219         uint32_t data, pattern = 0xDEADBEEF;
7220
7221         /*
7222          * check if mmVGT_ESGS_RING_SIZE_UMD
7223          * has been remapped to mmVGT_ESGS_RING_SIZE
7224          */
7225         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7226         case IP_VERSION(10, 3, 0):
7227         case IP_VERSION(10, 3, 2):
7228         case IP_VERSION(10, 3, 4):
7229         case IP_VERSION(10, 3, 5):
7230                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7231                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7232                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7233
7234                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7235                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7236                         return true;
7237                 }
7238                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7239                 break;
7240         case IP_VERSION(10, 3, 1):
7241         case IP_VERSION(10, 3, 3):
7242         case IP_VERSION(10, 3, 6):
7243         case IP_VERSION(10, 3, 7):
7244                 return true;
7245         default:
7246                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7247                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7248                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7249
7250                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7251                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7252                         return true;
7253                 }
7254                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7255                 break;
7256         }
7257
7258         return false;
7259 }
7260
7261 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7262 {
7263         uint32_t data;
7264
7265         if (amdgpu_sriov_vf(adev))
7266                 return;
7267
7268         /*
7269          * Initialize cam_index to 0
7270          * index will auto-inc after each data writing
7271          */
7272         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7273
7274         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7275         case IP_VERSION(10, 3, 0):
7276         case IP_VERSION(10, 3, 2):
7277         case IP_VERSION(10, 3, 1):
7278         case IP_VERSION(10, 3, 4):
7279         case IP_VERSION(10, 3, 5):
7280         case IP_VERSION(10, 3, 6):
7281         case IP_VERSION(10, 3, 3):
7282         case IP_VERSION(10, 3, 7):
7283                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7284                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7285                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7286                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7287                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7288                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7289                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7290
7291                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7292                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7293                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7294                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7295                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7296                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7297                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7298
7299                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7300                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7301                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7302                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7303                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7304                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7305                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7306
7307                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7308                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7309                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7310                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7311                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7312                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7313                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7314
7315                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7316                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7317                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7318                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7319                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7320                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7321                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7322
7323                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7324                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7325                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7326                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7327                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7328                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7329                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7330
7331                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7332                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7333                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7334                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7335                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7336                 break;
7337         default:
7338                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7339                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7340                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7341                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7342                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7343                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7344                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7345
7346                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7347                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7348                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7349                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7350                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7351                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7352                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7353
7354                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7355                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7356                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7357                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7358                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7359                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7360                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7361
7362                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7363                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7364                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7365                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7366                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7367                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7368                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7369
7370                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7371                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7372                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7373                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7374                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7375                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7376                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7377
7378                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7379                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7380                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7381                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7382                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7383                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7384                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7385
7386                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7387                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7388                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7389                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7390                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7391                 break;
7392         }
7393
7394         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7395         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7396 }
7397
7398 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7399 {
7400         uint32_t data;
7401
7402         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7403         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7404         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7405
7406         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7407         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7408         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7409 }
7410
7411 static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
7412 {
7413         int r;
7414         struct amdgpu_device *adev = ip_block->adev;
7415
7416         if (!amdgpu_emu_mode)
7417                 gfx_v10_0_init_golden_registers(adev);
7418
7419         amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size,
7420                                        adev->gfx.cleaner_shader_ptr);
7421
7422         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7423                 /**
7424                  * For gfx 10, rlc firmware loading relies on smu firmware is
7425                  * loaded firstly, so in direct type, it has to load smc ucode
7426                  * here before rlc.
7427                  */
7428                 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7429                 if (r)
7430                         return r;
7431                 gfx_v10_0_disable_gpa_mode(adev);
7432         }
7433
7434         /* if GRBM CAM not remapped, set up the remapping */
7435         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7436                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7437
7438         gfx_v10_0_constants_init(adev);
7439
7440         r = gfx_v10_0_rlc_resume(adev);
7441         if (r)
7442                 return r;
7443
7444         /*
7445          * init golden registers and rlc resume may override some registers,
7446          * reconfig them here
7447          */
7448         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 10) ||
7449             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 1) ||
7450             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2))
7451                 gfx_v10_0_tcp_harvest(adev);
7452
7453         r = gfx_v10_0_cp_resume(adev);
7454         if (r)
7455                 return r;
7456
7457         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
7458                 gfx_v10_3_program_pbb_mode(adev);
7459
7460         if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 3, 0) && !amdgpu_sriov_vf(adev))
7461                 gfx_v10_3_set_power_brake_sequence(adev);
7462
7463         return r;
7464 }
7465
7466 static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
7467 {
7468         struct amdgpu_device *adev = ip_block->adev;
7469
7470         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7471         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7472         amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
7473
7474         /* WA added for Vangogh asic fixing the SMU suspend failure
7475          * It needs to set power gating again during gfxoff control
7476          * otherwise the gfxoff disallowing will be failed to set.
7477          */
7478         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
7479                 gfx_v10_0_set_powergating_state(ip_block, AMD_PG_STATE_UNGATE);
7480
7481         if (!adev->no_hw_access) {
7482                 if (amdgpu_async_gfx_ring) {
7483                         if (amdgpu_gfx_disable_kgq(adev, 0))
7484                                 DRM_ERROR("KGQ disable failed\n");
7485                 }
7486
7487                 if (amdgpu_gfx_disable_kcq(adev, 0))
7488                         DRM_ERROR("KCQ disable failed\n");
7489         }
7490
7491         if (amdgpu_sriov_vf(adev)) {
7492                 gfx_v10_0_cp_gfx_enable(adev, false);
7493                 /* Remove the steps of clearing KIQ position.
7494                  * It causes GFX hang when another Win guest is rendering.
7495                  */
7496                 return 0;
7497         }
7498         gfx_v10_0_cp_enable(adev, false);
7499         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7500
7501         return 0;
7502 }
7503
7504 static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block)
7505 {
7506         return gfx_v10_0_hw_fini(ip_block);
7507 }
7508
7509 static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
7510 {
7511         return gfx_v10_0_hw_init(ip_block);
7512 }
7513
7514 static bool gfx_v10_0_is_idle(void *handle)
7515 {
7516         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7517
7518         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7519                                 GRBM_STATUS, GUI_ACTIVE))
7520                 return false;
7521         else
7522                 return true;
7523 }
7524
7525 static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
7526 {
7527         unsigned int i;
7528         u32 tmp;
7529         struct amdgpu_device *adev = ip_block->adev;
7530
7531         for (i = 0; i < adev->usec_timeout; i++) {
7532                 /* read MC_STATUS */
7533                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7534                         GRBM_STATUS__GUI_ACTIVE_MASK;
7535
7536                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7537                         return 0;
7538                 udelay(1);
7539         }
7540         return -ETIMEDOUT;
7541 }
7542
7543 static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
7544 {
7545         u32 grbm_soft_reset = 0;
7546         u32 tmp;
7547         struct amdgpu_device *adev = ip_block->adev;
7548
7549         /* GRBM_STATUS */
7550         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7551         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7552                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7553                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7554                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7555                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7556                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7557                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7558                                                 1);
7559                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7560                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7561                                                 1);
7562         }
7563
7564         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7565                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7566                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7567                                                 1);
7568         }
7569
7570         /* GRBM_STATUS2 */
7571         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7572         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7573         case IP_VERSION(10, 3, 0):
7574         case IP_VERSION(10, 3, 2):
7575         case IP_VERSION(10, 3, 1):
7576         case IP_VERSION(10, 3, 4):
7577         case IP_VERSION(10, 3, 5):
7578         case IP_VERSION(10, 3, 6):
7579         case IP_VERSION(10, 3, 3):
7580                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7581                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7582                                                         GRBM_SOFT_RESET,
7583                                                         SOFT_RESET_RLC,
7584                                                         1);
7585                 break;
7586         default:
7587                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7588                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7589                                                         GRBM_SOFT_RESET,
7590                                                         SOFT_RESET_RLC,
7591                                                         1);
7592                 break;
7593         }
7594
7595         if (grbm_soft_reset) {
7596                 /* stop the rlc */
7597                 gfx_v10_0_rlc_stop(adev);
7598
7599                 /* Disable GFX parsing/prefetching */
7600                 gfx_v10_0_cp_gfx_enable(adev, false);
7601
7602                 /* Disable MEC parsing/prefetching */
7603                 gfx_v10_0_cp_compute_enable(adev, false);
7604
7605                 if (grbm_soft_reset) {
7606                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7607                         tmp |= grbm_soft_reset;
7608                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7609                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7610                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7611
7612                         udelay(50);
7613
7614                         tmp &= ~grbm_soft_reset;
7615                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7616                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7617                 }
7618
7619                 /* Wait a little for things to settle down */
7620                 udelay(50);
7621         }
7622         return 0;
7623 }
7624
7625 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7626 {
7627         uint64_t clock, clock_lo, clock_hi, hi_check;
7628
7629         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7630         case IP_VERSION(10, 1, 3):
7631         case IP_VERSION(10, 1, 4):
7632                 preempt_disable();
7633                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7634                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7635                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Cyan_Skillfish);
7636                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7637                  * roughly every 42 seconds.
7638                  */
7639                 if (hi_check != clock_hi) {
7640                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Cyan_Skillfish);
7641                         clock_hi = hi_check;
7642                 }
7643                 preempt_enable();
7644                 clock = clock_lo | (clock_hi << 32ULL);
7645                 break;
7646         case IP_VERSION(10, 3, 1):
7647         case IP_VERSION(10, 3, 3):
7648         case IP_VERSION(10, 3, 7):
7649                 preempt_disable();
7650                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7651                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7652                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7653                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7654                  * roughly every 42 seconds.
7655                  */
7656                 if (hi_check != clock_hi) {
7657                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7658                         clock_hi = hi_check;
7659                 }
7660                 preempt_enable();
7661                 clock = clock_lo | (clock_hi << 32ULL);
7662                 break;
7663         case IP_VERSION(10, 3, 6):
7664                 preempt_disable();
7665                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7666                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7667                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7668                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7669                  * roughly every 42 seconds.
7670                  */
7671                 if (hi_check != clock_hi) {
7672                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7673                         clock_hi = hi_check;
7674                 }
7675                 preempt_enable();
7676                 clock = clock_lo | (clock_hi << 32ULL);
7677                 break;
7678         default:
7679                 preempt_disable();
7680                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7681                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7682                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7683                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7684                  * roughly every 42 seconds.
7685                  */
7686                 if (hi_check != clock_hi) {
7687                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7688                         clock_hi = hi_check;
7689                 }
7690                 preempt_enable();
7691                 clock = clock_lo | (clock_hi << 32ULL);
7692                 break;
7693         }
7694         return clock;
7695 }
7696
7697 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7698                                            uint32_t vmid,
7699                                            uint32_t gds_base, uint32_t gds_size,
7700                                            uint32_t gws_base, uint32_t gws_size,
7701                                            uint32_t oa_base, uint32_t oa_size)
7702 {
7703         struct amdgpu_device *adev = ring->adev;
7704
7705         /* GDS Base */
7706         gfx_v10_0_write_data_to_reg(ring, 0, false,
7707                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7708                                     gds_base);
7709
7710         /* GDS Size */
7711         gfx_v10_0_write_data_to_reg(ring, 0, false,
7712                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7713                                     gds_size);
7714
7715         /* GWS */
7716         gfx_v10_0_write_data_to_reg(ring, 0, false,
7717                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7718                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7719
7720         /* OA */
7721         gfx_v10_0_write_data_to_reg(ring, 0, false,
7722                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7723                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7724 }
7725
7726 static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block)
7727 {
7728         struct amdgpu_device *adev = ip_block->adev;
7729
7730         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7731
7732         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7733         case IP_VERSION(10, 1, 10):
7734         case IP_VERSION(10, 1, 1):
7735         case IP_VERSION(10, 1, 2):
7736         case IP_VERSION(10, 1, 3):
7737         case IP_VERSION(10, 1, 4):
7738                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7739                 break;
7740         case IP_VERSION(10, 3, 0):
7741         case IP_VERSION(10, 3, 2):
7742         case IP_VERSION(10, 3, 1):
7743         case IP_VERSION(10, 3, 4):
7744         case IP_VERSION(10, 3, 5):
7745         case IP_VERSION(10, 3, 6):
7746         case IP_VERSION(10, 3, 3):
7747         case IP_VERSION(10, 3, 7):
7748                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7749                 break;
7750         default:
7751                 break;
7752         }
7753
7754         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7755                                           AMDGPU_MAX_COMPUTE_RINGS);
7756
7757         gfx_v10_0_set_kiq_pm4_funcs(adev);
7758         gfx_v10_0_set_ring_funcs(adev);
7759         gfx_v10_0_set_irq_funcs(adev);
7760         gfx_v10_0_set_gds_init(adev);
7761         gfx_v10_0_set_rlc_funcs(adev);
7762         gfx_v10_0_set_mqd_funcs(adev);
7763
7764         /* init rlcg reg access ctrl */
7765         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7766
7767         return gfx_v10_0_init_microcode(adev);
7768 }
7769
7770 static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block)
7771 {
7772         struct amdgpu_device *adev = ip_block->adev;
7773         int r;
7774
7775         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7776         if (r)
7777                 return r;
7778
7779         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7780         if (r)
7781                 return r;
7782
7783         r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0);
7784         if (r)
7785                 return r;
7786
7787         return 0;
7788 }
7789
7790 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7791 {
7792         uint32_t rlc_cntl;
7793
7794         /* if RLC is not enabled, do nothing */
7795         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7796         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7797 }
7798
7799 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
7800 {
7801         uint32_t data;
7802         unsigned int i;
7803
7804         data = RLC_SAFE_MODE__CMD_MASK;
7805         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7806
7807         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7808         case IP_VERSION(10, 3, 0):
7809         case IP_VERSION(10, 3, 2):
7810         case IP_VERSION(10, 3, 1):
7811         case IP_VERSION(10, 3, 4):
7812         case IP_VERSION(10, 3, 5):
7813         case IP_VERSION(10, 3, 6):
7814         case IP_VERSION(10, 3, 3):
7815         case IP_VERSION(10, 3, 7):
7816                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7817
7818                 /* wait for RLC_SAFE_MODE */
7819                 for (i = 0; i < adev->usec_timeout; i++) {
7820                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7821                                            RLC_SAFE_MODE, CMD))
7822                                 break;
7823                         udelay(1);
7824                 }
7825                 break;
7826         default:
7827                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7828
7829                 /* wait for RLC_SAFE_MODE */
7830                 for (i = 0; i < adev->usec_timeout; i++) {
7831                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7832                                            RLC_SAFE_MODE, CMD))
7833                                 break;
7834                         udelay(1);
7835                 }
7836                 break;
7837         }
7838 }
7839
7840 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
7841 {
7842         uint32_t data;
7843
7844         data = RLC_SAFE_MODE__CMD_MASK;
7845         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
7846         case IP_VERSION(10, 3, 0):
7847         case IP_VERSION(10, 3, 2):
7848         case IP_VERSION(10, 3, 1):
7849         case IP_VERSION(10, 3, 4):
7850         case IP_VERSION(10, 3, 5):
7851         case IP_VERSION(10, 3, 6):
7852         case IP_VERSION(10, 3, 3):
7853         case IP_VERSION(10, 3, 7):
7854                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7855                 break;
7856         default:
7857                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7858                 break;
7859         }
7860 }
7861
7862 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7863                                                       bool enable)
7864 {
7865         uint32_t data, def;
7866
7867         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7868                 return;
7869
7870         /* It is disabled by HW by default */
7871         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7872                 /* 0 - Disable some blocks' MGCG */
7873                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7874                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7875                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7876                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7877
7878                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7879                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7880                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7881                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7882                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7883                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7884                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7885                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7886
7887                 if (def != data)
7888                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7889
7890                 /* MGLS is a global flag to control all MGLS in GFX */
7891                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7892                         /* 2 - RLC memory Light sleep */
7893                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7894                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7895                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7896                                 if (def != data)
7897                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7898                         }
7899                         /* 3 - CP memory Light sleep */
7900                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7901                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7902                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7903                                 if (def != data)
7904                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7905                         }
7906                 }
7907         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7908                 /* 1 - MGCG_OVERRIDE */
7909                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7910                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7911                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7912                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7913                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7914                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7915                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7916                 if (def != data)
7917                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7918
7919                 /* 2 - disable MGLS in CP */
7920                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7921                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7922                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7923                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7924                 }
7925
7926                 /* 3 - disable MGLS in RLC */
7927                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7928                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7929                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7930                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7931                 }
7932
7933         }
7934 }
7935
7936 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7937                                            bool enable)
7938 {
7939         uint32_t data, def;
7940
7941         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7942                 return;
7943
7944         /* Enable 3D CGCG/CGLS */
7945         if (enable) {
7946                 /* write cmd to clear cgcg/cgls ov */
7947                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7948
7949                 /* unset CGCG override */
7950                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7951                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7952
7953                 /* update CGCG and CGLS override bits */
7954                 if (def != data)
7955                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7956
7957                 /* enable 3Dcgcg FSM(0x0000363f) */
7958                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7959                 data = 0;
7960
7961                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7962                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7963                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7964
7965                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7966                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7967                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7968
7969                 if (def != data)
7970                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7971
7972                 /* set IDLE_POLL_COUNT(0x00900100) */
7973                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7974                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7975                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7976                 if (def != data)
7977                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7978         } else {
7979                 /* Disable CGCG/CGLS */
7980                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7981
7982                 /* disable cgcg, cgls should be disabled */
7983                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7984                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7985
7986                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7987                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7988
7989                 /* disable cgcg and cgls in FSM */
7990                 if (def != data)
7991                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7992         }
7993 }
7994
7995 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7996                                                       bool enable)
7997 {
7998         uint32_t def, data;
7999
8000         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8001                 return;
8002
8003         if (enable) {
8004                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8005
8006                 /* unset CGCG override */
8007                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8008                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8009
8010                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8011                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8012
8013                 /* update CGCG and CGLS override bits */
8014                 if (def != data)
8015                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8016
8017                 /* enable cgcg FSM(0x0000363F) */
8018                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8019                 data = 0;
8020
8021                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8022                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8023                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8024
8025                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8026                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8027                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8028
8029                 if (def != data)
8030                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8031
8032                 /* set IDLE_POLL_COUNT(0x00900100) */
8033                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8034                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8035                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8036                 if (def != data)
8037                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8038         } else {
8039                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8040
8041                 /* reset CGCG/CGLS bits */
8042                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8043                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8044
8045                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8046                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8047
8048                 /* disable cgcg and cgls in FSM */
8049                 if (def != data)
8050                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8051         }
8052 }
8053
8054 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8055                                                       bool enable)
8056 {
8057         uint32_t def, data;
8058
8059         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8060                 return;
8061
8062         if (enable) {
8063                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8064                 /* unset FGCG override */
8065                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8066                 /* update FGCG override bits */
8067                 if (def != data)
8068                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8069
8070                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8071                 /* unset RLC SRAM CLK GATER override */
8072                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8073                 /* update RLC SRAM CLK GATER override bits */
8074                 if (def != data)
8075                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8076         } else {
8077                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8078                 /* reset FGCG bits */
8079                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8080                 /* disable FGCG*/
8081                 if (def != data)
8082                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8083
8084                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8085                 /* reset RLC SRAM CLK GATER bits */
8086                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8087                 /* disable RLC SRAM CLK*/
8088                 if (def != data)
8089                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8090         }
8091 }
8092
8093 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8094 {
8095         uint32_t reg_data = 0;
8096         uint32_t reg_idx = 0;
8097         uint32_t i;
8098
8099         const uint32_t tcp_ctrl_regs[] = {
8100                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8101                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8102                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8103                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8104                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8105                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8106                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8107                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8108                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8109                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8110                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8111                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8112                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8113                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8114                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8115                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8116                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8117                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8118                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8119                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8120                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8121                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8122                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8123                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8124         };
8125
8126         const uint32_t tcp_ctrl_regs_nv12[] = {
8127                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8128                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8129                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8130                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8131                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8132                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8133                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8134                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8135                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8136                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8137                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8138                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8139                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8140                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8141                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8142                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8143                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8144                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8145                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8146                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8147         };
8148
8149         const uint32_t sm_ctlr_regs[] = {
8150                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8151                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8152                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8153                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8154         };
8155
8156         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 2)) {
8157                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8158                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8159                                   tcp_ctrl_regs_nv12[i];
8160                         reg_data = RREG32(reg_idx);
8161                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8162                         WREG32(reg_idx, reg_data);
8163                 }
8164         } else {
8165                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8166                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8167                                   tcp_ctrl_regs[i];
8168                         reg_data = RREG32(reg_idx);
8169                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8170                         WREG32(reg_idx, reg_data);
8171                 }
8172         }
8173
8174         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8175                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8176                           sm_ctlr_regs[i];
8177                 reg_data = RREG32(reg_idx);
8178                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8179                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8180                 WREG32(reg_idx, reg_data);
8181         }
8182 }
8183
8184 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8185                                             bool enable)
8186 {
8187         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8188
8189         if (enable) {
8190                 /* enable FGCG firstly*/
8191                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8192                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8193                  * ===  MGCG + MGLS ===
8194                  */
8195                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8196                 /* ===  CGCG /CGLS for GFX 3D Only === */
8197                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8198                 /* ===  CGCG + CGLS === */
8199                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8200
8201                 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
8202                      IP_VERSION(10, 1, 10)) ||
8203                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8204                      IP_VERSION(10, 1, 1)) ||
8205                     (amdgpu_ip_version(adev, GC_HWIP, 0) ==
8206                      IP_VERSION(10, 1, 2)))
8207                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8208         } else {
8209                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8210                  * ===  CGCG + CGLS ===
8211                  */
8212                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8213                 /* ===  CGCG /CGLS for GFX 3D Only === */
8214                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8215                 /* ===  MGCG + MGLS === */
8216                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8217                 /* disable fgcg at last*/
8218                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8219         }
8220
8221         if (adev->cg_flags &
8222             (AMD_CG_SUPPORT_GFX_MGCG |
8223              AMD_CG_SUPPORT_GFX_CGLS |
8224              AMD_CG_SUPPORT_GFX_CGCG |
8225              AMD_CG_SUPPORT_GFX_3D_CGCG |
8226              AMD_CG_SUPPORT_GFX_3D_CGLS))
8227                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8228
8229         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8230
8231         return 0;
8232 }
8233
8234 static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
8235                                                unsigned int vmid)
8236 {
8237         u32 reg, pre_data, data;
8238
8239         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8240         /* not for *_SOC15 */
8241         if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
8242                 pre_data = RREG32_NO_KIQ(reg);
8243         else
8244                 pre_data = RREG32(reg);
8245
8246         data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
8247         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8248
8249         if (pre_data != data) {
8250                 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
8251                         WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8252                 } else
8253                         WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8254         }
8255 }
8256
8257 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid)
8258 {
8259         amdgpu_gfx_off_ctrl(adev, false);
8260
8261         gfx_v10_0_update_spm_vmid_internal(adev, vmid);
8262
8263         amdgpu_gfx_off_ctrl(adev, true);
8264 }
8265
8266 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8267                                         uint32_t offset,
8268                                         struct soc15_reg_rlcg *entries, int arr_size)
8269 {
8270         int i;
8271         uint32_t reg;
8272
8273         if (!entries)
8274                 return false;
8275
8276         for (i = 0; i < arr_size; i++) {
8277                 const struct soc15_reg_rlcg *entry;
8278
8279                 entry = &entries[i];
8280                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8281                 if (offset == reg)
8282                         return true;
8283         }
8284
8285         return false;
8286 }
8287
8288 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8289 {
8290         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8291 }
8292
8293 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8294 {
8295         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8296
8297         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8298                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8299         else
8300                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8301
8302         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8303
8304         /*
8305          * CGPG enablement required and the register to program the hysteresis value
8306          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8307          * in refclk count. Note that RLC FW is modified to take 16 bits from
8308          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8309          *
8310          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8311          * of CGPG enablement starting point.
8312          * Power/performance team will optimize it and might give a new value later.
8313          */
8314         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8315                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8316                 case IP_VERSION(10, 3, 1):
8317                 case IP_VERSION(10, 3, 3):
8318                 case IP_VERSION(10, 3, 6):
8319                 case IP_VERSION(10, 3, 7):
8320                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8321                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8322                         break;
8323                 default:
8324                         break;
8325                 }
8326         }
8327 }
8328
8329 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8330 {
8331         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8332
8333         gfx_v10_cntl_power_gating(adev, enable);
8334
8335         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
8336 }
8337
8338 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8339         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8340         .set_safe_mode = gfx_v10_0_set_safe_mode,
8341         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8342         .init = gfx_v10_0_rlc_init,
8343         .get_csb_size = gfx_v10_0_get_csb_size,
8344         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8345         .resume = gfx_v10_0_rlc_resume,
8346         .stop = gfx_v10_0_rlc_stop,
8347         .reset = gfx_v10_0_rlc_reset,
8348         .start = gfx_v10_0_rlc_start,
8349         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8350 };
8351
8352 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8353         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8354         .set_safe_mode = gfx_v10_0_set_safe_mode,
8355         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8356         .init = gfx_v10_0_rlc_init,
8357         .get_csb_size = gfx_v10_0_get_csb_size,
8358         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8359         .resume = gfx_v10_0_rlc_resume,
8360         .stop = gfx_v10_0_rlc_stop,
8361         .reset = gfx_v10_0_rlc_reset,
8362         .start = gfx_v10_0_rlc_start,
8363         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8364         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8365 };
8366
8367 static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
8368                                           enum amd_powergating_state state)
8369 {
8370         struct amdgpu_device *adev = ip_block->adev;
8371         bool enable = (state == AMD_PG_STATE_GATE);
8372
8373         if (amdgpu_sriov_vf(adev))
8374                 return 0;
8375
8376         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8377         case IP_VERSION(10, 1, 10):
8378         case IP_VERSION(10, 1, 1):
8379         case IP_VERSION(10, 1, 2):
8380         case IP_VERSION(10, 3, 0):
8381         case IP_VERSION(10, 3, 2):
8382         case IP_VERSION(10, 3, 4):
8383         case IP_VERSION(10, 3, 5):
8384                 amdgpu_gfx_off_ctrl(adev, enable);
8385                 break;
8386         case IP_VERSION(10, 3, 1):
8387         case IP_VERSION(10, 3, 3):
8388         case IP_VERSION(10, 3, 6):
8389         case IP_VERSION(10, 3, 7):
8390                 if (!enable)
8391                         amdgpu_gfx_off_ctrl(adev, false);
8392
8393                 gfx_v10_cntl_pg(adev, enable);
8394
8395                 if (enable)
8396                         amdgpu_gfx_off_ctrl(adev, true);
8397
8398                 break;
8399         default:
8400                 break;
8401         }
8402         return 0;
8403 }
8404
8405 static int gfx_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
8406                                           enum amd_clockgating_state state)
8407 {
8408         struct amdgpu_device *adev = ip_block->adev;
8409
8410         if (amdgpu_sriov_vf(adev))
8411                 return 0;
8412
8413         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
8414         case IP_VERSION(10, 1, 10):
8415         case IP_VERSION(10, 1, 1):
8416         case IP_VERSION(10, 1, 2):
8417         case IP_VERSION(10, 3, 0):
8418         case IP_VERSION(10, 3, 2):
8419         case IP_VERSION(10, 3, 1):
8420         case IP_VERSION(10, 3, 4):
8421         case IP_VERSION(10, 3, 5):
8422         case IP_VERSION(10, 3, 6):
8423         case IP_VERSION(10, 3, 3):
8424         case IP_VERSION(10, 3, 7):
8425                 gfx_v10_0_update_gfx_clock_gating(adev,
8426                                                  state == AMD_CG_STATE_GATE);
8427                 break;
8428         default:
8429                 break;
8430         }
8431         return 0;
8432 }
8433
8434 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8435 {
8436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8437         int data;
8438
8439         /* AMD_CG_SUPPORT_GFX_FGCG */
8440         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8441         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8442                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8443
8444         /* AMD_CG_SUPPORT_GFX_MGCG */
8445         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8446         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8447                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8448
8449         /* AMD_CG_SUPPORT_GFX_CGCG */
8450         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8451         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8452                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8453
8454         /* AMD_CG_SUPPORT_GFX_CGLS */
8455         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8456                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8457
8458         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8459         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8460         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8461                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8462
8463         /* AMD_CG_SUPPORT_GFX_CP_LS */
8464         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8465         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8466                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8467
8468         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8469         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8470         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8471                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8472
8473         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8474         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8475                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8476 }
8477
8478 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8479 {
8480         /* gfx10 is 32bit rptr*/
8481         return *(uint32_t *)ring->rptr_cpu_addr;
8482 }
8483
8484 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8485 {
8486         struct amdgpu_device *adev = ring->adev;
8487         u64 wptr;
8488
8489         /* XXX check if swapping is necessary on BE */
8490         if (ring->use_doorbell) {
8491                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8492         } else {
8493                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8494                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8495         }
8496
8497         return wptr;
8498 }
8499
8500 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8501 {
8502         struct amdgpu_device *adev = ring->adev;
8503
8504         if (ring->use_doorbell) {
8505                 /* XXX check if swapping is necessary on BE */
8506                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8507                              ring->wptr);
8508                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8509         } else {
8510                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8511                              lower_32_bits(ring->wptr));
8512                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8513                              upper_32_bits(ring->wptr));
8514         }
8515 }
8516
8517 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8518 {
8519         /* gfx10 hardware is 32bit rptr */
8520         return *(uint32_t *)ring->rptr_cpu_addr;
8521 }
8522
8523 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8524 {
8525         u64 wptr;
8526
8527         /* XXX check if swapping is necessary on BE */
8528         if (ring->use_doorbell)
8529                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8530         else
8531                 BUG();
8532         return wptr;
8533 }
8534
8535 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8536 {
8537         struct amdgpu_device *adev = ring->adev;
8538
8539         if (ring->use_doorbell) {
8540                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8541                              ring->wptr);
8542                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8543         } else {
8544                 BUG(); /* only DOORBELL method supported on gfx10 now */
8545         }
8546 }
8547
8548 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8549 {
8550         struct amdgpu_device *adev = ring->adev;
8551         u32 ref_and_mask, reg_mem_engine;
8552         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8553
8554         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8555                 switch (ring->me) {
8556                 case 1:
8557                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8558                         break;
8559                 case 2:
8560                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8561                         break;
8562                 default:
8563                         return;
8564                 }
8565                 reg_mem_engine = 0;
8566         } else {
8567                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe;
8568                 reg_mem_engine = 1; /* pfp */
8569         }
8570
8571         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8572                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8573                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8574                                ref_and_mask, ref_and_mask, 0x20);
8575 }
8576
8577 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8578                                        struct amdgpu_job *job,
8579                                        struct amdgpu_ib *ib,
8580                                        uint32_t flags)
8581 {
8582         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8583         u32 header, control = 0;
8584
8585         if (ib->flags & AMDGPU_IB_FLAG_CE)
8586                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8587         else
8588                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8589
8590         control |= ib->length_dw | (vmid << 24);
8591
8592         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8593                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8594
8595                 if (flags & AMDGPU_IB_PREEMPTED)
8596                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8597
8598                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8599                         gfx_v10_0_ring_emit_de_meta(ring,
8600                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8601         }
8602
8603         amdgpu_ring_write(ring, header);
8604         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8605         amdgpu_ring_write(ring,
8606 #ifdef __BIG_ENDIAN
8607                 (2 << 0) |
8608 #endif
8609                 lower_32_bits(ib->gpu_addr));
8610         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8611         amdgpu_ring_write(ring, control);
8612 }
8613
8614 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8615                                            struct amdgpu_job *job,
8616                                            struct amdgpu_ib *ib,
8617                                            uint32_t flags)
8618 {
8619         unsigned int vmid = AMDGPU_JOB_GET_VMID(job);
8620         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8621
8622         /* Currently, there is a high possibility to get wave ID mismatch
8623          * between ME and GDS, leading to a hw deadlock, because ME generates
8624          * different wave IDs than the GDS expects. This situation happens
8625          * randomly when at least 5 compute pipes use GDS ordered append.
8626          * The wave IDs generated by ME are also wrong after suspend/resume.
8627          * Those are probably bugs somewhere else in the kernel driver.
8628          *
8629          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8630          * GDS to 0 for this ring (me/pipe).
8631          */
8632         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8633                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8634                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8635                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8636         }
8637
8638         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8639         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8640         amdgpu_ring_write(ring,
8641 #ifdef __BIG_ENDIAN
8642                                 (2 << 0) |
8643 #endif
8644                                 lower_32_bits(ib->gpu_addr));
8645         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8646         amdgpu_ring_write(ring, control);
8647 }
8648
8649 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8650                                      u64 seq, unsigned int flags)
8651 {
8652         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8653         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8654
8655         /* RELEASE_MEM - flush caches, send int */
8656         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8657         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8658                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8659                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8660                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8661                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8662                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8663                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8664         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8665                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8666
8667         /*
8668          * the address should be Qword aligned if 64bit write, Dword
8669          * aligned if only send 32bit data low (discard data high)
8670          */
8671         if (write64bit)
8672                 BUG_ON(addr & 0x7);
8673         else
8674                 BUG_ON(addr & 0x3);
8675         amdgpu_ring_write(ring, lower_32_bits(addr));
8676         amdgpu_ring_write(ring, upper_32_bits(addr));
8677         amdgpu_ring_write(ring, lower_32_bits(seq));
8678         amdgpu_ring_write(ring, upper_32_bits(seq));
8679         amdgpu_ring_write(ring, 0);
8680 }
8681
8682 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8683 {
8684         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8685         uint32_t seq = ring->fence_drv.sync_seq;
8686         uint64_t addr = ring->fence_drv.gpu_addr;
8687
8688         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8689                                upper_32_bits(addr), seq, 0xffffffff, 4);
8690 }
8691
8692 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8693                                    uint16_t pasid, uint32_t flush_type,
8694                                    bool all_hub, uint8_t dst_sel)
8695 {
8696         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8697         amdgpu_ring_write(ring,
8698                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8699                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8700                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8701                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8702 }
8703
8704 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8705                                          unsigned int vmid, uint64_t pd_addr)
8706 {
8707         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8708
8709         /* compute doesn't have PFP */
8710         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8711                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8712                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8713                 amdgpu_ring_write(ring, 0x0);
8714         }
8715 }
8716
8717 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8718                                           u64 seq, unsigned int flags)
8719 {
8720         struct amdgpu_device *adev = ring->adev;
8721
8722         /* we only allocate 32bit for each seq wb address */
8723         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8724
8725         /* write fence seq to the "addr" */
8726         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8727         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8728                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8729         amdgpu_ring_write(ring, lower_32_bits(addr));
8730         amdgpu_ring_write(ring, upper_32_bits(addr));
8731         amdgpu_ring_write(ring, lower_32_bits(seq));
8732
8733         if (flags & AMDGPU_FENCE_FLAG_INT) {
8734                 /* set register to trigger INT */
8735                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8736                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8737                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8738                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8739                 amdgpu_ring_write(ring, 0);
8740                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8741         }
8742 }
8743
8744 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8745 {
8746         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8747         amdgpu_ring_write(ring, 0);
8748 }
8749
8750 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8751                                          uint32_t flags)
8752 {
8753         uint32_t dw2 = 0;
8754
8755         if (ring->adev->gfx.mcbp)
8756                 gfx_v10_0_ring_emit_ce_meta(ring,
8757                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8758
8759         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8760         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8761                 /* set load_global_config & load_global_uconfig */
8762                 dw2 |= 0x8001;
8763                 /* set load_cs_sh_regs */
8764                 dw2 |= 0x01000000;
8765                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8766                 dw2 |= 0x10002;
8767
8768                 /* set load_ce_ram if preamble presented */
8769                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8770                         dw2 |= 0x10000000;
8771         } else {
8772                 /* still load_ce_ram if this is the first time preamble presented
8773                  * although there is no context switch happens.
8774                  */
8775                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8776                         dw2 |= 0x10000000;
8777         }
8778
8779         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8780         amdgpu_ring_write(ring, dw2);
8781         amdgpu_ring_write(ring, 0);
8782 }
8783
8784 static unsigned int gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring,
8785                                                        uint64_t addr)
8786 {
8787         unsigned int ret;
8788
8789         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8790         amdgpu_ring_write(ring, lower_32_bits(addr));
8791         amdgpu_ring_write(ring, upper_32_bits(addr));
8792         /* discard following DWs if *cond_exec_gpu_addr==0 */
8793         amdgpu_ring_write(ring, 0);
8794         ret = ring->wptr & ring->buf_mask;
8795         /* patch dummy value later */
8796         amdgpu_ring_write(ring, 0);
8797
8798         return ret;
8799 }
8800
8801 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8802 {
8803         int i, r = 0;
8804         struct amdgpu_device *adev = ring->adev;
8805         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8806         struct amdgpu_ring *kiq_ring = &kiq->ring;
8807         unsigned long flags;
8808
8809         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8810                 return -EINVAL;
8811
8812         spin_lock_irqsave(&kiq->ring_lock, flags);
8813
8814         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8815                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8816                 return -ENOMEM;
8817         }
8818
8819         /* assert preemption condition */
8820         amdgpu_ring_set_preempt_cond_exec(ring, false);
8821
8822         /* assert IB preemption, emit the trailing fence */
8823         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8824                                    ring->trail_fence_gpu_addr,
8825                                    ++ring->trail_seq);
8826         amdgpu_ring_commit(kiq_ring);
8827
8828         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8829
8830         /* poll the trailing fence */
8831         for (i = 0; i < adev->usec_timeout; i++) {
8832                 if (ring->trail_seq ==
8833                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8834                         break;
8835                 udelay(1);
8836         }
8837
8838         if (i >= adev->usec_timeout) {
8839                 r = -EINVAL;
8840                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8841         }
8842
8843         /* deassert preemption condition */
8844         amdgpu_ring_set_preempt_cond_exec(ring, true);
8845         return r;
8846 }
8847
8848 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8849 {
8850         struct amdgpu_device *adev = ring->adev;
8851         struct v10_ce_ib_state ce_payload = {0};
8852         uint64_t offset, ce_payload_gpu_addr;
8853         void *ce_payload_cpu_addr;
8854         int cnt;
8855
8856         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8857
8858         offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8859         ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8860         ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8861
8862         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8863         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8864                                  WRITE_DATA_DST_SEL(8) |
8865                                  WR_CONFIRM) |
8866                                  WRITE_DATA_CACHE_POLICY(0));
8867         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8868         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8869
8870         if (resume)
8871                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8872                                            sizeof(ce_payload) >> 2);
8873         else
8874                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8875                                            sizeof(ce_payload) >> 2);
8876 }
8877
8878 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8879 {
8880         struct amdgpu_device *adev = ring->adev;
8881         struct v10_de_ib_state de_payload = {0};
8882         uint64_t offset, gds_addr, de_payload_gpu_addr;
8883         void *de_payload_cpu_addr;
8884         int cnt;
8885
8886         offset = offsetof(struct v10_gfx_meta_data, de_payload);
8887         de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8888         de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8889
8890         gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8891                          AMDGPU_CSA_SIZE - adev->gds.gds_size,
8892                          PAGE_SIZE);
8893
8894         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8895         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8896
8897         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8898         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8899         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8900                                  WRITE_DATA_DST_SEL(8) |
8901                                  WR_CONFIRM) |
8902                                  WRITE_DATA_CACHE_POLICY(0));
8903         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8904         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8905
8906         if (resume)
8907                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8908                                            sizeof(de_payload) >> 2);
8909         else
8910                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8911                                            sizeof(de_payload) >> 2);
8912 }
8913
8914 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8915                                     bool secure)
8916 {
8917         uint32_t v = secure ? FRAME_TMZ : 0;
8918
8919         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8920         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8921 }
8922
8923 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8924                                      uint32_t reg_val_offs)
8925 {
8926         struct amdgpu_device *adev = ring->adev;
8927
8928         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8929         amdgpu_ring_write(ring, 0 |     /* src: register*/
8930                                 (5 << 8) |      /* dst: memory */
8931                                 (1 << 20));     /* write confirm */
8932         amdgpu_ring_write(ring, reg);
8933         amdgpu_ring_write(ring, 0);
8934         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8935                                 reg_val_offs * 4));
8936         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8937                                 reg_val_offs * 4));
8938 }
8939
8940 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8941                                    uint32_t val)
8942 {
8943         uint32_t cmd = 0;
8944
8945         switch (ring->funcs->type) {
8946         case AMDGPU_RING_TYPE_GFX:
8947                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8948                 break;
8949         case AMDGPU_RING_TYPE_KIQ:
8950                 cmd = (1 << 16); /* no inc addr */
8951                 break;
8952         default:
8953                 cmd = WR_CONFIRM;
8954                 break;
8955         }
8956         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8957         amdgpu_ring_write(ring, cmd);
8958         amdgpu_ring_write(ring, reg);
8959         amdgpu_ring_write(ring, 0);
8960         amdgpu_ring_write(ring, val);
8961 }
8962
8963 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8964                                         uint32_t val, uint32_t mask)
8965 {
8966         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8967 }
8968
8969 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8970                                                    uint32_t reg0, uint32_t reg1,
8971                                                    uint32_t ref, uint32_t mask)
8972 {
8973         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8974         struct amdgpu_device *adev = ring->adev;
8975         bool fw_version_ok = false;
8976
8977         fw_version_ok = adev->gfx.cp_fw_write_wait;
8978
8979         if (fw_version_ok)
8980                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8981                                        ref, mask, 0x20);
8982         else
8983                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8984                                                            ref, mask);
8985 }
8986
8987 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8988                                          unsigned int vmid)
8989 {
8990         struct amdgpu_device *adev = ring->adev;
8991         uint32_t value = 0;
8992
8993         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8994         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8995         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8996         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8997         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
8998         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8999         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9000 }
9001
9002 static void
9003 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9004                                       uint32_t me, uint32_t pipe,
9005                                       enum amdgpu_interrupt_state state)
9006 {
9007         uint32_t cp_int_cntl, cp_int_cntl_reg;
9008
9009         if (!me) {
9010                 switch (pipe) {
9011                 case 0:
9012                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9013                         break;
9014                 case 1:
9015                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9016                         break;
9017                 default:
9018                         DRM_DEBUG("invalid pipe %d\n", pipe);
9019                         return;
9020                 }
9021         } else {
9022                 DRM_DEBUG("invalid me %d\n", me);
9023                 return;
9024         }
9025
9026         switch (state) {
9027         case AMDGPU_IRQ_STATE_DISABLE:
9028                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9029                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9030                                             TIME_STAMP_INT_ENABLE, 0);
9031                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9032                 break;
9033         case AMDGPU_IRQ_STATE_ENABLE:
9034                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9035                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9036                                             TIME_STAMP_INT_ENABLE, 1);
9037                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9038                 break;
9039         default:
9040                 break;
9041         }
9042 }
9043
9044 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9045                                                      int me, int pipe,
9046                                                      enum amdgpu_interrupt_state state)
9047 {
9048         u32 mec_int_cntl, mec_int_cntl_reg;
9049
9050         /*
9051          * amdgpu controls only the first MEC. That's why this function only
9052          * handles the setting of interrupts for this specific MEC. All other
9053          * pipes' interrupts are set by amdkfd.
9054          */
9055
9056         if (me == 1) {
9057                 switch (pipe) {
9058                 case 0:
9059                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9060                         break;
9061                 case 1:
9062                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9063                         break;
9064                 case 2:
9065                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9066                         break;
9067                 case 3:
9068                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9069                         break;
9070                 default:
9071                         DRM_DEBUG("invalid pipe %d\n", pipe);
9072                         return;
9073                 }
9074         } else {
9075                 DRM_DEBUG("invalid me %d\n", me);
9076                 return;
9077         }
9078
9079         switch (state) {
9080         case AMDGPU_IRQ_STATE_DISABLE:
9081                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9082                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9083                                              TIME_STAMP_INT_ENABLE, 0);
9084                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9085                 break;
9086         case AMDGPU_IRQ_STATE_ENABLE:
9087                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9088                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9089                                              TIME_STAMP_INT_ENABLE, 1);
9090                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9091                 break;
9092         default:
9093                 break;
9094         }
9095 }
9096
9097 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9098                                             struct amdgpu_irq_src *src,
9099                                             unsigned int type,
9100                                             enum amdgpu_interrupt_state state)
9101 {
9102         switch (type) {
9103         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9104                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9105                 break;
9106         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9107                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9108                 break;
9109         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9110                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9111                 break;
9112         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9113                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9114                 break;
9115         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9116                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9117                 break;
9118         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9119                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9120                 break;
9121         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9122                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9123                 break;
9124         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9125                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9126                 break;
9127         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9128                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9129                 break;
9130         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9131                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9132                 break;
9133         default:
9134                 break;
9135         }
9136         return 0;
9137 }
9138
9139 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9140                              struct amdgpu_irq_src *source,
9141                              struct amdgpu_iv_entry *entry)
9142 {
9143         int i;
9144         u8 me_id, pipe_id, queue_id;
9145         struct amdgpu_ring *ring;
9146
9147         DRM_DEBUG("IH: CP EOP\n");
9148
9149         me_id = (entry->ring_id & 0x0c) >> 2;
9150         pipe_id = (entry->ring_id & 0x03) >> 0;
9151         queue_id = (entry->ring_id & 0x70) >> 4;
9152
9153         switch (me_id) {
9154         case 0:
9155                 if (pipe_id == 0)
9156                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9157                 else
9158                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9159                 break;
9160         case 1:
9161         case 2:
9162                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9163                         ring = &adev->gfx.compute_ring[i];
9164                         /* Per-queue interrupt is supported for MEC starting from VI.
9165                          * The interrupt can only be enabled/disabled per pipe instead
9166                          * of per queue.
9167                          */
9168                         if ((ring->me == me_id) &&
9169                             (ring->pipe == pipe_id) &&
9170                             (ring->queue == queue_id))
9171                                 amdgpu_fence_process(ring);
9172                 }
9173                 break;
9174         }
9175
9176         return 0;
9177 }
9178
9179 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9180                                               struct amdgpu_irq_src *source,
9181                                               unsigned int type,
9182                                               enum amdgpu_interrupt_state state)
9183 {
9184         u32 cp_int_cntl_reg, cp_int_cntl;
9185         int i, j;
9186
9187         switch (state) {
9188         case AMDGPU_IRQ_STATE_DISABLE:
9189         case AMDGPU_IRQ_STATE_ENABLE:
9190                 for (i = 0; i < adev->gfx.me.num_me; i++) {
9191                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9192                                 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9193
9194                                 if (cp_int_cntl_reg) {
9195                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9196                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9197                                                                     PRIV_REG_INT_ENABLE,
9198                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9199                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9200                                 }
9201                         }
9202                 }
9203                 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9204                         for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9205                                 /* MECs start at 1 */
9206                                 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9207
9208                                 if (cp_int_cntl_reg) {
9209                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9210                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9211                                                                     PRIV_REG_INT_ENABLE,
9212                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9213                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9214                                 }
9215                         }
9216                 }
9217                 break;
9218         default:
9219                 break;
9220         }
9221
9222         return 0;
9223 }
9224
9225 static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
9226                                             struct amdgpu_irq_src *source,
9227                                             unsigned type,
9228                                             enum amdgpu_interrupt_state state)
9229 {
9230         u32 cp_int_cntl_reg, cp_int_cntl;
9231         int i, j;
9232
9233         switch (state) {
9234         case AMDGPU_IRQ_STATE_DISABLE:
9235         case AMDGPU_IRQ_STATE_ENABLE:
9236                 for (i = 0; i < adev->gfx.me.num_me; i++) {
9237                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9238                                 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9239
9240                                 if (cp_int_cntl_reg) {
9241                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9242                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9243                                                                     OPCODE_ERROR_INT_ENABLE,
9244                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9245                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9246                                 }
9247                         }
9248                 }
9249                 for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9250                         for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9251                                 /* MECs start at 1 */
9252                                 cp_int_cntl_reg = gfx_v10_0_get_cpc_int_cntl(adev, i + 1, j);
9253
9254                                 if (cp_int_cntl_reg) {
9255                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9256                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9257                                                                     OPCODE_ERROR_INT_ENABLE,
9258                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9259                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9260                                 }
9261                         }
9262                 }
9263                 break;
9264         default:
9265                 break;
9266         }
9267         return 0;
9268 }
9269
9270 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9271                                                struct amdgpu_irq_src *source,
9272                                                unsigned int type,
9273                                                enum amdgpu_interrupt_state state)
9274 {
9275         u32 cp_int_cntl_reg, cp_int_cntl;
9276         int i, j;
9277
9278         switch (state) {
9279         case AMDGPU_IRQ_STATE_DISABLE:
9280         case AMDGPU_IRQ_STATE_ENABLE:
9281                 for (i = 0; i < adev->gfx.me.num_me; i++) {
9282                         for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9283                                 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j);
9284
9285                                 if (cp_int_cntl_reg) {
9286                                         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9287                                         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9288                                                                     PRIV_INSTR_INT_ENABLE,
9289                                                                     state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9290                                         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9291                                 }
9292                         }
9293                 }
9294                 break;
9295         default:
9296                 break;
9297         }
9298
9299         return 0;
9300 }
9301
9302 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9303                                         struct amdgpu_iv_entry *entry)
9304 {
9305         u8 me_id, pipe_id, queue_id;
9306         struct amdgpu_ring *ring;
9307         int i;
9308
9309         me_id = (entry->ring_id & 0x0c) >> 2;
9310         pipe_id = (entry->ring_id & 0x03) >> 0;
9311         queue_id = (entry->ring_id & 0x70) >> 4;
9312
9313         switch (me_id) {
9314         case 0:
9315                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9316                         ring = &adev->gfx.gfx_ring[i];
9317                         if (ring->me == me_id && ring->pipe == pipe_id &&
9318                             ring->queue == queue_id)
9319                                 drm_sched_fault(&ring->sched);
9320                 }
9321                 break;
9322         case 1:
9323         case 2:
9324                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9325                         ring = &adev->gfx.compute_ring[i];
9326                         if (ring->me == me_id && ring->pipe == pipe_id &&
9327                             ring->queue == queue_id)
9328                                 drm_sched_fault(&ring->sched);
9329                 }
9330                 break;
9331         default:
9332                 BUG();
9333         }
9334 }
9335
9336 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9337                                   struct amdgpu_irq_src *source,
9338                                   struct amdgpu_iv_entry *entry)
9339 {
9340         DRM_ERROR("Illegal register access in command stream\n");
9341         gfx_v10_0_handle_priv_fault(adev, entry);
9342         return 0;
9343 }
9344
9345 static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev,
9346                                 struct amdgpu_irq_src *source,
9347                                 struct amdgpu_iv_entry *entry)
9348 {
9349         DRM_ERROR("Illegal opcode in command stream \n");
9350         gfx_v10_0_handle_priv_fault(adev, entry);
9351         return 0;
9352 }
9353
9354 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9355                                    struct amdgpu_irq_src *source,
9356                                    struct amdgpu_iv_entry *entry)
9357 {
9358         DRM_ERROR("Illegal instruction in command stream\n");
9359         gfx_v10_0_handle_priv_fault(adev, entry);
9360         return 0;
9361 }
9362
9363 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9364                                              struct amdgpu_irq_src *src,
9365                                              unsigned int type,
9366                                              enum amdgpu_interrupt_state state)
9367 {
9368         uint32_t tmp, target;
9369         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9370
9371         if (ring->me == 1)
9372                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9373         else
9374                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9375         target += ring->pipe;
9376
9377         switch (type) {
9378         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9379                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9380                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9381                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9382                                             GENERIC2_INT_ENABLE, 0);
9383                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9384
9385                         tmp = RREG32_SOC15_IP(GC, target);
9386                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9387                                             GENERIC2_INT_ENABLE, 0);
9388                         WREG32_SOC15_IP(GC, target, tmp);
9389                 } else {
9390                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9391                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9392                                             GENERIC2_INT_ENABLE, 1);
9393                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9394
9395                         tmp = RREG32_SOC15_IP(GC, target);
9396                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9397                                             GENERIC2_INT_ENABLE, 1);
9398                         WREG32_SOC15_IP(GC, target, tmp);
9399                 }
9400                 break;
9401         default:
9402                 BUG(); /* kiq only support GENERIC2_INT now */
9403                 break;
9404         }
9405         return 0;
9406 }
9407
9408 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9409                              struct amdgpu_irq_src *source,
9410                              struct amdgpu_iv_entry *entry)
9411 {
9412         u8 me_id, pipe_id, queue_id;
9413         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9414
9415         me_id = (entry->ring_id & 0x0c) >> 2;
9416         pipe_id = (entry->ring_id & 0x03) >> 0;
9417         queue_id = (entry->ring_id & 0x70) >> 4;
9418         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9419                    me_id, pipe_id, queue_id);
9420
9421         amdgpu_fence_process(ring);
9422         return 0;
9423 }
9424
9425 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9426 {
9427         const unsigned int gcr_cntl =
9428                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9429                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9430                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9431                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9432                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9433                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9434                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9435                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9436
9437         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9438         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9439         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9440         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9441         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9442         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9443         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9444         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9445         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9446 }
9447
9448 static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop)
9449 {
9450         /* Header itself is a NOP packet */
9451         if (num_nop == 1) {
9452                 amdgpu_ring_write(ring, ring->funcs->nop);
9453                 return;
9454         }
9455
9456         /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/
9457         amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe)));
9458
9459         /* Header is at index 0, followed by num_nops - 1 NOP packet's */
9460         amdgpu_ring_insert_nop(ring, num_nop - 1);
9461 }
9462
9463 static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
9464 {
9465         struct amdgpu_device *adev = ring->adev;
9466         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9467         struct amdgpu_ring *kiq_ring = &kiq->ring;
9468         unsigned long flags;
9469         u32 tmp;
9470         u64 addr;
9471         int r;
9472
9473         if (amdgpu_sriov_vf(adev))
9474                 return -EINVAL;
9475
9476         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9477                 return -EINVAL;
9478
9479         spin_lock_irqsave(&kiq->ring_lock, flags);
9480
9481         if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) {
9482                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9483                 return -ENOMEM;
9484         }
9485
9486         addr = amdgpu_bo_gpu_offset(ring->mqd_obj) +
9487                 offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active);
9488         tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
9489         if (ring->pipe == 0)
9490                 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue);
9491         else
9492                 tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue);
9493
9494         gfx_v10_0_ring_emit_wreg(kiq_ring,
9495                                  SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp);
9496         gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0,
9497                                lower_32_bits(addr), upper_32_bits(addr),
9498                                0, 1, 0x20);
9499         gfx_v10_0_ring_emit_reg_wait(kiq_ring,
9500                                      SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff);
9501         kiq->pmf->kiq_map_queues(kiq_ring, ring);
9502         amdgpu_ring_commit(kiq_ring);
9503
9504         spin_unlock_irqrestore(&kiq->ring_lock, flags);
9505
9506         r = amdgpu_ring_test_ring(kiq_ring);
9507         if (r)
9508                 return r;
9509
9510         r = amdgpu_bo_reserve(ring->mqd_obj, false);
9511         if (unlikely(r != 0)) {
9512                 DRM_ERROR("fail to resv mqd_obj\n");
9513                 return r;
9514         }
9515         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9516         if (!r) {
9517                 r = gfx_v10_0_kgq_init_queue(ring, true);
9518                 amdgpu_bo_kunmap(ring->mqd_obj);
9519                 ring->mqd_ptr = NULL;
9520         }
9521         amdgpu_bo_unreserve(ring->mqd_obj);
9522         if (r) {
9523                 DRM_ERROR("fail to unresv mqd_obj\n");
9524                 return r;
9525         }
9526
9527         return amdgpu_ring_test_ring(ring);
9528 }
9529
9530 static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
9531                                unsigned int vmid)
9532 {
9533         struct amdgpu_device *adev = ring->adev;
9534         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
9535         struct amdgpu_ring *kiq_ring = &kiq->ring;
9536         unsigned long flags;
9537         int i, r;
9538
9539         if (amdgpu_sriov_vf(adev))
9540                 return -EINVAL;
9541
9542         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
9543                 return -EINVAL;
9544
9545         spin_lock_irqsave(&kiq->ring_lock, flags);
9546
9547         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
9548                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9549                 return -ENOMEM;
9550         }
9551
9552         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
9553                                    0, 0);
9554         amdgpu_ring_commit(kiq_ring);
9555         spin_unlock_irqrestore(&kiq->ring_lock, flags);
9556
9557         r = amdgpu_ring_test_ring(kiq_ring);
9558         if (r)
9559                 return r;
9560
9561         /* make sure dequeue is complete*/
9562         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
9563         mutex_lock(&adev->srbm_mutex);
9564         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
9565         for (i = 0; i < adev->usec_timeout; i++) {
9566                 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
9567                         break;
9568                 udelay(1);
9569         }
9570         if (i >= adev->usec_timeout)
9571                 r = -ETIMEDOUT;
9572         nv_grbm_select(adev, 0, 0, 0, 0);
9573         mutex_unlock(&adev->srbm_mutex);
9574         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
9575         if (r) {
9576                 dev_err(adev->dev, "fail to wait on hqd deactivate\n");
9577                 return r;
9578         }
9579
9580         r = amdgpu_bo_reserve(ring->mqd_obj, false);
9581         if (unlikely(r != 0)) {
9582                 dev_err(adev->dev, "fail to resv mqd_obj\n");
9583                 return r;
9584         }
9585         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
9586         if (!r) {
9587                 r = gfx_v10_0_kcq_init_queue(ring, true);
9588                 amdgpu_bo_kunmap(ring->mqd_obj);
9589                 ring->mqd_ptr = NULL;
9590         }
9591         amdgpu_bo_unreserve(ring->mqd_obj);
9592         if (r) {
9593                 dev_err(adev->dev, "fail to unresv mqd_obj\n");
9594                 return r;
9595         }
9596
9597         spin_lock_irqsave(&kiq->ring_lock, flags);
9598         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) {
9599                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
9600                 return -ENOMEM;
9601         }
9602         kiq->pmf->kiq_map_queues(kiq_ring, ring);
9603         amdgpu_ring_commit(kiq_ring);
9604         spin_unlock_irqrestore(&kiq->ring_lock, flags);
9605
9606         r = amdgpu_ring_test_ring(kiq_ring);
9607         if (r)
9608                 return r;
9609
9610         return amdgpu_ring_test_ring(ring);
9611 }
9612
9613 static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
9614 {
9615         struct amdgpu_device *adev = ip_block->adev;
9616         uint32_t i, j, k, reg, index = 0;
9617         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9618
9619         if (!adev->gfx.ip_dump_core)
9620                 return;
9621
9622         for (i = 0; i < reg_count; i++)
9623                 drm_printf(p, "%-50s \t 0x%08x\n",
9624                            gc_reg_list_10_1[i].reg_name,
9625                            adev->gfx.ip_dump_core[i]);
9626
9627         /* print compute queue registers for all instances */
9628         if (!adev->gfx.ip_dump_compute_queues)
9629                 return;
9630
9631         reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9632         drm_printf(p, "\nnum_mec: %d num_pipe: %d num_queue: %d\n",
9633                    adev->gfx.mec.num_mec,
9634                    adev->gfx.mec.num_pipe_per_mec,
9635                    adev->gfx.mec.num_queue_per_pipe);
9636
9637         for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9638                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9639                         for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9640                                 drm_printf(p, "\nmec %d, pipe %d, queue %d\n", i, j, k);
9641                                 for (reg = 0; reg < reg_count; reg++) {
9642                                         drm_printf(p, "%-50s \t 0x%08x\n",
9643                                                    gc_cp_reg_list_10[reg].reg_name,
9644                                                    adev->gfx.ip_dump_compute_queues[index + reg]);
9645                                 }
9646                                 index += reg_count;
9647                         }
9648                 }
9649         }
9650
9651         /* print gfx queue registers for all instances */
9652         if (!adev->gfx.ip_dump_gfx_queues)
9653                 return;
9654
9655         index = 0;
9656         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9657         drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
9658                    adev->gfx.me.num_me,
9659                    adev->gfx.me.num_pipe_per_me,
9660                    adev->gfx.me.num_queue_per_pipe);
9661
9662         for (i = 0; i < adev->gfx.me.num_me; i++) {
9663                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9664                         for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9665                                 drm_printf(p, "\nme %d, pipe %d, queue %d\n", i, j, k);
9666                                 for (reg = 0; reg < reg_count; reg++) {
9667                                         drm_printf(p, "%-50s \t 0x%08x\n",
9668                                                    gc_gfx_queue_reg_list_10[reg].reg_name,
9669                                                    adev->gfx.ip_dump_gfx_queues[index + reg]);
9670                                 }
9671                                 index += reg_count;
9672                         }
9673                 }
9674         }
9675 }
9676
9677 static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block)
9678 {
9679         struct amdgpu_device *adev = ip_block->adev;
9680         uint32_t i, j, k, reg, index = 0;
9681         uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
9682
9683         if (!adev->gfx.ip_dump_core)
9684                 return;
9685
9686         amdgpu_gfx_off_ctrl(adev, false);
9687         for (i = 0; i < reg_count; i++)
9688                 adev->gfx.ip_dump_core[i] = RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
9689         amdgpu_gfx_off_ctrl(adev, true);
9690
9691         /* dump compute queue registers for all instances */
9692         if (!adev->gfx.ip_dump_compute_queues)
9693                 return;
9694
9695         reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
9696         amdgpu_gfx_off_ctrl(adev, false);
9697         mutex_lock(&adev->srbm_mutex);
9698         for (i = 0; i < adev->gfx.mec.num_mec; i++) {
9699                 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
9700                         for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) {
9701                                 /* ME0 is for GFX so start from 1 for CP */
9702                                 nv_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0);
9703
9704                                 for (reg = 0; reg < reg_count; reg++) {
9705                                         adev->gfx.ip_dump_compute_queues[index + reg] =
9706                                                 RREG32(SOC15_REG_ENTRY_OFFSET(
9707                                                         gc_cp_reg_list_10[reg]));
9708                                 }
9709                                 index += reg_count;
9710                         }
9711                 }
9712         }
9713         nv_grbm_select(adev, 0, 0, 0, 0);
9714         mutex_unlock(&adev->srbm_mutex);
9715         amdgpu_gfx_off_ctrl(adev, true);
9716
9717         /* dump gfx queue registers for all instances */
9718         if (!adev->gfx.ip_dump_gfx_queues)
9719                 return;
9720
9721         index = 0;
9722         reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
9723         amdgpu_gfx_off_ctrl(adev, false);
9724         mutex_lock(&adev->srbm_mutex);
9725         for (i = 0; i < adev->gfx.me.num_me; i++) {
9726                 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) {
9727                         for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) {
9728                                 nv_grbm_select(adev, i, j, k, 0);
9729
9730                                 for (reg = 0; reg < reg_count; reg++) {
9731                                         adev->gfx.ip_dump_gfx_queues[index + reg] =
9732                                                 RREG32(SOC15_REG_ENTRY_OFFSET(
9733                                                         gc_gfx_queue_reg_list_10[reg]));
9734                                 }
9735                                 index += reg_count;
9736                         }
9737                 }
9738         }
9739         nv_grbm_select(adev, 0, 0, 0, 0);
9740         mutex_unlock(&adev->srbm_mutex);
9741         amdgpu_gfx_off_ctrl(adev, true);
9742 }
9743
9744 static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
9745 {
9746         /* Emit the cleaner shader */
9747         amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0));
9748         amdgpu_ring_write(ring, 0);  /* RESERVED field, programmed to zero */
9749 }
9750
9751 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9752         .name = "gfx_v10_0",
9753         .early_init = gfx_v10_0_early_init,
9754         .late_init = gfx_v10_0_late_init,
9755         .sw_init = gfx_v10_0_sw_init,
9756         .sw_fini = gfx_v10_0_sw_fini,
9757         .hw_init = gfx_v10_0_hw_init,
9758         .hw_fini = gfx_v10_0_hw_fini,
9759         .suspend = gfx_v10_0_suspend,
9760         .resume = gfx_v10_0_resume,
9761         .is_idle = gfx_v10_0_is_idle,
9762         .wait_for_idle = gfx_v10_0_wait_for_idle,
9763         .soft_reset = gfx_v10_0_soft_reset,
9764         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9765         .set_powergating_state = gfx_v10_0_set_powergating_state,
9766         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9767         .dump_ip_state = gfx_v10_ip_dump,
9768         .print_ip_state = gfx_v10_ip_print,
9769 };
9770
9771 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9772         .type = AMDGPU_RING_TYPE_GFX,
9773         .align_mask = 0xff,
9774         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9775         .support_64bit_ptrs = true,
9776         .secure_submission_supported = true,
9777         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9778         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9779         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9780         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9781                 5 + /* COND_EXEC */
9782                 7 + /* PIPELINE_SYNC */
9783                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9784                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9785                 4 + /* VM_FLUSH */
9786                 8 + /* FENCE for VM_FLUSH */
9787                 20 + /* GDS switch */
9788                 4 + /* double SWITCH_BUFFER,
9789                      * the first COND_EXEC jump to the place
9790                      * just prior to this double SWITCH_BUFFER
9791                      */
9792                 5 + /* COND_EXEC */
9793                 7 + /* HDP_flush */
9794                 4 + /* VGT_flush */
9795                 14 + /* CE_META */
9796                 31 + /* DE_META */
9797                 3 + /* CNTX_CTRL */
9798                 5 + /* HDP_INVL */
9799                 8 + 8 + /* FENCE x2 */
9800                 2 + /* SWITCH_BUFFER */
9801                 8 + /* gfx_v10_0_emit_mem_sync */
9802                 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9803         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9804         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9805         .emit_fence = gfx_v10_0_ring_emit_fence,
9806         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9807         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9808         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9809         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9810         .test_ring = gfx_v10_0_ring_test_ring,
9811         .test_ib = gfx_v10_0_ring_test_ib,
9812         .insert_nop = gfx_v10_ring_insert_nop,
9813         .pad_ib = amdgpu_ring_generic_pad_ib,
9814         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9815         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9816         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9817         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9818         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9819         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9820         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9821         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9822         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9823         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9824         .reset = gfx_v10_0_reset_kgq,
9825         .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9826         .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
9827         .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
9828 };
9829
9830 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9831         .type = AMDGPU_RING_TYPE_COMPUTE,
9832         .align_mask = 0xff,
9833         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9834         .support_64bit_ptrs = true,
9835         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9836         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9837         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9838         .emit_frame_size =
9839                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9840                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9841                 5 + /* hdp invalidate */
9842                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9843                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9844                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9845                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9846                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9847                 8 + /* gfx_v10_0_emit_mem_sync */
9848                 2, /* gfx_v10_0_ring_emit_cleaner_shader */
9849         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9850         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9851         .emit_fence = gfx_v10_0_ring_emit_fence,
9852         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9853         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9854         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9855         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9856         .test_ring = gfx_v10_0_ring_test_ring,
9857         .test_ib = gfx_v10_0_ring_test_ib,
9858         .insert_nop = gfx_v10_ring_insert_nop,
9859         .pad_ib = amdgpu_ring_generic_pad_ib,
9860         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9861         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9862         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9863         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9864         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9865         .reset = gfx_v10_0_reset_kcq,
9866         .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
9867         .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use,
9868         .end_use = amdgpu_gfx_enforce_isolation_ring_end_use,
9869 };
9870
9871 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9872         .type = AMDGPU_RING_TYPE_KIQ,
9873         .align_mask = 0xff,
9874         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9875         .support_64bit_ptrs = true,
9876         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9877         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9878         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9879         .emit_frame_size =
9880                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9881                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9882                 5 + /*hdp invalidate */
9883                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9884                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9885                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9886                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9887         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9888         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9889         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9890         .test_ring = gfx_v10_0_ring_test_ring,
9891         .test_ib = gfx_v10_0_ring_test_ib,
9892         .insert_nop = amdgpu_ring_insert_nop,
9893         .pad_ib = amdgpu_ring_generic_pad_ib,
9894         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9895         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9896         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9897         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9898 };
9899
9900 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9901 {
9902         int i;
9903
9904         adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9905
9906         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9907                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9908
9909         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9910                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9911 }
9912
9913 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9914         .set = gfx_v10_0_set_eop_interrupt_state,
9915         .process = gfx_v10_0_eop_irq,
9916 };
9917
9918 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9919         .set = gfx_v10_0_set_priv_reg_fault_state,
9920         .process = gfx_v10_0_priv_reg_irq,
9921 };
9922
9923 static const struct amdgpu_irq_src_funcs gfx_v10_0_bad_op_irq_funcs = {
9924         .set = gfx_v10_0_set_bad_op_fault_state,
9925         .process = gfx_v10_0_bad_op_irq,
9926 };
9927
9928 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9929         .set = gfx_v10_0_set_priv_inst_fault_state,
9930         .process = gfx_v10_0_priv_inst_irq,
9931 };
9932
9933 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9934         .set = gfx_v10_0_kiq_set_interrupt_state,
9935         .process = gfx_v10_0_kiq_irq,
9936 };
9937
9938 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9939 {
9940         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9941         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9942
9943         adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9944         adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9945
9946         adev->gfx.priv_reg_irq.num_types = 1;
9947         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9948
9949         adev->gfx.bad_op_irq.num_types = 1;
9950         adev->gfx.bad_op_irq.funcs = &gfx_v10_0_bad_op_irq_funcs;
9951
9952         adev->gfx.priv_inst_irq.num_types = 1;
9953         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9954 }
9955
9956 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9957 {
9958         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
9959         case IP_VERSION(10, 1, 10):
9960         case IP_VERSION(10, 1, 1):
9961         case IP_VERSION(10, 1, 3):
9962         case IP_VERSION(10, 1, 4):
9963         case IP_VERSION(10, 3, 2):
9964         case IP_VERSION(10, 3, 1):
9965         case IP_VERSION(10, 3, 4):
9966         case IP_VERSION(10, 3, 5):
9967         case IP_VERSION(10, 3, 6):
9968         case IP_VERSION(10, 3, 3):
9969         case IP_VERSION(10, 3, 7):
9970                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9971                 break;
9972         case IP_VERSION(10, 1, 2):
9973         case IP_VERSION(10, 3, 0):
9974                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9975                 break;
9976         default:
9977                 break;
9978         }
9979 }
9980
9981 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9982 {
9983         unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9984                             adev->gfx.config.max_sh_per_se *
9985                             adev->gfx.config.max_shader_engines;
9986
9987         adev->gds.gds_size = 0x10000;
9988         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9989         adev->gds.gws_size = 64;
9990         adev->gds.oa_size = 16;
9991 }
9992
9993 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9994 {
9995         /* set gfx eng mqd */
9996         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9997                 sizeof(struct v10_gfx_mqd);
9998         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9999                 gfx_v10_0_gfx_mqd_init;
10000         /* set compute eng mqd */
10001         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
10002                 sizeof(struct v10_compute_mqd);
10003         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
10004                 gfx_v10_0_compute_mqd_init;
10005 }
10006
10007 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
10008                                                           u32 bitmap)
10009 {
10010         u32 data;
10011
10012         if (!bitmap)
10013                 return;
10014
10015         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10016         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10017
10018         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
10019 }
10020
10021 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
10022 {
10023         u32 disabled_mask =
10024                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
10025         u32 efuse_setting = 0;
10026         u32 vbios_setting = 0;
10027
10028         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
10029         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10030         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10031
10032         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
10033         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
10034         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
10035
10036         disabled_mask |= efuse_setting | vbios_setting;
10037
10038         return (~disabled_mask);
10039 }
10040
10041 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
10042 {
10043         u32 wgp_idx, wgp_active_bitmap;
10044         u32 cu_bitmap_per_wgp, cu_active_bitmap;
10045
10046         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
10047         cu_active_bitmap = 0;
10048
10049         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
10050                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
10051                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
10052                 if (wgp_active_bitmap & (1 << wgp_idx))
10053                         cu_active_bitmap |= cu_bitmap_per_wgp;
10054         }
10055
10056         return cu_active_bitmap;
10057 }
10058
10059 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
10060                                  struct amdgpu_cu_info *cu_info)
10061 {
10062         int i, j, k, counter, active_cu_number = 0;
10063         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
10064         unsigned int disable_masks[4 * 2];
10065
10066         if (!adev || !cu_info)
10067                 return -EINVAL;
10068
10069         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
10070
10071         mutex_lock(&adev->grbm_idx_mutex);
10072         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
10073                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
10074                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
10075                         if (((amdgpu_ip_version(adev, GC_HWIP, 0) ==
10076                               IP_VERSION(10, 3, 0)) ||
10077                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10078                               IP_VERSION(10, 3, 3)) ||
10079                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10080                               IP_VERSION(10, 3, 6)) ||
10081                              (amdgpu_ip_version(adev, GC_HWIP, 0) ==
10082                               IP_VERSION(10, 3, 7))) &&
10083                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
10084                                 continue;
10085                         mask = 1;
10086                         ao_bitmap = 0;
10087                         counter = 0;
10088                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0);
10089                         if (i < 4 && j < 2)
10090                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
10091                                         adev, disable_masks[i * 2 + j]);
10092                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
10093                         cu_info->bitmap[0][i][j] = bitmap;
10094
10095                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
10096                                 if (bitmap & mask) {
10097                                         if (counter < adev->gfx.config.max_cu_per_sh)
10098                                                 ao_bitmap |= mask;
10099                                         counter++;
10100                                 }
10101                                 mask <<= 1;
10102                         }
10103                         active_cu_number += counter;
10104                         if (i < 2 && j < 2)
10105                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
10106                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
10107                 }
10108         }
10109         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
10110         mutex_unlock(&adev->grbm_idx_mutex);
10111
10112         cu_info->number = active_cu_number;
10113         cu_info->ao_cu_mask = ao_cu_mask;
10114         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
10115
10116         return 0;
10117 }
10118
10119 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
10120 {
10121         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
10122
10123         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
10124         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10125         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10126
10127         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
10128         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
10129         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
10130
10131         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
10132                                                 adev->gfx.config.max_shader_engines);
10133         disabled_sa = efuse_setting | vbios_setting;
10134         disabled_sa &= max_sa_mask;
10135
10136         return disabled_sa;
10137 }
10138
10139 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
10140 {
10141         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
10142         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
10143
10144         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
10145
10146         max_sa_per_se = adev->gfx.config.max_sh_per_se;
10147         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
10148         max_shader_engines = adev->gfx.config.max_shader_engines;
10149
10150         for (se_index = 0; max_shader_engines > se_index; se_index++) {
10151                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
10152                 disabled_sa_per_se &= max_sa_per_se_mask;
10153                 if (disabled_sa_per_se == max_sa_per_se_mask) {
10154                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
10155                         break;
10156                 }
10157         }
10158 }
10159
10160 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
10161 {
10162         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
10163                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
10164                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
10165                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
10166
10167         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
10168         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
10169                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
10170                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
10171                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
10172                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
10173
10174         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
10175                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
10176                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
10177                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
10178
10179         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
10180
10181         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
10182                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
10183 }
10184
10185 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = {
10186         .type = AMD_IP_BLOCK_TYPE_GFX,
10187         .major = 10,
10188         .minor = 0,
10189         .rev = 0,
10190         .funcs = &gfx_v10_0_ip_funcs,
10191 };