drivers/gpu/drm/amd/display/modules/freesync/freesync.c

   1 /*
   2  * Copyright 2016-2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dc.h"
  28 #include "mod_freesync.h"
  29 #include "core_types.h"
  30
  31 #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS  32
  32
  33 #define MIN_REFRESH_RANGE 10
  34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
  35 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
  36 /* Number of elements in the render times cache array */
  37 #define RENDER_TIMES_MAX_COUNT 10
  38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
  39 #define BTR_MAX_MARGIN 2500
  40 /* Threshold to change BTR multiplier (to avoid frequent changes) */
  41 #define BTR_DRIFT_MARGIN 2000
  42 /* Threshold to exit fixed refresh rate */
  43 #define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
  44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
  45 #define FIXED_REFRESH_ENTER_FRAME_COUNT 5
  46 #define FIXED_REFRESH_EXIT_FRAME_COUNT 10
  47 /* Flip interval workaround constants */
  48 #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2
  49 #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5
  50 #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500
  51
  52 struct core_freesync {
  53         struct mod_freesync public;
  54         struct dc *dc;
  55 };
  56
  57 #define MOD_FREESYNC_TO_CORE(mod_freesync)\
  58                 container_of(mod_freesync, struct core_freesync, public)
  59
  60 struct mod_freesync *mod_freesync_create(struct dc *dc)
  61 {
  62         struct core_freesync *core_freesync =
  63                         kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
  64
  65         if (core_freesync == NULL)
  66                 goto fail_alloc_context;
  67
  68         if (dc == NULL)
  69                 goto fail_construct;
  70
  71         core_freesync->dc = dc;
  72         return &core_freesync->public;
  73
  74 fail_construct:
  75         kfree(core_freesync);
  76
  77 fail_alloc_context:
  78         return NULL;
  79 }
  80
  81 void mod_freesync_destroy(struct mod_freesync *mod_freesync)
  82 {
  83         struct core_freesync *core_freesync = NULL;
  84
  85         if (mod_freesync == NULL)
  86                 return;
  87         core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
  88         kfree(core_freesync);
  89 }
  90
  91 #if 0 /* Unused currently */
  92 static unsigned int calc_refresh_in_uhz_from_duration(
  93                 unsigned int duration_in_ns)
  94 {
  95         unsigned int refresh_in_uhz =
  96                         ((unsigned int)(div64_u64((1000000000ULL * 1000000),
  97                                         duration_in_ns)));
  98         return refresh_in_uhz;
  99 }
 100 #endif
 101
 102 static unsigned int calc_duration_in_us_from_refresh_in_uhz(
 103                 unsigned int refresh_in_uhz)
 104 {
 105         unsigned int duration_in_us =
 106                         ((unsigned int)(div64_u64((1000000000ULL * 1000),
 107                                         refresh_in_uhz)));
 108         return duration_in_us;
 109 }
 110
 111 static unsigned int calc_duration_in_us_from_v_total(
 112                 const struct dc_stream_state *stream,
 113                 const struct mod_vrr_params *in_vrr,
 114                 unsigned int v_total)
 115 {
 116         unsigned int duration_in_us =
 117                         (unsigned int)(div64_u64(((unsigned long long)(v_total)
 118                                 * 10000) * stream->timing.h_total,
 119                                         stream->timing.pix_clk_100hz));
 120
 121         return duration_in_us;
 122 }
 123
 124 unsigned int mod_freesync_calc_v_total_from_refresh(
 125                 const struct dc_stream_state *stream,
 126                 unsigned int refresh_in_uhz)
 127 {
 128         unsigned int v_total;
 129         unsigned int frame_duration_in_ns;
 130
 131         frame_duration_in_ns =
 132                         ((unsigned int)(div64_u64((1000000000ULL * 1000000),
 133                                         refresh_in_uhz)));
 134
 135         v_total = div64_u64(div64_u64(((unsigned long long)(
 136                         frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
 137                         stream->timing.h_total), 1000000);
 138
 139         /* v_total cannot be less than nominal */
 140         if (v_total < stream->timing.v_total) {
 141                 ASSERT(v_total < stream->timing.v_total);
 142                 v_total = stream->timing.v_total;
 143         }
 144
 145         return v_total;
 146 }
 147
 148 static unsigned int calc_v_total_from_duration(
 149                 const struct dc_stream_state *stream,
 150                 const struct mod_vrr_params *vrr,
 151                 unsigned int duration_in_us)
 152 {
 153         unsigned int v_total = 0;
 154
 155         if (duration_in_us < vrr->min_duration_in_us)
 156                 duration_in_us = vrr->min_duration_in_us;
 157
 158         if (duration_in_us > vrr->max_duration_in_us)
 159                 duration_in_us = vrr->max_duration_in_us;
 160
 161         if (dc_is_hdmi_signal(stream->signal)) {
 162                 uint32_t h_total_up_scaled;
 163
 164                 h_total_up_scaled = stream->timing.h_total * 10000;
 165                 v_total = div_u64((unsigned long long)duration_in_us
 166                                         * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
 167                                         h_total_up_scaled);
 168         } else {
 169                 v_total = div64_u64(div64_u64(((unsigned long long)(
 170                                         duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
 171                                         stream->timing.h_total), 1000);
 172         }
 173
 174         /* v_total cannot be less than nominal */
 175         if (v_total < stream->timing.v_total) {
 176                 ASSERT(v_total < stream->timing.v_total);
 177                 v_total = stream->timing.v_total;
 178         }
 179
 180         return v_total;
 181 }
 182
 183 static void update_v_total_for_static_ramp(
 184                 struct core_freesync *core_freesync,
 185                 const struct dc_stream_state *stream,
 186                 struct mod_vrr_params *in_out_vrr)
 187 {
 188         unsigned int v_total = 0;
 189         unsigned int current_duration_in_us =
 190                         calc_duration_in_us_from_v_total(
 191                                 stream, in_out_vrr,
 192                                 in_out_vrr->adjust.v_total_max);
 193         unsigned int target_duration_in_us =
 194                         calc_duration_in_us_from_refresh_in_uhz(
 195                                 in_out_vrr->fixed.target_refresh_in_uhz);
 196         bool ramp_direction_is_up = (current_duration_in_us >
 197                                 target_duration_in_us) ? true : false;
 198
 199         /* Calculate ratio between new and current frame duration with 3 digit */
 200         unsigned int frame_duration_ratio = div64_u64(1000000,
 201                 (1000 +  div64_u64(((unsigned long long)(
 202                 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
 203                 current_duration_in_us),
 204                 1000000)));
 205
 206         /* Calculate delta between new and current frame duration in us */
 207         unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
 208                 current_duration_in_us) *
 209                 (1000 - frame_duration_ratio)), 1000);
 210
 211         /* Adjust frame duration delta based on ratio between current and
 212          * standard frame duration (frame duration at 60 Hz refresh rate).
 213          */
 214         unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
 215                 frame_duration_delta) * current_duration_in_us), 16666);
 216
 217         /* Going to a higher refresh rate (lower frame duration) */
 218         if (ramp_direction_is_up) {
 219                 /* Reduce frame duration */
 220                 current_duration_in_us -= ramp_rate_interpolated;
 221
 222                 /* Adjust for frame duration below min */
 223                 if (current_duration_in_us <= target_duration_in_us) {
 224                         in_out_vrr->fixed.ramping_active = false;
 225                         in_out_vrr->fixed.ramping_done = true;
 226                         current_duration_in_us =
 227                                 calc_duration_in_us_from_refresh_in_uhz(
 228                                 in_out_vrr->fixed.target_refresh_in_uhz);
 229                 }
 230         /* Going to a lower refresh rate (larger frame duration) */
 231         } else {
 232                 /* Increase frame duration */
 233                 current_duration_in_us += ramp_rate_interpolated;
 234
 235                 /* Adjust for frame duration above max */
 236                 if (current_duration_in_us >= target_duration_in_us) {
 237                         in_out_vrr->fixed.ramping_active = false;
 238                         in_out_vrr->fixed.ramping_done = true;
 239                         current_duration_in_us =
 240                                 calc_duration_in_us_from_refresh_in_uhz(
 241                                 in_out_vrr->fixed.target_refresh_in_uhz);
 242                 }
 243         }
 244
 245         v_total = div64_u64(div64_u64(((unsigned long long)(
 246                         current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
 247                                 stream->timing.h_total), 1000);
 248
 249         /* v_total cannot be less than nominal */
 250         if (v_total < stream->timing.v_total)
 251                 v_total = stream->timing.v_total;
 252
 253         in_out_vrr->adjust.v_total_min = v_total;
 254         in_out_vrr->adjust.v_total_max = v_total;
 255 }
 256
 257 static void apply_below_the_range(struct core_freesync *core_freesync,
 258                 const struct dc_stream_state *stream,
 259                 unsigned int last_render_time_in_us,
 260                 struct mod_vrr_params *in_out_vrr)
 261 {
 262         unsigned int inserted_frame_duration_in_us = 0;
 263         unsigned int mid_point_frames_ceil = 0;
 264         unsigned int mid_point_frames_floor = 0;
 265         unsigned int frame_time_in_us = 0;
 266         unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
 267         unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
 268         unsigned int frames_to_insert = 0;
 269         unsigned int delta_from_mid_point_delta_in_us;
 270         unsigned int max_render_time_in_us =
 271                         in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
 272
 273         /* Program BTR */
 274         if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
 275                 /* Exit Below the Range */
 276                 if (in_out_vrr->btr.btr_active) {
 277                         in_out_vrr->btr.frame_counter = 0;
 278                         in_out_vrr->btr.btr_active = false;
 279                 }
 280         } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
 281                 /* Enter Below the Range */
 282                 if (!in_out_vrr->btr.btr_active)
 283                         in_out_vrr->btr.btr_active = true;
 284         }
 285
 286         /* BTR set to "not active" so disengage */
 287         if (!in_out_vrr->btr.btr_active) {
 288                 in_out_vrr->btr.inserted_duration_in_us = 0;
 289                 in_out_vrr->btr.frames_to_insert = 0;
 290                 in_out_vrr->btr.frame_counter = 0;
 291
 292                 /* Restore FreeSync */
 293                 in_out_vrr->adjust.v_total_min =
 294                         mod_freesync_calc_v_total_from_refresh(stream,
 295                                 in_out_vrr->max_refresh_in_uhz);
 296                 in_out_vrr->adjust.v_total_max =
 297                         mod_freesync_calc_v_total_from_refresh(stream,
 298                                 in_out_vrr->min_refresh_in_uhz);
 299         /* BTR set to "active" so engage */
 300         } else {
 301
 302                 /* Calculate number of midPoint frames that could fit within
 303                  * the render time interval - take ceil of this value
 304                  */
 305                 mid_point_frames_ceil = (last_render_time_in_us +
 306                                 in_out_vrr->btr.mid_point_in_us - 1) /
 307                                         in_out_vrr->btr.mid_point_in_us;
 308
 309                 if (mid_point_frames_ceil > 0) {
 310                         frame_time_in_us = last_render_time_in_us /
 311                                 mid_point_frames_ceil;
 312                         delta_from_mid_point_in_us_1 =
 313                                 (in_out_vrr->btr.mid_point_in_us >
 314                                 frame_time_in_us) ?
 315                                 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
 316                                 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
 317                 }
 318
 319                 /* Calculate number of midPoint frames that could fit within
 320                  * the render time interval - take floor of this value
 321                  */
 322                 mid_point_frames_floor = last_render_time_in_us /
 323                                 in_out_vrr->btr.mid_point_in_us;
 324
 325                 if (mid_point_frames_floor > 0) {
 326
 327                         frame_time_in_us = last_render_time_in_us /
 328                                 mid_point_frames_floor;
 329                         delta_from_mid_point_in_us_2 =
 330                                 (in_out_vrr->btr.mid_point_in_us >
 331                                 frame_time_in_us) ?
 332                                 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
 333                                 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
 334                 }
 335
 336                 /* Choose number of frames to insert based on how close it
 337                  * can get to the mid point of the variable range.
 338                  *  - Delta for CEIL: delta_from_mid_point_in_us_1
 339                  *  - Delta for FLOOR: delta_from_mid_point_in_us_2
 340                  */
 341                 if (mid_point_frames_ceil &&
 342                     (last_render_time_in_us / mid_point_frames_ceil) <
 343                     in_out_vrr->min_duration_in_us) {
 344                         /* Check for out of range.
 345                          * If using CEIL produces a value that is out of range,
 346                          * then we are forced to use FLOOR.
 347                          */
 348                         frames_to_insert = mid_point_frames_floor;
 349                 } else if (mid_point_frames_floor < 2) {
 350                         /* Check if FLOOR would result in non-LFC. In this case
 351                          * choose to use CEIL
 352                          */
 353                         frames_to_insert = mid_point_frames_ceil;
 354                 } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
 355                         /* If choosing CEIL results in a frame duration that is
 356                          * closer to the mid point of the range.
 357                          * Choose CEIL
 358                          */
 359                         frames_to_insert = mid_point_frames_ceil;
 360                 } else {
 361                         /* If choosing FLOOR results in a frame duration that is
 362                          * closer to the mid point of the range.
 363                          * Choose FLOOR
 364                          */
 365                         frames_to_insert = mid_point_frames_floor;
 366                 }
 367
 368                 /* Prefer current frame multiplier when BTR is enabled unless it drifts
 369                  * too far from the midpoint
 370                  */
 371                 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
 372                         delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
 373                                         delta_from_mid_point_in_us_1;
 374                 } else {
 375                         delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
 376                                         delta_from_mid_point_in_us_2;
 377                 }
 378                 if (in_out_vrr->btr.frames_to_insert != 0 &&
 379                                 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
 380                         if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
 381                                         max_render_time_in_us) &&
 382                                 ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
 383                                         in_out_vrr->min_duration_in_us))
 384                                 frames_to_insert = in_out_vrr->btr.frames_to_insert;
 385                 }
 386
 387                 /* Either we've calculated the number of frames to insert,
 388                  * or we need to insert min duration frames
 389                  */
 390                 if (frames_to_insert &&
 391                     (last_render_time_in_us / frames_to_insert) <
 392                     in_out_vrr->min_duration_in_us){
 393                         frames_to_insert -= (frames_to_insert > 1) ?
 394                                         1 : 0;
 395                 }
 396
 397                 if (frames_to_insert > 0)
 398                         inserted_frame_duration_in_us = last_render_time_in_us /
 399                                                         frames_to_insert;
 400
 401                 if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)
 402                         inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;
 403
 404                 /* Cache the calculated variables */
 405                 in_out_vrr->btr.inserted_duration_in_us =
 406                         inserted_frame_duration_in_us;
 407                 in_out_vrr->btr.frames_to_insert = frames_to_insert;
 408                 in_out_vrr->btr.frame_counter = frames_to_insert;
 409         }
 410 }
 411
 412 static void apply_fixed_refresh(struct core_freesync *core_freesync,
 413                 const struct dc_stream_state *stream,
 414                 unsigned int last_render_time_in_us,
 415                 struct mod_vrr_params *in_out_vrr)
 416 {
 417         bool update = false;
 418         unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
 419
 420         /* Compute the exit refresh rate and exit frame duration */
 421         unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)
 422                         + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
 423         unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;
 424
 425         if (last_render_time_in_us < exit_frame_duration_in_us) {
 426                 /* Exit Fixed Refresh mode */
 427                 if (in_out_vrr->fixed.fixed_active) {
 428                         in_out_vrr->fixed.frame_counter++;
 429
 430                         if (in_out_vrr->fixed.frame_counter >
 431                                         FIXED_REFRESH_EXIT_FRAME_COUNT) {
 432                                 in_out_vrr->fixed.frame_counter = 0;
 433                                 in_out_vrr->fixed.fixed_active = false;
 434                                 in_out_vrr->fixed.target_refresh_in_uhz = 0;
 435                                 update = true;
 436                         }
 437                 } else
 438                         in_out_vrr->fixed.frame_counter = 0;
 439         } else if (last_render_time_in_us > max_render_time_in_us) {
 440                 /* Enter Fixed Refresh mode */
 441                 if (!in_out_vrr->fixed.fixed_active) {
 442                         in_out_vrr->fixed.frame_counter++;
 443
 444                         if (in_out_vrr->fixed.frame_counter >
 445                                         FIXED_REFRESH_ENTER_FRAME_COUNT) {
 446                                 in_out_vrr->fixed.frame_counter = 0;
 447                                 in_out_vrr->fixed.fixed_active = true;
 448                                 in_out_vrr->fixed.target_refresh_in_uhz =
 449                                                 in_out_vrr->max_refresh_in_uhz;
 450                                 update = true;
 451                         }
 452                 } else
 453                         in_out_vrr->fixed.frame_counter = 0;
 454         }
 455
 456         if (update) {
 457                 if (in_out_vrr->fixed.fixed_active) {
 458                         in_out_vrr->adjust.v_total_min =
 459                                 mod_freesync_calc_v_total_from_refresh(
 460                                 stream, in_out_vrr->max_refresh_in_uhz);
 461                         in_out_vrr->adjust.v_total_max =
 462                                         in_out_vrr->adjust.v_total_min;
 463                 } else {
 464                         in_out_vrr->adjust.v_total_min =
 465                                 mod_freesync_calc_v_total_from_refresh(stream,
 466                                         in_out_vrr->max_refresh_in_uhz);
 467                         in_out_vrr->adjust.v_total_max =
 468                                 mod_freesync_calc_v_total_from_refresh(stream,
 469                                         in_out_vrr->min_refresh_in_uhz);
 470                 }
 471         }
 472 }
 473
 474 static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,
 475                 unsigned int curr_time_stamp_in_us)
 476 {
 477         in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -
 478                         in_vrr->flip_interval.v_update_timestamp_in_us;
 479
 480         /* Determine conditions for stopping workaround */
 481         if (in_vrr->flip_interval.flip_interval_workaround_active &&
 482                         in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&
 483                         in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
 484                 in_vrr->flip_interval.flip_interval_detect_counter = 0;
 485                 in_vrr->flip_interval.program_flip_interval_workaround = true;
 486                 in_vrr->flip_interval.flip_interval_workaround_active = false;
 487         } else {
 488                 /* Determine conditions for starting workaround */
 489                 if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&
 490                                 in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
 491                         /* Increase flip interval counter we have 2 vsyncs between flips and
 492                          * vsync to flip interval is less than 500us
 493                          */
 494                         in_vrr->flip_interval.flip_interval_detect_counter++;
 495                         if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {
 496                                 /* Start workaround if we detect 5 consecutive instances of the above case */
 497                                 in_vrr->flip_interval.program_flip_interval_workaround = true;
 498                                 in_vrr->flip_interval.flip_interval_workaround_active = true;
 499                         }
 500                 } else {
 501                         /* Reset the flip interval counter if we condition is no longer met */
 502                         in_vrr->flip_interval.flip_interval_detect_counter = 0;
 503                 }
 504         }
 505
 506         in_vrr->flip_interval.vsyncs_between_flip = 0;
 507 }
 508
 509 static bool vrr_settings_require_update(struct core_freesync *core_freesync,
 510                 struct mod_freesync_config *in_config,
 511                 unsigned int min_refresh_in_uhz,
 512                 unsigned int max_refresh_in_uhz,
 513                 struct mod_vrr_params *in_vrr)
 514 {
 515         if (in_vrr->state != in_config->state) {
 516                 return true;
 517         } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
 518                         in_vrr->fixed.target_refresh_in_uhz !=
 519                                         in_config->fixed_refresh_in_uhz) {
 520                 return true;
 521         } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
 522                 return true;
 523         } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
 524                 return true;
 525         }
 526
 527         return false;
 528 }
 529
 530 bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
 531                 const struct dc_stream_state *stream,
 532                 unsigned int *vmin,
 533                 unsigned int *vmax)
 534 {
 535         *vmin = stream->adjust.v_total_min;
 536         *vmax = stream->adjust.v_total_max;
 537
 538         return true;
 539 }
 540
 541 bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
 542                 struct dc_stream_state *stream,
 543                 unsigned int *nom_v_pos,
 544                 unsigned int *v_pos)
 545 {
 546         struct core_freesync *core_freesync = NULL;
 547         struct crtc_position position;
 548
 549         if (mod_freesync == NULL)
 550                 return false;
 551
 552         core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
 553
 554         if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
 555                                         &position.vertical_count,
 556                                         &position.nominal_vcount)) {
 557
 558                 *nom_v_pos = position.nominal_vcount;
 559                 *v_pos = position.vertical_count;
 560
 561                 return true;
 562         }
 563
 564         return false;
 565 }
 566
 567 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
 568                 struct dc_info_packet *infopacket,
 569                 bool freesync_on_desktop)
 570 {
 571         /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
 572         infopacket->sb[1] = 0x1A;
 573
 574         /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
 575         infopacket->sb[2] = 0x00;
 576
 577         /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
 578         infopacket->sb[3] = 0x00;
 579
 580         /* PB4 = Reserved */
 581
 582         /* PB5 = Reserved */
 583
 584         /* PB6 = [Bits 7:3 = Reserved] */
 585
 586         /* PB6 = [Bit 0 = FreeSync Supported] */
 587         if (vrr->state != VRR_STATE_UNSUPPORTED)
 588                 infopacket->sb[6] |= 0x01;
 589
 590         /* PB6 = [Bit 1 = FreeSync Enabled] */
 591         if (vrr->state != VRR_STATE_DISABLED &&
 592                         vrr->state != VRR_STATE_UNSUPPORTED)
 593                 infopacket->sb[6] |= 0x02;
 594
 595         if (freesync_on_desktop) {
 596                 /* PB6 = [Bit 2 = FreeSync Active] */
 597                 if (vrr->state != VRR_STATE_DISABLED &&
 598                         vrr->state != VRR_STATE_UNSUPPORTED)
 599                         infopacket->sb[6] |= 0x04;
 600         } else {
 601                 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
 602                         vrr->state == VRR_STATE_ACTIVE_FIXED)
 603                         infopacket->sb[6] |= 0x04;
 604         }
 605
 606         // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
 607         /* PB7 = FreeSync Minimum refresh rate (Hz) */
 608         if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
 609                         vrr->state == VRR_STATE_ACTIVE_FIXED) {
 610                 infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);
 611         } else {
 612                 infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
 613         }
 614
 615         /* PB8 = FreeSync Maximum refresh rate (Hz)
 616          * Note: We should never go above the field rate of the mode timing set.
 617          */
 618         infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
 619 }
 620
 621 static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
 622                 struct dc_info_packet *infopacket,
 623                 bool freesync_on_desktop)
 624 {
 625         unsigned int min_refresh;
 626         unsigned int max_refresh;
 627         unsigned int fixed_refresh;
 628         unsigned int min_programmed;
 629
 630         /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
 631         infopacket->sb[1] = 0x1A;
 632
 633         /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
 634         infopacket->sb[2] = 0x00;
 635
 636         /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
 637         infopacket->sb[3] = 0x00;
 638
 639         /* PB4 = Reserved */
 640
 641         /* PB5 = Reserved */
 642
 643         /* PB6 = [Bits 7:3 = Reserved] */
 644
 645         /* PB6 = [Bit 0 = FreeSync Supported] */
 646         if (vrr->state != VRR_STATE_UNSUPPORTED)
 647                 infopacket->sb[6] |= 0x01;
 648
 649         /* PB6 = [Bit 1 = FreeSync Enabled] */
 650         if (vrr->state != VRR_STATE_DISABLED &&
 651                         vrr->state != VRR_STATE_UNSUPPORTED)
 652                 infopacket->sb[6] |= 0x02;
 653
 654         /* PB6 = [Bit 2 = FreeSync Active] */
 655         if (freesync_on_desktop) {
 656                 if (vrr->state != VRR_STATE_DISABLED &&
 657                         vrr->state != VRR_STATE_UNSUPPORTED)
 658                         infopacket->sb[6] |= 0x04;
 659         } else {
 660                 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
 661                         vrr->state == VRR_STATE_ACTIVE_FIXED)
 662                         infopacket->sb[6] |= 0x04;
 663         }
 664
 665         min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;
 666         max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;
 667         fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;
 668
 669         min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
 670                         (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
 671                         (vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
 672                         max_refresh; // Non-fs case, program nominal range
 673
 674         /* PB7 = FreeSync Minimum refresh rate (Hz) */
 675         infopacket->sb[7] = min_programmed & 0xFF;
 676
 677         /* PB8 = FreeSync Maximum refresh rate (Hz) */
 678         infopacket->sb[8] = max_refresh & 0xFF;
 679
 680         /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
 681         infopacket->sb[11] = (min_programmed >> 8) & 0x03;
 682
 683         /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
 684         infopacket->sb[12] = (max_refresh >> 8) & 0x03;
 685
 686         /* PB16 : Reserved bits 7:1, FixedRate bit 0 */
 687         infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
 688 }
 689
 690 static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
 691                 struct dc_info_packet *infopacket)
 692 {
 693         if (app_tf != TRANSFER_FUNC_UNKNOWN) {
 694                 infopacket->valid = true;
 695
 696                 if (app_tf == TRANSFER_FUNC_PQ2084)
 697                         infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
 698                 else {
 699                         infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
 700                         if (app_tf == TRANSFER_FUNC_GAMMA_22)
 701                                 infopacket->sb[9] |= 0x04;  // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
 702                 }
 703         }
 704 }
 705
 706 static void build_vrr_infopacket_header_v1(enum signal_type signal,
 707                 struct dc_info_packet *infopacket,
 708                 unsigned int *payload_size)
 709 {
 710         if (dc_is_hdmi_signal(signal)) {
 711
 712                 /* HEADER */
 713
 714                 /* HB0  = Packet Type = 0x83 (Source Product
 715                  *        Descriptor InfoFrame)
 716                  */
 717                 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
 718
 719                 /* HB1  = Version = 0x01 */
 720                 infopacket->hb1 = 0x01;
 721
 722                 /* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
 723                 infopacket->hb2 = 0x08;
 724
 725                 *payload_size = 0x08;
 726
 727         } else if (dc_is_dp_signal(signal)) {
 728
 729                 /* HEADER */
 730
 731                 /* HB0  = Secondary-data Packet ID = 0 - Only non-zero
 732                  *        when used to associate audio related info packets
 733                  */
 734                 infopacket->hb0 = 0x00;
 735
 736                 /* HB1  = Packet Type = 0x83 (Source Product
 737                  *        Descriptor InfoFrame)
 738                  */
 739                 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
 740
 741                 /* HB2  = [Bits 7:0 = Least significant eight bits -
 742                  *        For INFOFRAME, the value must be 1Bh]
 743                  */
 744                 infopacket->hb2 = 0x1B;
 745
 746                 /* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
 747                  *        [Bits 1:0 = Most significant two bits = 0x00]
 748                  */
 749                 infopacket->hb3 = 0x04;
 750
 751                 *payload_size = 0x1B;
 752         }
 753 }
 754
 755 static void build_vrr_infopacket_header_v2(enum signal_type signal,
 756                 struct dc_info_packet *infopacket,
 757                 unsigned int *payload_size)
 758 {
 759         if (dc_is_hdmi_signal(signal)) {
 760
 761                 /* HEADER */
 762
 763                 /* HB0  = Packet Type = 0x83 (Source Product
 764                  *        Descriptor InfoFrame)
 765                  */
 766                 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
 767
 768                 /* HB1  = Version = 0x02 */
 769                 infopacket->hb1 = 0x02;
 770
 771                 /* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
 772                 infopacket->hb2 = 0x09;
 773
 774                 *payload_size = 0x09;
 775         } else if (dc_is_dp_signal(signal)) {
 776
 777                 /* HEADER */
 778
 779                 /* HB0  = Secondary-data Packet ID = 0 - Only non-zero
 780                  *        when used to associate audio related info packets
 781                  */
 782                 infopacket->hb0 = 0x00;
 783
 784                 /* HB1  = Packet Type = 0x83 (Source Product
 785                  *        Descriptor InfoFrame)
 786                  */
 787                 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
 788
 789                 /* HB2  = [Bits 7:0 = Least significant eight bits -
 790                  *        For INFOFRAME, the value must be 1Bh]
 791                  */
 792                 infopacket->hb2 = 0x1B;
 793
 794                 /* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
 795                  *        [Bits 1:0 = Most significant two bits = 0x00]
 796                  */
 797                 infopacket->hb3 = 0x08;
 798
 799                 *payload_size = 0x1B;
 800         }
 801 }
 802
 803 static void build_vrr_infopacket_header_v3(enum signal_type signal,
 804                 struct dc_info_packet *infopacket,
 805                 unsigned int *payload_size)
 806 {
 807         unsigned char version;
 808
 809         version = 3;
 810         if (dc_is_hdmi_signal(signal)) {
 811
 812                 /* HEADER */
 813
 814                 /* HB0  = Packet Type = 0x83 (Source Product
 815                  *        Descriptor InfoFrame)
 816                  */
 817                 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
 818
 819                 /* HB1  = Version = 0x03 */
 820                 infopacket->hb1 = version;
 821
 822                 /* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length] */
 823                 infopacket->hb2 = 0x10;
 824
 825                 *payload_size = 0x10;
 826         } else if (dc_is_dp_signal(signal)) {
 827
 828                 /* HEADER */
 829
 830                 /* HB0  = Secondary-data Packet ID = 0 - Only non-zero
 831                  *        when used to associate audio related info packets
 832                  */
 833                 infopacket->hb0 = 0x00;
 834
 835                 /* HB1  = Packet Type = 0x83 (Source Product
 836                  *        Descriptor InfoFrame)
 837                  */
 838                 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
 839
 840                 /* HB2  = [Bits 7:0 = Least significant eight bits -
 841                  *        For INFOFRAME, the value must be 1Bh]
 842                  */
 843                 infopacket->hb2 = 0x1B;
 844
 845                 /* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
 846                  *        [Bits 1:0 = Most significant two bits = 0x00]
 847                  */
 848
 849                 infopacket->hb3 = (version & 0x3F) << 2;
 850
 851                 *payload_size = 0x1B;
 852         }
 853 }
 854
 855 static void build_vrr_infopacket_checksum(unsigned int *payload_size,
 856                 struct dc_info_packet *infopacket)
 857 {
 858         /* Calculate checksum */
 859         unsigned int idx = 0;
 860         unsigned char checksum = 0;
 861
 862         checksum += infopacket->hb0;
 863         checksum += infopacket->hb1;
 864         checksum += infopacket->hb2;
 865         checksum += infopacket->hb3;
 866
 867         for (idx = 1; idx <= *payload_size; idx++)
 868                 checksum += infopacket->sb[idx];
 869
 870         /* PB0 = Checksum (one byte complement) */
 871         infopacket->sb[0] = (unsigned char)(0x100 - checksum);
 872
 873         infopacket->valid = true;
 874 }
 875
 876 static void build_vrr_infopacket_v1(enum signal_type signal,
 877                 const struct mod_vrr_params *vrr,
 878                 struct dc_info_packet *infopacket,
 879                 bool freesync_on_desktop)
 880 {
 881         /* SPD info packet for FreeSync */
 882         unsigned int payload_size = 0;
 883
 884         build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
 885         build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 886         build_vrr_infopacket_checksum(&payload_size, infopacket);
 887
 888         infopacket->valid = true;
 889 }
 890
 891 static void build_vrr_infopacket_v2(enum signal_type signal,
 892                 const struct mod_vrr_params *vrr,
 893                 enum color_transfer_func app_tf,
 894                 struct dc_info_packet *infopacket,
 895                 bool freesync_on_desktop)
 896 {
 897         unsigned int payload_size = 0;
 898
 899         build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
 900         build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
 901
 902         build_vrr_infopacket_fs2_data(app_tf, infopacket);
 903
 904         build_vrr_infopacket_checksum(&payload_size, infopacket);
 905
 906         infopacket->valid = true;
 907 }
 908
 909 static void build_vrr_infopacket_v3(enum signal_type signal,
 910                 const struct mod_vrr_params *vrr,
 911                 enum color_transfer_func app_tf,
 912                 struct dc_info_packet *infopacket,
 913                 bool freesync_on_desktop)
 914 {
 915         unsigned int payload_size = 0;
 916
 917         build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);
 918         build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);
 919
 920         build_vrr_infopacket_fs2_data(app_tf, infopacket);
 921
 922         build_vrr_infopacket_checksum(&payload_size, infopacket);
 923
 924         infopacket->valid = true;
 925 }
 926
 927 static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,
 928                                                                                 struct dc_info_packet *infopacket)
 929 {
 930         uint8_t idx = 0, size = 0;
 931
 932         size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :
 933                         (packet_type == PACKET_TYPE_FS_V3) ? 0x10 :
 934                                                                                                 0x09);
 935
 936         for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B
 937                 infopacket->sb[idx] = infopacket->sb[idx-1];
 938
 939         infopacket->sb[1] = size;                         // Length
 940         infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version
 941         infopacket->hb3   = (0x13 << 2);                  // Header,SDP 1.3
 942         infopacket->hb2   = 0x1D;
 943 }
 944
 945 void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
 946                 const struct dc_stream_state *stream,
 947                 const struct mod_vrr_params *vrr,
 948                 enum vrr_packet_type packet_type,
 949                 enum color_transfer_func app_tf,
 950                 struct dc_info_packet *infopacket,
 951                 bool pack_sdp_v1_3)
 952 {
 953         /* SPD info packet for FreeSync
 954          * VTEM info packet for HdmiVRR
 955          * Check if Freesync is supported. Return if false. If true,
 956          * set the corresponding bit in the info packet
 957          */
 958         if (!vrr->send_info_frame)
 959                 return;
 960
 961         switch (packet_type) {
 962         case PACKET_TYPE_FS_V3:
 963                 build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
 964                 break;
 965         case PACKET_TYPE_FS_V2:
 966                 build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
 967                 break;
 968         case PACKET_TYPE_VRR:
 969         case PACKET_TYPE_FS_V1:
 970         default:
 971                 build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
 972         }
 973
 974         if (true == pack_sdp_v1_3 &&
 975                 true == dc_is_dp_signal(stream->signal) &&
 976                 packet_type != PACKET_TYPE_VRR &&
 977                 packet_type != PACKET_TYPE_VTEM)
 978                 build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);
 979 }
 980
 981 void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
 982                 const struct dc_stream_state *stream,
 983                 struct mod_freesync_config *in_config,
 984                 struct mod_vrr_params *in_out_vrr)
 985 {
 986         struct core_freesync *core_freesync = NULL;
 987         unsigned long long nominal_field_rate_in_uhz = 0;
 988         unsigned long long rounded_nominal_in_uhz = 0;
 989         unsigned int refresh_range = 0;
 990         unsigned long long min_refresh_in_uhz = 0;
 991         unsigned long long max_refresh_in_uhz = 0;
 992         unsigned long long min_hardware_refresh_in_uhz = 0;
 993
 994         if (mod_freesync == NULL)
 995                 return;
 996
 997         core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
 998
 999         /* Calculate nominal field rate for stream */
1000         nominal_field_rate_in_uhz =
1001                         mod_freesync_calc_nominal_field_rate(stream);
1002
1003         if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
1004                 min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
1005                         (stream->timing.h_total * stream->ctx->dc->caps.max_v_total));
1006         }
1007         /* Limit minimum refresh rate to what can be supported by hardware */
1008         min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
1009                 min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
1010         max_refresh_in_uhz = in_config->max_refresh_in_uhz;
1011
1012         /* Full range may be larger than current video timing, so cap at nominal */
1013         if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
1014                 max_refresh_in_uhz = nominal_field_rate_in_uhz;
1015
1016         /* Full range may be larger than current video timing, so cap at nominal */
1017         if (min_refresh_in_uhz > max_refresh_in_uhz)
1018                 min_refresh_in_uhz = max_refresh_in_uhz;
1019
1020         /* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
1021         rounded_nominal_in_uhz =
1022                         div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
1023         if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
1024                 in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
1025                 min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
1026
1027         if (!vrr_settings_require_update(core_freesync,
1028                         in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
1029                         in_out_vrr))
1030                 return;
1031
1032         in_out_vrr->state = in_config->state;
1033         in_out_vrr->send_info_frame = in_config->vsif_supported;
1034
1035         if (in_config->state == VRR_STATE_UNSUPPORTED) {
1036                 in_out_vrr->state = VRR_STATE_UNSUPPORTED;
1037                 in_out_vrr->supported = false;
1038                 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1039                 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1040
1041                 return;
1042
1043         } else {
1044                 in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
1045                 in_out_vrr->max_duration_in_us =
1046                                 calc_duration_in_us_from_refresh_in_uhz(
1047                                                 (unsigned int)min_refresh_in_uhz);
1048
1049                 in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
1050                 in_out_vrr->min_duration_in_us =
1051                                 calc_duration_in_us_from_refresh_in_uhz(
1052                                                 (unsigned int)max_refresh_in_uhz);
1053
1054                 if (in_config->state == VRR_STATE_ACTIVE_FIXED)
1055                         in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;
1056                 else
1057                         in_out_vrr->fixed_refresh_in_uhz = 0;
1058
1059                 refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
1060 +                               div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
1061
1062                 in_out_vrr->supported = true;
1063         }
1064
1065         in_out_vrr->fixed.ramping_active = in_config->ramping;
1066
1067         in_out_vrr->btr.btr_enabled = in_config->btr;
1068
1069         if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))
1070                 in_out_vrr->btr.btr_enabled = false;
1071         else {
1072                 in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
1073                                 2 * in_out_vrr->min_duration_in_us;
1074                 if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
1075                         in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
1076         }
1077
1078         in_out_vrr->btr.btr_active = false;
1079         in_out_vrr->btr.inserted_duration_in_us = 0;
1080         in_out_vrr->btr.frames_to_insert = 0;
1081         in_out_vrr->btr.frame_counter = 0;
1082         in_out_vrr->fixed.fixed_active = false;
1083         in_out_vrr->fixed.target_refresh_in_uhz = 0;
1084
1085         in_out_vrr->btr.mid_point_in_us =
1086                                 (in_out_vrr->min_duration_in_us +
1087                                  in_out_vrr->max_duration_in_us) / 2;
1088
1089         if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
1090                 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1091                 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1092         } else if (in_out_vrr->state == VRR_STATE_DISABLED) {
1093                 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1094                 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1095         } else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1096                 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1097                 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1098         } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1099                         refresh_range >= MIN_REFRESH_RANGE) {
1100
1101                 in_out_vrr->adjust.v_total_min =
1102                         mod_freesync_calc_v_total_from_refresh(stream,
1103                                 in_out_vrr->max_refresh_in_uhz);
1104                 in_out_vrr->adjust.v_total_max =
1105                         mod_freesync_calc_v_total_from_refresh(stream,
1106                                 in_out_vrr->min_refresh_in_uhz);
1107         } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
1108                 in_out_vrr->fixed.target_refresh_in_uhz =
1109                                 in_out_vrr->fixed_refresh_in_uhz;
1110                 if (in_out_vrr->fixed.ramping_active &&
1111                                 in_out_vrr->fixed.fixed_active) {
1112                         /* Do not update vtotals if ramping is already active
1113                          * in order to continue ramp from current refresh.
1114                          */
1115                         in_out_vrr->fixed.fixed_active = true;
1116                 } else {
1117                         in_out_vrr->fixed.fixed_active = true;
1118                         in_out_vrr->adjust.v_total_min =
1119                                 mod_freesync_calc_v_total_from_refresh(stream,
1120                                         in_out_vrr->fixed.target_refresh_in_uhz);
1121                         in_out_vrr->adjust.v_total_max =
1122                                 in_out_vrr->adjust.v_total_min;
1123                 }
1124         } else {
1125                 in_out_vrr->state = VRR_STATE_INACTIVE;
1126                 in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1127                 in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1128         }
1129 }
1130
1131 void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
1132                 const struct dc_plane_state *plane,
1133                 const struct dc_stream_state *stream,
1134                 unsigned int curr_time_stamp_in_us,
1135                 struct mod_vrr_params *in_out_vrr)
1136 {
1137         struct core_freesync *core_freesync = NULL;
1138         unsigned int last_render_time_in_us = 0;
1139
1140         if (mod_freesync == NULL)
1141                 return;
1142
1143         core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1144
1145         if (in_out_vrr->supported &&
1146                         in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
1147
1148                 last_render_time_in_us = curr_time_stamp_in_us -
1149                                 plane->time.prev_update_time_in_us;
1150
1151                 if (in_out_vrr->btr.btr_enabled) {
1152                         apply_below_the_range(core_freesync,
1153                                         stream,
1154                                         last_render_time_in_us,
1155                                         in_out_vrr);
1156                 } else {
1157                         apply_fixed_refresh(core_freesync,
1158                                 stream,
1159                                 last_render_time_in_us,
1160                                 in_out_vrr);
1161                 }
1162
1163                 determine_flip_interval_workaround_req(in_out_vrr,
1164                                 curr_time_stamp_in_us);
1165
1166         }
1167 }
1168
1169 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
1170                 const struct dc_stream_state *stream,
1171                 struct mod_vrr_params *in_out_vrr)
1172 {
1173         struct core_freesync *core_freesync = NULL;
1174         unsigned int cur_timestamp_in_us;
1175         unsigned long long cur_tick;
1176
1177         if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
1178                 return;
1179
1180         core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1181
1182         if (in_out_vrr->supported == false)
1183                 return;
1184
1185         cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
1186         cur_timestamp_in_us = (unsigned int)
1187                         div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
1188
1189         in_out_vrr->flip_interval.vsyncs_between_flip++;
1190         in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
1191
1192         if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1193                         (in_out_vrr->flip_interval.flip_interval_workaround_active ||
1194                         (!in_out_vrr->flip_interval.flip_interval_workaround_active &&
1195                         in_out_vrr->flip_interval.program_flip_interval_workaround))) {
1196                 // set freesync vmin vmax to nominal for workaround
1197                 in_out_vrr->adjust.v_total_min =
1198                         mod_freesync_calc_v_total_from_refresh(
1199                         stream, in_out_vrr->max_refresh_in_uhz);
1200                 in_out_vrr->adjust.v_total_max =
1201                                 in_out_vrr->adjust.v_total_min;
1202                 in_out_vrr->flip_interval.program_flip_interval_workaround = false;
1203                 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;
1204                 return;
1205         }
1206
1207         if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&
1208                         in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {
1209                 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
1210                 in_out_vrr->flip_interval.flip_interval_detect_counter = 0;
1211                 in_out_vrr->flip_interval.vsyncs_between_flip = 0;
1212                 in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;
1213         }
1214
1215         /* Below the Range Logic */
1216
1217         /* Only execute if in fullscreen mode */
1218         if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1219                                         in_out_vrr->btr.btr_active) {
1220                 /* TODO: pass in flag for Pre-DCE12 ASIC
1221                  * in order for frame variable duration to take affect,
1222                  * it needs to be done one VSYNC early, which is at
1223                  * frameCounter == 1.
1224                  * For DCE12 and newer updates to V_TOTAL_MIN/MAX
1225                  * will take affect on current frame
1226                  */
1227                 if (in_out_vrr->btr.frames_to_insert ==
1228                                 in_out_vrr->btr.frame_counter) {
1229                         in_out_vrr->adjust.v_total_min =
1230                                 calc_v_total_from_duration(stream,
1231                                 in_out_vrr,
1232                                 in_out_vrr->btr.inserted_duration_in_us);
1233                         in_out_vrr->adjust.v_total_max =
1234                                 in_out_vrr->adjust.v_total_min;
1235                 }
1236
1237                 if (in_out_vrr->btr.frame_counter > 0)
1238                         in_out_vrr->btr.frame_counter--;
1239
1240                 /* Restore FreeSync */
1241                 if (in_out_vrr->btr.frame_counter == 0) {
1242                         in_out_vrr->adjust.v_total_min =
1243                                 mod_freesync_calc_v_total_from_refresh(stream,
1244                                 in_out_vrr->max_refresh_in_uhz);
1245                         in_out_vrr->adjust.v_total_max =
1246                                 mod_freesync_calc_v_total_from_refresh(stream,
1247                                 in_out_vrr->min_refresh_in_uhz);
1248                 }
1249         }
1250
1251         /* If in fullscreen freesync mode or in video, do not program
1252          * static screen ramp values
1253          */
1254         if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
1255                 in_out_vrr->fixed.ramping_active = false;
1256
1257         /* Gradual Static Screen Ramping Logic
1258          * Execute if ramp is active and user enabled freesync static screen
1259          */
1260         if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
1261                                 in_out_vrr->fixed.ramping_active) {
1262                 update_v_total_for_static_ramp(
1263                                 core_freesync, stream, in_out_vrr);
1264         }
1265 }
1266
1267 void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
1268                 const struct mod_vrr_params *vrr,
1269                 unsigned int *v_total_min, unsigned int *v_total_max,
1270                 unsigned int *event_triggers,
1271                 unsigned int *window_min, unsigned int *window_max,
1272                 unsigned int *lfc_mid_point_in_us,
1273                 unsigned int *inserted_frames,
1274                 unsigned int *inserted_duration_in_us)
1275 {
1276         if (mod_freesync == NULL)
1277                 return;
1278
1279         if (vrr->supported) {
1280                 *v_total_min = vrr->adjust.v_total_min;
1281                 *v_total_max = vrr->adjust.v_total_max;
1282                 *event_triggers = 0;
1283                 *lfc_mid_point_in_us = vrr->btr.mid_point_in_us;
1284                 *inserted_frames = vrr->btr.frames_to_insert;
1285                 *inserted_duration_in_us = vrr->btr.inserted_duration_in_us;
1286         }
1287 }
1288
1289 unsigned long long mod_freesync_calc_nominal_field_rate(
1290                         const struct dc_stream_state *stream)
1291 {
1292         unsigned long long nominal_field_rate_in_uhz = 0;
1293         unsigned int total = stream->timing.h_total * stream->timing.v_total;
1294
1295         /* Calculate nominal field rate for stream, rounded up to nearest integer */
1296         nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
1297         nominal_field_rate_in_uhz *= 100000000ULL;
1298
1299         nominal_field_rate_in_uhz =     div_u64(nominal_field_rate_in_uhz, total);
1300
1301         return nominal_field_rate_in_uhz;
1302 }
1303
1304 unsigned long long mod_freesync_calc_field_rate_from_timing(
1305                 unsigned int vtotal, unsigned int htotal, unsigned int pix_clk)
1306 {
1307         unsigned long long field_rate_in_uhz = 0;
1308         unsigned int total = htotal * vtotal;
1309
1310         /* Calculate nominal field rate for stream, rounded up to nearest integer */
1311         field_rate_in_uhz = pix_clk;
1312         field_rate_in_uhz *= 1000000ULL;
1313
1314         field_rate_in_uhz =     div_u64(field_rate_in_uhz, total);
1315
1316         return field_rate_in_uhz;
1317 }
1318
1319 bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
1320 {
1321         return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
1322 }
1323
1324 bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
1325                 uint32_t max_refresh_cap_in_uhz,
1326                 uint32_t nominal_field_rate_in_uhz)
1327 {
1328
1329         /* Typically nominal refresh calculated can have some fractional part.
1330          * Allow for some rounding error of actual video timing by taking floor
1331          * of caps and request. Round the nominal refresh rate.
1332          *
1333          * Dividing will convert everything to units in Hz although input
1334          * variable name is in uHz!
1335          *
1336          * Also note, this takes care of rounding error on the nominal refresh
1337          * so by rounding error we only expect it to be off by a small amount,
1338          * such as < 0.1 Hz. i.e. 143.9xxx or 144.1xxx.
1339          *
1340          * Example 1. Caps    Min = 40 Hz, Max = 144 Hz
1341          *            Request Min = 40 Hz, Max = 144 Hz
1342          *                    Nominal = 143.5x Hz rounded to 144 Hz
1343          *            This function should allow this as valid request
1344          *
1345          * Example 2. Caps    Min = 40 Hz, Max = 144 Hz
1346          *            Request Min = 40 Hz, Max = 144 Hz
1347          *                    Nominal = 144.4x Hz rounded to 144 Hz
1348          *            This function should allow this as valid request
1349          *
1350          * Example 3. Caps    Min = 40 Hz, Max = 144 Hz
1351          *            Request Min = 40 Hz, Max = 144 Hz
1352          *                    Nominal = 120.xx Hz rounded to 120 Hz
1353          *            This function should return NOT valid since the requested
1354          *            max is greater than current timing's nominal
1355          *
1356          * Example 4. Caps    Min = 40 Hz, Max = 120 Hz
1357          *            Request Min = 40 Hz, Max = 120 Hz
1358          *                    Nominal = 144.xx Hz rounded to 144 Hz
1359          *            This function should return NOT valid since the nominal
1360          *            is greater than the capability's max refresh
1361          */
1362         nominal_field_rate_in_uhz =
1363                         div_u64(nominal_field_rate_in_uhz + 500000, 1000000);
1364         min_refresh_cap_in_uhz /= 1000000;
1365         max_refresh_cap_in_uhz /= 1000000;
1366
1367         /* Check nominal is within range */
1368         if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
1369                 nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
1370                 return false;
1371
1372         /* If nominal is less than max, limit the max allowed refresh rate */
1373         if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz)
1374                 max_refresh_cap_in_uhz = nominal_field_rate_in_uhz;
1375
1376         /* Check min is within range */
1377         if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz)
1378                 return false;
1379
1380         /* For variable range, check for at least 10 Hz range */
1381         if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10)
1382                 return false;
1383
1384         return true;
1385 }