1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/plat-iop/pci.c
5 * PCI support for the Intel IOP32X and IOP33X processors
8 * Copyright (C) 2002 Rory Bolt
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/ioport.h>
19 #include <asm/signal.h>
20 #include <asm/mach/pci.h>
27 #define DBG(x...) printk(x)
29 #define DBG(x...) do { } while (0)
33 * This routine builds either a type0 or type1 configuration command. If the
34 * bus is on the 803xx then a type0 made, else a type1 is created.
36 static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
38 struct pci_sys_data *sys = bus->sysdata;
41 if (sys->busnr == bus->number)
42 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
44 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
46 addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
52 * This routine checks the status of the last configuration cycle. If an error
53 * was detected it returns a 1, else it returns a 0. The errors being checked
54 * are parity, master abort, target abort (master and target). These types of
55 * errors occur during a config cycle where there is no device, like during
56 * the discovery stage.
58 static int iop3xx_pci_status(void)
64 * Check the status registers.
66 status = *IOP3XX_ATUSR;
67 if (status & 0xf900) {
68 DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
69 *IOP3XX_ATUSR = status & 0xf900;
73 status = *IOP3XX_ATUISR;
74 if (status & 0x679f) {
75 DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
76 *IOP3XX_ATUISR = status & 0x679f;
84 * Simply write the address register and read the configuration
85 * data. Note that the 4 nops ensure that we are able to handle
86 * a delayed abort (in theory.)
88 static u32 iop3xx_read(unsigned long addr)
100 : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
106 * The read routines must check the error status of the last configuration
107 * cycle. If there was an error, the routine returns all hex f's.
110 iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
111 int size, u32 *value)
113 unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
114 u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
116 if (iop3xx_pci_status())
121 return PCIBIOS_SUCCESSFUL;
125 iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
128 unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
132 val = iop3xx_read(addr);
133 if (iop3xx_pci_status())
134 return PCIBIOS_SUCCESSFUL;
136 where = (where & 3) * 8;
139 val &= ~(0xff << where);
141 val &= ~(0xffff << where);
143 *IOP3XX_OCCDR = val | value << where;
153 : "r" (value), "r" (addr),
154 "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
157 return PCIBIOS_SUCCESSFUL;
160 struct pci_ops iop3xx_ops = {
161 .read = iop3xx_read_config,
162 .write = iop3xx_write_config,
166 * When a PCI device does not exist during config cycles, the 80200 gets a
167 * bus error instead of returning 0xffffffff. This handler simply returns.
170 iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
172 DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
173 addr, fsr, regs->ARM_pc, regs->ARM_lr);
176 * If it was an imprecise abort, then we need to correct the
177 * return address to be _after_ the instruction.
185 int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
187 struct resource *res;
192 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
194 panic("PCI: unable to alloc resources");
196 res->start = IOP3XX_PCI_LOWER_MEM_PA;
197 res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
198 res->name = "IOP3XX PCI Memory Space";
199 res->flags = IORESOURCE_MEM;
200 request_resource(&iomem_resource, res);
203 * Use whatever translation is already setup.
205 sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
207 pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
209 pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
214 void __init iop3xx_atu_setup(void)
216 /* BAR 0 ( Disabled ) */
217 *IOP3XX_IAUBAR0 = 0x0;
218 *IOP3XX_IABAR0 = 0x0;
219 *IOP3XX_IATVR0 = 0x0;
222 /* BAR 1 ( Disabled ) */
223 *IOP3XX_IAUBAR1 = 0x0;
224 *IOP3XX_IABAR1 = 0x0;
227 /* BAR 2 (1:1 mapping with Physical RAM) */
228 /* Set limit and enable */
229 *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
230 *IOP3XX_IAUBAR2 = 0x0;
232 /* Align the inbound bar with the base of memory */
233 *IOP3XX_IABAR2 = PHYS_OFFSET |
234 PCI_BASE_ADDRESS_MEM_TYPE_64 |
235 PCI_BASE_ADDRESS_MEM_PREFETCH;
237 *IOP3XX_IATVR2 = PHYS_OFFSET;
239 /* Outbound window 0 */
240 *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
241 *IOP3XX_OUMWTVR0 = 0;
243 /* Outbound window 1 */
244 *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA +
245 IOP3XX_PCI_MEM_WINDOW_SIZE / 2;
246 *IOP3XX_OUMWTVR1 = 0;
248 /* BAR 3 ( Disabled ) */
249 *IOP3XX_IAUBAR3 = 0x0;
250 *IOP3XX_IABAR3 = 0x0;
251 *IOP3XX_IATVR3 = 0x0;
256 *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
258 /* Enable inbound and outbound cycles
260 *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
261 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
262 *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
265 void __init iop3xx_atu_disable(void)
270 /* wait for cycles to quiesce */
271 while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
272 IOP3XX_PCSR_IN_Q_BUSY))
275 /* BAR 0 ( Disabled ) */
276 *IOP3XX_IAUBAR0 = 0x0;
277 *IOP3XX_IABAR0 = 0x0;
278 *IOP3XX_IATVR0 = 0x0;
281 /* BAR 1 ( Disabled ) */
282 *IOP3XX_IAUBAR1 = 0x0;
283 *IOP3XX_IABAR1 = 0x0;
286 /* BAR 2 ( Disabled ) */
287 *IOP3XX_IAUBAR2 = 0x0;
288 *IOP3XX_IABAR2 = 0x0;
289 *IOP3XX_IATVR2 = 0x0;
292 /* BAR 3 ( Disabled ) */
293 *IOP3XX_IAUBAR3 = 0x0;
294 *IOP3XX_IABAR3 = 0x0;
295 *IOP3XX_IATVR3 = 0x0;
298 /* Clear the outbound windows */
301 /* Outbound window 0 */
303 *IOP3XX_OUMWTVR0 = 0;
305 /* Outbound window 1 */
307 *IOP3XX_OUMWTVR1 = 0;
310 /* Flag to determine whether the ATU is initialized and the PCI bus scanned */
313 int iop3xx_get_init_atu(void) {
314 /* check if default has been overridden */
315 if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
318 return IOP3XX_INIT_ATU_DISABLE;
321 static void __init iop3xx_atu_debug(void)
323 DBG("PCI: Intel IOP3xx PCI init.\n");
324 DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
325 *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
326 DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
327 *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
328 DBG("PCI: Outbound IO window: PCI 0x%08x\n",
331 DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
332 *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
333 DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
334 *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
335 DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
336 *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
337 DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
338 *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
340 DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
341 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
343 DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
344 DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
346 hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
349 /* for platforms that might be host-bus-adapters */
350 void __init iop3xx_pci_preinit_cond(void)
352 if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
353 iop3xx_atu_disable();
359 void __init iop3xx_pci_preinit(void)
363 iop3xx_atu_disable();
368 /* allow init_atu to be user overridden */
369 static int __init iop3xx_init_atu_setup(char *str)
371 init_atu = IOP3XX_INIT_ATU_DEFAULT;
373 while (*str != '\0') {
377 init_atu = IOP3XX_INIT_ATU_ENABLE;
381 init_atu = IOP3XX_INIT_ATU_DISABLE;
387 printk(KERN_DEBUG "\"%s\" malformed at "
400 __setup("iop3xx_init_atu", iop3xx_init_atu_setup);