2 * DaVinci Voice Codec Core Interface for TI platforms
4 * Copyright (C) 2010 Texas Instruments, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
24 #define __LINUX_MFD_DAVINIC_VOICECODEC_H_
26 #include <linux/kernel.h>
27 #include <linux/platform_device.h>
28 #include <linux/mfd/core.h>
29 #include <linux/platform_data/edma.h>
31 #include <mach/hardware.h>
38 #define DAVINCI_VC_PID 0x00
39 #define DAVINCI_VC_CTRL 0x04
40 #define DAVINCI_VC_INTEN 0x08
41 #define DAVINCI_VC_INTSTATUS 0x0c
42 #define DAVINCI_VC_INTCLR 0x10
43 #define DAVINCI_VC_EMUL_CTRL 0x14
44 #define DAVINCI_VC_RFIFO 0x20
45 #define DAVINCI_VC_WFIFO 0x24
46 #define DAVINCI_VC_FIFOSTAT 0x28
47 #define DAVINCI_VC_TST_CTRL 0x2C
48 #define DAVINCI_VC_REG05 0x94
49 #define DAVINCI_VC_REG09 0xA4
50 #define DAVINCI_VC_REG12 0xB0
52 /* DAVINCI_VC_CTRL bit fields */
53 #define DAVINCI_VC_CTRL_MASK 0x5500
54 #define DAVINCI_VC_CTRL_RSTADC BIT(0)
55 #define DAVINCI_VC_CTRL_RSTDAC BIT(1)
56 #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
57 #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
58 #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
59 #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
60 #define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
61 #define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
62 #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
63 #define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
64 #define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
65 #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
67 /* DAVINCI_VC_INT bit fields */
68 #define DAVINCI_VC_INT_MASK 0x3F
69 #define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
70 #define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
71 #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
72 #define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
73 #define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
74 #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
76 /* DAVINCI_VC_REG05 bit fields */
77 #define DAVINCI_VC_REG05_PGA_GAIN 0x07
79 /* DAVINCI_VC_REG09 bit fields */
80 #define DAVINCI_VC_REG09_MUTE 0x40
81 #define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
83 /* DAVINCI_VC_REG12 bit fields */
84 #define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
85 #define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
87 #define DAVINCI_VC_CELLS 2
89 enum davinci_vc_cells {
91 DAVINCI_VC_CQ93VC_CELL,
95 struct platform_device *pdev;
98 dma_addr_t dma_tx_addr;
99 dma_addr_t dma_rx_addr;
103 struct platform_device *pdev;
104 struct snd_soc_codec *codec;
113 struct platform_device *pdev;
116 /* Memory resources */
118 struct regmap *regmap;
121 struct mfd_cell cells[DAVINCI_VC_CELLS];
124 struct davinci_vcif davinci_vcif;
125 struct cq93vc cq93vc;