drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* exynos_drm_fimd.c
   3  *
   4  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   5  * Authors:
   6  *      Joonyoung Shim <[email protected]>
   7  *      Inki Dae <[email protected]>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19
  20 #include <video/of_display_timing.h>
  21 #include <video/of_videomode.h>
  22 #include <video/samsung_fimd.h>
  23
  24 #include <drm/drm_fourcc.h>
  25 #include <drm/drm_vblank.h>
  26 #include <drm/exynos_drm.h>
  27
  28 #include "exynos_drm_crtc.h"
  29 #include "exynos_drm_drv.h"
  30 #include "exynos_drm_fb.h"
  31 #include "exynos_drm_plane.h"
  32
  33 /*
  34  * FIMD stands for Fully Interactive Mobile Display and
  35  * as a display controller, it transfers contents drawn on memory
  36  * to a LCD Panel through Display Interfaces such as RGB or
  37  * CPU Interface.
  38  */
  39
  40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  41
  42 /* position control register for hardware window 0, 2 ~ 4.*/
  43 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  44 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  45 /*
  46  * size control register for hardware windows 0 and alpha control register
  47  * for hardware windows 1 ~ 4
  48  */
  49 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  50 /* size control register for hardware windows 1 ~ 2. */
  51 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  52
  53 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  54 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  55
  56 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  57 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  58 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  59 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  60
  61 /* color key control register for hardware window 1 ~ 4. */
  62 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  63 /* color key value register for hardware window 1 ~ 4. */
  64 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  65
  66 /* I80 trigger control register */
  67 #define TRIGCON                         0x1A4
  68 #define TRGMODE_ENABLE                  (1 << 0)
  69 #define SWTRGCMD_ENABLE                 (1 << 1)
  70 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
  71 #define HWTRGEN_ENABLE                  (1 << 3)
  72 #define HWTRGMASK_ENABLE                (1 << 4)
  73 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
  74 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  75
  76 /* display mode change control register except exynos4 */
  77 #define VIDOUT_CON                      0x000
  78 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  79
  80 /* I80 interface control for main LDI register */
  81 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  82 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  83 #define LCD_CS_SETUP(x)                 ((x) << 16)
  84 #define LCD_WR_SETUP(x)                 ((x) << 12)
  85 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  86 #define LCD_WR_HOLD(x)                  ((x) << 4)
  87 #define I80IFEN_ENABLE                  (1 << 0)
  88
  89 /* FIMD has totally five hardware windows. */
  90 #define WINDOWS_NR      5
  91
  92 /* HW trigger flag on i80 panel. */
  93 #define I80_HW_TRG     (1 << 1)
  94
  95 struct fimd_driver_data {
  96         unsigned int timing_base;
  97         unsigned int lcdblk_offset;
  98         unsigned int lcdblk_vt_shift;
  99         unsigned int lcdblk_bypass_shift;
 100         unsigned int lcdblk_mic_bypass_shift;
 101         unsigned int trg_type;
 102
 103         unsigned int has_shadowcon:1;
 104         unsigned int has_clksel:1;
 105         unsigned int has_limited_fmt:1;
 106         unsigned int has_vidoutcon:1;
 107         unsigned int has_vtsel:1;
 108         unsigned int has_mic_bypass:1;
 109         unsigned int has_dp_clk:1;
 110         unsigned int has_hw_trigger:1;
 111         unsigned int has_trigger_per_te:1;
 112 };
 113
 114 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 115         .timing_base = 0x0,
 116         .has_clksel = 1,
 117         .has_limited_fmt = 1,
 118 };
 119
 120 static struct fimd_driver_data s5pv210_fimd_driver_data = {
 121         .timing_base = 0x0,
 122         .has_shadowcon = 1,
 123         .has_clksel = 1,
 124 };
 125
 126 static struct fimd_driver_data exynos3_fimd_driver_data = {
 127         .timing_base = 0x20000,
 128         .lcdblk_offset = 0x210,
 129         .lcdblk_bypass_shift = 1,
 130         .has_shadowcon = 1,
 131         .has_vidoutcon = 1,
 132 };
 133
 134 static struct fimd_driver_data exynos4_fimd_driver_data = {
 135         .timing_base = 0x0,
 136         .lcdblk_offset = 0x210,
 137         .lcdblk_vt_shift = 10,
 138         .lcdblk_bypass_shift = 1,
 139         .has_shadowcon = 1,
 140         .has_vtsel = 1,
 141 };
 142
 143 static struct fimd_driver_data exynos5_fimd_driver_data = {
 144         .timing_base = 0x20000,
 145         .lcdblk_offset = 0x214,
 146         .lcdblk_vt_shift = 24,
 147         .lcdblk_bypass_shift = 15,
 148         .has_shadowcon = 1,
 149         .has_vidoutcon = 1,
 150         .has_vtsel = 1,
 151         .has_dp_clk = 1,
 152 };
 153
 154 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 155         .timing_base = 0x20000,
 156         .lcdblk_offset = 0x214,
 157         .lcdblk_vt_shift = 24,
 158         .lcdblk_bypass_shift = 15,
 159         .lcdblk_mic_bypass_shift = 11,
 160         .has_shadowcon = 1,
 161         .has_vidoutcon = 1,
 162         .has_vtsel = 1,
 163         .has_mic_bypass = 1,
 164         .has_dp_clk = 1,
 165 };
 166
 167 struct fimd_context {
 168         struct device                   *dev;
 169         struct drm_device               *drm_dev;
 170         void                            *dma_priv;
 171         struct exynos_drm_crtc          *crtc;
 172         struct exynos_drm_plane         planes[WINDOWS_NR];
 173         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 174         struct clk                      *bus_clk;
 175         struct clk                      *lcd_clk;
 176         void __iomem                    *regs;
 177         struct regmap                   *sysreg;
 178         unsigned long                   irq_flags;
 179         u32                             vidcon0;
 180         u32                             vidcon1;
 181         u32                             vidout_con;
 182         u32                             i80ifcon;
 183         bool                            i80_if;
 184         bool                            suspended;
 185         wait_queue_head_t               wait_vsync_queue;
 186         atomic_t                        wait_vsync_event;
 187         atomic_t                        win_updated;
 188         atomic_t                        triggering;
 189         u32                             clkdiv;
 190
 191         const struct fimd_driver_data *driver_data;
 192         struct drm_encoder *encoder;
 193         struct exynos_drm_clk           dp_clk;
 194 };
 195
 196 static const struct of_device_id fimd_driver_dt_match[] = {
 197         { .compatible = "samsung,s3c6400-fimd",
 198           .data = &s3c64xx_fimd_driver_data },
 199         { .compatible = "samsung,s5pv210-fimd",
 200           .data = &s5pv210_fimd_driver_data },
 201         { .compatible = "samsung,exynos3250-fimd",
 202           .data = &exynos3_fimd_driver_data },
 203         { .compatible = "samsung,exynos4210-fimd",
 204           .data = &exynos4_fimd_driver_data },
 205         { .compatible = "samsung,exynos5250-fimd",
 206           .data = &exynos5_fimd_driver_data },
 207         { .compatible = "samsung,exynos5420-fimd",
 208           .data = &exynos5420_fimd_driver_data },
 209         {},
 210 };
 211 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 212
 213 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 214         DRM_PLANE_TYPE_PRIMARY,
 215         DRM_PLANE_TYPE_OVERLAY,
 216         DRM_PLANE_TYPE_OVERLAY,
 217         DRM_PLANE_TYPE_OVERLAY,
 218         DRM_PLANE_TYPE_CURSOR,
 219 };
 220
 221 static const uint32_t fimd_formats[] = {
 222         DRM_FORMAT_C8,
 223         DRM_FORMAT_XRGB1555,
 224         DRM_FORMAT_RGB565,
 225         DRM_FORMAT_XRGB8888,
 226         DRM_FORMAT_ARGB8888,
 227 };
 228
 229 static const unsigned int capabilities[WINDOWS_NR] = {
 230         0,
 231         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 232         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 233         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 234         EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
 235 };
 236
 237 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
 238                                  u32 val)
 239 {
 240         val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
 241         writel(val, ctx->regs + reg);
 242 }
 243
 244 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 245 {
 246         struct fimd_context *ctx = crtc->ctx;
 247         u32 val;
 248
 249         if (ctx->suspended)
 250                 return -EPERM;
 251
 252         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 253                 val = readl(ctx->regs + VIDINTCON0);
 254
 255                 val |= VIDINTCON0_INT_ENABLE;
 256
 257                 if (ctx->i80_if) {
 258                         val |= VIDINTCON0_INT_I80IFDONE;
 259                         val |= VIDINTCON0_INT_SYSMAINCON;
 260                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 261                 } else {
 262                         val |= VIDINTCON0_INT_FRAME;
 263
 264                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 265                         val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 266                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 267                         val |= VIDINTCON0_FRAMESEL1_NONE;
 268                 }
 269
 270                 writel(val, ctx->regs + VIDINTCON0);
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 277 {
 278         struct fimd_context *ctx = crtc->ctx;
 279         u32 val;
 280
 281         if (ctx->suspended)
 282                 return;
 283
 284         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 285                 val = readl(ctx->regs + VIDINTCON0);
 286
 287                 val &= ~VIDINTCON0_INT_ENABLE;
 288
 289                 if (ctx->i80_if) {
 290                         val &= ~VIDINTCON0_INT_I80IFDONE;
 291                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 292                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 293                 } else
 294                         val &= ~VIDINTCON0_INT_FRAME;
 295
 296                 writel(val, ctx->regs + VIDINTCON0);
 297         }
 298 }
 299
 300 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 301 {
 302         struct fimd_context *ctx = crtc->ctx;
 303
 304         if (ctx->suspended)
 305                 return;
 306
 307         atomic_set(&ctx->wait_vsync_event, 1);
 308
 309         /*
 310          * wait for FIMD to signal VSYNC interrupt or return after
 311          * timeout which is set to 50ms (refresh rate of 20).
 312          */
 313         if (!wait_event_timeout(ctx->wait_vsync_queue,
 314                                 !atomic_read(&ctx->wait_vsync_event),
 315                                 HZ/20))
 316                 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
 317 }
 318
 319 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 320                                         bool enable)
 321 {
 322         u32 val = readl(ctx->regs + WINCON(win));
 323
 324         if (enable)
 325                 val |= WINCONx_ENWIN;
 326         else
 327                 val &= ~WINCONx_ENWIN;
 328
 329         writel(val, ctx->regs + WINCON(win));
 330 }
 331
 332 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 333                                                 unsigned int win,
 334                                                 bool enable)
 335 {
 336         u32 val = readl(ctx->regs + SHADOWCON);
 337
 338         if (enable)
 339                 val |= SHADOWCON_CHx_ENABLE(win);
 340         else
 341                 val &= ~SHADOWCON_CHx_ENABLE(win);
 342
 343         writel(val, ctx->regs + SHADOWCON);
 344 }
 345
 346 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 347 {
 348         struct fimd_context *ctx = crtc->ctx;
 349         unsigned int win, ch_enabled = 0;
 350
 351         /* Hardware is in unknown state, so ensure it gets enabled properly */
 352         pm_runtime_get_sync(ctx->dev);
 353
 354         clk_prepare_enable(ctx->bus_clk);
 355         clk_prepare_enable(ctx->lcd_clk);
 356
 357         /* Check if any channel is enabled. */
 358         for (win = 0; win < WINDOWS_NR; win++) {
 359                 u32 val = readl(ctx->regs + WINCON(win));
 360
 361                 if (val & WINCONx_ENWIN) {
 362                         fimd_enable_video_output(ctx, win, false);
 363
 364                         if (ctx->driver_data->has_shadowcon)
 365                                 fimd_enable_shadow_channel_path(ctx, win,
 366                                                                 false);
 367
 368                         ch_enabled = 1;
 369                 }
 370         }
 371
 372         /* Wait for vsync, as disable channel takes effect at next vsync */
 373         if (ch_enabled) {
 374                 ctx->suspended = false;
 375
 376                 fimd_enable_vblank(ctx->crtc);
 377                 fimd_wait_for_vblank(ctx->crtc);
 378                 fimd_disable_vblank(ctx->crtc);
 379
 380                 ctx->suspended = true;
 381         }
 382
 383         clk_disable_unprepare(ctx->lcd_clk);
 384         clk_disable_unprepare(ctx->bus_clk);
 385
 386         pm_runtime_put(ctx->dev);
 387 }
 388
 389
 390 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
 391                 struct drm_crtc_state *state)
 392 {
 393         struct drm_display_mode *mode = &state->adjusted_mode;
 394         struct fimd_context *ctx = crtc->ctx;
 395         unsigned long ideal_clk, lcd_rate;
 396         u32 clkdiv;
 397
 398         if (mode->clock == 0) {
 399                 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
 400                 return -EINVAL;
 401         }
 402
 403         ideal_clk = mode->clock * 1000;
 404
 405         if (ctx->i80_if) {
 406                 /*
 407                  * The frame done interrupt should be occurred prior to the
 408                  * next TE signal.
 409                  */
 410                 ideal_clk *= 2;
 411         }
 412
 413         lcd_rate = clk_get_rate(ctx->lcd_clk);
 414         if (2 * lcd_rate < ideal_clk) {
 415                 DRM_DEV_ERROR(ctx->dev,
 416                               "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
 417                               lcd_rate, ideal_clk);
 418                 return -EINVAL;
 419         }
 420
 421         /* Find the clock divider value that gets us closest to ideal_clk */
 422         clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
 423         if (clkdiv >= 0x200) {
 424                 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
 425                               ideal_clk);
 426                 return -EINVAL;
 427         }
 428
 429         ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
 430
 431         return 0;
 432 }
 433
 434 static void fimd_setup_trigger(struct fimd_context *ctx)
 435 {
 436         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 437         u32 trg_type = ctx->driver_data->trg_type;
 438         u32 val = readl(timing_base + TRIGCON);
 439
 440         val &= ~(TRGMODE_ENABLE);
 441
 442         if (trg_type == I80_HW_TRG) {
 443                 if (ctx->driver_data->has_hw_trigger)
 444                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 445                 if (ctx->driver_data->has_trigger_per_te)
 446                         val |= HWTRIGEN_PER_ENABLE;
 447         } else {
 448                 val |= TRGMODE_ENABLE;
 449         }
 450
 451         writel(val, timing_base + TRIGCON);
 452 }
 453
 454 static void fimd_commit(struct exynos_drm_crtc *crtc)
 455 {
 456         struct fimd_context *ctx = crtc->ctx;
 457         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 458         const struct fimd_driver_data *driver_data = ctx->driver_data;
 459         void *timing_base = ctx->regs + driver_data->timing_base;
 460         u32 val;
 461
 462         if (ctx->suspended)
 463                 return;
 464
 465         /* nothing to do if we haven't set the mode yet */
 466         if (mode->htotal == 0 || mode->vtotal == 0)
 467                 return;
 468
 469         if (ctx->i80_if) {
 470                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 471                 writel(val, timing_base + I80IFCONFAx(0));
 472
 473                 /* disable auto frame rate */
 474                 writel(0, timing_base + I80IFCONFBx(0));
 475
 476                 /* set video type selection to I80 interface */
 477                 if (driver_data->has_vtsel && ctx->sysreg &&
 478                                 regmap_update_bits(ctx->sysreg,
 479                                         driver_data->lcdblk_offset,
 480                                         0x3 << driver_data->lcdblk_vt_shift,
 481                                         0x1 << driver_data->lcdblk_vt_shift)) {
 482                         DRM_DEV_ERROR(ctx->dev,
 483                                       "Failed to update sysreg for I80 i/f.\n");
 484                         return;
 485                 }
 486         } else {
 487                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 488                 u32 vidcon1;
 489
 490                 /* setup polarity values */
 491                 vidcon1 = ctx->vidcon1;
 492                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 493                         vidcon1 |= VIDCON1_INV_VSYNC;
 494                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 495                         vidcon1 |= VIDCON1_INV_HSYNC;
 496                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 497
 498                 /* setup vertical timing values. */
 499                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 500                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 501                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 502
 503                 val = VIDTCON0_VBPD(vbpd - 1) |
 504                         VIDTCON0_VFPD(vfpd - 1) |
 505                         VIDTCON0_VSPW(vsync_len - 1);
 506                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 507
 508                 /* setup horizontal timing values.  */
 509                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 510                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 511                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 512
 513                 val = VIDTCON1_HBPD(hbpd - 1) |
 514                         VIDTCON1_HFPD(hfpd - 1) |
 515                         VIDTCON1_HSPW(hsync_len - 1);
 516                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 517         }
 518
 519         if (driver_data->has_vidoutcon)
 520                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 521
 522         /* set bypass selection */
 523         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 524                                 driver_data->lcdblk_offset,
 525                                 0x1 << driver_data->lcdblk_bypass_shift,
 526                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 527                 DRM_DEV_ERROR(ctx->dev,
 528                               "Failed to update sysreg for bypass setting.\n");
 529                 return;
 530         }
 531
 532         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 533          * bit should be cleared.
 534          */
 535         if (driver_data->has_mic_bypass && ctx->sysreg &&
 536             regmap_update_bits(ctx->sysreg,
 537                                 driver_data->lcdblk_offset,
 538                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 539                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 540                 DRM_DEV_ERROR(ctx->dev,
 541                               "Failed to update sysreg for bypass mic.\n");
 542                 return;
 543         }
 544
 545         /* setup horizontal and vertical display size. */
 546         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 547                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 548                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 549                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 550         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 551
 552         fimd_setup_trigger(ctx);
 553
 554         /*
 555          * fields of register with prefix '_F' would be updated
 556          * at vsync(same as dma start)
 557          */
 558         val = ctx->vidcon0;
 559         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 560
 561         if (ctx->driver_data->has_clksel)
 562                 val |= VIDCON0_CLKSEL_LCD;
 563
 564         if (ctx->clkdiv > 1)
 565                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 566
 567         writel(val, ctx->regs + VIDCON0);
 568 }
 569
 570 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
 571                                unsigned int alpha, unsigned int pixel_alpha)
 572 {
 573         u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
 574         u32 val = 0;
 575
 576         switch (pixel_alpha) {
 577         case DRM_MODE_BLEND_PIXEL_NONE:
 578         case DRM_MODE_BLEND_COVERAGE:
 579                 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
 580                 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 581                 break;
 582         case DRM_MODE_BLEND_PREMULTI:
 583         default:
 584                 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
 585                         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
 586                         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 587                 } else {
 588                         val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
 589                         val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
 590                 }
 591                 break;
 592         }
 593         fimd_set_bits(ctx, BLENDEQx(win), mask, val);
 594 }
 595
 596 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
 597                                 unsigned int alpha, unsigned int pixel_alpha)
 598 {
 599         u32 win_alpha_l = (alpha >> 8) & 0xf;
 600         u32 win_alpha_h = alpha >> 12;
 601         u32 val = 0;
 602
 603         switch (pixel_alpha) {
 604         case DRM_MODE_BLEND_PIXEL_NONE:
 605                 break;
 606         case DRM_MODE_BLEND_COVERAGE:
 607         case DRM_MODE_BLEND_PREMULTI:
 608         default:
 609                 val |= WINCON1_ALPHA_SEL;
 610                 val |= WINCON1_BLD_PIX;
 611                 val |= WINCON1_ALPHA_MUL;
 612                 break;
 613         }
 614         fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
 615
 616         /* OSD alpha */
 617         val = VIDISD14C_ALPHA0_R(win_alpha_h) |
 618                 VIDISD14C_ALPHA0_G(win_alpha_h) |
 619                 VIDISD14C_ALPHA0_B(win_alpha_h) |
 620                 VIDISD14C_ALPHA1_R(0x0) |
 621                 VIDISD14C_ALPHA1_G(0x0) |
 622                 VIDISD14C_ALPHA1_B(0x0);
 623         writel(val, ctx->regs + VIDOSD_C(win));
 624
 625         val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
 626                 VIDW_ALPHA_B(win_alpha_l);
 627         writel(val, ctx->regs + VIDWnALPHA0(win));
 628
 629         val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
 630                 VIDW_ALPHA_B(0x0);
 631         writel(val, ctx->regs + VIDWnALPHA1(win));
 632
 633         fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
 634                         BLENDCON_NEW_8BIT_ALPHA_VALUE);
 635 }
 636
 637 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 638                                 struct drm_framebuffer *fb, int width)
 639 {
 640         struct exynos_drm_plane plane = ctx->planes[win];
 641         struct exynos_drm_plane_state *state =
 642                 to_exynos_plane_state(plane.base.state);
 643         uint32_t pixel_format = fb->format->format;
 644         unsigned int alpha = state->base.alpha;
 645         u32 val = WINCONx_ENWIN;
 646         unsigned int pixel_alpha;
 647
 648         if (fb->format->has_alpha)
 649                 pixel_alpha = state->base.pixel_blend_mode;
 650         else
 651                 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
 652
 653         /*
 654          * In case of s3c64xx, window 0 doesn't support alpha channel.
 655          * So the request format is ARGB8888 then change it to XRGB8888.
 656          */
 657         if (ctx->driver_data->has_limited_fmt && !win) {
 658                 if (pixel_format == DRM_FORMAT_ARGB8888)
 659                         pixel_format = DRM_FORMAT_XRGB8888;
 660         }
 661
 662         switch (pixel_format) {
 663         case DRM_FORMAT_C8:
 664                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 665                 val |= WINCONx_BURSTLEN_8WORD;
 666                 val |= WINCONx_BYTSWP;
 667                 break;
 668         case DRM_FORMAT_XRGB1555:
 669                 val |= WINCON0_BPPMODE_16BPP_1555;
 670                 val |= WINCONx_HAWSWP;
 671                 val |= WINCONx_BURSTLEN_16WORD;
 672                 break;
 673         case DRM_FORMAT_RGB565:
 674                 val |= WINCON0_BPPMODE_16BPP_565;
 675                 val |= WINCONx_HAWSWP;
 676                 val |= WINCONx_BURSTLEN_16WORD;
 677                 break;
 678         case DRM_FORMAT_XRGB8888:
 679                 val |= WINCON0_BPPMODE_24BPP_888;
 680                 val |= WINCONx_WSWP;
 681                 val |= WINCONx_BURSTLEN_16WORD;
 682                 break;
 683         case DRM_FORMAT_ARGB8888:
 684         default:
 685                 val |= WINCON1_BPPMODE_25BPP_A1888;
 686                 val |= WINCONx_WSWP;
 687                 val |= WINCONx_BURSTLEN_16WORD;
 688                 break;
 689         }
 690
 691         /*
 692          * Setting dma-burst to 16Word causes permanent tearing for very small
 693          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 694          * plane size is not recommended as plane size varies alot towards the
 695          * end of the screen and rapid movement causes unstable DMA, but it is
 696          * still better to change dma-burst than displaying garbage.
 697          */
 698
 699         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 700                 val &= ~WINCONx_BURSTLEN_MASK;
 701                 val |= WINCONx_BURSTLEN_4WORD;
 702         }
 703         fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
 704
 705         /* hardware window 0 doesn't support alpha channel. */
 706         if (win != 0) {
 707                 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
 708                 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
 709         }
 710 }
 711
 712 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 713 {
 714         unsigned int keycon0 = 0, keycon1 = 0;
 715
 716         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 717                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 718
 719         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 720
 721         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 722         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 723 }
 724
 725 /**
 726  * shadow_protect_win() - disable updating values from shadow registers at vsync
 727  *
 728  * @ctx: local driver data
 729  * @win: window to protect registers for
 730  * @protect: 1 to protect (disable updates)
 731  */
 732 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 733                                     unsigned int win, bool protect)
 734 {
 735         u32 reg, bits, val;
 736
 737         /*
 738          * SHADOWCON/PRTCON register is used for enabling timing.
 739          *
 740          * for example, once only width value of a register is set,
 741          * if the dma is started then fimd hardware could malfunction so
 742          * with protect window setting, the register fields with prefix '_F'
 743          * wouldn't be updated at vsync also but updated once unprotect window
 744          * is set.
 745          */
 746
 747         if (ctx->driver_data->has_shadowcon) {
 748                 reg = SHADOWCON;
 749                 bits = SHADOWCON_WINx_PROTECT(win);
 750         } else {
 751                 reg = PRTCON;
 752                 bits = PRTCON_PROTECT;
 753         }
 754
 755         val = readl(ctx->regs + reg);
 756         if (protect)
 757                 val |= bits;
 758         else
 759                 val &= ~bits;
 760         writel(val, ctx->regs + reg);
 761 }
 762
 763 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 764 {
 765         struct fimd_context *ctx = crtc->ctx;
 766         int i;
 767
 768         if (ctx->suspended)
 769                 return;
 770
 771         for (i = 0; i < WINDOWS_NR; i++)
 772                 fimd_shadow_protect_win(ctx, i, true);
 773 }
 774
 775 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 776 {
 777         struct fimd_context *ctx = crtc->ctx;
 778         int i;
 779
 780         if (ctx->suspended)
 781                 return;
 782
 783         for (i = 0; i < WINDOWS_NR; i++)
 784                 fimd_shadow_protect_win(ctx, i, false);
 785
 786         exynos_crtc_handle_event(crtc);
 787 }
 788
 789 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 790                               struct exynos_drm_plane *plane)
 791 {
 792         struct exynos_drm_plane_state *state =
 793                                 to_exynos_plane_state(plane->base.state);
 794         struct fimd_context *ctx = crtc->ctx;
 795         struct drm_framebuffer *fb = state->base.fb;
 796         dma_addr_t dma_addr;
 797         unsigned long val, size, offset;
 798         unsigned int last_x, last_y, buf_offsize, line_size;
 799         unsigned int win = plane->index;
 800         unsigned int cpp = fb->format->cpp[0];
 801         unsigned int pitch = fb->pitches[0];
 802
 803         if (ctx->suspended)
 804                 return;
 805
 806         offset = state->src.x * cpp;
 807         offset += state->src.y * pitch;
 808
 809         /* buffer start address */
 810         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 811         val = (unsigned long)dma_addr;
 812         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 813
 814         /* buffer end address */
 815         size = pitch * state->crtc.h;
 816         val = (unsigned long)(dma_addr + size);
 817         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 818
 819         DRM_DEV_DEBUG_KMS(ctx->dev,
 820                           "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 821                           (unsigned long)dma_addr, val, size);
 822         DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
 823                           state->crtc.w, state->crtc.h);
 824
 825         /* buffer size */
 826         buf_offsize = pitch - (state->crtc.w * cpp);
 827         line_size = state->crtc.w * cpp;
 828         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 829                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 830                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 831                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 832         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 833
 834         /* OSD position */
 835         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 836                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 837                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 838                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 839         writel(val, ctx->regs + VIDOSD_A(win));
 840
 841         last_x = state->crtc.x + state->crtc.w;
 842         if (last_x)
 843                 last_x--;
 844         last_y = state->crtc.y + state->crtc.h;
 845         if (last_y)
 846                 last_y--;
 847
 848         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 849                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 850
 851         writel(val, ctx->regs + VIDOSD_B(win));
 852
 853         DRM_DEV_DEBUG_KMS(ctx->dev,
 854                           "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 855                           state->crtc.x, state->crtc.y, last_x, last_y);
 856
 857         /* OSD size */
 858         if (win != 3 && win != 4) {
 859                 u32 offset = VIDOSD_D(win);
 860                 if (win == 0)
 861                         offset = VIDOSD_C(win);
 862                 val = state->crtc.w * state->crtc.h;
 863                 writel(val, ctx->regs + offset);
 864
 865                 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
 866                                   (unsigned int)val);
 867         }
 868
 869         fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
 870
 871         /* hardware window 0 doesn't support color key. */
 872         if (win != 0)
 873                 fimd_win_set_colkey(ctx, win);
 874
 875         fimd_enable_video_output(ctx, win, true);
 876
 877         if (ctx->driver_data->has_shadowcon)
 878                 fimd_enable_shadow_channel_path(ctx, win, true);
 879
 880         if (ctx->i80_if)
 881                 atomic_set(&ctx->win_updated, 1);
 882 }
 883
 884 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 885                                struct exynos_drm_plane *plane)
 886 {
 887         struct fimd_context *ctx = crtc->ctx;
 888         unsigned int win = plane->index;
 889
 890         if (ctx->suspended)
 891                 return;
 892
 893         fimd_enable_video_output(ctx, win, false);
 894
 895         if (ctx->driver_data->has_shadowcon)
 896                 fimd_enable_shadow_channel_path(ctx, win, false);
 897 }
 898
 899 static void fimd_atomic_enable(struct exynos_drm_crtc *crtc)
 900 {
 901         struct fimd_context *ctx = crtc->ctx;
 902
 903         if (!ctx->suspended)
 904                 return;
 905
 906         ctx->suspended = false;
 907
 908         pm_runtime_get_sync(ctx->dev);
 909
 910         /* if vblank was enabled status, enable it again. */
 911         if (test_and_clear_bit(0, &ctx->irq_flags))
 912                 fimd_enable_vblank(ctx->crtc);
 913
 914         fimd_commit(ctx->crtc);
 915 }
 916
 917 static void fimd_atomic_disable(struct exynos_drm_crtc *crtc)
 918 {
 919         struct fimd_context *ctx = crtc->ctx;
 920         int i;
 921
 922         if (ctx->suspended)
 923                 return;
 924
 925         /*
 926          * We need to make sure that all windows are disabled before we
 927          * suspend that connector. Otherwise we might try to scan from
 928          * a destroyed buffer later.
 929          */
 930         for (i = 0; i < WINDOWS_NR; i++)
 931                 fimd_disable_plane(crtc, &ctx->planes[i]);
 932
 933         fimd_enable_vblank(crtc);
 934         fimd_wait_for_vblank(crtc);
 935         fimd_disable_vblank(crtc);
 936
 937         writel(0, ctx->regs + VIDCON0);
 938
 939         pm_runtime_put_sync(ctx->dev);
 940         ctx->suspended = true;
 941 }
 942
 943 static void fimd_trigger(struct device *dev)
 944 {
 945         struct fimd_context *ctx = dev_get_drvdata(dev);
 946         const struct fimd_driver_data *driver_data = ctx->driver_data;
 947         void *timing_base = ctx->regs + driver_data->timing_base;
 948         u32 reg;
 949
 950          /*
 951           * Skips triggering if in triggering state, because multiple triggering
 952           * requests can cause panel reset.
 953           */
 954         if (atomic_read(&ctx->triggering))
 955                 return;
 956
 957         /* Enters triggering mode */
 958         atomic_set(&ctx->triggering, 1);
 959
 960         reg = readl(timing_base + TRIGCON);
 961         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 962         writel(reg, timing_base + TRIGCON);
 963
 964         /*
 965          * Exits triggering mode if vblank is not enabled yet, because when the
 966          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 967          */
 968         if (!test_bit(0, &ctx->irq_flags))
 969                 atomic_set(&ctx->triggering, 0);
 970 }
 971
 972 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 973 {
 974         struct fimd_context *ctx = crtc->ctx;
 975         u32 trg_type = ctx->driver_data->trg_type;
 976
 977         /* Checks the crtc is detached already from encoder */
 978         if (!ctx->drm_dev)
 979                 return;
 980
 981         if (trg_type == I80_HW_TRG)
 982                 goto out;
 983
 984         /*
 985          * If there is a page flip request, triggers and handles the page flip
 986          * event so that current fb can be updated into panel GRAM.
 987          */
 988         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 989                 fimd_trigger(ctx->dev);
 990
 991 out:
 992         /* Wakes up vsync event queue */
 993         if (atomic_read(&ctx->wait_vsync_event)) {
 994                 atomic_set(&ctx->wait_vsync_event, 0);
 995                 wake_up(&ctx->wait_vsync_queue);
 996         }
 997
 998         if (test_bit(0, &ctx->irq_flags))
 999                 drm_crtc_handle_vblank(&ctx->crtc->base);
1000 }
1001
1002 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
1003 {
1004         struct fimd_context *ctx = container_of(clk, struct fimd_context,
1005                                                 dp_clk);
1006         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1007         writel(val, ctx->regs + DP_MIE_CLKCON);
1008 }
1009
1010 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
1011         .atomic_enable = fimd_atomic_enable,
1012         .atomic_disable = fimd_atomic_disable,
1013         .enable_vblank = fimd_enable_vblank,
1014         .disable_vblank = fimd_disable_vblank,
1015         .atomic_begin = fimd_atomic_begin,
1016         .update_plane = fimd_update_plane,
1017         .disable_plane = fimd_disable_plane,
1018         .atomic_flush = fimd_atomic_flush,
1019         .atomic_check = fimd_atomic_check,
1020         .te_handler = fimd_te_handler,
1021 };
1022
1023 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1024 {
1025         struct fimd_context *ctx = (struct fimd_context *)dev_id;
1026         u32 val, clear_bit;
1027
1028         val = readl(ctx->regs + VIDINTCON1);
1029
1030         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1031         if (val & clear_bit)
1032                 writel(clear_bit, ctx->regs + VIDINTCON1);
1033
1034         /* check the crtc is detached already from encoder */
1035         if (!ctx->drm_dev)
1036                 goto out;
1037
1038         if (!ctx->i80_if)
1039                 drm_crtc_handle_vblank(&ctx->crtc->base);
1040
1041         if (ctx->i80_if) {
1042                 /* Exits triggering mode */
1043                 atomic_set(&ctx->triggering, 0);
1044         } else {
1045                 /* set wait vsync event to zero and wake up queue. */
1046                 if (atomic_read(&ctx->wait_vsync_event)) {
1047                         atomic_set(&ctx->wait_vsync_event, 0);
1048                         wake_up(&ctx->wait_vsync_queue);
1049                 }
1050         }
1051
1052 out:
1053         return IRQ_HANDLED;
1054 }
1055
1056 static int fimd_bind(struct device *dev, struct device *master, void *data)
1057 {
1058         struct fimd_context *ctx = dev_get_drvdata(dev);
1059         struct drm_device *drm_dev = data;
1060         struct exynos_drm_plane *exynos_plane;
1061         unsigned int i;
1062         int ret;
1063
1064         ctx->drm_dev = drm_dev;
1065
1066         for (i = 0; i < WINDOWS_NR; i++) {
1067                 ctx->configs[i].pixel_formats = fimd_formats;
1068                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1069                 ctx->configs[i].zpos = i;
1070                 ctx->configs[i].type = fimd_win_types[i];
1071                 ctx->configs[i].capabilities = capabilities[i];
1072                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1073                                         &ctx->configs[i]);
1074                 if (ret)
1075                         return ret;
1076         }
1077
1078         exynos_plane = &ctx->planes[DEFAULT_WIN];
1079         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1080                         EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1081         if (IS_ERR(ctx->crtc))
1082                 return PTR_ERR(ctx->crtc);
1083
1084         if (ctx->driver_data->has_dp_clk) {
1085                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1086                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1087         }
1088
1089         if (ctx->encoder)
1090                 exynos_dpi_bind(drm_dev, ctx->encoder);
1091
1092         if (is_drm_iommu_supported(drm_dev))
1093                 fimd_clear_channels(ctx->crtc);
1094
1095         return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1096 }
1097
1098 static void fimd_unbind(struct device *dev, struct device *master,
1099                         void *data)
1100 {
1101         struct fimd_context *ctx = dev_get_drvdata(dev);
1102
1103         fimd_atomic_disable(ctx->crtc);
1104
1105         exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
1106
1107         if (ctx->encoder)
1108                 exynos_dpi_remove(ctx->encoder);
1109 }
1110
1111 static const struct component_ops fimd_component_ops = {
1112         .bind   = fimd_bind,
1113         .unbind = fimd_unbind,
1114 };
1115
1116 static int fimd_probe(struct platform_device *pdev)
1117 {
1118         struct device *dev = &pdev->dev;
1119         struct fimd_context *ctx;
1120         struct device_node *i80_if_timings;
1121         struct resource *res;
1122         int ret;
1123
1124         if (!dev->of_node)
1125                 return -ENODEV;
1126
1127         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1128         if (!ctx)
1129                 return -ENOMEM;
1130
1131         ctx->dev = dev;
1132         ctx->suspended = true;
1133         ctx->driver_data = of_device_get_match_data(dev);
1134
1135         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1136                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1137         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1138                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1139
1140         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1141         if (i80_if_timings) {
1142                 u32 val;
1143
1144                 ctx->i80_if = true;
1145
1146                 if (ctx->driver_data->has_vidoutcon)
1147                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1148                 else
1149                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1150                 /*
1151                  * The user manual describes that this "DSI_EN" bit is required
1152                  * to enable I80 24-bit data interface.
1153                  */
1154                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1155
1156                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1157                         val = 0;
1158                 ctx->i80ifcon = LCD_CS_SETUP(val);
1159                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1160                         val = 0;
1161                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1162                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1163                         val = 1;
1164                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1165                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1166                         val = 0;
1167                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1168         }
1169         of_node_put(i80_if_timings);
1170
1171         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1172                                                         "samsung,sysreg");
1173         if (IS_ERR(ctx->sysreg)) {
1174                 dev_warn(dev, "failed to get system register.\n");
1175                 ctx->sysreg = NULL;
1176         }
1177
1178         ctx->bus_clk = devm_clk_get(dev, "fimd");
1179         if (IS_ERR(ctx->bus_clk)) {
1180                 dev_err(dev, "failed to get bus clock\n");
1181                 return PTR_ERR(ctx->bus_clk);
1182         }
1183
1184         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1185         if (IS_ERR(ctx->lcd_clk)) {
1186                 dev_err(dev, "failed to get lcd clock\n");
1187                 return PTR_ERR(ctx->lcd_clk);
1188         }
1189
1190         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1191
1192         ctx->regs = devm_ioremap_resource(dev, res);
1193         if (IS_ERR(ctx->regs))
1194                 return PTR_ERR(ctx->regs);
1195
1196         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1197                                            ctx->i80_if ? "lcd_sys" : "vsync");
1198         if (!res) {
1199                 dev_err(dev, "irq request failed.\n");
1200                 return -ENXIO;
1201         }
1202
1203         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1204                                                         0, "drm_fimd", ctx);
1205         if (ret) {
1206                 dev_err(dev, "irq request failed.\n");
1207                 return ret;
1208         }
1209
1210         init_waitqueue_head(&ctx->wait_vsync_queue);
1211         atomic_set(&ctx->wait_vsync_event, 0);
1212
1213         platform_set_drvdata(pdev, ctx);
1214
1215         ctx->encoder = exynos_dpi_probe(dev);
1216         if (IS_ERR(ctx->encoder))
1217                 return PTR_ERR(ctx->encoder);
1218
1219         pm_runtime_enable(dev);
1220
1221         ret = component_add(dev, &fimd_component_ops);
1222         if (ret)
1223                 goto err_disable_pm_runtime;
1224
1225         return ret;
1226
1227 err_disable_pm_runtime:
1228         pm_runtime_disable(dev);
1229
1230         return ret;
1231 }
1232
1233 static int fimd_remove(struct platform_device *pdev)
1234 {
1235         pm_runtime_disable(&pdev->dev);
1236
1237         component_del(&pdev->dev, &fimd_component_ops);
1238
1239         return 0;
1240 }
1241
1242 #ifdef CONFIG_PM
1243 static int exynos_fimd_suspend(struct device *dev)
1244 {
1245         struct fimd_context *ctx = dev_get_drvdata(dev);
1246
1247         clk_disable_unprepare(ctx->lcd_clk);
1248         clk_disable_unprepare(ctx->bus_clk);
1249
1250         return 0;
1251 }
1252
1253 static int exynos_fimd_resume(struct device *dev)
1254 {
1255         struct fimd_context *ctx = dev_get_drvdata(dev);
1256         int ret;
1257
1258         ret = clk_prepare_enable(ctx->bus_clk);
1259         if (ret < 0) {
1260                 DRM_DEV_ERROR(dev,
1261                               "Failed to prepare_enable the bus clk [%d]\n",
1262                               ret);
1263                 return ret;
1264         }
1265
1266         ret = clk_prepare_enable(ctx->lcd_clk);
1267         if  (ret < 0) {
1268                 DRM_DEV_ERROR(dev,
1269                               "Failed to prepare_enable the lcd clk [%d]\n",
1270                               ret);
1271                 return ret;
1272         }
1273
1274         return 0;
1275 }
1276 #endif
1277
1278 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1279         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1280         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1281                                 pm_runtime_force_resume)
1282 };
1283
1284 struct platform_driver fimd_driver = {
1285         .probe          = fimd_probe,
1286         .remove         = fimd_remove,
1287         .driver         = {
1288                 .name   = "exynos4-fb",
1289                 .owner  = THIS_MODULE,
1290                 .pm     = &exynos_fimd_pm_ops,
1291                 .of_match_table = fimd_driver_dt_match,
1292         },
1293 };