drivers/interconnect/qcom/sdm660.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Qualcomm SDM630/SDM636/SDM660 Network-on-Chip (NoC) QoS driver
   4  * Copyright (C) 2020, AngeloGioacchino Del Regno <[email protected]>
   5  */
   6
   7 #include <dt-bindings/interconnect/qcom,sdm660.h>
   8 #include <linux/device.h>
   9 #include <linux/interconnect-provider.h>
  10 #include <linux/io.h>
  11 #include <linux/mod_devicetable.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/regmap.h>
  15 #include <linux/slab.h>
  16
  17 #include "icc-rpm.h"
  18
  19 enum {
  20         SDM660_MASTER_IPA = 1,
  21         SDM660_MASTER_CNOC_A2NOC,
  22         SDM660_MASTER_SDCC_1,
  23         SDM660_MASTER_SDCC_2,
  24         SDM660_MASTER_BLSP_1,
  25         SDM660_MASTER_BLSP_2,
  26         SDM660_MASTER_UFS,
  27         SDM660_MASTER_USB_HS,
  28         SDM660_MASTER_USB3,
  29         SDM660_MASTER_CRYPTO_C0,
  30         SDM660_MASTER_GNOC_BIMC,
  31         SDM660_MASTER_OXILI,
  32         SDM660_MASTER_MNOC_BIMC,
  33         SDM660_MASTER_SNOC_BIMC,
  34         SDM660_MASTER_PIMEM,
  35         SDM660_MASTER_SNOC_CNOC,
  36         SDM660_MASTER_QDSS_DAP,
  37         SDM660_MASTER_APPS_PROC,
  38         SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
  39         SDM660_MASTER_CNOC_MNOC_CFG,
  40         SDM660_MASTER_CPP,
  41         SDM660_MASTER_JPEG,
  42         SDM660_MASTER_MDP_P0,
  43         SDM660_MASTER_MDP_P1,
  44         SDM660_MASTER_VENUS,
  45         SDM660_MASTER_VFE,
  46         SDM660_MASTER_QDSS_ETR,
  47         SDM660_MASTER_QDSS_BAM,
  48         SDM660_MASTER_SNOC_CFG,
  49         SDM660_MASTER_BIMC_SNOC,
  50         SDM660_MASTER_A2NOC_SNOC,
  51         SDM660_MASTER_GNOC_SNOC,
  52
  53         SDM660_SLAVE_A2NOC_SNOC,
  54         SDM660_SLAVE_EBI,
  55         SDM660_SLAVE_HMSS_L3,
  56         SDM660_SLAVE_BIMC_SNOC,
  57         SDM660_SLAVE_CNOC_A2NOC,
  58         SDM660_SLAVE_MPM,
  59         SDM660_SLAVE_PMIC_ARB,
  60         SDM660_SLAVE_TLMM_NORTH,
  61         SDM660_SLAVE_TCSR,
  62         SDM660_SLAVE_PIMEM_CFG,
  63         SDM660_SLAVE_IMEM_CFG,
  64         SDM660_SLAVE_MESSAGE_RAM,
  65         SDM660_SLAVE_GLM,
  66         SDM660_SLAVE_BIMC_CFG,
  67         SDM660_SLAVE_PRNG,
  68         SDM660_SLAVE_SPDM,
  69         SDM660_SLAVE_QDSS_CFG,
  70         SDM660_SLAVE_CNOC_MNOC_CFG,
  71         SDM660_SLAVE_SNOC_CFG,
  72         SDM660_SLAVE_QM_CFG,
  73         SDM660_SLAVE_CLK_CTL,
  74         SDM660_SLAVE_MSS_CFG,
  75         SDM660_SLAVE_TLMM_SOUTH,
  76         SDM660_SLAVE_UFS_CFG,
  77         SDM660_SLAVE_A2NOC_CFG,
  78         SDM660_SLAVE_A2NOC_SMMU_CFG,
  79         SDM660_SLAVE_GPUSS_CFG,
  80         SDM660_SLAVE_AHB2PHY,
  81         SDM660_SLAVE_BLSP_1,
  82         SDM660_SLAVE_SDCC_1,
  83         SDM660_SLAVE_SDCC_2,
  84         SDM660_SLAVE_TLMM_CENTER,
  85         SDM660_SLAVE_BLSP_2,
  86         SDM660_SLAVE_PDM,
  87         SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
  88         SDM660_SLAVE_USB_HS,
  89         SDM660_SLAVE_USB3_0,
  90         SDM660_SLAVE_SRVC_CNOC,
  91         SDM660_SLAVE_GNOC_BIMC,
  92         SDM660_SLAVE_GNOC_SNOC,
  93         SDM660_SLAVE_CAMERA_CFG,
  94         SDM660_SLAVE_CAMERA_THROTTLE_CFG,
  95         SDM660_SLAVE_MISC_CFG,
  96         SDM660_SLAVE_VENUS_THROTTLE_CFG,
  97         SDM660_SLAVE_VENUS_CFG,
  98         SDM660_SLAVE_MMSS_CLK_XPU_CFG,
  99         SDM660_SLAVE_MMSS_CLK_CFG,
 100         SDM660_SLAVE_MNOC_MPU_CFG,
 101         SDM660_SLAVE_DISPLAY_CFG,
 102         SDM660_SLAVE_CSI_PHY_CFG,
 103         SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
 104         SDM660_SLAVE_SMMU_CFG,
 105         SDM660_SLAVE_MNOC_BIMC,
 106         SDM660_SLAVE_SRVC_MNOC,
 107         SDM660_SLAVE_HMSS,
 108         SDM660_SLAVE_LPASS,
 109         SDM660_SLAVE_WLAN,
 110         SDM660_SLAVE_CDSP,
 111         SDM660_SLAVE_IPA,
 112         SDM660_SLAVE_SNOC_BIMC,
 113         SDM660_SLAVE_SNOC_CNOC,
 114         SDM660_SLAVE_IMEM,
 115         SDM660_SLAVE_PIMEM,
 116         SDM660_SLAVE_QDSS_STM,
 117         SDM660_SLAVE_SRVC_SNOC,
 118
 119         SDM660_A2NOC,
 120         SDM660_BIMC,
 121         SDM660_CNOC,
 122         SDM660_GNOC,
 123         SDM660_MNOC,
 124         SDM660_SNOC,
 125 };
 126
 127 static const char * const mm_intf_clocks[] = {
 128         "iface",
 129 };
 130
 131 static const char * const a2noc_intf_clocks[] = {
 132         "ipa",
 133         "ufs_axi",
 134         "aggre2_ufs_axi",
 135         "aggre2_usb3_axi",
 136         "cfg_noc_usb2_axi",
 137 };
 138
 139 static const u16 mas_ipa_links[] = {
 140         SDM660_SLAVE_A2NOC_SNOC
 141 };
 142
 143 static struct qcom_icc_node mas_ipa = {
 144         .name = "mas_ipa",
 145         .id = SDM660_MASTER_IPA,
 146         .buswidth = 8,
 147         .mas_rpm_id = 59,
 148         .slv_rpm_id = -1,
 149         .qos.ap_owned = true,
 150         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 151         .qos.areq_prio = 1,
 152         .qos.prio_level = 1,
 153         .qos.qos_port = 3,
 154         .num_links = ARRAY_SIZE(mas_ipa_links),
 155         .links = mas_ipa_links,
 156 };
 157
 158 static const u16 mas_cnoc_a2noc_links[] = {
 159         SDM660_SLAVE_A2NOC_SNOC
 160 };
 161
 162 static struct qcom_icc_node mas_cnoc_a2noc = {
 163         .name = "mas_cnoc_a2noc",
 164         .id = SDM660_MASTER_CNOC_A2NOC,
 165         .buswidth = 8,
 166         .mas_rpm_id = 146,
 167         .slv_rpm_id = -1,
 168         .qos.ap_owned = true,
 169         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 170         .num_links = ARRAY_SIZE(mas_cnoc_a2noc_links),
 171         .links = mas_cnoc_a2noc_links,
 172 };
 173
 174 static const u16 mas_sdcc_1_links[] = {
 175         SDM660_SLAVE_A2NOC_SNOC
 176 };
 177
 178 static struct qcom_icc_node mas_sdcc_1 = {
 179         .name = "mas_sdcc_1",
 180         .id = SDM660_MASTER_SDCC_1,
 181         .buswidth = 8,
 182         .mas_rpm_id = 33,
 183         .slv_rpm_id = -1,
 184         .num_links = ARRAY_SIZE(mas_sdcc_1_links),
 185         .links = mas_sdcc_1_links,
 186 };
 187
 188 static const u16 mas_sdcc_2_links[] = {
 189         SDM660_SLAVE_A2NOC_SNOC
 190 };
 191
 192 static struct qcom_icc_node mas_sdcc_2 = {
 193         .name = "mas_sdcc_2",
 194         .id = SDM660_MASTER_SDCC_2,
 195         .buswidth = 8,
 196         .mas_rpm_id = 35,
 197         .slv_rpm_id = -1,
 198         .num_links = ARRAY_SIZE(mas_sdcc_2_links),
 199         .links = mas_sdcc_2_links,
 200 };
 201
 202 static const u16 mas_blsp_1_links[] = {
 203         SDM660_SLAVE_A2NOC_SNOC
 204 };
 205
 206 static struct qcom_icc_node mas_blsp_1 = {
 207         .name = "mas_blsp_1",
 208         .id = SDM660_MASTER_BLSP_1,
 209         .buswidth = 4,
 210         .mas_rpm_id = 41,
 211         .slv_rpm_id = -1,
 212         .num_links = ARRAY_SIZE(mas_blsp_1_links),
 213         .links = mas_blsp_1_links,
 214 };
 215
 216 static const u16 mas_blsp_2_links[] = {
 217         SDM660_SLAVE_A2NOC_SNOC
 218 };
 219
 220 static struct qcom_icc_node mas_blsp_2 = {
 221         .name = "mas_blsp_2",
 222         .id = SDM660_MASTER_BLSP_2,
 223         .buswidth = 4,
 224         .mas_rpm_id = 39,
 225         .slv_rpm_id = -1,
 226         .num_links = ARRAY_SIZE(mas_blsp_2_links),
 227         .links = mas_blsp_2_links,
 228 };
 229
 230 static const u16 mas_ufs_links[] = {
 231         SDM660_SLAVE_A2NOC_SNOC
 232 };
 233
 234 static struct qcom_icc_node mas_ufs = {
 235         .name = "mas_ufs",
 236         .id = SDM660_MASTER_UFS,
 237         .buswidth = 8,
 238         .mas_rpm_id = 68,
 239         .slv_rpm_id = -1,
 240         .qos.ap_owned = true,
 241         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 242         .qos.areq_prio = 1,
 243         .qos.prio_level = 1,
 244         .qos.qos_port = 4,
 245         .num_links = ARRAY_SIZE(mas_ufs_links),
 246         .links = mas_ufs_links,
 247 };
 248
 249 static const u16 mas_usb_hs_links[] = {
 250         SDM660_SLAVE_A2NOC_SNOC
 251 };
 252
 253 static struct qcom_icc_node mas_usb_hs = {
 254         .name = "mas_usb_hs",
 255         .id = SDM660_MASTER_USB_HS,
 256         .buswidth = 8,
 257         .mas_rpm_id = 42,
 258         .slv_rpm_id = -1,
 259         .qos.ap_owned = true,
 260         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 261         .qos.areq_prio = 1,
 262         .qos.prio_level = 1,
 263         .qos.qos_port = 1,
 264         .num_links = ARRAY_SIZE(mas_usb_hs_links),
 265         .links = mas_usb_hs_links,
 266 };
 267
 268 static const u16 mas_usb3_links[] = {
 269         SDM660_SLAVE_A2NOC_SNOC
 270 };
 271
 272 static struct qcom_icc_node mas_usb3 = {
 273         .name = "mas_usb3",
 274         .id = SDM660_MASTER_USB3,
 275         .buswidth = 8,
 276         .mas_rpm_id = 32,
 277         .slv_rpm_id = -1,
 278         .qos.ap_owned = true,
 279         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 280         .qos.areq_prio = 1,
 281         .qos.prio_level = 1,
 282         .qos.qos_port = 2,
 283         .num_links = ARRAY_SIZE(mas_usb3_links),
 284         .links = mas_usb3_links,
 285 };
 286
 287 static const u16 mas_crypto_links[] = {
 288         SDM660_SLAVE_A2NOC_SNOC
 289 };
 290
 291 static struct qcom_icc_node mas_crypto = {
 292         .name = "mas_crypto",
 293         .id = SDM660_MASTER_CRYPTO_C0,
 294         .buswidth = 8,
 295         .mas_rpm_id = 23,
 296         .slv_rpm_id = -1,
 297         .qos.ap_owned = true,
 298         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 299         .qos.areq_prio = 1,
 300         .qos.prio_level = 1,
 301         .qos.qos_port = 11,
 302         .num_links = ARRAY_SIZE(mas_crypto_links),
 303         .links = mas_crypto_links,
 304 };
 305
 306 static const u16 mas_gnoc_bimc_links[] = {
 307         SDM660_SLAVE_EBI
 308 };
 309
 310 static struct qcom_icc_node mas_gnoc_bimc = {
 311         .name = "mas_gnoc_bimc",
 312         .id = SDM660_MASTER_GNOC_BIMC,
 313         .buswidth = 4,
 314         .mas_rpm_id = 144,
 315         .slv_rpm_id = -1,
 316         .qos.ap_owned = true,
 317         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 318         .qos.areq_prio = 0,
 319         .qos.prio_level = 0,
 320         .qos.qos_port = 0,
 321         .num_links = ARRAY_SIZE(mas_gnoc_bimc_links),
 322         .links = mas_gnoc_bimc_links,
 323 };
 324
 325 static const u16 mas_oxili_links[] = {
 326         SDM660_SLAVE_HMSS_L3,
 327         SDM660_SLAVE_EBI,
 328         SDM660_SLAVE_BIMC_SNOC
 329 };
 330
 331 static struct qcom_icc_node mas_oxili = {
 332         .name = "mas_oxili",
 333         .id = SDM660_MASTER_OXILI,
 334         .buswidth = 4,
 335         .mas_rpm_id = 6,
 336         .slv_rpm_id = -1,
 337         .qos.ap_owned = true,
 338         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 339         .qos.areq_prio = 0,
 340         .qos.prio_level = 0,
 341         .qos.qos_port = 1,
 342         .num_links = ARRAY_SIZE(mas_oxili_links),
 343         .links = mas_oxili_links,
 344 };
 345
 346 static const u16 mas_mnoc_bimc_links[] = {
 347         SDM660_SLAVE_HMSS_L3,
 348         SDM660_SLAVE_EBI,
 349         SDM660_SLAVE_BIMC_SNOC
 350 };
 351
 352 static struct qcom_icc_node mas_mnoc_bimc = {
 353         .name = "mas_mnoc_bimc",
 354         .id = SDM660_MASTER_MNOC_BIMC,
 355         .buswidth = 4,
 356         .mas_rpm_id = 2,
 357         .slv_rpm_id = -1,
 358         .qos.ap_owned = true,
 359         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 360         .qos.areq_prio = 0,
 361         .qos.prio_level = 0,
 362         .qos.qos_port = 2,
 363         .num_links = ARRAY_SIZE(mas_mnoc_bimc_links),
 364         .links = mas_mnoc_bimc_links,
 365 };
 366
 367 static const u16 mas_snoc_bimc_links[] = {
 368         SDM660_SLAVE_HMSS_L3,
 369         SDM660_SLAVE_EBI
 370 };
 371
 372 static struct qcom_icc_node mas_snoc_bimc = {
 373         .name = "mas_snoc_bimc",
 374         .id = SDM660_MASTER_SNOC_BIMC,
 375         .buswidth = 4,
 376         .mas_rpm_id = 3,
 377         .slv_rpm_id = -1,
 378         .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
 379         .links = mas_snoc_bimc_links,
 380 };
 381
 382 static const u16 mas_pimem_links[] = {
 383         SDM660_SLAVE_HMSS_L3,
 384         SDM660_SLAVE_EBI
 385 };
 386
 387 static struct qcom_icc_node mas_pimem = {
 388         .name = "mas_pimem",
 389         .id = SDM660_MASTER_PIMEM,
 390         .buswidth = 4,
 391         .mas_rpm_id = 113,
 392         .slv_rpm_id = -1,
 393         .qos.ap_owned = true,
 394         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 395         .qos.areq_prio = 1,
 396         .qos.prio_level = 1,
 397         .qos.qos_port = 4,
 398         .num_links = ARRAY_SIZE(mas_pimem_links),
 399         .links = mas_pimem_links,
 400 };
 401
 402 static const u16 mas_snoc_cnoc_links[] = {
 403         SDM660_SLAVE_CLK_CTL,
 404         SDM660_SLAVE_QDSS_CFG,
 405         SDM660_SLAVE_QM_CFG,
 406         SDM660_SLAVE_SRVC_CNOC,
 407         SDM660_SLAVE_UFS_CFG,
 408         SDM660_SLAVE_TCSR,
 409         SDM660_SLAVE_A2NOC_SMMU_CFG,
 410         SDM660_SLAVE_SNOC_CFG,
 411         SDM660_SLAVE_TLMM_SOUTH,
 412         SDM660_SLAVE_MPM,
 413         SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
 414         SDM660_SLAVE_SDCC_2,
 415         SDM660_SLAVE_SDCC_1,
 416         SDM660_SLAVE_SPDM,
 417         SDM660_SLAVE_PMIC_ARB,
 418         SDM660_SLAVE_PRNG,
 419         SDM660_SLAVE_MSS_CFG,
 420         SDM660_SLAVE_GPUSS_CFG,
 421         SDM660_SLAVE_IMEM_CFG,
 422         SDM660_SLAVE_USB3_0,
 423         SDM660_SLAVE_A2NOC_CFG,
 424         SDM660_SLAVE_TLMM_NORTH,
 425         SDM660_SLAVE_USB_HS,
 426         SDM660_SLAVE_PDM,
 427         SDM660_SLAVE_TLMM_CENTER,
 428         SDM660_SLAVE_AHB2PHY,
 429         SDM660_SLAVE_BLSP_2,
 430         SDM660_SLAVE_BLSP_1,
 431         SDM660_SLAVE_PIMEM_CFG,
 432         SDM660_SLAVE_GLM,
 433         SDM660_SLAVE_MESSAGE_RAM,
 434         SDM660_SLAVE_BIMC_CFG,
 435         SDM660_SLAVE_CNOC_MNOC_CFG
 436 };
 437
 438 static struct qcom_icc_node mas_snoc_cnoc = {
 439         .name = "mas_snoc_cnoc",
 440         .id = SDM660_MASTER_SNOC_CNOC,
 441         .buswidth = 8,
 442         .mas_rpm_id = 52,
 443         .slv_rpm_id = -1,
 444         .qos.ap_owned = true,
 445         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 446         .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
 447         .links = mas_snoc_cnoc_links,
 448 };
 449
 450 static const u16 mas_qdss_dap_links[] = {
 451         SDM660_SLAVE_CLK_CTL,
 452         SDM660_SLAVE_QDSS_CFG,
 453         SDM660_SLAVE_QM_CFG,
 454         SDM660_SLAVE_SRVC_CNOC,
 455         SDM660_SLAVE_UFS_CFG,
 456         SDM660_SLAVE_TCSR,
 457         SDM660_SLAVE_A2NOC_SMMU_CFG,
 458         SDM660_SLAVE_SNOC_CFG,
 459         SDM660_SLAVE_TLMM_SOUTH,
 460         SDM660_SLAVE_MPM,
 461         SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
 462         SDM660_SLAVE_SDCC_2,
 463         SDM660_SLAVE_SDCC_1,
 464         SDM660_SLAVE_SPDM,
 465         SDM660_SLAVE_PMIC_ARB,
 466         SDM660_SLAVE_PRNG,
 467         SDM660_SLAVE_MSS_CFG,
 468         SDM660_SLAVE_GPUSS_CFG,
 469         SDM660_SLAVE_IMEM_CFG,
 470         SDM660_SLAVE_USB3_0,
 471         SDM660_SLAVE_A2NOC_CFG,
 472         SDM660_SLAVE_TLMM_NORTH,
 473         SDM660_SLAVE_USB_HS,
 474         SDM660_SLAVE_PDM,
 475         SDM660_SLAVE_TLMM_CENTER,
 476         SDM660_SLAVE_AHB2PHY,
 477         SDM660_SLAVE_BLSP_2,
 478         SDM660_SLAVE_BLSP_1,
 479         SDM660_SLAVE_PIMEM_CFG,
 480         SDM660_SLAVE_GLM,
 481         SDM660_SLAVE_MESSAGE_RAM,
 482         SDM660_SLAVE_CNOC_A2NOC,
 483         SDM660_SLAVE_BIMC_CFG,
 484         SDM660_SLAVE_CNOC_MNOC_CFG
 485 };
 486
 487 static struct qcom_icc_node mas_qdss_dap = {
 488         .name = "mas_qdss_dap",
 489         .id = SDM660_MASTER_QDSS_DAP,
 490         .buswidth = 8,
 491         .mas_rpm_id = 49,
 492         .slv_rpm_id = -1,
 493         .qos.ap_owned = true,
 494         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 495         .num_links = ARRAY_SIZE(mas_qdss_dap_links),
 496         .links = mas_qdss_dap_links,
 497 };
 498
 499 static const u16 mas_apss_proc_links[] = {
 500         SDM660_SLAVE_GNOC_SNOC,
 501         SDM660_SLAVE_GNOC_BIMC
 502 };
 503
 504 static struct qcom_icc_node mas_apss_proc = {
 505         .name = "mas_apss_proc",
 506         .id = SDM660_MASTER_APPS_PROC,
 507         .buswidth = 16,
 508         .mas_rpm_id = 0,
 509         .slv_rpm_id = -1,
 510         .qos.ap_owned = true,
 511         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 512         .num_links = ARRAY_SIZE(mas_apss_proc_links),
 513         .links = mas_apss_proc_links,
 514 };
 515
 516 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = {
 517         SDM660_SLAVE_VENUS_THROTTLE_CFG,
 518         SDM660_SLAVE_VENUS_CFG,
 519         SDM660_SLAVE_CAMERA_THROTTLE_CFG,
 520         SDM660_SLAVE_SMMU_CFG,
 521         SDM660_SLAVE_CAMERA_CFG,
 522         SDM660_SLAVE_CSI_PHY_CFG,
 523         SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
 524         SDM660_SLAVE_DISPLAY_CFG,
 525         SDM660_SLAVE_MMSS_CLK_CFG,
 526         SDM660_SLAVE_MNOC_MPU_CFG,
 527         SDM660_SLAVE_MISC_CFG,
 528         SDM660_SLAVE_MMSS_CLK_XPU_CFG
 529 };
 530
 531 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = {
 532         .name = "mas_cnoc_mnoc_mmss_cfg",
 533         .id = SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
 534         .buswidth = 8,
 535         .mas_rpm_id = 4,
 536         .slv_rpm_id = -1,
 537         .qos.ap_owned = true,
 538         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 539         .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links),
 540         .links = mas_cnoc_mnoc_mmss_cfg_links,
 541 };
 542
 543 static const u16 mas_cnoc_mnoc_cfg_links[] = {
 544         SDM660_SLAVE_SRVC_MNOC
 545 };
 546
 547 static struct qcom_icc_node mas_cnoc_mnoc_cfg = {
 548         .name = "mas_cnoc_mnoc_cfg",
 549         .id = SDM660_MASTER_CNOC_MNOC_CFG,
 550         .buswidth = 4,
 551         .mas_rpm_id = 5,
 552         .slv_rpm_id = -1,
 553         .qos.ap_owned = true,
 554         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 555         .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links),
 556         .links = mas_cnoc_mnoc_cfg_links,
 557 };
 558
 559 static const u16 mas_cpp_links[] = {
 560         SDM660_SLAVE_MNOC_BIMC
 561 };
 562
 563 static struct qcom_icc_node mas_cpp = {
 564         .name = "mas_cpp",
 565         .id = SDM660_MASTER_CPP,
 566         .buswidth = 16,
 567         .mas_rpm_id = 115,
 568         .slv_rpm_id = -1,
 569         .qos.ap_owned = true,
 570         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 571         .qos.areq_prio = 0,
 572         .qos.prio_level = 0,
 573         .qos.qos_port = 4,
 574         .num_links = ARRAY_SIZE(mas_cpp_links),
 575         .links = mas_cpp_links,
 576 };
 577
 578 static const u16 mas_jpeg_links[] = {
 579         SDM660_SLAVE_MNOC_BIMC
 580 };
 581
 582 static struct qcom_icc_node mas_jpeg = {
 583         .name = "mas_jpeg",
 584         .id = SDM660_MASTER_JPEG,
 585         .buswidth = 16,
 586         .mas_rpm_id = 7,
 587         .slv_rpm_id = -1,
 588         .qos.ap_owned = true,
 589         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 590         .qos.areq_prio = 0,
 591         .qos.prio_level = 0,
 592         .qos.qos_port = 6,
 593         .num_links = ARRAY_SIZE(mas_jpeg_links),
 594         .links = mas_jpeg_links,
 595 };
 596
 597 static const u16 mas_mdp_p0_links[] = {
 598         SDM660_SLAVE_MNOC_BIMC
 599 };
 600
 601 static struct qcom_icc_node mas_mdp_p0 = {
 602         .name = "mas_mdp_p0",
 603         .id = SDM660_MASTER_MDP_P0,
 604         .buswidth = 16,
 605         .mas_rpm_id = 8,
 606         .slv_rpm_id = -1,
 607         .qos.ap_owned = true,
 608         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 609         .qos.areq_prio = 0,
 610         .qos.prio_level = 0,
 611         .qos.qos_port = 0,
 612         .num_links = ARRAY_SIZE(mas_mdp_p0_links),
 613         .links = mas_mdp_p0_links,
 614 };
 615
 616 static const u16 mas_mdp_p1_links[] = {
 617         SDM660_SLAVE_MNOC_BIMC
 618 };
 619
 620 static struct qcom_icc_node mas_mdp_p1 = {
 621         .name = "mas_mdp_p1",
 622         .id = SDM660_MASTER_MDP_P1,
 623         .buswidth = 16,
 624         .mas_rpm_id = 61,
 625         .slv_rpm_id = -1,
 626         .qos.ap_owned = true,
 627         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 628         .qos.areq_prio = 0,
 629         .qos.prio_level = 0,
 630         .qos.qos_port = 1,
 631         .num_links = ARRAY_SIZE(mas_mdp_p1_links),
 632         .links = mas_mdp_p1_links,
 633 };
 634
 635 static const u16 mas_venus_links[] = {
 636         SDM660_SLAVE_MNOC_BIMC
 637 };
 638
 639 static struct qcom_icc_node mas_venus = {
 640         .name = "mas_venus",
 641         .id = SDM660_MASTER_VENUS,
 642         .buswidth = 16,
 643         .mas_rpm_id = 9,
 644         .slv_rpm_id = -1,
 645         .qos.ap_owned = true,
 646         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 647         .qos.areq_prio = 0,
 648         .qos.prio_level = 0,
 649         .qos.qos_port = 1,
 650         .num_links = ARRAY_SIZE(mas_venus_links),
 651         .links = mas_venus_links,
 652 };
 653
 654 static const u16 mas_vfe_links[] = {
 655         SDM660_SLAVE_MNOC_BIMC
 656 };
 657
 658 static struct qcom_icc_node mas_vfe = {
 659         .name = "mas_vfe",
 660         .id = SDM660_MASTER_VFE,
 661         .buswidth = 16,
 662         .mas_rpm_id = 11,
 663         .slv_rpm_id = -1,
 664         .qos.ap_owned = true,
 665         .qos.qos_mode = NOC_QOS_MODE_BYPASS,
 666         .qos.areq_prio = 0,
 667         .qos.prio_level = 0,
 668         .qos.qos_port = 5,
 669         .num_links = ARRAY_SIZE(mas_vfe_links),
 670         .links = mas_vfe_links,
 671 };
 672
 673 static const u16 mas_qdss_etr_links[] = {
 674         SDM660_SLAVE_PIMEM,
 675         SDM660_SLAVE_IMEM,
 676         SDM660_SLAVE_SNOC_CNOC,
 677         SDM660_SLAVE_SNOC_BIMC
 678 };
 679
 680 static struct qcom_icc_node mas_qdss_etr = {
 681         .name = "mas_qdss_etr",
 682         .id = SDM660_MASTER_QDSS_ETR,
 683         .buswidth = 8,
 684         .mas_rpm_id = 31,
 685         .slv_rpm_id = -1,
 686         .qos.ap_owned = true,
 687         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 688         .qos.areq_prio = 1,
 689         .qos.prio_level = 1,
 690         .qos.qos_port = 1,
 691         .num_links = ARRAY_SIZE(mas_qdss_etr_links),
 692         .links = mas_qdss_etr_links,
 693 };
 694
 695 static const u16 mas_qdss_bam_links[] = {
 696         SDM660_SLAVE_PIMEM,
 697         SDM660_SLAVE_IMEM,
 698         SDM660_SLAVE_SNOC_CNOC,
 699         SDM660_SLAVE_SNOC_BIMC
 700 };
 701
 702 static struct qcom_icc_node mas_qdss_bam = {
 703         .name = "mas_qdss_bam",
 704         .id = SDM660_MASTER_QDSS_BAM,
 705         .buswidth = 4,
 706         .mas_rpm_id = 19,
 707         .slv_rpm_id = -1,
 708         .qos.ap_owned = true,
 709         .qos.qos_mode = NOC_QOS_MODE_FIXED,
 710         .qos.areq_prio = 1,
 711         .qos.prio_level = 1,
 712         .qos.qos_port = 0,
 713         .num_links = ARRAY_SIZE(mas_qdss_bam_links),
 714         .links = mas_qdss_bam_links,
 715 };
 716
 717 static const u16 mas_snoc_cfg_links[] = {
 718         SDM660_SLAVE_SRVC_SNOC
 719 };
 720
 721 static struct qcom_icc_node mas_snoc_cfg = {
 722         .name = "mas_snoc_cfg",
 723         .id = SDM660_MASTER_SNOC_CFG,
 724         .buswidth = 4,
 725         .mas_rpm_id = 20,
 726         .slv_rpm_id = -1,
 727         .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
 728         .links = mas_snoc_cfg_links,
 729 };
 730
 731 static const u16 mas_bimc_snoc_links[] = {
 732         SDM660_SLAVE_PIMEM,
 733         SDM660_SLAVE_IPA,
 734         SDM660_SLAVE_QDSS_STM,
 735         SDM660_SLAVE_LPASS,
 736         SDM660_SLAVE_HMSS,
 737         SDM660_SLAVE_CDSP,
 738         SDM660_SLAVE_SNOC_CNOC,
 739         SDM660_SLAVE_WLAN,
 740         SDM660_SLAVE_IMEM
 741 };
 742
 743 static struct qcom_icc_node mas_bimc_snoc = {
 744         .name = "mas_bimc_snoc",
 745         .id = SDM660_MASTER_BIMC_SNOC,
 746         .buswidth = 8,
 747         .mas_rpm_id = 21,
 748         .slv_rpm_id = -1,
 749         .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
 750         .links = mas_bimc_snoc_links,
 751 };
 752
 753 static const u16 mas_gnoc_snoc_links[] = {
 754         SDM660_SLAVE_PIMEM,
 755         SDM660_SLAVE_IPA,
 756         SDM660_SLAVE_QDSS_STM,
 757         SDM660_SLAVE_LPASS,
 758         SDM660_SLAVE_HMSS,
 759         SDM660_SLAVE_CDSP,
 760         SDM660_SLAVE_SNOC_CNOC,
 761         SDM660_SLAVE_WLAN,
 762         SDM660_SLAVE_IMEM
 763 };
 764
 765 static struct qcom_icc_node mas_gnoc_snoc = {
 766         .name = "mas_gnoc_snoc",
 767         .id = SDM660_MASTER_GNOC_SNOC,
 768         .buswidth = 8,
 769         .mas_rpm_id = 150,
 770         .slv_rpm_id = -1,
 771         .num_links = ARRAY_SIZE(mas_gnoc_snoc_links),
 772         .links = mas_gnoc_snoc_links,
 773 };
 774
 775 static const u16 mas_a2noc_snoc_links[] = {
 776         SDM660_SLAVE_PIMEM,
 777         SDM660_SLAVE_IPA,
 778         SDM660_SLAVE_QDSS_STM,
 779         SDM660_SLAVE_LPASS,
 780         SDM660_SLAVE_HMSS,
 781         SDM660_SLAVE_SNOC_BIMC,
 782         SDM660_SLAVE_CDSP,
 783         SDM660_SLAVE_SNOC_CNOC,
 784         SDM660_SLAVE_WLAN,
 785         SDM660_SLAVE_IMEM
 786 };
 787
 788 static struct qcom_icc_node mas_a2noc_snoc = {
 789         .name = "mas_a2noc_snoc",
 790         .id = SDM660_MASTER_A2NOC_SNOC,
 791         .buswidth = 16,
 792         .mas_rpm_id = 112,
 793         .slv_rpm_id = -1,
 794         .num_links = ARRAY_SIZE(mas_a2noc_snoc_links),
 795         .links = mas_a2noc_snoc_links,
 796 };
 797
 798 static const u16 slv_a2noc_snoc_links[] = {
 799         SDM660_MASTER_A2NOC_SNOC
 800 };
 801
 802 static struct qcom_icc_node slv_a2noc_snoc = {
 803         .name = "slv_a2noc_snoc",
 804         .id = SDM660_SLAVE_A2NOC_SNOC,
 805         .buswidth = 16,
 806         .mas_rpm_id = -1,
 807         .slv_rpm_id = 143,
 808         .num_links = ARRAY_SIZE(slv_a2noc_snoc_links),
 809         .links = slv_a2noc_snoc_links,
 810 };
 811
 812 static struct qcom_icc_node slv_ebi = {
 813         .name = "slv_ebi",
 814         .id = SDM660_SLAVE_EBI,
 815         .buswidth = 4,
 816         .mas_rpm_id = -1,
 817         .slv_rpm_id = 0,
 818 };
 819
 820 static struct qcom_icc_node slv_hmss_l3 = {
 821         .name = "slv_hmss_l3",
 822         .id = SDM660_SLAVE_HMSS_L3,
 823         .buswidth = 4,
 824         .mas_rpm_id = -1,
 825         .slv_rpm_id = 160,
 826 };
 827
 828 static const u16 slv_bimc_snoc_links[] = {
 829         SDM660_MASTER_BIMC_SNOC
 830 };
 831
 832 static struct qcom_icc_node slv_bimc_snoc = {
 833         .name = "slv_bimc_snoc",
 834         .id = SDM660_SLAVE_BIMC_SNOC,
 835         .buswidth = 4,
 836         .mas_rpm_id = -1,
 837         .slv_rpm_id = 2,
 838         .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
 839         .links = slv_bimc_snoc_links,
 840 };
 841
 842 static const u16 slv_cnoc_a2noc_links[] = {
 843         SDM660_MASTER_CNOC_A2NOC
 844 };
 845
 846 static struct qcom_icc_node slv_cnoc_a2noc = {
 847         .name = "slv_cnoc_a2noc",
 848         .id = SDM660_SLAVE_CNOC_A2NOC,
 849         .buswidth = 8,
 850         .mas_rpm_id = -1,
 851         .slv_rpm_id = 208,
 852         .qos.ap_owned = true,
 853         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 854         .num_links = ARRAY_SIZE(slv_cnoc_a2noc_links),
 855         .links = slv_cnoc_a2noc_links,
 856 };
 857
 858 static struct qcom_icc_node slv_mpm = {
 859         .name = "slv_mpm",
 860         .id = SDM660_SLAVE_MPM,
 861         .buswidth = 4,
 862         .mas_rpm_id = -1,
 863         .slv_rpm_id = 62,
 864         .qos.ap_owned = true,
 865         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 866 };
 867
 868 static struct qcom_icc_node slv_pmic_arb = {
 869         .name = "slv_pmic_arb",
 870         .id = SDM660_SLAVE_PMIC_ARB,
 871         .buswidth = 4,
 872         .mas_rpm_id = -1,
 873         .slv_rpm_id = 59,
 874         .qos.ap_owned = true,
 875         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 876 };
 877
 878 static struct qcom_icc_node slv_tlmm_north = {
 879         .name = "slv_tlmm_north",
 880         .id = SDM660_SLAVE_TLMM_NORTH,
 881         .buswidth = 8,
 882         .mas_rpm_id = -1,
 883         .slv_rpm_id = 214,
 884         .qos.ap_owned = true,
 885         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 886 };
 887
 888 static struct qcom_icc_node slv_tcsr = {
 889         .name = "slv_tcsr",
 890         .id = SDM660_SLAVE_TCSR,
 891         .buswidth = 4,
 892         .mas_rpm_id = -1,
 893         .slv_rpm_id = 50,
 894         .qos.ap_owned = true,
 895         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 896 };
 897
 898 static struct qcom_icc_node slv_pimem_cfg = {
 899         .name = "slv_pimem_cfg",
 900         .id = SDM660_SLAVE_PIMEM_CFG,
 901         .buswidth = 4,
 902         .mas_rpm_id = -1,
 903         .slv_rpm_id = 167,
 904         .qos.ap_owned = true,
 905         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 906 };
 907
 908 static struct qcom_icc_node slv_imem_cfg = {
 909         .name = "slv_imem_cfg",
 910         .id = SDM660_SLAVE_IMEM_CFG,
 911         .buswidth = 4,
 912         .mas_rpm_id = -1,
 913         .slv_rpm_id = 54,
 914         .qos.ap_owned = true,
 915         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 916 };
 917
 918 static struct qcom_icc_node slv_message_ram = {
 919         .name = "slv_message_ram",
 920         .id = SDM660_SLAVE_MESSAGE_RAM,
 921         .buswidth = 4,
 922         .mas_rpm_id = -1,
 923         .slv_rpm_id = 55,
 924         .qos.ap_owned = true,
 925         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 926 };
 927
 928 static struct qcom_icc_node slv_glm = {
 929         .name = "slv_glm",
 930         .id = SDM660_SLAVE_GLM,
 931         .buswidth = 4,
 932         .mas_rpm_id = -1,
 933         .slv_rpm_id = 209,
 934         .qos.ap_owned = true,
 935         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 936 };
 937
 938 static struct qcom_icc_node slv_bimc_cfg = {
 939         .name = "slv_bimc_cfg",
 940         .id = SDM660_SLAVE_BIMC_CFG,
 941         .buswidth = 4,
 942         .mas_rpm_id = -1,
 943         .slv_rpm_id = 56,
 944         .qos.ap_owned = true,
 945         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 946 };
 947
 948 static struct qcom_icc_node slv_prng = {
 949         .name = "slv_prng",
 950         .id = SDM660_SLAVE_PRNG,
 951         .buswidth = 4,
 952         .mas_rpm_id = -1,
 953         .slv_rpm_id = 44,
 954         .qos.ap_owned = true,
 955         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 956 };
 957
 958 static struct qcom_icc_node slv_spdm = {
 959         .name = "slv_spdm",
 960         .id = SDM660_SLAVE_SPDM,
 961         .buswidth = 4,
 962         .mas_rpm_id = -1,
 963         .slv_rpm_id = 60,
 964         .qos.ap_owned = true,
 965         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 966 };
 967
 968 static struct qcom_icc_node slv_qdss_cfg = {
 969         .name = "slv_qdss_cfg",
 970         .id = SDM660_SLAVE_QDSS_CFG,
 971         .buswidth = 4,
 972         .mas_rpm_id = -1,
 973         .slv_rpm_id = 63,
 974         .qos.ap_owned = true,
 975         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 976 };
 977
 978 static const u16 slv_cnoc_mnoc_cfg_links[] = {
 979         SDM660_MASTER_CNOC_MNOC_CFG
 980 };
 981
 982 static struct qcom_icc_node slv_cnoc_mnoc_cfg = {
 983         .name = "slv_cnoc_mnoc_cfg",
 984         .id = SDM660_SLAVE_CNOC_MNOC_CFG,
 985         .buswidth = 4,
 986         .mas_rpm_id = -1,
 987         .slv_rpm_id = 66,
 988         .qos.ap_owned = true,
 989         .qos.qos_mode = NOC_QOS_MODE_INVALID,
 990         .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links),
 991         .links = slv_cnoc_mnoc_cfg_links,
 992 };
 993
 994 static struct qcom_icc_node slv_snoc_cfg = {
 995         .name = "slv_snoc_cfg",
 996         .id = SDM660_SLAVE_SNOC_CFG,
 997         .buswidth = 4,
 998         .mas_rpm_id = -1,
 999         .slv_rpm_id = 70,
1000         .qos.ap_owned = true,
1001         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1002 };
1003
1004 static struct qcom_icc_node slv_qm_cfg = {
1005         .name = "slv_qm_cfg",
1006         .id = SDM660_SLAVE_QM_CFG,
1007         .buswidth = 4,
1008         .mas_rpm_id = -1,
1009         .slv_rpm_id = 212,
1010         .qos.ap_owned = true,
1011         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1012 };
1013
1014 static struct qcom_icc_node slv_clk_ctl = {
1015         .name = "slv_clk_ctl",
1016         .id = SDM660_SLAVE_CLK_CTL,
1017         .buswidth = 4,
1018         .mas_rpm_id = -1,
1019         .slv_rpm_id = 47,
1020         .qos.ap_owned = true,
1021         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1022 };
1023
1024 static struct qcom_icc_node slv_mss_cfg = {
1025         .name = "slv_mss_cfg",
1026         .id = SDM660_SLAVE_MSS_CFG,
1027         .buswidth = 4,
1028         .mas_rpm_id = -1,
1029         .slv_rpm_id = 48,
1030         .qos.ap_owned = true,
1031         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1032 };
1033
1034 static struct qcom_icc_node slv_tlmm_south = {
1035         .name = "slv_tlmm_south",
1036         .id = SDM660_SLAVE_TLMM_SOUTH,
1037         .buswidth = 4,
1038         .mas_rpm_id = -1,
1039         .slv_rpm_id = 217,
1040         .qos.ap_owned = true,
1041         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1042 };
1043
1044 static struct qcom_icc_node slv_ufs_cfg = {
1045         .name = "slv_ufs_cfg",
1046         .id = SDM660_SLAVE_UFS_CFG,
1047         .buswidth = 4,
1048         .mas_rpm_id = -1,
1049         .slv_rpm_id = 92,
1050         .qos.ap_owned = true,
1051         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1052 };
1053
1054 static struct qcom_icc_node slv_a2noc_cfg = {
1055         .name = "slv_a2noc_cfg",
1056         .id = SDM660_SLAVE_A2NOC_CFG,
1057         .buswidth = 4,
1058         .mas_rpm_id = -1,
1059         .slv_rpm_id = 150,
1060         .qos.ap_owned = true,
1061         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1062 };
1063
1064 static struct qcom_icc_node slv_a2noc_smmu_cfg = {
1065         .name = "slv_a2noc_smmu_cfg",
1066         .id = SDM660_SLAVE_A2NOC_SMMU_CFG,
1067         .buswidth = 8,
1068         .mas_rpm_id = -1,
1069         .slv_rpm_id = 152,
1070         .qos.ap_owned = true,
1071         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1072 };
1073
1074 static struct qcom_icc_node slv_gpuss_cfg = {
1075         .name = "slv_gpuss_cfg",
1076         .id = SDM660_SLAVE_GPUSS_CFG,
1077         .buswidth = 8,
1078         .mas_rpm_id = -1,
1079         .slv_rpm_id = 11,
1080         .qos.ap_owned = true,
1081         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1082 };
1083
1084 static struct qcom_icc_node slv_ahb2phy = {
1085         .name = "slv_ahb2phy",
1086         .id = SDM660_SLAVE_AHB2PHY,
1087         .buswidth = 4,
1088         .mas_rpm_id = -1,
1089         .slv_rpm_id = 163,
1090         .qos.ap_owned = true,
1091         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1092 };
1093
1094 static struct qcom_icc_node slv_blsp_1 = {
1095         .name = "slv_blsp_1",
1096         .id = SDM660_SLAVE_BLSP_1,
1097         .buswidth = 4,
1098         .mas_rpm_id = -1,
1099         .slv_rpm_id = 39,
1100         .qos.ap_owned = true,
1101         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1102 };
1103
1104 static struct qcom_icc_node slv_sdcc_1 = {
1105         .name = "slv_sdcc_1",
1106         .id = SDM660_SLAVE_SDCC_1,
1107         .buswidth = 4,
1108         .mas_rpm_id = -1,
1109         .slv_rpm_id = 31,
1110         .qos.ap_owned = true,
1111         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1112 };
1113
1114 static struct qcom_icc_node slv_sdcc_2 = {
1115         .name = "slv_sdcc_2",
1116         .id = SDM660_SLAVE_SDCC_2,
1117         .buswidth = 4,
1118         .mas_rpm_id = -1,
1119         .slv_rpm_id = 33,
1120         .qos.ap_owned = true,
1121         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1122 };
1123
1124 static struct qcom_icc_node slv_tlmm_center = {
1125         .name = "slv_tlmm_center",
1126         .id = SDM660_SLAVE_TLMM_CENTER,
1127         .buswidth = 4,
1128         .mas_rpm_id = -1,
1129         .slv_rpm_id = 218,
1130         .qos.ap_owned = true,
1131         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1132 };
1133
1134 static struct qcom_icc_node slv_blsp_2 = {
1135         .name = "slv_blsp_2",
1136         .id = SDM660_SLAVE_BLSP_2,
1137         .buswidth = 4,
1138         .mas_rpm_id = -1,
1139         .slv_rpm_id = 37,
1140         .qos.ap_owned = true,
1141         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1142 };
1143
1144 static struct qcom_icc_node slv_pdm = {
1145         .name = "slv_pdm",
1146         .id = SDM660_SLAVE_PDM,
1147         .buswidth = 4,
1148         .mas_rpm_id = -1,
1149         .slv_rpm_id = 41,
1150         .qos.ap_owned = true,
1151         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1152 };
1153
1154 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = {
1155         SDM660_MASTER_CNOC_MNOC_MMSS_CFG
1156 };
1157
1158 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = {
1159         .name = "slv_cnoc_mnoc_mmss_cfg",
1160         .id = SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
1161         .buswidth = 8,
1162         .mas_rpm_id = -1,
1163         .slv_rpm_id = 58,
1164         .qos.ap_owned = true,
1165         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1166         .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links),
1167         .links = slv_cnoc_mnoc_mmss_cfg_links,
1168 };
1169
1170 static struct qcom_icc_node slv_usb_hs = {
1171         .name = "slv_usb_hs",
1172         .id = SDM660_SLAVE_USB_HS,
1173         .buswidth = 4,
1174         .mas_rpm_id = -1,
1175         .slv_rpm_id = 40,
1176         .qos.ap_owned = true,
1177         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1178 };
1179
1180 static struct qcom_icc_node slv_usb3_0 = {
1181         .name = "slv_usb3_0",
1182         .id = SDM660_SLAVE_USB3_0,
1183         .buswidth = 4,
1184         .mas_rpm_id = -1,
1185         .slv_rpm_id = 22,
1186         .qos.ap_owned = true,
1187         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1188 };
1189
1190 static struct qcom_icc_node slv_srvc_cnoc = {
1191         .name = "slv_srvc_cnoc",
1192         .id = SDM660_SLAVE_SRVC_CNOC,
1193         .buswidth = 4,
1194         .mas_rpm_id = -1,
1195         .slv_rpm_id = 76,
1196         .qos.ap_owned = true,
1197         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1198 };
1199
1200 static const u16 slv_gnoc_bimc_links[] = {
1201         SDM660_MASTER_GNOC_BIMC
1202 };
1203
1204 static struct qcom_icc_node slv_gnoc_bimc = {
1205         .name = "slv_gnoc_bimc",
1206         .id = SDM660_SLAVE_GNOC_BIMC,
1207         .buswidth = 16,
1208         .mas_rpm_id = -1,
1209         .slv_rpm_id = 210,
1210         .qos.ap_owned = true,
1211         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1212         .num_links = ARRAY_SIZE(slv_gnoc_bimc_links),
1213         .links = slv_gnoc_bimc_links,
1214 };
1215
1216 static const u16 slv_gnoc_snoc_links[] = {
1217         SDM660_MASTER_GNOC_SNOC
1218 };
1219
1220 static struct qcom_icc_node slv_gnoc_snoc = {
1221         .name = "slv_gnoc_snoc",
1222         .id = SDM660_SLAVE_GNOC_SNOC,
1223         .buswidth = 8,
1224         .mas_rpm_id = -1,
1225         .slv_rpm_id = 211,
1226         .qos.ap_owned = true,
1227         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1228         .num_links = ARRAY_SIZE(slv_gnoc_snoc_links),
1229         .links = slv_gnoc_snoc_links,
1230 };
1231
1232 static struct qcom_icc_node slv_camera_cfg = {
1233         .name = "slv_camera_cfg",
1234         .id = SDM660_SLAVE_CAMERA_CFG,
1235         .buswidth = 4,
1236         .mas_rpm_id = -1,
1237         .slv_rpm_id = 3,
1238         .qos.ap_owned = true,
1239         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1240 };
1241
1242 static struct qcom_icc_node slv_camera_throttle_cfg = {
1243         .name = "slv_camera_throttle_cfg",
1244         .id = SDM660_SLAVE_CAMERA_THROTTLE_CFG,
1245         .buswidth = 4,
1246         .mas_rpm_id = -1,
1247         .slv_rpm_id = 154,
1248         .qos.ap_owned = true,
1249         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1250 };
1251
1252 static struct qcom_icc_node slv_misc_cfg = {
1253         .name = "slv_misc_cfg",
1254         .id = SDM660_SLAVE_MISC_CFG,
1255         .buswidth = 4,
1256         .mas_rpm_id = -1,
1257         .slv_rpm_id = 8,
1258         .qos.ap_owned = true,
1259         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1260 };
1261
1262 static struct qcom_icc_node slv_venus_throttle_cfg = {
1263         .name = "slv_venus_throttle_cfg",
1264         .id = SDM660_SLAVE_VENUS_THROTTLE_CFG,
1265         .buswidth = 4,
1266         .mas_rpm_id = -1,
1267         .slv_rpm_id = 178,
1268         .qos.ap_owned = true,
1269         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1270 };
1271
1272 static struct qcom_icc_node slv_venus_cfg = {
1273         .name = "slv_venus_cfg",
1274         .id = SDM660_SLAVE_VENUS_CFG,
1275         .buswidth = 4,
1276         .mas_rpm_id = -1,
1277         .slv_rpm_id = 10,
1278         .qos.ap_owned = true,
1279         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1280 };
1281
1282 static struct qcom_icc_node slv_mmss_clk_xpu_cfg = {
1283         .name = "slv_mmss_clk_xpu_cfg",
1284         .id = SDM660_SLAVE_MMSS_CLK_XPU_CFG,
1285         .buswidth = 4,
1286         .mas_rpm_id = -1,
1287         .slv_rpm_id = 13,
1288         .qos.ap_owned = true,
1289         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1290 };
1291
1292 static struct qcom_icc_node slv_mmss_clk_cfg = {
1293         .name = "slv_mmss_clk_cfg",
1294         .id = SDM660_SLAVE_MMSS_CLK_CFG,
1295         .buswidth = 4,
1296         .mas_rpm_id = -1,
1297         .slv_rpm_id = 12,
1298         .qos.ap_owned = true,
1299         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1300 };
1301
1302 static struct qcom_icc_node slv_mnoc_mpu_cfg = {
1303         .name = "slv_mnoc_mpu_cfg",
1304         .id = SDM660_SLAVE_MNOC_MPU_CFG,
1305         .buswidth = 4,
1306         .mas_rpm_id = -1,
1307         .slv_rpm_id = 14,
1308         .qos.ap_owned = true,
1309         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1310 };
1311
1312 static struct qcom_icc_node slv_display_cfg = {
1313         .name = "slv_display_cfg",
1314         .id = SDM660_SLAVE_DISPLAY_CFG,
1315         .buswidth = 4,
1316         .mas_rpm_id = -1,
1317         .slv_rpm_id = 4,
1318         .qos.ap_owned = true,
1319         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1320 };
1321
1322 static struct qcom_icc_node slv_csi_phy_cfg = {
1323         .name = "slv_csi_phy_cfg",
1324         .id = SDM660_SLAVE_CSI_PHY_CFG,
1325         .buswidth = 4,
1326         .mas_rpm_id = -1,
1327         .slv_rpm_id = 224,
1328         .qos.ap_owned = true,
1329         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1330 };
1331
1332 static struct qcom_icc_node slv_display_throttle_cfg = {
1333         .name = "slv_display_throttle_cfg",
1334         .id = SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
1335         .buswidth = 4,
1336         .mas_rpm_id = -1,
1337         .slv_rpm_id = 156,
1338         .qos.ap_owned = true,
1339         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1340 };
1341
1342 static struct qcom_icc_node slv_smmu_cfg = {
1343         .name = "slv_smmu_cfg",
1344         .id = SDM660_SLAVE_SMMU_CFG,
1345         .buswidth = 8,
1346         .mas_rpm_id = -1,
1347         .slv_rpm_id = 205,
1348         .qos.ap_owned = true,
1349         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1350 };
1351
1352 static const u16 slv_mnoc_bimc_links[] = {
1353         SDM660_MASTER_MNOC_BIMC
1354 };
1355
1356 static struct qcom_icc_node slv_mnoc_bimc = {
1357         .name = "slv_mnoc_bimc",
1358         .id = SDM660_SLAVE_MNOC_BIMC,
1359         .buswidth = 16,
1360         .mas_rpm_id = -1,
1361         .slv_rpm_id = 16,
1362         .qos.ap_owned = true,
1363         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1364         .num_links = ARRAY_SIZE(slv_mnoc_bimc_links),
1365         .links = slv_mnoc_bimc_links,
1366 };
1367
1368 static struct qcom_icc_node slv_srvc_mnoc = {
1369         .name = "slv_srvc_mnoc",
1370         .id = SDM660_SLAVE_SRVC_MNOC,
1371         .buswidth = 8,
1372         .mas_rpm_id = -1,
1373         .slv_rpm_id = 17,
1374         .qos.ap_owned = true,
1375         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1376 };
1377
1378 static struct qcom_icc_node slv_hmss = {
1379         .name = "slv_hmss",
1380         .id = SDM660_SLAVE_HMSS,
1381         .buswidth = 8,
1382         .mas_rpm_id = -1,
1383         .slv_rpm_id = 20,
1384         .qos.ap_owned = true,
1385         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1386 };
1387
1388 static struct qcom_icc_node slv_lpass = {
1389         .name = "slv_lpass",
1390         .id = SDM660_SLAVE_LPASS,
1391         .buswidth = 4,
1392         .mas_rpm_id = -1,
1393         .slv_rpm_id = 21,
1394         .qos.ap_owned = true,
1395         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1396 };
1397
1398 static struct qcom_icc_node slv_wlan = {
1399         .name = "slv_wlan",
1400         .id = SDM660_SLAVE_WLAN,
1401         .buswidth = 4,
1402         .mas_rpm_id = -1,
1403         .slv_rpm_id = 206,
1404 };
1405
1406 static struct qcom_icc_node slv_cdsp = {
1407         .name = "slv_cdsp",
1408         .id = SDM660_SLAVE_CDSP,
1409         .buswidth = 4,
1410         .mas_rpm_id = -1,
1411         .slv_rpm_id = 221,
1412         .qos.ap_owned = true,
1413         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1414 };
1415
1416 static struct qcom_icc_node slv_ipa = {
1417         .name = "slv_ipa",
1418         .id = SDM660_SLAVE_IPA,
1419         .buswidth = 4,
1420         .mas_rpm_id = -1,
1421         .slv_rpm_id = 183,
1422         .qos.ap_owned = true,
1423         .qos.qos_mode = NOC_QOS_MODE_INVALID,
1424 };
1425
1426 static const u16 slv_snoc_bimc_links[] = {
1427         SDM660_MASTER_SNOC_BIMC
1428 };
1429
1430 static struct qcom_icc_node slv_snoc_bimc = {
1431         .name = "slv_snoc_bimc",
1432         .id = SDM660_SLAVE_SNOC_BIMC,
1433         .buswidth = 16,
1434         .mas_rpm_id = -1,
1435         .slv_rpm_id = 24,
1436         .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1437         .links = slv_snoc_bimc_links,
1438 };
1439
1440 static const u16 slv_snoc_cnoc_links[] = {
1441         SDM660_MASTER_SNOC_CNOC
1442 };
1443
1444 static struct qcom_icc_node slv_snoc_cnoc = {
1445         .name = "slv_snoc_cnoc",
1446         .id = SDM660_SLAVE_SNOC_CNOC,
1447         .buswidth = 8,
1448         .mas_rpm_id = -1,
1449         .slv_rpm_id = 25,
1450         .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1451         .links = slv_snoc_cnoc_links,
1452 };
1453
1454 static struct qcom_icc_node slv_imem = {
1455         .name = "slv_imem",
1456         .id = SDM660_SLAVE_IMEM,
1457         .buswidth = 8,
1458         .mas_rpm_id = -1,
1459         .slv_rpm_id = 26,
1460 };
1461
1462 static struct qcom_icc_node slv_pimem = {
1463         .name = "slv_pimem",
1464         .id = SDM660_SLAVE_PIMEM,
1465         .buswidth = 8,
1466         .mas_rpm_id = -1,
1467         .slv_rpm_id = 166,
1468 };
1469
1470 static struct qcom_icc_node slv_qdss_stm = {
1471         .name = "slv_qdss_stm",
1472         .id = SDM660_SLAVE_QDSS_STM,
1473         .buswidth = 4,
1474         .mas_rpm_id = -1,
1475         .slv_rpm_id = 30,
1476 };
1477
1478 static struct qcom_icc_node slv_srvc_snoc = {
1479         .name = "slv_srvc_snoc",
1480         .id = SDM660_SLAVE_SRVC_SNOC,
1481         .buswidth = 16,
1482         .mas_rpm_id = -1,
1483         .slv_rpm_id = 29,
1484 };
1485
1486 static struct qcom_icc_node * const sdm660_a2noc_nodes[] = {
1487         [MASTER_IPA] = &mas_ipa,
1488         [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
1489         [MASTER_SDCC_1] = &mas_sdcc_1,
1490         [MASTER_SDCC_2] = &mas_sdcc_2,
1491         [MASTER_BLSP_1] = &mas_blsp_1,
1492         [MASTER_BLSP_2] = &mas_blsp_2,
1493         [MASTER_UFS] = &mas_ufs,
1494         [MASTER_USB_HS] = &mas_usb_hs,
1495         [MASTER_USB3] = &mas_usb3,
1496         [MASTER_CRYPTO_C0] = &mas_crypto,
1497         [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
1498 };
1499
1500 static const struct regmap_config sdm660_a2noc_regmap_config = {
1501         .reg_bits       = 32,
1502         .reg_stride     = 4,
1503         .val_bits       = 32,
1504         .max_register   = 0x20000,
1505         .fast_io        = true,
1506 };
1507
1508 static const struct qcom_icc_desc sdm660_a2noc = {
1509         .type = QCOM_ICC_NOC,
1510         .nodes = sdm660_a2noc_nodes,
1511         .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
1512         .bus_clk_desc = &aggre2_clk,
1513         .intf_clocks = a2noc_intf_clocks,
1514         .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks),
1515         .regmap_cfg = &sdm660_a2noc_regmap_config,
1516 };
1517
1518 static struct qcom_icc_node * const sdm660_bimc_nodes[] = {
1519         [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
1520         [MASTER_OXILI] = &mas_oxili,
1521         [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
1522         [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1523         [MASTER_PIMEM] = &mas_pimem,
1524         [SLAVE_EBI] = &slv_ebi,
1525         [SLAVE_HMSS_L3] = &slv_hmss_l3,
1526         [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1527 };
1528
1529 static const struct regmap_config sdm660_bimc_regmap_config = {
1530         .reg_bits       = 32,
1531         .reg_stride     = 4,
1532         .val_bits       = 32,
1533         .max_register   = 0x80000,
1534         .fast_io        = true,
1535 };
1536
1537 static const struct qcom_icc_desc sdm660_bimc = {
1538         .type = QCOM_ICC_BIMC,
1539         .nodes = sdm660_bimc_nodes,
1540         .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
1541         .bus_clk_desc = &bimc_clk,
1542         .regmap_cfg = &sdm660_bimc_regmap_config,
1543 };
1544
1545 static struct qcom_icc_node * const sdm660_cnoc_nodes[] = {
1546         [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1547         [MASTER_QDSS_DAP] = &mas_qdss_dap,
1548         [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
1549         [SLAVE_MPM] = &slv_mpm,
1550         [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1551         [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
1552         [SLAVE_TCSR] = &slv_tcsr,
1553         [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1554         [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1555         [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1556         [SLAVE_GLM] = &slv_glm,
1557         [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1558         [SLAVE_PRNG] = &slv_prng,
1559         [SLAVE_SPDM] = &slv_spdm,
1560         [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1561         [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
1562         [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1563         [SLAVE_QM_CFG] = &slv_qm_cfg,
1564         [SLAVE_CLK_CTL] = &slv_clk_ctl,
1565         [SLAVE_MSS_CFG] = &slv_mss_cfg,
1566         [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
1567         [SLAVE_UFS_CFG] = &slv_ufs_cfg,
1568         [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
1569         [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
1570         [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
1571         [SLAVE_AHB2PHY] = &slv_ahb2phy,
1572         [SLAVE_BLSP_1] = &slv_blsp_1,
1573         [SLAVE_SDCC_1] = &slv_sdcc_1,
1574         [SLAVE_SDCC_2] = &slv_sdcc_2,
1575         [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
1576         [SLAVE_BLSP_2] = &slv_blsp_2,
1577         [SLAVE_PDM] = &slv_pdm,
1578         [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
1579         [SLAVE_USB_HS] = &slv_usb_hs,
1580         [SLAVE_USB3_0] = &slv_usb3_0,
1581         [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
1582 };
1583
1584 static const struct regmap_config sdm660_cnoc_regmap_config = {
1585         .reg_bits       = 32,
1586         .reg_stride     = 4,
1587         .val_bits       = 32,
1588         .max_register   = 0x10000,
1589         .fast_io        = true,
1590 };
1591
1592 static const struct qcom_icc_desc sdm660_cnoc = {
1593         .type = QCOM_ICC_NOC,
1594         .nodes = sdm660_cnoc_nodes,
1595         .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
1596         .bus_clk_desc = &bus_2_clk,
1597         .regmap_cfg = &sdm660_cnoc_regmap_config,
1598 };
1599
1600 static struct qcom_icc_node * const sdm660_gnoc_nodes[] = {
1601         [MASTER_APSS_PROC] = &mas_apss_proc,
1602         [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
1603         [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
1604 };
1605
1606 static const struct regmap_config sdm660_gnoc_regmap_config = {
1607         .reg_bits       = 32,
1608         .reg_stride     = 4,
1609         .val_bits       = 32,
1610         .max_register   = 0xe000,
1611         .fast_io        = true,
1612 };
1613
1614 static const struct qcom_icc_desc sdm660_gnoc = {
1615         .type = QCOM_ICC_NOC,
1616         .nodes = sdm660_gnoc_nodes,
1617         .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
1618         .regmap_cfg = &sdm660_gnoc_regmap_config,
1619 };
1620
1621 static struct qcom_icc_node * const sdm660_mnoc_nodes[] = {
1622         [MASTER_CPP] = &mas_cpp,
1623         [MASTER_JPEG] = &mas_jpeg,
1624         [MASTER_MDP_P0] = &mas_mdp_p0,
1625         [MASTER_MDP_P1] = &mas_mdp_p1,
1626         [MASTER_VENUS] = &mas_venus,
1627         [MASTER_VFE] = &mas_vfe,
1628         [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
1629         [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
1630         [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1631         [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
1632         [SLAVE_MISC_CFG] = &slv_misc_cfg,
1633         [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1634         [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1635         [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
1636         [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
1637         [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
1638         [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1639         [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
1640         [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1641         [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
1642         [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
1643         [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
1644 };
1645
1646 static const struct regmap_config sdm660_mnoc_regmap_config = {
1647         .reg_bits       = 32,
1648         .reg_stride     = 4,
1649         .val_bits       = 32,
1650         .max_register   = 0x10000,
1651         .fast_io        = true,
1652 };
1653
1654 static const struct qcom_icc_desc sdm660_mnoc = {
1655         .type = QCOM_ICC_NOC,
1656         .nodes = sdm660_mnoc_nodes,
1657         .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
1658         .bus_clk_desc = &mmaxi_0_clk,
1659         .intf_clocks = mm_intf_clocks,
1660         .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks),
1661         .regmap_cfg = &sdm660_mnoc_regmap_config,
1662 };
1663
1664 static struct qcom_icc_node * const sdm660_snoc_nodes[] = {
1665         [MASTER_QDSS_ETR] = &mas_qdss_etr,
1666         [MASTER_QDSS_BAM] = &mas_qdss_bam,
1667         [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1668         [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1669         [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
1670         [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
1671         [SLAVE_HMSS] = &slv_hmss,
1672         [SLAVE_LPASS] = &slv_lpass,
1673         [SLAVE_WLAN] = &slv_wlan,
1674         [SLAVE_CDSP] = &slv_cdsp,
1675         [SLAVE_IPA] = &slv_ipa,
1676         [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1677         [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1678         [SLAVE_IMEM] = &slv_imem,
1679         [SLAVE_PIMEM] = &slv_pimem,
1680         [SLAVE_QDSS_STM] = &slv_qdss_stm,
1681         [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
1682 };
1683
1684 static const struct regmap_config sdm660_snoc_regmap_config = {
1685         .reg_bits       = 32,
1686         .reg_stride     = 4,
1687         .val_bits       = 32,
1688         .max_register   = 0x20000,
1689         .fast_io        = true,
1690 };
1691
1692 static const struct qcom_icc_desc sdm660_snoc = {
1693         .type = QCOM_ICC_NOC,
1694         .nodes = sdm660_snoc_nodes,
1695         .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
1696         .bus_clk_desc = &bus_1_clk,
1697         .regmap_cfg = &sdm660_snoc_regmap_config,
1698 };
1699
1700 static const struct of_device_id sdm660_noc_of_match[] = {
1701         { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
1702         { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
1703         { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
1704         { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
1705         { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
1706         { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
1707         { },
1708 };
1709 MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
1710
1711 static struct platform_driver sdm660_noc_driver = {
1712         .probe = qnoc_probe,
1713         .remove = qnoc_remove,
1714         .driver = {
1715                 .name = "qnoc-sdm660",
1716                 .of_match_table = sdm660_noc_of_match,
1717         },
1718 };
1719 module_platform_driver(sdm660_noc_driver);
1720 MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
1721 MODULE_LICENSE("GPL v2");