arch/mips/include/asm/io.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <[email protected]>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #include <linux/compiler.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/irqflags.h>
  19
  20 #include <asm/addrspace.h>
  21 #include <asm/barrier.h>
  22 #include <asm/bug.h>
  23 #include <asm/byteorder.h>
  24 #include <asm/cpu.h>
  25 #include <asm/cpu-features.h>
  26 #include <asm/page.h>
  27 #include <asm/pgtable-bits.h>
  28 #include <asm/processor.h>
  29 #include <asm/string.h>
  30 #include <mangle-port.h>
  31
  32 /*
  33  * Raw operations are never swapped in software.  OTOH values that raw
  34  * operations are working on may or may not have been swapped by the bus
  35  * hardware.  An example use would be for flash memory that's used for
  36  * execute in place.
  37  */
  38 # define __raw_ioswabb(a, x)    (x)
  39 # define __raw_ioswabw(a, x)    (x)
  40 # define __raw_ioswabl(a, x)    (x)
  41 # define __raw_ioswabq(a, x)    (x)
  42 # define ____raw_ioswabq(a, x)  (x)
  43
  44 # define __relaxed_ioswabb ioswabb
  45 # define __relaxed_ioswabw ioswabw
  46 # define __relaxed_ioswabl ioswabl
  47 # define __relaxed_ioswabq ioswabq
  48
  49 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  50
  51 /*
  52  * On MIPS I/O ports are memory mapped, so we access them using normal
  53  * load/store instructions. mips_io_port_base is the virtual address to
  54  * which all ports are being mapped.  For sake of efficiency some code
  55  * assumes that this is an address that can be loaded with a single lui
  56  * instruction, so the lower 16 bits must be zero.  Should be true on
  57  * any sane architecture; generic code does not use this assumption.
  58  */
  59 extern unsigned long mips_io_port_base;
  60
  61 static inline void set_io_port_base(unsigned long base)
  62 {
  63         mips_io_port_base = base;
  64 }
  65
  66 /*
  67  * Provide the necessary definitions for generic iomap. We make use of
  68  * mips_io_port_base for iomap(), but we don't reserve any low addresses for
  69  * use with I/O ports.
  70  */
  71
  72 #define HAVE_ARCH_PIO_SIZE
  73 #define PIO_OFFSET      mips_io_port_base
  74 #define PIO_MASK        IO_SPACE_LIMIT
  75 #define PIO_RESERVED    0x0UL
  76
  77 /*
  78  * Enforce in-order execution of data I/O.  In the MIPS architecture
  79  * these are equivalent to corresponding platform-specific memory
  80  * barriers defined in <asm/barrier.h>.  API pinched from PowerPC,
  81  * with sync additionally defined.
  82  */
  83 #define iobarrier_rw() mb()
  84 #define iobarrier_r() rmb()
  85 #define iobarrier_w() wmb()
  86 #define iobarrier_sync() iob()
  87
  88 /*
  89  *     virt_to_phys    -       map virtual addresses to physical
  90  *     @address: address to remap
  91  *
  92  *     The returned physical address is the physical (CPU) mapping for
  93  *     the memory address given. It is only valid to use this function on
  94  *     addresses directly mapped or allocated via kmalloc.
  95  *
  96  *     This function does not give bus mappings for DMA transfers. In
  97  *     almost all conceivable cases a device driver should not be using
  98  *     this function
  99  */
 100 static inline unsigned long __virt_to_phys_nodebug(volatile const void *address)
 101 {
 102         return __pa(address);
 103 }
 104
 105 #ifdef CONFIG_DEBUG_VIRTUAL
 106 extern phys_addr_t __virt_to_phys(volatile const void *x);
 107 #else
 108 #define __virt_to_phys(x)       __virt_to_phys_nodebug(x)
 109 #endif
 110
 111 #define virt_to_phys virt_to_phys
 112 static inline phys_addr_t virt_to_phys(const volatile void *x)
 113 {
 114         return __virt_to_phys(x);
 115 }
 116
 117 /*
 118  *     phys_to_virt    -       map physical address to virtual
 119  *     @address: address to remap
 120  *
 121  *     The returned virtual address is a current CPU mapping for
 122  *     the memory address given. It is only valid to use this function on
 123  *     addresses that have a kernel mapping
 124  *
 125  *     This function does not handle bus mappings for DMA transfers. In
 126  *     almost all conceivable cases a device driver should not be using
 127  *     this function
 128  */
 129 static inline void * phys_to_virt(unsigned long address)
 130 {
 131         return __va(address);
 132 }
 133
 134 /*
 135  * ISA I/O bus memory addresses are 1:1 with the physical address.
 136  */
 137 static inline unsigned long isa_virt_to_bus(volatile void *address)
 138 {
 139         return virt_to_phys(address);
 140 }
 141
 142 static inline void *isa_bus_to_virt(unsigned long address)
 143 {
 144         return phys_to_virt(address);
 145 }
 146
 147 /*
 148  * Change "struct page" to physical address.
 149  */
 150 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 151
 152 void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
 153                 unsigned long prot_val);
 154 void iounmap(const volatile void __iomem *addr);
 155
 156 /*
 157  * ioremap     -   map bus memory into CPU space
 158  * @offset:    bus address of the memory
 159  * @size:      size of the resource to map
 160  *
 161  * ioremap performs a platform specific sequence of operations to
 162  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 163  * writew/writel functions and the other mmio helpers. The returned
 164  * address is not guaranteed to be usable directly as a virtual
 165  * address.
 166  */
 167 #define ioremap(offset, size)                                           \
 168         ioremap_prot((offset), (size), _CACHE_UNCACHED)
 169 #define ioremap_uc              ioremap
 170
 171 /*
 172  * ioremap_cache -      map bus memory into CPU space
 173  * @offset:         bus address of the memory
 174  * @size:           size of the resource to map
 175  *
 176  * ioremap_cache performs a platform specific sequence of operations to
 177  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 178  * writew/writel functions and the other mmio helpers. The returned
 179  * address is not guaranteed to be usable directly as a virtual
 180  * address.
 181  *
 182  * This version of ioremap ensures that the memory is marked cachable by
 183  * the CPU.  Also enables full write-combining.  Useful for some
 184  * memory-like regions on I/O busses.
 185  */
 186 #define ioremap_cache(offset, size)                                     \
 187         ioremap_prot((offset), (size), _page_cachable_default)
 188
 189 /*
 190  * ioremap_wc     -   map bus memory into CPU space
 191  * @offset:    bus address of the memory
 192  * @size:      size of the resource to map
 193  *
 194  * ioremap_wc performs a platform specific sequence of operations to
 195  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 196  * writew/writel functions and the other mmio helpers. The returned
 197  * address is not guaranteed to be usable directly as a virtual
 198  * address.
 199  *
 200  * This version of ioremap ensures that the memory is marked uncachable
 201  * but accelerated by means of write-combining feature. It is specifically
 202  * useful for PCIe prefetchable windows, which may vastly improve a
 203  * communications performance. If it was determined on boot stage, what
 204  * CPU CCA doesn't support UCA, the method shall fall-back to the
 205  * _CACHE_UNCACHED option (see cpu_probe() method).
 206  */
 207 #define ioremap_wc(offset, size)                                        \
 208         ioremap_prot((offset), (size), boot_cpu_data.writecombine)
 209
 210 #include <asm-generic/iomap.h>
 211
 212 #if defined(CONFIG_CPU_CAVIUM_OCTEON)
 213 #define war_io_reorder_wmb()            wmb()
 214 #else
 215 #define war_io_reorder_wmb()            barrier()
 216 #endif
 217
 218 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq)     \
 219                                                                         \
 220 static inline void pfx##write##bwlq(type val,                           \
 221                                     volatile void __iomem *mem)         \
 222 {                                                                       \
 223         volatile type *__mem;                                           \
 224         type __val;                                                     \
 225                                                                         \
 226         if (barrier)                                                    \
 227                 iobarrier_rw();                                         \
 228         else                                                            \
 229                 war_io_reorder_wmb();                                   \
 230                                                                         \
 231         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 232                                                                         \
 233         __val = pfx##ioswab##bwlq(__mem, val);                          \
 234                                                                         \
 235         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 236                 *__mem = __val;                                         \
 237         else if (cpu_has_64bits) {                                      \
 238                 unsigned long __flags;                                  \
 239                 type __tmp;                                             \
 240                                                                         \
 241                 if (irq)                                                \
 242                         local_irq_save(__flags);                        \
 243                 __asm__ __volatile__(                                   \
 244                         ".set   push"           "\t\t# __writeq""\n\t"  \
 245                         ".set   arch=r4000"                     "\n\t"  \
 246                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 247                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 248                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 249                         "or     %L0, %L0, %M0"                  "\n\t"  \
 250                         "sd     %L0, %2"                        "\n\t"  \
 251                         ".set   pop"                            "\n"    \
 252                         : "=r" (__tmp)                                  \
 253                         : "0" (__val), "m" (*__mem));                   \
 254                 if (irq)                                                \
 255                         local_irq_restore(__flags);                     \
 256         } else                                                          \
 257                 BUG();                                                  \
 258 }                                                                       \
 259                                                                         \
 260 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
 261 {                                                                       \
 262         volatile type *__mem;                                           \
 263         type __val;                                                     \
 264                                                                         \
 265         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 266                                                                         \
 267         if (barrier)                                                    \
 268                 iobarrier_rw();                                         \
 269                                                                         \
 270         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 271                 __val = *__mem;                                         \
 272         else if (cpu_has_64bits) {                                      \
 273                 unsigned long __flags;                                  \
 274                                                                         \
 275                 if (irq)                                                \
 276                         local_irq_save(__flags);                        \
 277                 __asm__ __volatile__(                                   \
 278                         ".set   push"           "\t\t# __readq" "\n\t"  \
 279                         ".set   arch=r4000"                     "\n\t"  \
 280                         "ld     %L0, %1"                        "\n\t"  \
 281                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 282                         "sll    %L0, %L0, 0"                    "\n\t"  \
 283                         ".set   pop"                            "\n"    \
 284                         : "=r" (__val)                                  \
 285                         : "m" (*__mem));                                \
 286                 if (irq)                                                \
 287                         local_irq_restore(__flags);                     \
 288         } else {                                                        \
 289                 __val = 0;                                              \
 290                 BUG();                                                  \
 291         }                                                               \
 292                                                                         \
 293         /* prevent prefetching of coherent DMA data prematurely */      \
 294         if (!relax)                                                     \
 295                 rmb();                                                  \
 296         return pfx##ioswab##bwlq(__mem, __val);                         \
 297 }
 298
 299 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p)       \
 300                                                                         \
 301 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 302 {                                                                       \
 303         volatile type *__addr;                                          \
 304         type __val;                                                     \
 305                                                                         \
 306         if (barrier)                                                    \
 307                 iobarrier_rw();                                         \
 308         else                                                            \
 309                 war_io_reorder_wmb();                                   \
 310                                                                         \
 311         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 312                                                                         \
 313         __val = pfx##ioswab##bwlq(__addr, val);                         \
 314                                                                         \
 315         /* Really, we want this to be atomic */                         \
 316         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 317                                                                         \
 318         *__addr = __val;                                                \
 319 }                                                                       \
 320                                                                         \
 321 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 322 {                                                                       \
 323         volatile type *__addr;                                          \
 324         type __val;                                                     \
 325                                                                         \
 326         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
 327                                                                         \
 328         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
 329                                                                         \
 330         if (barrier)                                                    \
 331                 iobarrier_rw();                                         \
 332                                                                         \
 333         __val = *__addr;                                                \
 334                                                                         \
 335         /* prevent prefetching of coherent DMA data prematurely */      \
 336         if (!relax)                                                     \
 337                 rmb();                                                  \
 338         return pfx##ioswab##bwlq(__addr, __val);                        \
 339 }
 340
 341 #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax)                      \
 342                                                                         \
 343 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
 344
 345 #define BUILDIO_MEM(bwlq, type)                                         \
 346                                                                         \
 347 __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0)                               \
 348 __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1)                           \
 349 __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0)                               \
 350 __BUILD_MEMORY_PFX(, bwlq, type, 0)
 351
 352 BUILDIO_MEM(b, u8)
 353 BUILDIO_MEM(w, u16)
 354 BUILDIO_MEM(l, u32)
 355 #ifdef CONFIG_64BIT
 356 BUILDIO_MEM(q, u64)
 357 #else
 358 __BUILD_MEMORY_PFX(__raw_, q, u64, 0)
 359 __BUILD_MEMORY_PFX(__mem_, q, u64, 0)
 360 #endif
 361
 362 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 363         __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,)                   \
 364         __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
 365
 366 #define BUILDIO_IOPORT(bwlq, type)                                      \
 367         __BUILD_IOPORT_PFX(, bwlq, type)                                \
 368         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
 369
 370 BUILDIO_IOPORT(b, u8)
 371 BUILDIO_IOPORT(w, u16)
 372 BUILDIO_IOPORT(l, u32)
 373 #ifdef CONFIG_64BIT
 374 BUILDIO_IOPORT(q, u64)
 375 #endif
 376
 377 #define __BUILDIO(bwlq, type)                                           \
 378                                                                         \
 379 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
 380
 381 __BUILDIO(q, u64)
 382
 383 #define readb_relaxed                   __relaxed_readb
 384 #define readw_relaxed                   __relaxed_readw
 385 #define readl_relaxed                   __relaxed_readl
 386 #ifdef CONFIG_64BIT
 387 #define readq_relaxed                   __relaxed_readq
 388 #endif
 389
 390 #define writeb_relaxed                  __relaxed_writeb
 391 #define writew_relaxed                  __relaxed_writew
 392 #define writel_relaxed                  __relaxed_writel
 393 #ifdef CONFIG_64BIT
 394 #define writeq_relaxed                  __relaxed_writeq
 395 #endif
 396
 397 #define readb_be(addr)                                                  \
 398         __raw_readb((__force unsigned *)(addr))
 399 #define readw_be(addr)                                                  \
 400         be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
 401 #define readl_be(addr)                                                  \
 402         be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
 403 #define readq_be(addr)                                                  \
 404         be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
 405
 406 #define writeb_be(val, addr)                                            \
 407         __raw_writeb((val), (__force unsigned *)(addr))
 408 #define writew_be(val, addr)                                            \
 409         __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
 410 #define writel_be(val, addr)                                            \
 411         __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
 412 #define writeq_be(val, addr)                                            \
 413         __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
 414
 415 /*
 416  * Some code tests for these symbols
 417  */
 418 #ifdef CONFIG_64BIT
 419 #define readq                           readq
 420 #define writeq                          writeq
 421 #endif
 422
 423 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 424                                                                         \
 425 static inline void writes##bwlq(volatile void __iomem *mem,             \
 426                                 const void *addr, unsigned int count)   \
 427 {                                                                       \
 428         const volatile type *__addr = addr;                             \
 429                                                                         \
 430         while (count--) {                                               \
 431                 __mem_write##bwlq(*__addr, mem);                        \
 432                 __addr++;                                               \
 433         }                                                               \
 434 }                                                                       \
 435                                                                         \
 436 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 437                                unsigned int count)                      \
 438 {                                                                       \
 439         volatile type *__addr = addr;                                   \
 440                                                                         \
 441         while (count--) {                                               \
 442                 *__addr = __mem_read##bwlq(mem);                        \
 443                 __addr++;                                               \
 444         }                                                               \
 445 }
 446
 447 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 448                                                                         \
 449 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 450                               unsigned int count)                       \
 451 {                                                                       \
 452         const volatile type *__addr = addr;                             \
 453                                                                         \
 454         while (count--) {                                               \
 455                 __mem_out##bwlq(*__addr, port);                         \
 456                 __addr++;                                               \
 457         }                                                               \
 458 }                                                                       \
 459                                                                         \
 460 static inline void ins##bwlq(unsigned long port, void *addr,            \
 461                              unsigned int count)                        \
 462 {                                                                       \
 463         volatile type *__addr = addr;                                   \
 464                                                                         \
 465         while (count--) {                                               \
 466                 *__addr = __mem_in##bwlq(port);                         \
 467                 __addr++;                                               \
 468         }                                                               \
 469 }
 470
 471 #define BUILDSTRING(bwlq, type)                                         \
 472                                                                         \
 473 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 474 __BUILD_IOPORT_STRING(bwlq, type)
 475
 476 BUILDSTRING(b, u8)
 477 BUILDSTRING(w, u16)
 478 BUILDSTRING(l, u32)
 479 #ifdef CONFIG_64BIT
 480 BUILDSTRING(q, u64)
 481 #endif
 482
 483 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 484 {
 485         memset((void __force *) addr, val, count);
 486 }
 487 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 488 {
 489         memcpy(dst, (void __force *) src, count);
 490 }
 491 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 492 {
 493         memcpy((void __force *) dst, src, count);
 494 }
 495
 496 /*
 497  * The caches on some architectures aren't dma-coherent and have need to
 498  * handle this in software.  There are three types of operations that
 499  * can be applied to dma buffers.
 500  *
 501  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 502  *    writing the content of the caches back to memory, if necessary.
 503  *    The function also invalidates the affected part of the caches as
 504  *    necessary before DMA transfers from outside to memory.
 505  *  - dma_cache_wback(start, size) makes caches and coherent by
 506  *    writing the content of the caches back to memory, if necessary.
 507  *    The function also invalidates the affected part of the caches as
 508  *    necessary before DMA transfers from outside to memory.
 509  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 510  *    caches.  Dirty lines of the caches may be written back or simply
 511  *    be discarded.  This operation is necessary before dma operations
 512  *    to the memory.
 513  *
 514  * This API used to be exported; it now is for arch code internal use only.
 515  */
 516 #ifdef CONFIG_DMA_NONCOHERENT
 517
 518 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 519 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 520 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 521
 522 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
 523 #define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
 524 #define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
 525
 526 #else /* Sane hardware */
 527
 528 #define dma_cache_wback_inv(start,size) \
 529         do { (void) (start); (void) (size); } while (0)
 530 #define dma_cache_wback(start,size)     \
 531         do { (void) (start); (void) (size); } while (0)
 532 #define dma_cache_inv(start,size)       \
 533         do { (void) (start); (void) (size); } while (0)
 534
 535 #endif /* CONFIG_DMA_NONCOHERENT */
 536
 537 /*
 538  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 539  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 540  * Assume the addresses are 8-byte aligned.
 541  */
 542 #ifdef __MIPSEB__
 543 #define __CSR_32_ADJUST 4
 544 #else
 545 #define __CSR_32_ADJUST 0
 546 #endif
 547
 548 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 549 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 550
 551 /*
 552  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 553  * access
 554  */
 555 #define xlate_dev_mem_ptr(p)    __va(p)
 556 #define unxlate_dev_mem_ptr(p, v) do { } while (0)
 557
 558 void __ioread64_copy(void *to, const void __iomem *from, size_t count);
 559
 560 #endif /* _ASM_IO_H */