3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7 select ARCH_HAS_ELF_RANDOMIZE
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_HAS_SG_CHAIN
10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_SUPPORTS_ATOMIC_RMW
13 select ARCH_WANT_OPTIONAL_GPIOLIB
14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15 select ARCH_WANT_FRAME_POINTERS
19 select AUDIT_ARCH_COMPAT_GENERIC
20 select ARM_GIC_V2M if PCI_MSI
22 select ARM_GIC_V3_ITS if PCI_MSI
24 select BUILDTIME_EXTABLE_SORT
25 select CLONE_BACKWARDS
27 select CPU_PM if (SUSPEND || CPU_IDLE)
28 select DCACHE_WORD_ACCESS
30 select GENERIC_ALLOCATOR
31 select GENERIC_CLOCKEVENTS
32 select GENERIC_CLOCKEVENTS_BROADCAST
33 select GENERIC_CPU_AUTOPROBE
34 select GENERIC_EARLY_IOREMAP
35 select GENERIC_IRQ_PROBE
36 select GENERIC_IRQ_SHOW
37 select GENERIC_IRQ_SHOW_LEVEL
38 select GENERIC_PCI_IOMAP
39 select GENERIC_SCHED_CLOCK
40 select GENERIC_SMP_IDLE_THREAD
41 select GENERIC_STRNCPY_FROM_USER
42 select GENERIC_STRNLEN_USER
43 select GENERIC_TIME_VSYSCALL
44 select HANDLE_DOMAIN_IRQ
45 select HARDIRQS_SW_RESEND
46 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
47 select HAVE_ARCH_AUDITSYSCALL
48 select HAVE_ARCH_BITREVERSE
49 select HAVE_ARCH_JUMP_LABEL
51 select HAVE_ARCH_SECCOMP_FILTER
52 select HAVE_ARCH_TRACEHOOK
54 select HAVE_C_RECORDMCOUNT
55 select HAVE_CC_STACKPROTECTOR
56 select HAVE_CMPXCHG_DOUBLE
57 select HAVE_CMPXCHG_LOCAL
58 select HAVE_DEBUG_BUGVERBOSE
59 select HAVE_DEBUG_KMEMLEAK
60 select HAVE_DMA_API_DEBUG
62 select HAVE_DMA_CONTIGUOUS
63 select HAVE_DYNAMIC_FTRACE
64 select HAVE_EFFICIENT_UNALIGNED_ACCESS
65 select HAVE_FTRACE_MCOUNT_RECORD
66 select HAVE_FUNCTION_TRACER
67 select HAVE_FUNCTION_GRAPH_TRACER
68 select HAVE_GENERIC_DMA_COHERENT
69 select HAVE_HW_BREAKPOINT if PERF_EVENTS
71 select HAVE_PATA_PLATFORM
72 select HAVE_PERF_EVENTS
74 select HAVE_PERF_USER_STACK_DUMP
75 select HAVE_RCU_TABLE_FREE
76 select HAVE_SYSCALL_TRACEPOINTS
78 select IRQ_FORCED_THREADING
79 select MODULES_USE_ELF_RELA
82 select OF_EARLY_FLATTREE
83 select OF_RESERVED_MEM
84 select PERF_USE_VMALLOC
89 select SYSCTL_EXCEPTION_TRACE
90 select HAVE_CONTEXT_TRACKING
92 ARM 64-bit (AArch64) Linux support.
97 config ARCH_PHYS_ADDR_T_64BIT
106 config STACKTRACE_SUPPORT
109 config ILLEGAL_POINTER_VALUE
111 default 0xdead000000000000
113 config LOCKDEP_SUPPORT
116 config TRACE_IRQFLAGS_SUPPORT
119 config RWSEM_XCHGADD_ALGORITHM
126 config GENERIC_BUG_RELATIVE_POINTERS
128 depends on GENERIC_BUG
130 config GENERIC_HWEIGHT
136 config GENERIC_CALIBRATE_DELAY
142 config HAVE_GENERIC_RCU_GUP
145 config ARCH_DMA_ADDR_T_64BIT
148 config NEED_DMA_MAP_STATE
151 config NEED_SG_DMA_LENGTH
163 config KERNEL_MODE_NEON
166 config FIX_EARLYCON_MEM
169 config PGTABLE_LEVELS
171 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
172 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
173 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
174 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
176 source "init/Kconfig"
178 source "kernel/Kconfig.freezer"
180 source "arch/arm64/Kconfig.platforms"
187 This feature enables support for PCI bus system. If you say Y
188 here, the kernel will include drivers and infrastructure code
189 to support PCI bus devices.
194 config PCI_DOMAINS_GENERIC
200 source "drivers/pci/Kconfig"
201 source "drivers/pci/pcie/Kconfig"
202 source "drivers/pci/hotplug/Kconfig"
206 menu "Kernel Features"
208 menu "ARM errata workarounds via the alternatives framework"
210 config ARM64_ERRATUM_826319
211 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
214 This option adds an alternative code sequence to work around ARM
215 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
216 AXI master interface and an L2 cache.
218 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
219 and is unable to accept a certain write via this interface, it will
220 not progress on read data presented on the read data channel and the
223 The workaround promotes data cache clean instructions to
224 data cache clean-and-invalidate.
225 Please note that this does not necessarily enable the workaround,
226 as it depends on the alternative framework, which will only patch
227 the kernel if an affected CPU is detected.
231 config ARM64_ERRATUM_827319
232 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
235 This option adds an alternative code sequence to work around ARM
236 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
237 master interface and an L2 cache.
239 Under certain conditions this erratum can cause a clean line eviction
240 to occur at the same time as another transaction to the same address
241 on the AMBA 5 CHI interface, which can cause data corruption if the
242 interconnect reorders the two transactions.
244 The workaround promotes data cache clean instructions to
245 data cache clean-and-invalidate.
246 Please note that this does not necessarily enable the workaround,
247 as it depends on the alternative framework, which will only patch
248 the kernel if an affected CPU is detected.
252 config ARM64_ERRATUM_824069
253 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
256 This option adds an alternative code sequence to work around ARM
257 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
258 to a coherent interconnect.
260 If a Cortex-A53 processor is executing a store or prefetch for
261 write instruction at the same time as a processor in another
262 cluster is executing a cache maintenance operation to the same
263 address, then this erratum might cause a clean cache line to be
264 incorrectly marked as dirty.
266 The workaround promotes data cache clean instructions to
267 data cache clean-and-invalidate.
268 Please note that this option does not necessarily enable the
269 workaround, as it depends on the alternative framework, which will
270 only patch the kernel if an affected CPU is detected.
274 config ARM64_ERRATUM_819472
275 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
278 This option adds an alternative code sequence to work around ARM
279 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
280 present when it is connected to a coherent interconnect.
282 If the processor is executing a load and store exclusive sequence at
283 the same time as a processor in another cluster is executing a cache
284 maintenance operation to the same address, then this erratum might
285 cause data corruption.
287 The workaround promotes data cache clean instructions to
288 data cache clean-and-invalidate.
289 Please note that this does not necessarily enable the workaround,
290 as it depends on the alternative framework, which will only patch
291 the kernel if an affected CPU is detected.
295 config ARM64_ERRATUM_832075
296 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
299 This option adds an alternative code sequence to work around ARM
300 erratum 832075 on Cortex-A57 parts up to r1p2.
302 Affected Cortex-A57 parts might deadlock when exclusive load/store
303 instructions to Write-Back memory are mixed with Device loads.
305 The workaround is to promote device loads to use Load-Acquire
307 Please note that this does not necessarily enable the workaround,
308 as it depends on the alternative framework, which will only patch
309 the kernel if an affected CPU is detected.
313 config ARM64_ERRATUM_845719
314 bool "Cortex-A53: 845719: a load might read incorrect data"
318 This option adds an alternative code sequence to work around ARM
319 erratum 845719 on Cortex-A53 parts up to r0p4.
321 When running a compat (AArch32) userspace on an affected Cortex-A53
322 part, a load at EL0 from a virtual address that matches the bottom 32
323 bits of the virtual address used by a recent load at (AArch64) EL1
324 might return incorrect data.
326 The workaround is to write the contextidr_el1 register on exception
327 return to a 32-bit task.
328 Please note that this does not necessarily enable the workaround,
329 as it depends on the alternative framework, which will only patch
330 the kernel if an affected CPU is detected.
339 default ARM64_4K_PAGES
341 Page size (translation granule) configuration.
343 config ARM64_4K_PAGES
346 This feature enables 4KB pages support.
348 config ARM64_64K_PAGES
351 This feature enables 64KB pages support (4KB by default)
352 allowing only two levels of page tables and faster TLB
353 look-up. AArch32 emulation is not available when this feature
359 prompt "Virtual address space size"
360 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
361 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
363 Allows choosing one of multiple possible virtual address
364 space sizes. The level of translation table is determined by
365 a combination of page size and virtual address space size.
367 config ARM64_VA_BITS_39
369 depends on ARM64_4K_PAGES
371 config ARM64_VA_BITS_42
373 depends on ARM64_64K_PAGES
375 config ARM64_VA_BITS_48
382 default 39 if ARM64_VA_BITS_39
383 default 42 if ARM64_VA_BITS_42
384 default 48 if ARM64_VA_BITS_48
386 config CPU_BIG_ENDIAN
387 bool "Build big-endian kernel"
389 Say Y if you plan on running a kernel in big-endian mode.
392 bool "Multi-core scheduler support"
394 Multi-core scheduler support improves the CPU scheduler's decision
395 making when dealing with multi-core CPU chips at a cost of slightly
396 increased overhead in some places. If unsure say N here.
399 bool "SMT scheduler support"
401 Improves the CPU scheduler's decision making when dealing with
402 MultiThreading at a cost of slightly increased overhead in some
403 places. If unsure say N here.
406 int "Maximum number of CPUs (2-4096)"
408 # These have to remain sorted largest to smallest
412 bool "Support for hot-pluggable CPUs"
414 Say Y here to experiment with turning CPUs off and on. CPUs
415 can be controlled through /sys/devices/system/cpu.
417 source kernel/Kconfig.preempt
423 config ARCH_HAS_HOLES_MEMORYMODEL
424 def_bool y if SPARSEMEM
426 config ARCH_SPARSEMEM_ENABLE
428 select SPARSEMEM_VMEMMAP_ENABLE
430 config ARCH_SPARSEMEM_DEFAULT
431 def_bool ARCH_SPARSEMEM_ENABLE
433 config ARCH_SELECT_MEMORY_MODEL
434 def_bool ARCH_SPARSEMEM_ENABLE
436 config HAVE_ARCH_PFN_VALID
437 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
439 config HW_PERF_EVENTS
440 bool "Enable hardware performance counter support for perf events"
441 depends on PERF_EVENTS
444 Enable hardware performance counter support for perf events. If
445 disabled, perf events will use software events only.
447 config SYS_SUPPORTS_HUGETLBFS
450 config ARCH_WANT_GENERAL_HUGETLB
453 config ARCH_WANT_HUGE_PMD_SHARE
454 def_bool y if !ARM64_64K_PAGES
456 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
459 config ARCH_HAS_CACHE_LINE_SIZE
465 bool "Enable seccomp to safely compute untrusted bytecode"
467 This kernel feature is useful for number crunching applications
468 that may need to compute untrusted bytecode during their
469 execution. By using pipes or other transports made available to
470 the process as file descriptors supporting the read/write
471 syscalls, it's possible to isolate those applications in
472 their own address space using seccomp. Once seccomp is
473 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
474 and the task is only allowed to execute a few safe syscalls
475 defined by each seccomp mode.
482 bool "Xen guest support on ARM64"
483 depends on ARM64 && OF
486 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
488 config FORCE_MAX_ZONEORDER
490 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
493 menuconfig ARMV8_DEPRECATED
494 bool "Emulate deprecated/obsolete ARMv8 instructions"
497 Legacy software support may require certain instructions
498 that have been deprecated or obsoleted in the architecture.
500 Enable this config to enable selective emulation of these
508 bool "Emulate SWP/SWPB instructions"
510 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
511 they are always undefined. Say Y here to enable software
512 emulation of these instructions for userspace using LDXR/STXR.
514 In some older versions of glibc [<=2.8] SWP is used during futex
515 trylock() operations with the assumption that the code will not
516 be preempted. This invalid assumption may be more likely to fail
517 with SWP emulation enabled, leading to deadlock of the user
520 NOTE: when accessing uncached shared regions, LDXR/STXR rely
521 on an external transaction monitoring block called a global
522 monitor to maintain update atomicity. If your system does not
523 implement a global monitor, this option can cause programs that
524 perform SWP operations to uncached memory to deadlock.
528 config CP15_BARRIER_EMULATION
529 bool "Emulate CP15 Barrier instructions"
531 The CP15 barrier instructions - CP15ISB, CP15DSB, and
532 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
533 strongly recommended to use the ISB, DSB, and DMB
534 instructions instead.
536 Say Y here to enable software emulation of these
537 instructions for AArch32 userspace code. When this option is
538 enabled, CP15 barrier usage is traced which can help
539 identify software that needs updating.
543 config SETEND_EMULATION
544 bool "Emulate SETEND instruction"
546 The SETEND instruction alters the data-endianness of the
547 AArch32 EL0, and is deprecated in ARMv8.
549 Say Y here to enable software emulation of the instruction
550 for AArch32 userspace code.
552 Note: All the cpus on the system must have mixed endian support at EL0
553 for this feature to be enabled. If a new CPU - which doesn't support mixed
554 endian - is hotplugged in after this feature has been enabled, there could
555 be unexpected results in the applications.
560 menu "ARMv8.1 architectural features"
562 config ARM64_HW_AFDBM
563 bool "Support for hardware updates of the Access and Dirty page flags"
566 The ARMv8.1 architecture extensions introduce support for
567 hardware updates of the access and dirty information in page
568 table entries. When enabled in TCR_EL1 (HA and HD bits) on
569 capable processors, accesses to pages with PTE_AF cleared will
570 set this bit instead of raising an access flag fault.
571 Similarly, writes to read-only pages with the DBM bit set will
572 clear the read-only bit (AP[2]) instead of raising a
575 Kernels built with this configuration option enabled continue
576 to work on pre-ARMv8.1 hardware and the performance impact is
577 minimal. If unsure, say Y.
580 bool "Enable support for Privileged Access Never (PAN)"
583 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
584 prevents the kernel or hypervisor from accessing user-space (EL0)
587 Choosing this option will cause any unprotected (not using
588 copy_to_user et al) memory access to fail with a permission fault.
590 The feature is detected at runtime, and will remain as a 'nop'
591 instruction if the cpu does not implement the feature.
593 config ARM64_LSE_ATOMICS
594 bool "Atomic instructions"
596 As part of the Large System Extensions, ARMv8.1 introduces new
597 atomic instructions that are designed specifically to scale in
600 Say Y here to make use of these instructions for the in-kernel
601 atomic routines. This incurs a small overhead on CPUs that do
602 not support these instructions and requires the kernel to be
603 built with binutils >= 2.25.
612 string "Default kernel command string"
615 Provide a set of default command-line options at build time by
616 entering them here. As a minimum, you should specify the the
617 root device (e.g. root=/dev/nfs).
620 bool "Always use the default kernel command string"
622 Always use the default kernel command string, even if the boot
623 loader passes other arguments to the kernel.
624 This is useful if you cannot or don't want to change the
625 command-line options your boot loader passes to the kernel.
631 bool "UEFI runtime support"
632 depends on OF && !CPU_BIG_ENDIAN
635 select EFI_PARAMS_FROM_FDT
636 select EFI_RUNTIME_WRAPPERS
641 This option provides support for runtime services provided
642 by UEFI firmware (such as non-volatile variables, realtime
643 clock, and platform reset). A UEFI stub is also provided to
644 allow the kernel to be booted as an EFI application. This
645 is only useful on systems that have UEFI firmware.
648 bool "Enable support for SMBIOS (DMI) tables"
652 This enables SMBIOS/DMI feature for systems.
654 This option is only useful on systems that have UEFI firmware.
655 However, even with this option, the resultant kernel should
656 continue to boot on existing non-UEFI platforms.
660 menu "Userspace binary formats"
662 source "fs/Kconfig.binfmt"
665 bool "Kernel support for 32-bit EL0"
666 depends on !ARM64_64K_PAGES || EXPERT
667 select COMPAT_BINFMT_ELF
669 select OLD_SIGSUSPEND3
670 select COMPAT_OLD_SIGACTION
672 This option enables support for a 32-bit EL0 running under a 64-bit
673 kernel at EL1. AArch32-specific components such as system calls,
674 the user helper functions, VFP support and the ptrace interface are
675 handled appropriately by the kernel.
677 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
678 will only be able to execute AArch32 binaries that were compiled with
679 64k aligned segments.
681 If you want to execute 32-bit userspace applications, say Y.
683 config SYSVIPC_COMPAT
685 depends on COMPAT && SYSVIPC
689 menu "Power management options"
691 source "kernel/power/Kconfig"
693 config ARCH_SUSPEND_POSSIBLE
698 menu "CPU Power Management"
700 source "drivers/cpuidle/Kconfig"
702 source "drivers/cpufreq/Kconfig"
708 source "drivers/Kconfig"
710 source "drivers/firmware/Kconfig"
712 source "drivers/acpi/Kconfig"
716 source "arch/arm64/kvm/Kconfig"
718 source "arch/arm64/Kconfig.debug"
720 source "security/Kconfig"
722 source "crypto/Kconfig"
724 source "arch/arm64/crypto/Kconfig"