drivers/gpu/drm/bridge/sil-sii8620.c

   1 /*
   2  * Silicon Image SiI8620 HDMI/MHL bridge driver
   3  *
   4  * Copyright (C) 2015, Samsung Electronics Co., Ltd.
   5  * Andrzej Hajda <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <asm/unaligned.h>
  13
  14 #include <drm/bridge/mhl.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_edid.h>
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/gpio/consumer.h>
  22 #include <linux/i2c.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/kernel.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/mutex.h>
  29 #include <linux/of_graph.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/slab.h>
  32
  33 #include <media/rc-core.h>
  34
  35 #include "sil-sii8620.h"
  36
  37 #define SII8620_BURST_BUF_LEN 288
  38 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3)
  39 #define MHL1_MAX_LCLK 225000
  40 #define MHL3_MAX_LCLK 600000
  41
  42 enum sii8620_mode {
  43         CM_DISCONNECTED,
  44         CM_DISCOVERY,
  45         CM_MHL1,
  46         CM_MHL3,
  47         CM_ECBUS_S
  48 };
  49
  50 enum sii8620_sink_type {
  51         SINK_NONE,
  52         SINK_HDMI,
  53         SINK_DVI
  54 };
  55
  56 enum sii8620_mt_state {
  57         MT_STATE_READY,
  58         MT_STATE_BUSY,
  59         MT_STATE_DONE
  60 };
  61
  62 struct sii8620 {
  63         struct drm_bridge bridge;
  64         struct device *dev;
  65         struct rc_dev *rc_dev;
  66         struct clk *clk_xtal;
  67         struct gpio_desc *gpio_reset;
  68         struct gpio_desc *gpio_int;
  69         struct regulator_bulk_data supplies[2];
  70         struct mutex lock; /* context lock, protects fields below */
  71         int error;
  72         int pixel_clock;
  73         unsigned int use_packed_pixel:1;
  74         int video_code;
  75         enum sii8620_mode mode;
  76         enum sii8620_sink_type sink_type;
  77         u8 cbus_status;
  78         u8 stat[MHL_DST_SIZE];
  79         u8 xstat[MHL_XDS_SIZE];
  80         u8 devcap[MHL_DCAP_SIZE];
  81         u8 xdevcap[MHL_XDC_SIZE];
  82         u8 avif[HDMI_INFOFRAME_SIZE(AVI)];
  83         struct edid *edid;
  84         unsigned int gen2_write_burst:1;
  85         enum sii8620_mt_state mt_state;
  86         struct extcon_dev *extcon;
  87         struct notifier_block extcon_nb;
  88         struct work_struct extcon_wq;
  89         int cable_state;
  90         struct list_head mt_queue;
  91         struct {
  92                 int r_size;
  93                 int r_count;
  94                 int rx_ack;
  95                 int rx_count;
  96                 u8 rx_buf[32];
  97                 int tx_count;
  98                 u8 tx_buf[32];
  99         } burst;
 100 };
 101
 102 struct sii8620_mt_msg;
 103
 104 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx,
 105                                   struct sii8620_mt_msg *msg);
 106
 107 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret);
 108
 109 struct sii8620_mt_msg {
 110         struct list_head node;
 111         u8 reg[4];
 112         u8 ret;
 113         sii8620_mt_msg_cb send;
 114         sii8620_mt_msg_cb recv;
 115         sii8620_cb continuation;
 116 };
 117
 118 static const u8 sii8620_i2c_page[] = {
 119         0x39, /* Main System */
 120         0x3d, /* TDM and HSIC */
 121         0x49, /* TMDS Receiver, MHL EDID */
 122         0x4d, /* eMSC, HDCP, HSIC */
 123         0x5d, /* MHL Spec */
 124         0x64, /* MHL CBUS */
 125         0x59, /* Hardware TPI (Transmitter Programming Interface) */
 126         0x61, /* eCBUS-S, eCBUS-D */
 127 };
 128
 129 static void sii8620_fetch_edid(struct sii8620 *ctx);
 130 static void sii8620_set_upstream_edid(struct sii8620 *ctx);
 131 static void sii8620_enable_hpd(struct sii8620 *ctx);
 132 static void sii8620_mhl_disconnected(struct sii8620 *ctx);
 133 static void sii8620_disconnect(struct sii8620 *ctx);
 134
 135 static int sii8620_clear_error(struct sii8620 *ctx)
 136 {
 137         int ret = ctx->error;
 138
 139         ctx->error = 0;
 140         return ret;
 141 }
 142
 143 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len)
 144 {
 145         struct device *dev = ctx->dev;
 146         struct i2c_client *client = to_i2c_client(dev);
 147         u8 data = addr;
 148         struct i2c_msg msg[] = {
 149                 {
 150                         .addr = sii8620_i2c_page[addr >> 8],
 151                         .flags = client->flags,
 152                         .len = 1,
 153                         .buf = &data
 154                 },
 155                 {
 156                         .addr = sii8620_i2c_page[addr >> 8],
 157                         .flags = client->flags | I2C_M_RD,
 158                         .len = len,
 159                         .buf = buf
 160                 },
 161         };
 162         int ret;
 163
 164         if (ctx->error)
 165                 return;
 166
 167         ret = i2c_transfer(client->adapter, msg, 2);
 168         dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret);
 169
 170         if (ret != 2) {
 171                 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n",
 172                         addr, len, ret);
 173                 ctx->error = ret < 0 ? ret : -EIO;
 174         }
 175 }
 176
 177 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr)
 178 {
 179         u8 ret;
 180
 181         sii8620_read_buf(ctx, addr, &ret, 1);
 182         return ret;
 183 }
 184
 185 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf,
 186                               int len)
 187 {
 188         struct device *dev = ctx->dev;
 189         struct i2c_client *client = to_i2c_client(dev);
 190         u8 data[2];
 191         struct i2c_msg msg = {
 192                 .addr = sii8620_i2c_page[addr >> 8],
 193                 .flags = client->flags,
 194                 .len = len + 1,
 195         };
 196         int ret;
 197
 198         if (ctx->error)
 199                 return;
 200
 201         if (len > 1) {
 202                 msg.buf = kmalloc(len + 1, GFP_KERNEL);
 203                 if (!msg.buf) {
 204                         ctx->error = -ENOMEM;
 205                         return;
 206                 }
 207                 memcpy(msg.buf + 1, buf, len);
 208         } else {
 209                 msg.buf = data;
 210                 msg.buf[1] = *buf;
 211         }
 212
 213         msg.buf[0] = addr;
 214
 215         ret = i2c_transfer(client->adapter, &msg, 1);
 216         dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret);
 217
 218         if (ret != 1) {
 219                 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n",
 220                         addr, len, buf, ret);
 221                 ctx->error = ret ?: -EIO;
 222         }
 223
 224         if (len > 1)
 225                 kfree(msg.buf);
 226 }
 227
 228 #define sii8620_write(ctx, addr, arr...) \
 229 ({\
 230         u8 d[] = { arr }; \
 231         sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \
 232 })
 233
 234 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len)
 235 {
 236         int i;
 237
 238         for (i = 0; i < len; i += 2)
 239                 sii8620_write(ctx, seq[i], seq[i + 1]);
 240 }
 241
 242 #define sii8620_write_seq(ctx, seq...) \
 243 ({\
 244         const u16 d[] = { seq }; \
 245         __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
 246 })
 247
 248 #define sii8620_write_seq_static(ctx, seq...) \
 249 ({\
 250         static const u16 d[] = { seq }; \
 251         __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \
 252 })
 253
 254 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val)
 255 {
 256         val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask);
 257         sii8620_write(ctx, addr, val);
 258 }
 259
 260 static inline bool sii8620_is_mhl3(struct sii8620 *ctx)
 261 {
 262         return ctx->mode >= CM_MHL3;
 263 }
 264
 265 static void sii8620_mt_cleanup(struct sii8620 *ctx)
 266 {
 267         struct sii8620_mt_msg *msg, *n;
 268
 269         list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) {
 270                 list_del(&msg->node);
 271                 kfree(msg);
 272         }
 273         ctx->mt_state = MT_STATE_READY;
 274 }
 275
 276 static void sii8620_mt_work(struct sii8620 *ctx)
 277 {
 278         struct sii8620_mt_msg *msg;
 279
 280         if (ctx->error)
 281                 return;
 282         if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue))
 283                 return;
 284
 285         if (ctx->mt_state == MT_STATE_DONE) {
 286                 ctx->mt_state = MT_STATE_READY;
 287                 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg,
 288                                        node);
 289                 list_del(&msg->node);
 290                 if (msg->recv)
 291                         msg->recv(ctx, msg);
 292                 if (msg->continuation)
 293                         msg->continuation(ctx, msg->ret);
 294                 kfree(msg);
 295         }
 296
 297         if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue))
 298                 return;
 299
 300         ctx->mt_state = MT_STATE_BUSY;
 301         msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
 302         if (msg->send)
 303                 msg->send(ctx, msg);
 304 }
 305
 306 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx)
 307 {
 308         u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN;
 309
 310         if (ctx->gen2_write_burst)
 311                 return;
 312
 313         if (ctx->mode >= CM_MHL1)
 314                 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN;
 315
 316         sii8620_write_seq(ctx,
 317                 REG_MDT_RCV_TIMEOUT, 100,
 318                 REG_MDT_RCV_CTRL, ctrl
 319         );
 320         ctx->gen2_write_burst = 1;
 321 }
 322
 323 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx)
 324 {
 325         if (!ctx->gen2_write_burst)
 326                 return;
 327
 328         sii8620_write_seq_static(ctx,
 329                 REG_MDT_XMIT_CTRL, 0,
 330                 REG_MDT_RCV_CTRL, 0
 331         );
 332         ctx->gen2_write_burst = 0;
 333 }
 334
 335 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx)
 336 {
 337         sii8620_write_seq_static(ctx,
 338                 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT
 339                         | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR
 340                         | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD
 341                         | BIT_MDT_XMIT_SM_ERROR,
 342                 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY
 343                         | BIT_MDT_IDLE_AFTER_HAWB_DISABLE
 344                         | BIT_MDT_RFIFO_DATA_RDY
 345         );
 346         sii8620_enable_gen2_write_burst(ctx);
 347 }
 348
 349 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx,
 350                                     struct sii8620_mt_msg *msg)
 351 {
 352         if (msg->reg[0] == MHL_SET_INT &&
 353             msg->reg[1] == MHL_INT_REG(RCHANGE) &&
 354             msg->reg[2] == MHL_INT_RC_FEAT_REQ)
 355                 sii8620_enable_gen2_write_burst(ctx);
 356         else
 357                 sii8620_disable_gen2_write_burst(ctx);
 358
 359         switch (msg->reg[0]) {
 360         case MHL_WRITE_STAT:
 361         case MHL_SET_INT:
 362                 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2);
 363                 sii8620_write(ctx, REG_MSC_COMMAND_START,
 364                               BIT_MSC_COMMAND_START_WRITE_STAT);
 365                 break;
 366         case MHL_MSC_MSG:
 367                 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3);
 368                 sii8620_write(ctx, REG_MSC_COMMAND_START,
 369                               BIT_MSC_COMMAND_START_MSC_MSG);
 370                 break;
 371         case MHL_READ_DEVCAP_REG:
 372         case MHL_READ_XDEVCAP_REG:
 373                 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]);
 374                 sii8620_write(ctx, REG_MSC_COMMAND_START,
 375                               BIT_MSC_COMMAND_START_READ_DEVCAP);
 376                 break;
 377         default:
 378                 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__,
 379                         msg->reg[0]);
 380         }
 381 }
 382
 383 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx)
 384 {
 385         struct sii8620_mt_msg *msg = kzalloc(sizeof(*msg), GFP_KERNEL);
 386
 387         if (!msg)
 388                 ctx->error = -ENOMEM;
 389         else
 390                 list_add_tail(&msg->node, &ctx->mt_queue);
 391
 392         return msg;
 393 }
 394
 395 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont)
 396 {
 397         struct sii8620_mt_msg *msg;
 398
 399         if (ctx->error)
 400                 return;
 401
 402         if (list_empty(&ctx->mt_queue)) {
 403                 ctx->error = -EINVAL;
 404                 return;
 405         }
 406         msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
 407         msg->continuation = cont;
 408 }
 409
 410 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2)
 411 {
 412         struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 413
 414         if (!msg)
 415                 return;
 416
 417         msg->reg[0] = cmd;
 418         msg->reg[1] = arg1;
 419         msg->reg[2] = arg2;
 420         msg->send = sii8620_mt_msc_cmd_send;
 421 }
 422
 423 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val)
 424 {
 425         sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val);
 426 }
 427
 428 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask)
 429 {
 430         sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask);
 431 }
 432
 433 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data)
 434 {
 435         sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data);
 436 }
 437
 438 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code)
 439 {
 440         sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code);
 441 }
 442
 443 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code)
 444 {
 445         sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code);
 446 }
 447
 448 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code)
 449 {
 450         sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code);
 451 }
 452
 453 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx,
 454                                         struct sii8620_mt_msg *msg)
 455 {
 456         u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
 457                         | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 458                         | BIT_EDID_CTRL_EDID_MODE_EN;
 459
 460         if (msg->reg[0] == MHL_READ_XDEVCAP)
 461                 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
 462
 463         sii8620_write_seq(ctx,
 464                 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE,
 465                 REG_EDID_CTRL, ctrl,
 466                 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START
 467         );
 468 }
 469
 470 /* copy src to dst and set changed bits in src */
 471 static void sii8620_update_array(u8 *dst, u8 *src, int count)
 472 {
 473         while (--count >= 0) {
 474                 *src ^= *dst;
 475                 *dst++ ^= *src++;
 476         }
 477 }
 478
 479 static void sii8620_sink_detected(struct sii8620 *ctx, int ret)
 480 {
 481         static const char * const sink_str[] = {
 482                 [SINK_NONE] = "NONE",
 483                 [SINK_HDMI] = "HDMI",
 484                 [SINK_DVI] = "DVI"
 485         };
 486
 487         char sink_name[20];
 488         struct device *dev = ctx->dev;
 489
 490         if (ret < 0)
 491                 return;
 492
 493         sii8620_fetch_edid(ctx);
 494         if (!ctx->edid) {
 495                 dev_err(ctx->dev, "Cannot fetch EDID\n");
 496                 sii8620_mhl_disconnected(ctx);
 497                 return;
 498         }
 499
 500         if (drm_detect_hdmi_monitor(ctx->edid))
 501                 ctx->sink_type = SINK_HDMI;
 502         else
 503                 ctx->sink_type = SINK_DVI;
 504
 505         drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name));
 506
 507         dev_info(dev, "detected sink(type: %s): %s\n",
 508                  sink_str[ctx->sink_type], sink_name);
 509 }
 510
 511 static void sii8620_hsic_init(struct sii8620 *ctx)
 512 {
 513         if (!sii8620_is_mhl3(ctx))
 514                 return;
 515
 516         sii8620_write(ctx, REG_FCGC,
 517                 BIT_FCGC_HSIC_HOSTMODE | BIT_FCGC_HSIC_ENABLE);
 518         sii8620_setbits(ctx, REG_HRXCTRL3,
 519                 BIT_HRXCTRL3_HRX_STAY_RESET | BIT_HRXCTRL3_STATUS_EN, ~0);
 520         sii8620_setbits(ctx, REG_TTXNUMB, MSK_TTXNUMB_TTX_NUMBPS, 4);
 521         sii8620_setbits(ctx, REG_TRXCTRL, BIT_TRXCTRL_TRX_FROM_SE_COC, ~0);
 522         sii8620_setbits(ctx, REG_HTXCTRL, BIT_HTXCTRL_HTX_DRVCONN1, 0);
 523         sii8620_setbits(ctx, REG_KEEPER, MSK_KEEPER_MODE, VAL_KEEPER_MODE_HOST);
 524         sii8620_write_seq_static(ctx,
 525                 REG_TDMLLCTL, 0,
 526                 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST |
 527                         BIT_UTSRST_KEEPER_SRST | BIT_UTSRST_FC_SRST,
 528                 REG_UTSRST, BIT_UTSRST_HRX_SRST | BIT_UTSRST_HTX_SRST,
 529                 REG_HRXINTL, 0xff,
 530                 REG_HRXINTH, 0xff,
 531                 REG_TTXINTL, 0xff,
 532                 REG_TTXINTH, 0xff,
 533                 REG_TRXINTL, 0xff,
 534                 REG_TRXINTH, 0xff,
 535                 REG_HTXINTL, 0xff,
 536                 REG_HTXINTH, 0xff,
 537                 REG_FCINTR0, 0xff,
 538                 REG_FCINTR1, 0xff,
 539                 REG_FCINTR2, 0xff,
 540                 REG_FCINTR3, 0xff,
 541                 REG_FCINTR4, 0xff,
 542                 REG_FCINTR5, 0xff,
 543                 REG_FCINTR6, 0xff,
 544                 REG_FCINTR7, 0xff
 545         );
 546 }
 547
 548 static void sii8620_edid_read(struct sii8620 *ctx, int ret)
 549 {
 550         if (ret < 0)
 551                 return;
 552
 553         sii8620_set_upstream_edid(ctx);
 554         sii8620_hsic_init(ctx);
 555         sii8620_enable_hpd(ctx);
 556 }
 557
 558 static void sii8620_mr_devcap(struct sii8620 *ctx)
 559 {
 560         u8 dcap[MHL_DCAP_SIZE];
 561         struct device *dev = ctx->dev;
 562
 563         sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE);
 564         if (ctx->error < 0)
 565                 return;
 566
 567         dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n",
 568                  dcap[MHL_DCAP_MHL_VERSION] / 16,
 569                  dcap[MHL_DCAP_MHL_VERSION] % 16,
 570                  dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L],
 571                  dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]);
 572         sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE);
 573 }
 574
 575 static void sii8620_mr_xdevcap(struct sii8620 *ctx)
 576 {
 577         sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap,
 578                          MHL_XDC_SIZE);
 579 }
 580
 581 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx,
 582                                         struct sii8620_mt_msg *msg)
 583 {
 584         u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP
 585                 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 586                 | BIT_EDID_CTRL_EDID_MODE_EN;
 587
 588         if (msg->reg[0] == MHL_READ_XDEVCAP)
 589                 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN;
 590
 591         sii8620_write_seq(ctx,
 592                 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE
 593                         | BIT_INTR9_EDID_ERROR,
 594                 REG_EDID_CTRL, ctrl,
 595                 REG_EDID_FIFO_ADDR, 0
 596         );
 597
 598         if (msg->reg[0] == MHL_READ_XDEVCAP)
 599                 sii8620_mr_xdevcap(ctx);
 600         else
 601                 sii8620_mr_devcap(ctx);
 602 }
 603
 604 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap)
 605 {
 606         struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 607
 608         if (!msg)
 609                 return;
 610
 611         msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP;
 612         msg->send = sii8620_mt_read_devcap_send;
 613         msg->recv = sii8620_mt_read_devcap_recv;
 614 }
 615
 616 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx,
 617                 struct sii8620_mt_msg *msg)
 618 {
 619         u8 reg = msg->reg[1] & 0x7f;
 620
 621         if (msg->reg[1] & 0x80)
 622                 ctx->xdevcap[reg] = msg->ret;
 623         else
 624                 ctx->devcap[reg] = msg->ret;
 625 }
 626
 627 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg)
 628 {
 629         struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx);
 630
 631         if (!msg)
 632                 return;
 633
 634         msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG;
 635         msg->reg[1] = reg;
 636         msg->send = sii8620_mt_msc_cmd_send;
 637         msg->recv = sii8620_mt_read_devcap_reg_recv;
 638 }
 639
 640 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg)
 641 {
 642         sii8620_mt_read_devcap_reg(ctx, reg | 0x80);
 643 }
 644
 645 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len)
 646 {
 647         u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count];
 648         int size = len + 2;
 649
 650         if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
 651                 dev_err(ctx->dev, "TX-BLK buffer exhausted\n");
 652                 ctx->error = -EINVAL;
 653                 return NULL;
 654         }
 655
 656         ctx->burst.tx_count += size;
 657         buf[1] = len;
 658
 659         return buf + 2;
 660 }
 661
 662 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len)
 663 {
 664         u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count];
 665         int size = len + 1;
 666
 667         if (ctx->burst.tx_count + size > ARRAY_SIZE(ctx->burst.tx_buf)) {
 668                 dev_err(ctx->dev, "RX-BLK buffer exhausted\n");
 669                 ctx->error = -EINVAL;
 670                 return NULL;
 671         }
 672
 673         ctx->burst.rx_count += size;
 674         buf[0] = len;
 675
 676         return buf + 1;
 677 }
 678
 679 static void sii8620_burst_send(struct sii8620 *ctx)
 680 {
 681         int tx_left = ctx->burst.tx_count;
 682         u8 *d = ctx->burst.tx_buf;
 683
 684         while (tx_left > 0) {
 685                 int len = d[1] + 2;
 686
 687                 if (ctx->burst.r_count + len > ctx->burst.r_size)
 688                         break;
 689                 d[0] = min(ctx->burst.rx_ack, 255);
 690                 ctx->burst.rx_ack -= d[0];
 691                 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len);
 692                 ctx->burst.r_count += len;
 693                 tx_left -= len;
 694                 d += len;
 695         }
 696
 697         ctx->burst.tx_count = tx_left;
 698
 699         while (ctx->burst.rx_ack > 0) {
 700                 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 };
 701
 702                 if (ctx->burst.r_count + 2 > ctx->burst.r_size)
 703                         break;
 704                 ctx->burst.rx_ack -= b[0];
 705                 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2);
 706                 ctx->burst.r_count += 2;
 707         }
 708 }
 709
 710 static void sii8620_burst_receive(struct sii8620 *ctx)
 711 {
 712         u8 buf[3], *d;
 713         int count;
 714
 715         sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2);
 716         count = get_unaligned_le16(buf);
 717         while (count > 0) {
 718                 int len = min(count, 3);
 719
 720                 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len);
 721                 count -= len;
 722                 ctx->burst.rx_ack += len - 1;
 723                 ctx->burst.r_count -= buf[1];
 724                 if (ctx->burst.r_count < 0)
 725                         ctx->burst.r_count = 0;
 726
 727                 if (len < 3 || !buf[2])
 728                         continue;
 729
 730                 len = buf[2];
 731                 d = sii8620_burst_get_rx_buf(ctx, len);
 732                 if (!d)
 733                         continue;
 734                 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len);
 735                 count -= len;
 736                 ctx->burst.rx_ack += len;
 737         }
 738 }
 739
 740 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size)
 741 {
 742         struct mhl_burst_blk_rcv_buffer_info *d =
 743                 sii8620_burst_get_tx_buf(ctx, sizeof(*d));
 744         if (!d)
 745                 return;
 746
 747         d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO);
 748         d->size = cpu_to_le16(size);
 749 }
 750
 751 static u8 sii8620_checksum(void *ptr, int size)
 752 {
 753         u8 *d = ptr, sum = 0;
 754
 755         while (size--)
 756                 sum += *d++;
 757
 758         return sum;
 759 }
 760
 761 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h,
 762         enum mhl_burst_id id)
 763 {
 764         h->id = cpu_to_be16(id);
 765         h->total_entries = 1;
 766         h->sequence_index = 1;
 767 }
 768
 769 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt)
 770 {
 771         struct mhl_burst_bits_per_pixel_fmt *d;
 772         const int size = sizeof(*d) + sizeof(d->desc[0]);
 773
 774         d = sii8620_burst_get_tx_buf(ctx, size);
 775         if (!d)
 776                 return;
 777
 778         sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT);
 779         d->num_entries = 1;
 780         d->desc[0].stream_id = 0;
 781         d->desc[0].pixel_format = fmt;
 782         d->hdr.checksum -= sii8620_checksum(d, size);
 783 }
 784
 785 static void sii8620_burst_rx_all(struct sii8620 *ctx)
 786 {
 787         u8 *d = ctx->burst.rx_buf;
 788         int count = ctx->burst.rx_count;
 789
 790         while (count-- > 0) {
 791                 int len = *d++;
 792                 int id = get_unaligned_be16(&d[0]);
 793
 794                 switch (id) {
 795                 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO:
 796                         ctx->burst.r_size = get_unaligned_le16(&d[2]);
 797                         break;
 798                 default:
 799                         break;
 800                 }
 801                 count -= len;
 802                 d += len;
 803         }
 804         ctx->burst.rx_count = 0;
 805 }
 806
 807 static void sii8620_fetch_edid(struct sii8620 *ctx)
 808 {
 809         u8 lm_ddc, ddc_cmd, int3, cbus;
 810         int fetched, i;
 811         int edid_len = EDID_LENGTH;
 812         u8 *edid;
 813
 814         sii8620_readb(ctx, REG_CBUS_STATUS);
 815         lm_ddc = sii8620_readb(ctx, REG_LM_DDC);
 816         ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD);
 817
 818         sii8620_write_seq(ctx,
 819                 REG_INTR9_MASK, 0,
 820                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
 821                 REG_HDCP2X_POLL_CS, 0x71,
 822                 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX,
 823                 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED,
 824         );
 825
 826         for (i = 0; i < 256; ++i) {
 827                 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS);
 828
 829                 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG))
 830                         break;
 831                 sii8620_write(ctx, REG_DDC_STATUS,
 832                               BIT_DDC_STATUS_DDC_FIFO_EMPTY);
 833         }
 834
 835         sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1);
 836
 837         edid = kmalloc(EDID_LENGTH, GFP_KERNEL);
 838         if (!edid) {
 839                 ctx->error = -ENOMEM;
 840                 return;
 841         }
 842
 843 #define FETCH_SIZE 16
 844         for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) {
 845                 sii8620_readb(ctx, REG_DDC_STATUS);
 846                 sii8620_write_seq(ctx,
 847                         REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT,
 848                         REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO,
 849                         REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY
 850                 );
 851                 sii8620_write_seq(ctx,
 852                         REG_DDC_SEGM, fetched >> 8,
 853                         REG_DDC_OFFSET, fetched & 0xff,
 854                         REG_DDC_DIN_CNT1, FETCH_SIZE,
 855                         REG_DDC_DIN_CNT2, 0,
 856                         REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
 857                 );
 858
 859                 do {
 860                         int3 = sii8620_readb(ctx, REG_INTR3);
 861                         cbus = sii8620_readb(ctx, REG_CBUS_STATUS);
 862
 863                         if (int3 & BIT_DDC_CMD_DONE)
 864                                 break;
 865
 866                         if (!(cbus & BIT_CBUS_STATUS_CBUS_CONNECTED)) {
 867                                 kfree(edid);
 868                                 edid = NULL;
 869                                 goto end;
 870                         }
 871                 } while (1);
 872
 873                 sii8620_readb(ctx, REG_DDC_STATUS);
 874                 while (sii8620_readb(ctx, REG_DDC_DOUT_CNT) < FETCH_SIZE)
 875                         usleep_range(10, 20);
 876
 877                 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE);
 878                 if (fetched + FETCH_SIZE == EDID_LENGTH) {
 879                         u8 ext = ((struct edid *)edid)->extensions;
 880
 881                         if (ext) {
 882                                 u8 *new_edid;
 883
 884                                 edid_len += ext * EDID_LENGTH;
 885                                 new_edid = krealloc(edid, edid_len, GFP_KERNEL);
 886                                 if (!new_edid) {
 887                                         kfree(edid);
 888                                         ctx->error = -ENOMEM;
 889                                         return;
 890                                 }
 891                                 edid = new_edid;
 892                         }
 893                 }
 894         }
 895
 896         sii8620_write_seq(ctx,
 897                 REG_INTR3_MASK, BIT_DDC_CMD_DONE,
 898                 REG_LM_DDC, lm_ddc
 899         );
 900
 901 end:
 902         kfree(ctx->edid);
 903         ctx->edid = (struct edid *)edid;
 904 }
 905
 906 static void sii8620_set_upstream_edid(struct sii8620 *ctx)
 907 {
 908         sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N
 909                         | BIT_DPD_PD_MHL_CLK_N, 0xff);
 910
 911         sii8620_write_seq_static(ctx,
 912                 REG_RX_HDMI_CTRL3, 0x00,
 913                 REG_PKT_FILTER_0, 0xFF,
 914                 REG_PKT_FILTER_1, 0xFF,
 915                 REG_ALICE0_BW_I2C, 0x06
 916         );
 917
 918         sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER,
 919                         BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff);
 920
 921         sii8620_write_seq_static(ctx,
 922                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 923                         | BIT_EDID_CTRL_EDID_MODE_EN,
 924                 REG_EDID_FIFO_ADDR, 0,
 925         );
 926
 927         sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid,
 928                           (ctx->edid->extensions + 1) * EDID_LENGTH);
 929
 930         sii8620_write_seq_static(ctx,
 931                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID
 932                         | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO
 933                         | BIT_EDID_CTRL_EDID_MODE_EN,
 934                 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE,
 935                 REG_INTR9_MASK, 0
 936         );
 937 }
 938
 939 static void sii8620_xtal_set_rate(struct sii8620 *ctx)
 940 {
 941         static const struct {
 942                 unsigned int rate;
 943                 u8 div;
 944                 u8 tp1;
 945         } rates[] = {
 946                 { 19200, 0x04, 0x53 },
 947                 { 20000, 0x04, 0x62 },
 948                 { 24000, 0x05, 0x75 },
 949                 { 30000, 0x06, 0x92 },
 950                 { 38400, 0x0c, 0xbc },
 951         };
 952         unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000;
 953         int i;
 954
 955         for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i)
 956                 if (rate <= rates[i].rate)
 957                         break;
 958
 959         if (rate != rates[i].rate)
 960                 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n",
 961                         rate, rates[i].rate);
 962
 963         sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div);
 964         sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1);
 965 }
 966
 967 static int sii8620_hw_on(struct sii8620 *ctx)
 968 {
 969         int ret;
 970
 971         ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 972         if (ret)
 973                 return ret;
 974         usleep_range(10000, 20000);
 975         return clk_prepare_enable(ctx->clk_xtal);
 976 }
 977
 978 static int sii8620_hw_off(struct sii8620 *ctx)
 979 {
 980         clk_disable_unprepare(ctx->clk_xtal);
 981         gpiod_set_value(ctx->gpio_reset, 1);
 982         return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
 983 }
 984
 985 static void sii8620_hw_reset(struct sii8620 *ctx)
 986 {
 987         usleep_range(10000, 20000);
 988         gpiod_set_value(ctx->gpio_reset, 0);
 989         usleep_range(5000, 20000);
 990         gpiod_set_value(ctx->gpio_reset, 1);
 991         usleep_range(10000, 20000);
 992         gpiod_set_value(ctx->gpio_reset, 0);
 993         msleep(300);
 994 }
 995
 996 static void sii8620_cbus_reset(struct sii8620 *ctx)
 997 {
 998         sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST
 999                       | BIT_PWD_SRST_CBUS_RST_SW_EN);
1000         usleep_range(10000, 20000);
1001         sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN);
1002 }
1003
1004 static void sii8620_set_auto_zone(struct sii8620 *ctx)
1005 {
1006         if (ctx->mode != CM_MHL1) {
1007                 sii8620_write_seq_static(ctx,
1008                         REG_TX_ZONE_CTL1, 0x0,
1009                         REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1010                                 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1011                                 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
1012                 );
1013         } else {
1014                 sii8620_write_seq_static(ctx,
1015                         REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE,
1016                         REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1017                                 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE
1018                 );
1019         }
1020 }
1021
1022 static void sii8620_stop_video(struct sii8620 *ctx)
1023 {
1024         u8 uninitialized_var(val);
1025
1026         sii8620_write_seq_static(ctx,
1027                 REG_TPI_INTR_EN, 0,
1028                 REG_HDCP2X_INTR0_MASK, 0,
1029                 REG_TPI_COPP_DATA2, 0,
1030                 REG_TPI_INTR_ST0, ~0,
1031         );
1032
1033         switch (ctx->sink_type) {
1034         case SINK_DVI:
1035                 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1036                         | BIT_TPI_SC_TPI_AV_MUTE;
1037                 break;
1038         case SINK_HDMI:
1039         default:
1040                 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN
1041                         | BIT_TPI_SC_TPI_AV_MUTE
1042                         | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI;
1043                 break;
1044         }
1045
1046         sii8620_write(ctx, REG_TPI_SC, val);
1047 }
1048
1049 static void sii8620_set_format(struct sii8620 *ctx)
1050 {
1051         u8 out_fmt;
1052
1053         if (sii8620_is_mhl3(ctx)) {
1054                 sii8620_setbits(ctx, REG_M3_P0CTRL,
1055                                 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED,
1056                                 ctx->use_packed_pixel ? ~0 : 0);
1057         } else {
1058                 if (ctx->use_packed_pixel)
1059                         sii8620_write_seq_static(ctx,
1060                                 REG_VID_MODE, BIT_VID_MODE_M1080P,
1061                                 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1,
1062                                 REG_MHLTX_CTL6, 0x60
1063                         );
1064                 else
1065                         sii8620_write_seq_static(ctx,
1066                                 REG_VID_MODE, 0,
1067                                 REG_MHL_TOP_CTL, 1,
1068                                 REG_MHLTX_CTL6, 0xa0
1069                         );
1070         }
1071
1072         if (ctx->use_packed_pixel)
1073                 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL) |
1074                         BIT_TPI_OUTPUT_CSCMODE709;
1075         else
1076                 out_fmt = VAL_TPI_FORMAT(RGB, FULL);
1077
1078         sii8620_write_seq(ctx,
1079                 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL),
1080                 REG_TPI_OUTPUT, out_fmt,
1081         );
1082 }
1083
1084 static int mhl3_infoframe_init(struct mhl3_infoframe *frame)
1085 {
1086         memset(frame, 0, sizeof(*frame));
1087
1088         frame->version = 3;
1089         frame->hev_format = -1;
1090         return 0;
1091 }
1092
1093 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame,
1094                  void *buffer, size_t size)
1095 {
1096         const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE;
1097         u8 *ptr = buffer;
1098
1099         if (size < frm_len)
1100                 return -ENOSPC;
1101
1102         memset(buffer, 0, size);
1103         ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR;
1104         ptr[1] = frame->version;
1105         ptr[2] = MHL3_INFOFRAME_SIZE;
1106         ptr[4] = MHL3_IEEE_OUI & 0xff;
1107         ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff;
1108         ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff;
1109         ptr[7] = frame->video_format & 0x3;
1110         ptr[7] |= (frame->format_type & 0x7) << 2;
1111         ptr[7] |= frame->sep_audio ? BIT(5) : 0;
1112         if (frame->hev_format >= 0) {
1113                 ptr[9] = 1;
1114                 ptr[10] = (frame->hev_format >> 8) & 0xff;
1115                 ptr[11] = frame->hev_format & 0xff;
1116         }
1117         if (frame->av_delay) {
1118                 bool sign = frame->av_delay < 0;
1119                 int delay = sign ? -frame->av_delay : frame->av_delay;
1120
1121                 ptr[12] = (delay >> 16) & 0xf;
1122                 if (sign)
1123                         ptr[12] |= BIT(4);
1124                 ptr[13] = (delay >> 8) & 0xff;
1125                 ptr[14] = delay & 0xff;
1126         }
1127         ptr[3] -= sii8620_checksum(buffer, frm_len);
1128         return frm_len;
1129 }
1130
1131 static void sii8620_set_infoframes(struct sii8620 *ctx)
1132 {
1133         struct mhl3_infoframe mhl_frm;
1134         union hdmi_infoframe frm;
1135         u8 buf[31];
1136         int ret;
1137
1138         if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) {
1139                 sii8620_write(ctx, REG_TPI_SC,
1140                         BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI);
1141                 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, ctx->avif + 3,
1142                         ARRAY_SIZE(ctx->avif) - 3);
1143                 sii8620_write(ctx, REG_PKT_FILTER_0,
1144                         BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1145                         BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1146                         BIT_PKT_FILTER_0_DROP_GCP_PKT,
1147                         BIT_PKT_FILTER_1_DROP_GEN_PKT);
1148                 return;
1149         }
1150
1151         ret = hdmi_avi_infoframe_init(&frm.avi);
1152         frm.avi.colorspace = HDMI_COLORSPACE_YUV422;
1153         frm.avi.active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
1154         frm.avi.picture_aspect = HDMI_PICTURE_ASPECT_16_9;
1155         frm.avi.colorimetry = HDMI_COLORIMETRY_ITU_709;
1156         frm.avi.video_code = ctx->video_code;
1157         if (!ret)
1158                 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf));
1159         if (ret > 0)
1160                 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3);
1161         sii8620_write(ctx, REG_PKT_FILTER_0,
1162                 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT |
1163                 BIT_PKT_FILTER_0_DROP_MPEG_PKT |
1164                 BIT_PKT_FILTER_0_DROP_AVI_PKT |
1165                 BIT_PKT_FILTER_0_DROP_GCP_PKT,
1166                 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS |
1167                 BIT_PKT_FILTER_1_DROP_GEN_PKT |
1168                 BIT_PKT_FILTER_1_DROP_VSIF_PKT);
1169
1170         sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN
1171                 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI);
1172         ret = mhl3_infoframe_init(&mhl_frm);
1173         if (!ret)
1174                 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf));
1175         sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret);
1176 }
1177
1178 static void sii8620_start_video(struct sii8620 *ctx)
1179 {
1180         if (!sii8620_is_mhl3(ctx))
1181                 sii8620_stop_video(ctx);
1182
1183         if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) {
1184                 sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1185                               VAL_RX_HDMI_CTRL2_DEFVAL);
1186                 sii8620_write(ctx, REG_TPI_SC, 0);
1187                 return;
1188         }
1189
1190         sii8620_write_seq_static(ctx,
1191                 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL
1192                         | BIT_RX_HDMI_CTRL2_USE_AV_MUTE,
1193                 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE
1194                         | BIT_VID_OVRRD_M1080P_OVRRD);
1195         sii8620_set_format(ctx);
1196
1197         if (!sii8620_is_mhl3(ctx)) {
1198                 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1199                         MHL_DST_LM_CLK_MODE_NORMAL | MHL_DST_LM_PATH_ENABLED);
1200                 sii8620_set_auto_zone(ctx);
1201         } else {
1202                 static const struct {
1203                         int max_clk;
1204                         u8 zone;
1205                         u8 link_rate;
1206                         u8 rrp_decode;
1207                 } clk_spec[] = {
1208                         { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS,
1209                           MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 },
1210                         { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS,
1211                           MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 },
1212                         { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS,
1213                           MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 },
1214                 };
1215                 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN;
1216                 int clk = ctx->pixel_clock * (ctx->use_packed_pixel ? 2 : 3);
1217                 int i;
1218
1219                 for (i = 0; i < ARRAY_SIZE(clk_spec); ++i)
1220                         if (clk < clk_spec[i].max_clk)
1221                                 break;
1222
1223                 if (100 * clk >= 98 * clk_spec[i].max_clk)
1224                         p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN;
1225
1226                 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel);
1227                 sii8620_burst_send(ctx);
1228                 sii8620_write_seq(ctx,
1229                         REG_MHL_DP_CTL0, 0xf0,
1230                         REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone);
1231                 sii8620_setbits(ctx, REG_M3_P0CTRL,
1232                         BIT_M3_P0CTRL_MHL3_P0_PORT_EN
1233                         | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl);
1234                 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE,
1235                         clk_spec[i].rrp_decode);
1236                 sii8620_write_seq_static(ctx,
1237                         REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1238                                 | BIT_M3_CTRL_H2M_SWRST,
1239                         REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE
1240                 );
1241                 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL),
1242                         clk_spec[i].link_rate);
1243         }
1244
1245         sii8620_set_infoframes(ctx);
1246 }
1247
1248 static void sii8620_disable_hpd(struct sii8620 *ctx)
1249 {
1250         sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0);
1251         sii8620_write_seq_static(ctx,
1252                 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN,
1253                 REG_INTR8_MASK, 0
1254         );
1255 }
1256
1257 static void sii8620_enable_hpd(struct sii8620 *ctx)
1258 {
1259         sii8620_setbits(ctx, REG_TMDS_CSTAT_P3,
1260                         BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS
1261                         | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0);
1262         sii8620_write_seq_static(ctx,
1263                 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN
1264                         | BIT_HPD_CTRL_HPD_HIGH,
1265         );
1266 }
1267
1268 static void sii8620_mhl_discover(struct sii8620 *ctx)
1269 {
1270         sii8620_write_seq_static(ctx,
1271                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1272                         | BIT_DISC_CTRL9_DISC_PULSE_PROCEED,
1273                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K),
1274                 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT
1275                         | BIT_MHL_EST_INT
1276                         | BIT_NOT_MHL_EST_INT
1277                         | BIT_CBUS_MHL3_DISCON_INT
1278                         | BIT_CBUS_MHL12_DISCON_INT
1279                         | BIT_RGND_READY_INT,
1280                 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1281                         | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1282                         | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1283                 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1284                         | BIT_MHL_DP_CTL0_TX_OE_OVR,
1285                 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1286                 REG_MHL_DP_CTL1, 0xA2,
1287                 REG_MHL_DP_CTL2, 0x03,
1288                 REG_MHL_DP_CTL3, 0x35,
1289                 REG_MHL_DP_CTL5, 0x02,
1290                 REG_MHL_DP_CTL6, 0x02,
1291                 REG_MHL_DP_CTL7, 0x03,
1292                 REG_COC_CTLC, 0xFF,
1293                 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1294                         | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC,
1295                 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE
1296                         | BIT_COC_CALIBRATION_DONE,
1297                 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD
1298                         | BIT_CBUS_CMD_ABORT,
1299                 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE
1300                         | BIT_CBUS_HPD_CHG
1301                         | BIT_CBUS_MSC_MR_WRITE_STAT
1302                         | BIT_CBUS_MSC_MR_MSC_MSG
1303                         | BIT_CBUS_MSC_MR_WRITE_BURST
1304                         | BIT_CBUS_MSC_MR_SET_INT
1305                         | BIT_CBUS_MSC_MT_DONE_NACK
1306         );
1307 }
1308
1309 static void sii8620_peer_specific_init(struct sii8620 *ctx)
1310 {
1311         if (sii8620_is_mhl3(ctx))
1312                 sii8620_write_seq_static(ctx,
1313                         REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD,
1314                         REG_EMSCINTRMASK1,
1315                                 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR
1316                 );
1317         else
1318                 sii8620_write_seq_static(ctx,
1319                         REG_HDCP2X_INTR0_MASK, 0x00,
1320                         REG_EMSCINTRMASK1, 0x00,
1321                         REG_HDCP2X_INTR0, 0xFF,
1322                         REG_INTR1, 0xFF,
1323                         REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD
1324                                 | BIT_SYS_CTRL1_TX_CTRL_HDMI
1325                 );
1326 }
1327
1328 #define SII8620_MHL_VERSION                     0x32
1329 #define SII8620_SCRATCHPAD_SIZE                 16
1330 #define SII8620_INT_STAT_SIZE                   0x33
1331
1332 static void sii8620_set_dev_cap(struct sii8620 *ctx)
1333 {
1334         static const u8 devcap[MHL_DCAP_SIZE] = {
1335                 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION,
1336                 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER,
1337                 [MHL_DCAP_ADOPTER_ID_H] = 0x01,
1338                 [MHL_DCAP_ADOPTER_ID_L] = 0x41,
1339                 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444
1340                         | MHL_DCAP_VID_LINK_PPIXEL
1341                         | MHL_DCAP_VID_LINK_16BPP,
1342                 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH,
1343                 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS,
1344                 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI,
1345                 [MHL_DCAP_BANDWIDTH] = 0x0f,
1346                 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT
1347                         | MHL_DCAP_FEATURE_RAP_SUPPORT
1348                         | MHL_DCAP_FEATURE_SP_SUPPORT,
1349                 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE,
1350                 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE,
1351         };
1352         static const u8 xdcap[MHL_XDC_SIZE] = {
1353                 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075
1354                         | MHL_XDC_ECBUS_S_8BIT,
1355                 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150
1356                         | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600,
1357                 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST,
1358                 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE,
1359         };
1360
1361         sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap));
1362         sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap));
1363 }
1364
1365 static void sii8620_mhl_init(struct sii8620 *ctx)
1366 {
1367         sii8620_write_seq_static(ctx,
1368                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1369                 REG_CBUS_MSC_COMPAT_CTRL,
1370                         BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN,
1371         );
1372
1373         sii8620_peer_specific_init(ctx);
1374
1375         sii8620_disable_hpd(ctx);
1376
1377         sii8620_write_seq_static(ctx,
1378                 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO,
1379                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1380                         | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1381                 REG_TMDS0_CCTRL1, 0x90,
1382                 REG_TMDS_CLK_EN, 0x01,
1383                 REG_TMDS_CH_EN, 0x11,
1384                 REG_BGR_BIAS, 0x87,
1385                 REG_ALICE0_ZONE_CTRL, 0xE8,
1386                 REG_ALICE0_MODE_CTRL, 0x04,
1387         );
1388         sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0);
1389         sii8620_write_seq_static(ctx,
1390                 REG_TPI_HW_OPT3, 0x76,
1391                 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE,
1392                 REG_TPI_DTD_B2, 79,
1393         );
1394         sii8620_set_dev_cap(ctx);
1395         sii8620_write_seq_static(ctx,
1396                 REG_MDT_XMIT_TIMEOUT, 100,
1397                 REG_MDT_XMIT_CTRL, 0x03,
1398                 REG_MDT_XFIFO_STAT, 0x00,
1399                 REG_MDT_RCV_TIMEOUT, 100,
1400                 REG_CBUS_LINK_CTRL_8, 0x1D,
1401         );
1402
1403         sii8620_start_gen2_write_burst(ctx);
1404         sii8620_write_seq_static(ctx,
1405                 REG_BIST_CTRL, 0x00,
1406                 REG_COC_CTL1, 0x10,
1407                 REG_COC_CTL2, 0x18,
1408                 REG_COC_CTLF, 0x07,
1409                 REG_COC_CTL11, 0xF8,
1410                 REG_COC_CTL17, 0x61,
1411                 REG_COC_CTL18, 0x46,
1412                 REG_COC_CTL19, 0x15,
1413                 REG_COC_CTL1A, 0x01,
1414                 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN,
1415                 REG_MHL_COC_CTL4, 0x2D,
1416                 REG_MHL_COC_CTL5, 0xF9,
1417                 REG_MSC_HEARTBEAT_CTRL, 0x27,
1418         );
1419         sii8620_disable_gen2_write_burst(ctx);
1420
1421         sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION);
1422         sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
1423                               MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
1424                               | MHL_DST_CONN_POW_STAT);
1425         sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG);
1426 }
1427
1428 static void sii8620_emsc_enable(struct sii8620 *ctx)
1429 {
1430         u8 reg;
1431
1432         sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN
1433                                          | BIT_GENCTL_CLR_EMSC_RFIFO
1434                                          | BIT_GENCTL_CLR_EMSC_XFIFO, ~0);
1435         sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO
1436                                          | BIT_GENCTL_CLR_EMSC_XFIFO, 0);
1437         sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0);
1438         reg = sii8620_readb(ctx, REG_EMSCINTR);
1439         sii8620_write(ctx, REG_EMSCINTR, reg);
1440         sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD);
1441 }
1442
1443 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state)
1444 {
1445         int i;
1446
1447         for (i = 0; i < 10; ++i) {
1448                 u8 s = sii8620_readb(ctx, REG_COC_STAT_0);
1449
1450                 if ((s & MSK_COC_STAT_0_FSM_STATE) == state)
1451                         return 0;
1452                 if (!(s & BIT_COC_STAT_0_PLL_LOCKED))
1453                         return -EBUSY;
1454                 usleep_range(4000, 6000);
1455         }
1456         return -ETIMEDOUT;
1457 }
1458
1459 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode)
1460 {
1461         int ret;
1462
1463         if (ctx->mode == mode)
1464                 return;
1465
1466         switch (mode) {
1467         case CM_MHL1:
1468                 sii8620_write_seq_static(ctx,
1469                         REG_CBUS_MSC_COMPAT_CTRL, 0x02,
1470                         REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE,
1471                         REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12
1472                                 | BIT_DPD_OSC_EN,
1473                         REG_COC_INTR_MASK, 0
1474                 );
1475                 ctx->mode = mode;
1476                 break;
1477         case CM_MHL3:
1478                 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
1479                 ctx->mode = mode;
1480                 return;
1481         case CM_ECBUS_S:
1482                 sii8620_emsc_enable(ctx);
1483                 sii8620_write_seq_static(ctx,
1484                         REG_TTXSPINUMS, 4,
1485                         REG_TRXSPINUMS, 4,
1486                         REG_TTXHSICNUMS, 0x14,
1487                         REG_TRXHSICNUMS, 0x14,
1488                         REG_TTXTOTNUMS, 0x18,
1489                         REG_TRXTOTNUMS, 0x18,
1490                         REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST
1491                                       | BIT_PWD_SRST_CBUS_RST_SW_EN,
1492                         REG_MHL_COC_CTL1, 0xbd,
1493                         REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN,
1494                         REG_COC_CTLB, 0x01,
1495                         REG_COC_CTL0, 0x5c,
1496                         REG_COC_CTL14, 0x03,
1497                         REG_COC_CTL15, 0x80,
1498                         REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN
1499                                          | BIT_MHL_DP_CTL6_DP_TAP1_EN
1500                                          | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN,
1501                         REG_MHL_DP_CTL8, 0x03
1502                 );
1503                 ret = sii8620_wait_for_fsm_state(ctx, 0x03);
1504                 sii8620_write_seq_static(ctx,
1505                         REG_COC_CTL14, 0x00,
1506                         REG_COC_CTL15, 0x80
1507                 );
1508                 if (!ret)
1509                         sii8620_write(ctx, REG_CBUS3_CNVT, 0x85);
1510                 else
1511                         sii8620_disconnect(ctx);
1512                 return;
1513         case CM_DISCONNECTED:
1514                 ctx->mode = mode;
1515                 break;
1516         default:
1517                 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode);
1518                 break;
1519         }
1520
1521         sii8620_set_auto_zone(ctx);
1522
1523         if (mode != CM_MHL1)
1524                 return;
1525
1526         sii8620_write_seq_static(ctx,
1527                 REG_MHL_DP_CTL0, 0xBC,
1528                 REG_MHL_DP_CTL1, 0xBB,
1529                 REG_MHL_DP_CTL3, 0x48,
1530                 REG_MHL_DP_CTL5, 0x39,
1531                 REG_MHL_DP_CTL2, 0x2A,
1532                 REG_MHL_DP_CTL6, 0x2A,
1533                 REG_MHL_DP_CTL7, 0x08
1534         );
1535 }
1536
1537 static void sii8620_disconnect(struct sii8620 *ctx)
1538 {
1539         sii8620_disable_gen2_write_burst(ctx);
1540         sii8620_stop_video(ctx);
1541         msleep(100);
1542         sii8620_cbus_reset(ctx);
1543         sii8620_set_mode(ctx, CM_DISCONNECTED);
1544         sii8620_write_seq_static(ctx,
1545                 REG_TX_ZONE_CTL1, 0,
1546                 REG_MHL_PLL_CTL0, 0x07,
1547                 REG_COC_CTL0, 0x40,
1548                 REG_CBUS3_CNVT, 0x84,
1549                 REG_COC_CTL14, 0x00,
1550                 REG_COC_CTL0, 0x40,
1551                 REG_HRXCTRL3, 0x07,
1552                 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
1553                         | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL
1554                         | BIT_MHL_PLL_CTL0_ZONE_MASK_OE,
1555                 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE
1556                         | BIT_MHL_DP_CTL0_TX_OE_OVR,
1557                 REG_MHL_DP_CTL1, 0xBB,
1558                 REG_MHL_DP_CTL3, 0x48,
1559                 REG_MHL_DP_CTL5, 0x3F,
1560                 REG_MHL_DP_CTL2, 0x2F,
1561                 REG_MHL_DP_CTL6, 0x2A,
1562                 REG_MHL_DP_CTL7, 0x03
1563         );
1564         sii8620_disable_hpd(ctx);
1565         sii8620_write_seq_static(ctx,
1566                 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
1567                 REG_MHL_COC_CTL1, 0x07,
1568                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1569                 REG_DISC_CTRL8, 0x00,
1570                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1571                         | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1572                 REG_INT_CTRL, 0x00,
1573                 REG_MSC_HEARTBEAT_CTRL, 0x27,
1574                 REG_DISC_CTRL1, 0x25,
1575                 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT,
1576                 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT,
1577                 REG_MDT_INT_1, 0xff,
1578                 REG_MDT_INT_1_MASK, 0x00,
1579                 REG_MDT_INT_0, 0xff,
1580                 REG_MDT_INT_0_MASK, 0x00,
1581                 REG_COC_INTR, 0xff,
1582                 REG_COC_INTR_MASK, 0x00,
1583                 REG_TRXINTH, 0xff,
1584                 REG_TRXINTMH, 0x00,
1585                 REG_CBUS_INT_0, 0xff,
1586                 REG_CBUS_INT_0_MASK, 0x00,
1587                 REG_CBUS_INT_1, 0xff,
1588                 REG_CBUS_INT_1_MASK, 0x00,
1589                 REG_EMSCINTR, 0xff,
1590                 REG_EMSCINTRMASK, 0x00,
1591                 REG_EMSCINTR1, 0xff,
1592                 REG_EMSCINTRMASK1, 0x00,
1593                 REG_INTR8, 0xff,
1594                 REG_INTR8_MASK, 0x00,
1595                 REG_TPI_INTR_ST0, 0xff,
1596                 REG_TPI_INTR_EN, 0x00,
1597                 REG_HDCP2X_INTR0, 0xff,
1598                 REG_HDCP2X_INTR0_MASK, 0x00,
1599                 REG_INTR9, 0xff,
1600                 REG_INTR9_MASK, 0x00,
1601                 REG_INTR3, 0xff,
1602                 REG_INTR3_MASK, 0x00,
1603                 REG_INTR5, 0xff,
1604                 REG_INTR5_MASK, 0x00,
1605                 REG_INTR2, 0xff,
1606                 REG_INTR2_MASK, 0x00,
1607         );
1608         memset(ctx->stat, 0, sizeof(ctx->stat));
1609         memset(ctx->xstat, 0, sizeof(ctx->xstat));
1610         memset(ctx->devcap, 0, sizeof(ctx->devcap));
1611         memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap));
1612         ctx->cbus_status = 0;
1613         ctx->sink_type = SINK_NONE;
1614         kfree(ctx->edid);
1615         ctx->edid = NULL;
1616         sii8620_mt_cleanup(ctx);
1617 }
1618
1619 static void sii8620_mhl_disconnected(struct sii8620 *ctx)
1620 {
1621         sii8620_write_seq_static(ctx,
1622                 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K),
1623                 REG_CBUS_MSC_COMPAT_CTRL,
1624                         BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN
1625         );
1626         sii8620_disconnect(ctx);
1627 }
1628
1629 static void sii8620_irq_disc(struct sii8620 *ctx)
1630 {
1631         u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0);
1632
1633         if (stat & VAL_CBUS_MHL_DISCON)
1634                 sii8620_mhl_disconnected(ctx);
1635
1636         if (stat & BIT_RGND_READY_INT) {
1637                 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2);
1638
1639                 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) {
1640                         sii8620_mhl_discover(ctx);
1641                 } else {
1642                         sii8620_write_seq_static(ctx,
1643                                 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT
1644                                         | BIT_DISC_CTRL9_NOMHL_EST
1645                                         | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS,
1646                                 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT
1647                                         | BIT_CBUS_MHL3_DISCON_INT
1648                                         | BIT_CBUS_MHL12_DISCON_INT
1649                                         | BIT_NOT_MHL_EST_INT
1650                         );
1651                 }
1652         }
1653         if (stat & BIT_MHL_EST_INT)
1654                 sii8620_mhl_init(ctx);
1655
1656         sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat);
1657 }
1658
1659 static void sii8620_read_burst(struct sii8620 *ctx)
1660 {
1661         u8 buf[17];
1662
1663         sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf));
1664         sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN |
1665                       BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN |
1666                       BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR);
1667         sii8620_readb(ctx, REG_MDT_RFIFO_STAT);
1668 }
1669
1670 static void sii8620_irq_g2wb(struct sii8620 *ctx)
1671 {
1672         u8 stat = sii8620_readb(ctx, REG_MDT_INT_0);
1673
1674         if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE)
1675                 if (sii8620_is_mhl3(ctx))
1676                         sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
1677                                 MHL_INT_RC_FEAT_COMPLETE);
1678
1679         if (stat & BIT_MDT_RFIFO_DATA_RDY)
1680                 sii8620_read_burst(ctx);
1681
1682         if (stat & BIT_MDT_XFIFO_EMPTY)
1683                 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0);
1684
1685         sii8620_write(ctx, REG_MDT_INT_0, stat);
1686 }
1687
1688 static void sii8620_status_dcap_ready(struct sii8620 *ctx)
1689 {
1690         enum sii8620_mode mode;
1691
1692         mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1;
1693         if (mode > ctx->mode)
1694                 sii8620_set_mode(ctx, mode);
1695         sii8620_peer_specific_init(ctx);
1696         sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
1697                       | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
1698 }
1699
1700 static void sii8620_status_changed_path(struct sii8620 *ctx)
1701 {
1702         if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) {
1703                 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1704                                       MHL_DST_LM_CLK_MODE_NORMAL
1705                                       | MHL_DST_LM_PATH_ENABLED);
1706                 if (!sii8620_is_mhl3(ctx))
1707                         sii8620_mt_read_devcap(ctx, false);
1708                 sii8620_mt_set_cont(ctx, sii8620_sink_detected);
1709         } else {
1710                 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE),
1711                                       MHL_DST_LM_CLK_MODE_NORMAL);
1712         }
1713 }
1714
1715 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
1716 {
1717         u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE];
1718
1719         sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE);
1720         sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE);
1721
1722         sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
1723         sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
1724
1725         if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY)
1726                 sii8620_status_dcap_ready(ctx);
1727
1728         if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
1729                 sii8620_status_changed_path(ctx);
1730 }
1731
1732 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret)
1733 {
1734         if (ret < 0)
1735                 return;
1736
1737         sii8620_set_mode(ctx, CM_ECBUS_S);
1738 }
1739
1740 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret)
1741 {
1742         if (ret < 0)
1743                 return;
1744
1745         sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE),
1746                               MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT);
1747         sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP);
1748         sii8620_mt_set_cont(ctx, sii8620_ecbus_up);
1749 }
1750
1751 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d,
1752         enum mhl_burst_id id)
1753 {
1754         sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT);
1755         d->num_entries = 1;
1756         d->burst_id[0] = cpu_to_be16(id);
1757 }
1758
1759 static void sii8620_send_features(struct sii8620 *ctx)
1760 {
1761         u8 buf[16];
1762
1763         sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN
1764                 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN);
1765         sii8620_mhl_burst_emsc_support_set((void *)buf,
1766                 MHL_BURST_ID_HID_PAYLOAD);
1767         sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf));
1768 }
1769
1770 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode)
1771 {
1772         bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK);
1773
1774         scancode &= MHL_RCP_KEY_ID_MASK;
1775
1776         if (!ctx->rc_dev) {
1777                 dev_dbg(ctx->dev, "RCP input device not initialized\n");
1778                 return false;
1779         }
1780
1781         if (pressed)
1782                 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0);
1783         else
1784                 rc_keyup(ctx->rc_dev);
1785
1786         return true;
1787 }
1788
1789 static void sii8620_msc_mr_set_int(struct sii8620 *ctx)
1790 {
1791         u8 ints[MHL_INT_SIZE];
1792
1793         sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1794         sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE);
1795
1796         if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) {
1797                 switch (ctx->mode) {
1798                 case CM_MHL3:
1799                         sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS);
1800                         sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed);
1801                         break;
1802                 case CM_ECBUS_S:
1803                         sii8620_mt_read_devcap(ctx, true);
1804                         break;
1805                 default:
1806                         break;
1807                 }
1808         }
1809         if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ)
1810                 sii8620_send_features(ctx);
1811         if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE)
1812                 sii8620_edid_read(ctx, 0);
1813 }
1814
1815 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx)
1816 {
1817         struct device *dev = ctx->dev;
1818
1819         if (list_empty(&ctx->mt_queue)) {
1820                 dev_err(dev, "unexpected MSC MT response\n");
1821                 return NULL;
1822         }
1823
1824         return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node);
1825 }
1826
1827 static void sii8620_msc_mt_done(struct sii8620 *ctx)
1828 {
1829         struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx);
1830
1831         if (!msg)
1832                 return;
1833
1834         msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0);
1835         ctx->mt_state = MT_STATE_DONE;
1836 }
1837
1838 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx)
1839 {
1840         struct sii8620_mt_msg *msg;
1841         u8 buf[2];
1842
1843         sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2);
1844
1845         switch (buf[0]) {
1846         case MHL_MSC_MSG_RAPK:
1847                 msg = sii8620_msc_msg_first(ctx);
1848                 if (!msg)
1849                         return;
1850                 msg->ret = buf[1];
1851                 ctx->mt_state = MT_STATE_DONE;
1852                 break;
1853         case MHL_MSC_MSG_RCP:
1854                 if (!sii8620_rcp_consume(ctx, buf[1]))
1855                         sii8620_mt_rcpe(ctx,
1856                                         MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE);
1857                 sii8620_mt_rcpk(ctx, buf[1]);
1858                 break;
1859         default:
1860                 dev_err(ctx->dev, "%s message type %d,%d not supported",
1861                         __func__, buf[0], buf[1]);
1862         }
1863 }
1864
1865 static void sii8620_irq_msc(struct sii8620 *ctx)
1866 {
1867         u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0);
1868
1869         if (stat & ~BIT_CBUS_HPD_CHG)
1870                 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG);
1871
1872         if (stat & BIT_CBUS_HPD_CHG) {
1873                 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS);
1874
1875                 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) {
1876                         sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG);
1877                 } else {
1878                         stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1879                         cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD;
1880                 }
1881                 ctx->cbus_status = cbus_stat;
1882         }
1883
1884         if (stat & BIT_CBUS_MSC_MR_WRITE_STAT)
1885                 sii8620_msc_mr_write_stat(ctx);
1886
1887         if (stat & BIT_CBUS_MSC_MR_SET_INT)
1888                 sii8620_msc_mr_set_int(ctx);
1889
1890         if (stat & BIT_CBUS_MSC_MT_DONE)
1891                 sii8620_msc_mt_done(ctx);
1892
1893         if (stat & BIT_CBUS_MSC_MR_MSC_MSG)
1894                 sii8620_msc_mr_msc_msg(ctx);
1895 }
1896
1897 static void sii8620_irq_coc(struct sii8620 *ctx)
1898 {
1899         u8 stat = sii8620_readb(ctx, REG_COC_INTR);
1900
1901         if (stat & BIT_COC_CALIBRATION_DONE) {
1902                 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0);
1903
1904                 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE;
1905                 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) {
1906                         sii8620_write_seq_static(ctx,
1907                                 REG_COC_CTLB, 0,
1908                                 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA
1909                                               | BIT_TDM_INTR_SYNC_WAIT
1910                         );
1911                 }
1912         }
1913
1914         sii8620_write(ctx, REG_COC_INTR, stat);
1915 }
1916
1917 static void sii8620_irq_merr(struct sii8620 *ctx)
1918 {
1919         u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1);
1920
1921         sii8620_write(ctx, REG_CBUS_INT_1, stat);
1922 }
1923
1924 static void sii8620_irq_edid(struct sii8620 *ctx)
1925 {
1926         u8 stat = sii8620_readb(ctx, REG_INTR9);
1927
1928         sii8620_write(ctx, REG_INTR9, stat);
1929
1930         if (stat & BIT_INTR9_DEVCAP_DONE)
1931                 ctx->mt_state = MT_STATE_DONE;
1932 }
1933
1934 static void sii8620_scdt_high(struct sii8620 *ctx)
1935 {
1936         sii8620_write_seq_static(ctx,
1937                 REG_INTR8_MASK, BIT_CEA_NEW_AVI | BIT_CEA_NEW_VSI,
1938                 REG_TPI_SC, BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI,
1939         );
1940 }
1941
1942 static void sii8620_irq_scdt(struct sii8620 *ctx)
1943 {
1944         u8 stat = sii8620_readb(ctx, REG_INTR5);
1945
1946         if (stat & BIT_INTR_SCDT_CHANGE) {
1947                 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3);
1948
1949                 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) {
1950                         if (ctx->sink_type == SINK_HDMI)
1951                                 /* enable infoframe interrupt */
1952                                 sii8620_scdt_high(ctx);
1953                         else
1954                                 sii8620_start_video(ctx);
1955                 }
1956         }
1957
1958         sii8620_write(ctx, REG_INTR5, stat);
1959 }
1960
1961 static void sii8620_new_vsi(struct sii8620 *ctx)
1962 {
1963         u8 vsif[11];
1964
1965         sii8620_write(ctx, REG_RX_HDMI_CTRL2,
1966                       VAL_RX_HDMI_CTRL2_DEFVAL |
1967                       BIT_RX_HDMI_CTRL2_VSI_MON_SEL_VSI);
1968         sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, vsif,
1969                          ARRAY_SIZE(vsif));
1970 }
1971
1972 static void sii8620_new_avi(struct sii8620 *ctx)
1973 {
1974         sii8620_write(ctx, REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL);
1975         sii8620_read_buf(ctx, REG_RX_HDMI_MON_PKT_HEADER1, ctx->avif,
1976                          ARRAY_SIZE(ctx->avif));
1977 }
1978
1979 static void sii8620_irq_infr(struct sii8620 *ctx)
1980 {
1981         u8 stat = sii8620_readb(ctx, REG_INTR8)
1982                 & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI);
1983
1984         sii8620_write(ctx, REG_INTR8, stat);
1985
1986         if (stat & BIT_CEA_NEW_VSI)
1987                 sii8620_new_vsi(ctx);
1988
1989         if (stat & BIT_CEA_NEW_AVI)
1990                 sii8620_new_avi(ctx);
1991
1992         if (stat & (BIT_CEA_NEW_VSI | BIT_CEA_NEW_AVI))
1993                 sii8620_start_video(ctx);
1994 }
1995
1996 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret)
1997 {
1998         if (ret < 0)
1999                 return;
2000
2001         sii8620_mt_read_devcap(ctx, false);
2002 }
2003
2004 static void sii8620_irq_tdm(struct sii8620 *ctx)
2005 {
2006         u8 stat = sii8620_readb(ctx, REG_TRXINTH);
2007         u8 tdm = sii8620_readb(ctx, REG_TRXSTA2);
2008
2009         if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) {
2010                 ctx->mode = CM_ECBUS_S;
2011                 ctx->burst.rx_ack = 0;
2012                 ctx->burst.r_size = SII8620_BURST_BUF_LEN;
2013                 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN);
2014                 sii8620_mt_read_devcap(ctx, true);
2015                 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap);
2016         } else {
2017                 sii8620_write_seq_static(ctx,
2018                         REG_MHL_PLL_CTL2, 0,
2019                         REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN
2020                 );
2021         }
2022
2023         sii8620_write(ctx, REG_TRXINTH, stat);
2024 }
2025
2026 static void sii8620_irq_block(struct sii8620 *ctx)
2027 {
2028         u8 stat = sii8620_readb(ctx, REG_EMSCINTR);
2029
2030         if (stat & BIT_EMSCINTR_SPI_DVLD) {
2031                 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT);
2032
2033                 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE)
2034                         sii8620_burst_receive(ctx);
2035         }
2036
2037         sii8620_write(ctx, REG_EMSCINTR, stat);
2038 }
2039
2040 static void sii8620_irq_ddc(struct sii8620 *ctx)
2041 {
2042         u8 stat = sii8620_readb(ctx, REG_INTR3);
2043
2044         if (stat & BIT_DDC_CMD_DONE) {
2045                 sii8620_write(ctx, REG_INTR3_MASK, 0);
2046                 if (sii8620_is_mhl3(ctx))
2047                         sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE),
2048                                            MHL_INT_RC_FEAT_REQ);
2049                 else
2050                         sii8620_edid_read(ctx, 0);
2051         }
2052         sii8620_write(ctx, REG_INTR3, stat);
2053 }
2054
2055 /* endian agnostic, non-volatile version of test_bit */
2056 static bool sii8620_test_bit(unsigned int nr, const u8 *addr)
2057 {
2058         return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE));
2059 }
2060
2061 static irqreturn_t sii8620_irq_thread(int irq, void *data)
2062 {
2063         static const struct {
2064                 int bit;
2065                 void (*handler)(struct sii8620 *ctx);
2066         } irq_vec[] = {
2067                 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc },
2068                 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb },
2069                 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc },
2070                 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm },
2071                 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc },
2072                 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr },
2073                 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block },
2074                 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid },
2075                 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc },
2076                 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt },
2077                 { BIT_FAST_INTR_STAT_INFR, sii8620_irq_infr },
2078         };
2079         struct sii8620 *ctx = data;
2080         u8 stats[LEN_FAST_INTR_STAT];
2081         int i, ret;
2082
2083         mutex_lock(&ctx->lock);
2084
2085         sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats));
2086         for (i = 0; i < ARRAY_SIZE(irq_vec); ++i)
2087                 if (sii8620_test_bit(irq_vec[i].bit, stats))
2088                         irq_vec[i].handler(ctx);
2089
2090         sii8620_burst_rx_all(ctx);
2091         sii8620_mt_work(ctx);
2092         sii8620_burst_send(ctx);
2093
2094         ret = sii8620_clear_error(ctx);
2095         if (ret) {
2096                 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret);
2097                 sii8620_mhl_disconnected(ctx);
2098         }
2099         mutex_unlock(&ctx->lock);
2100
2101         return IRQ_HANDLED;
2102 }
2103
2104 static void sii8620_cable_in(struct sii8620 *ctx)
2105 {
2106         struct device *dev = ctx->dev;
2107         u8 ver[5];
2108         int ret;
2109
2110         ret = sii8620_hw_on(ctx);
2111         if (ret) {
2112                 dev_err(dev, "Error powering on, %d.\n", ret);
2113                 return;
2114         }
2115         sii8620_hw_reset(ctx);
2116
2117         sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver));
2118         ret = sii8620_clear_error(ctx);
2119         if (ret) {
2120                 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2121                 return;
2122         }
2123
2124         dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0],
2125                  ver[3], ver[2], ver[4]);
2126
2127         sii8620_write(ctx, REG_DPD,
2128                       BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN);
2129
2130         sii8620_xtal_set_rate(ctx);
2131         sii8620_disconnect(ctx);
2132
2133         sii8620_write_seq_static(ctx,
2134                 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
2135                         | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734,
2136                 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM,
2137                 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN,
2138         );
2139
2140         ret = sii8620_clear_error(ctx);
2141         if (ret) {
2142                 dev_err(dev, "Error accessing I2C bus, %d.\n", ret);
2143                 return;
2144         }
2145
2146         enable_irq(to_i2c_client(ctx->dev)->irq);
2147 }
2148
2149 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx)
2150 {
2151         struct rc_dev *rc_dev;
2152         int ret;
2153
2154         rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE);
2155         if (!rc_dev) {
2156                 dev_err(ctx->dev, "Failed to allocate RC device\n");
2157                 ctx->error = -ENOMEM;
2158                 return;
2159         }
2160
2161         rc_dev->input_phys = "sii8620/input0";
2162         rc_dev->input_id.bustype = BUS_VIRTUAL;
2163         rc_dev->map_name = RC_MAP_CEC;
2164         rc_dev->allowed_protocols = RC_PROTO_BIT_CEC;
2165         rc_dev->driver_name = "sii8620";
2166         rc_dev->device_name = "sii8620";
2167
2168         ret = rc_register_device(rc_dev);
2169
2170         if (ret) {
2171                 dev_err(ctx->dev, "Failed to register RC device\n");
2172                 ctx->error = ret;
2173                 rc_free_device(ctx->rc_dev);
2174                 return;
2175         }
2176         ctx->rc_dev = rc_dev;
2177 }
2178
2179 static void sii8620_cable_out(struct sii8620 *ctx)
2180 {
2181         disable_irq(to_i2c_client(ctx->dev)->irq);
2182         sii8620_hw_off(ctx);
2183 }
2184
2185 static void sii8620_extcon_work(struct work_struct *work)
2186 {
2187         struct sii8620 *ctx =
2188                 container_of(work, struct sii8620, extcon_wq);
2189         int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL);
2190
2191         if (state == ctx->cable_state)
2192                 return;
2193
2194         ctx->cable_state = state;
2195
2196         if (state > 0)
2197                 sii8620_cable_in(ctx);
2198         else
2199                 sii8620_cable_out(ctx);
2200 }
2201
2202 static int sii8620_extcon_notifier(struct notifier_block *self,
2203                         unsigned long event, void *ptr)
2204 {
2205         struct sii8620 *ctx =
2206                 container_of(self, struct sii8620, extcon_nb);
2207
2208         schedule_work(&ctx->extcon_wq);
2209
2210         return NOTIFY_DONE;
2211 }
2212
2213 static int sii8620_extcon_init(struct sii8620 *ctx)
2214 {
2215         struct extcon_dev *edev;
2216         struct device_node *musb, *muic;
2217         int ret;
2218
2219         /* get micro-USB connector node */
2220         musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1);
2221         /* next get micro-USB Interface Controller node */
2222         muic = of_get_next_parent(musb);
2223
2224         if (!muic) {
2225                 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n");
2226                 return 0;
2227         }
2228
2229         edev = extcon_find_edev_by_node(muic);
2230         of_node_put(muic);
2231         if (IS_ERR(edev)) {
2232                 if (PTR_ERR(edev) == -EPROBE_DEFER)
2233                         return -EPROBE_DEFER;
2234                 dev_err(ctx->dev, "Invalid or missing extcon\n");
2235                 return PTR_ERR(edev);
2236         }
2237
2238         ctx->extcon = edev;
2239         ctx->extcon_nb.notifier_call = sii8620_extcon_notifier;
2240         INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work);
2241         ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb);
2242         if (ret) {
2243                 dev_err(ctx->dev, "failed to register notifier for MHL\n");
2244                 return ret;
2245         }
2246
2247         return 0;
2248 }
2249
2250 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge)
2251 {
2252         return container_of(bridge, struct sii8620, bridge);
2253 }
2254
2255 static int sii8620_attach(struct drm_bridge *bridge)
2256 {
2257         struct sii8620 *ctx = bridge_to_sii8620(bridge);
2258
2259         sii8620_init_rcp_input_dev(ctx);
2260
2261         return sii8620_clear_error(ctx);
2262 }
2263
2264 static void sii8620_detach(struct drm_bridge *bridge)
2265 {
2266         struct sii8620 *ctx = bridge_to_sii8620(bridge);
2267
2268         rc_unregister_device(ctx->rc_dev);
2269 }
2270
2271 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge,
2272                                          const struct drm_display_mode *mode)
2273 {
2274         struct sii8620 *ctx = bridge_to_sii8620(bridge);
2275         bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] &
2276                         MHL_DCAP_VID_LINK_PPIXEL;
2277         unsigned int max_pclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK :
2278                                                        MHL1_MAX_LCLK;
2279         max_pclk /= can_pack ? 2 : 3;
2280
2281         return (mode->clock > max_pclk) ? MODE_CLOCK_HIGH : MODE_OK;
2282 }
2283
2284 static bool sii8620_mode_fixup(struct drm_bridge *bridge,
2285                                const struct drm_display_mode *mode,
2286                                struct drm_display_mode *adjusted_mode)
2287 {
2288         struct sii8620 *ctx = bridge_to_sii8620(bridge);
2289         int max_lclk;
2290         bool ret = true;
2291
2292         mutex_lock(&ctx->lock);
2293
2294         max_lclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : MHL1_MAX_LCLK;
2295         if (max_lclk > 3 * adjusted_mode->clock) {
2296                 ctx->use_packed_pixel = 0;
2297                 goto end;
2298         }
2299         if ((ctx->devcap[MHL_DCAP_VID_LINK_MODE] & MHL_DCAP_VID_LINK_PPIXEL) &&
2300             max_lclk > 2 * adjusted_mode->clock) {
2301                 ctx->use_packed_pixel = 1;
2302                 goto end;
2303         }
2304         ret = false;
2305 end:
2306         if (ret) {
2307                 u8 vic = drm_match_cea_mode(adjusted_mode);
2308
2309                 if (!vic) {
2310                         union hdmi_infoframe frm;
2311                         u8 mhl_vic[] = { 0, 95, 94, 93, 98 };
2312
2313                         /* FIXME: We need the connector here */
2314                         drm_hdmi_vendor_infoframe_from_display_mode(
2315                                 &frm.vendor.hdmi, NULL, adjusted_mode);
2316                         vic = frm.vendor.hdmi.vic;
2317                         if (vic >= ARRAY_SIZE(mhl_vic))
2318                                 vic = 0;
2319                         vic = mhl_vic[vic];
2320                 }
2321                 ctx->video_code = vic;
2322                 ctx->pixel_clock = adjusted_mode->clock;
2323         }
2324         mutex_unlock(&ctx->lock);
2325         return ret;
2326 }
2327
2328 static const struct drm_bridge_funcs sii8620_bridge_funcs = {
2329         .attach = sii8620_attach,
2330         .detach = sii8620_detach,
2331         .mode_fixup = sii8620_mode_fixup,
2332         .mode_valid = sii8620_mode_valid,
2333 };
2334
2335 static int sii8620_probe(struct i2c_client *client,
2336                          const struct i2c_device_id *id)
2337 {
2338         struct device *dev = &client->dev;
2339         struct sii8620 *ctx;
2340         int ret;
2341
2342         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2343         if (!ctx)
2344                 return -ENOMEM;
2345
2346         ctx->dev = dev;
2347         mutex_init(&ctx->lock);
2348         INIT_LIST_HEAD(&ctx->mt_queue);
2349
2350         ctx->clk_xtal = devm_clk_get(dev, "xtal");
2351         if (IS_ERR(ctx->clk_xtal)) {
2352                 dev_err(dev, "failed to get xtal clock from DT\n");
2353                 return PTR_ERR(ctx->clk_xtal);
2354         }
2355
2356         if (!client->irq) {
2357                 dev_err(dev, "no irq provided\n");
2358                 return -EINVAL;
2359         }
2360         irq_set_status_flags(client->irq, IRQ_NOAUTOEN);
2361         ret = devm_request_threaded_irq(dev, client->irq, NULL,
2362                                         sii8620_irq_thread,
2363                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2364                                         "sii8620", ctx);
2365         if (ret < 0) {
2366                 dev_err(dev, "failed to install IRQ handler\n");
2367                 return ret;
2368         }
2369
2370         ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
2371         if (IS_ERR(ctx->gpio_reset)) {
2372                 dev_err(dev, "failed to get reset gpio from DT\n");
2373                 return PTR_ERR(ctx->gpio_reset);
2374         }
2375
2376         ctx->supplies[0].supply = "cvcc10";
2377         ctx->supplies[1].supply = "iovcc18";
2378         ret = devm_regulator_bulk_get(dev, 2, ctx->supplies);
2379         if (ret)
2380                 return ret;
2381
2382         ret = sii8620_extcon_init(ctx);
2383         if (ret < 0) {
2384                 dev_err(ctx->dev, "failed to initialize EXTCON\n");
2385                 return ret;
2386         }
2387
2388         i2c_set_clientdata(client, ctx);
2389
2390         ctx->bridge.funcs = &sii8620_bridge_funcs;
2391         ctx->bridge.of_node = dev->of_node;
2392         drm_bridge_add(&ctx->bridge);
2393
2394         if (!ctx->extcon)
2395                 sii8620_cable_in(ctx);
2396
2397         return 0;
2398 }
2399
2400 static int sii8620_remove(struct i2c_client *client)
2401 {
2402         struct sii8620 *ctx = i2c_get_clientdata(client);
2403
2404         if (ctx->extcon) {
2405                 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL,
2406                                            &ctx->extcon_nb);
2407                 flush_work(&ctx->extcon_wq);
2408                 if (ctx->cable_state > 0)
2409                         sii8620_cable_out(ctx);
2410         } else {
2411                 sii8620_cable_out(ctx);
2412         }
2413         drm_bridge_remove(&ctx->bridge);
2414
2415         return 0;
2416 }
2417
2418 static const struct of_device_id sii8620_dt_match[] = {
2419         { .compatible = "sil,sii8620" },
2420         { },
2421 };
2422 MODULE_DEVICE_TABLE(of, sii8620_dt_match);
2423
2424 static const struct i2c_device_id sii8620_id[] = {
2425         { "sii8620", 0 },
2426         { },
2427 };
2428
2429 MODULE_DEVICE_TABLE(i2c, sii8620_id);
2430 static struct i2c_driver sii8620_driver = {
2431         .driver = {
2432                 .name   = "sii8620",
2433                 .of_match_table = of_match_ptr(sii8620_dt_match),
2434         },
2435         .probe          = sii8620_probe,
2436         .remove         = sii8620_remove,
2437         .id_table = sii8620_id,
2438 };
2439
2440 module_i2c_driver(sii8620_driver);
2441 MODULE_LICENSE("GPL v2");