drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
  47 module_param(logging_level, ulong, 0644);
  48 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  49
  50 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  51 module_param(link_rate, ulong, 0644);
  52 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  53                 " 1: Link rate 1.5G\n"
  54                 " 2: Link rate 3.0G\n"
  55                 " 4: Link rate 6.0G\n"
  56                 " 8: Link rate 12.0G\n");
  57
  58 static struct scsi_transport_template *pm8001_stt;
  59
  60 /**
  61  * chip info structure to identify chip key functionality as
  62  * encryption available/not, no of ports, hw specific function ref
  63  */
  64 static const struct pm8001_chip_info pm8001_chips[] = {
  65         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  66         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  67         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  68         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  69         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  70         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  71         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  72         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  73         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  75         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  76 };
  77 static int pm8001_id;
  78
  79 LIST_HEAD(hba_list);
  80
  81 struct workqueue_struct *pm8001_wq;
  82
  83 /**
  84  * The main structure which LLDD must register for scsi core.
  85  */
  86 static struct scsi_host_template pm8001_sht = {
  87         .module                 = THIS_MODULE,
  88         .name                   = DRV_NAME,
  89         .queuecommand           = sas_queuecommand,
  90         .dma_need_drain         = ata_scsi_dma_need_drain,
  91         .target_alloc           = sas_target_alloc,
  92         .slave_configure        = sas_slave_configure,
  93         .scan_finished          = pm8001_scan_finished,
  94         .scan_start             = pm8001_scan_start,
  95         .change_queue_depth     = sas_change_queue_depth,
  96         .bios_param             = sas_bios_param,
  97         .can_queue              = 1,
  98         .this_id                = -1,
  99         .sg_tablesize           = PM8001_MAX_DMA_SG,
 100         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 101         .eh_device_reset_handler = sas_eh_device_reset_handler,
 102         .eh_target_reset_handler = sas_eh_target_reset_handler,
 103         .target_destroy         = sas_target_destroy,
 104         .ioctl                  = sas_ioctl,
 105 #ifdef CONFIG_COMPAT
 106         .compat_ioctl           = sas_ioctl,
 107 #endif
 108         .shost_attrs            = pm8001_host_attrs,
 109         .track_queue_depth      = 1,
 110 };
 111
 112 /**
 113  * Sas layer call this function to execute specific task.
 114  */
 115 static struct sas_domain_function_template pm8001_transport_ops = {
 116         .lldd_dev_found         = pm8001_dev_found,
 117         .lldd_dev_gone          = pm8001_dev_gone,
 118
 119         .lldd_execute_task      = pm8001_queue_command,
 120         .lldd_control_phy       = pm8001_phy_control,
 121
 122         .lldd_abort_task        = pm8001_abort_task,
 123         .lldd_abort_task_set    = pm8001_abort_task_set,
 124         .lldd_clear_aca         = pm8001_clear_aca,
 125         .lldd_clear_task_set    = pm8001_clear_task_set,
 126         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 127         .lldd_lu_reset          = pm8001_lu_reset,
 128         .lldd_query_task        = pm8001_query_task,
 129 };
 130
 131 /**
 132  *pm8001_phy_init - initiate our adapter phys
 133  *@pm8001_ha: our hba structure.
 134  *@phy_id: phy id.
 135  */
 136 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 137 {
 138         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 139         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 140         phy->phy_state = PHY_LINK_DISABLE;
 141         phy->pm8001_ha = pm8001_ha;
 142         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 143         sas_phy->class = SAS;
 144         sas_phy->iproto = SAS_PROTOCOL_ALL;
 145         sas_phy->tproto = 0;
 146         sas_phy->type = PHY_TYPE_PHYSICAL;
 147         sas_phy->role = PHY_ROLE_INITIATOR;
 148         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 149         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 150         sas_phy->id = phy_id;
 151         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 152         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 153         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 154         sas_phy->lldd_phy = phy;
 155 }
 156
 157 /**
 158  *pm8001_free - free hba
 159  *@pm8001_ha:   our hba structure.
 160  *
 161  */
 162 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 163 {
 164         int i;
 165
 166         if (!pm8001_ha)
 167                 return;
 168
 169         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 170                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 171                         dma_free_coherent(&pm8001_ha->pdev->dev,
 172                                 (pm8001_ha->memoryMap.region[i].total_len +
 173                                 pm8001_ha->memoryMap.region[i].alignment),
 174                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 175                                 pm8001_ha->memoryMap.region[i].phys_addr);
 176                         }
 177         }
 178         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 179         flush_workqueue(pm8001_wq);
 180         kfree(pm8001_ha->tags);
 181         kfree(pm8001_ha);
 182 }
 183
 184 #ifdef PM8001_USE_TASKLET
 185
 186 /**
 187  * tasklet for 64 msi-x interrupt handler
 188  * @opaque: the passed general host adapter struct
 189  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 190  */
 191 static void pm8001_tasklet(unsigned long opaque)
 192 {
 193         struct pm8001_hba_info *pm8001_ha;
 194         struct isr_param *irq_vector;
 195
 196         irq_vector = (struct isr_param *)opaque;
 197         pm8001_ha = irq_vector->drv_inst;
 198         if (unlikely(!pm8001_ha))
 199                 BUG_ON(1);
 200         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 201 }
 202 #endif
 203
 204 /**
 205  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 206  * It obtains the vector number and calls the equivalent bottom
 207  * half or services directly.
 208  * @opaque: the passed outbound queue/vector. Host structure is
 209  * retrieved from the same.
 210  */
 211 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 212 {
 213         struct isr_param *irq_vector;
 214         struct pm8001_hba_info *pm8001_ha;
 215         irqreturn_t ret = IRQ_HANDLED;
 216         irq_vector = (struct isr_param *)opaque;
 217         pm8001_ha = irq_vector->drv_inst;
 218
 219         if (unlikely(!pm8001_ha))
 220                 return IRQ_NONE;
 221         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 222                 return IRQ_NONE;
 223 #ifdef PM8001_USE_TASKLET
 224         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 225 #else
 226         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 227 #endif
 228         return ret;
 229 }
 230
 231 /**
 232  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 233  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 234  */
 235
 236 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 237 {
 238         struct pm8001_hba_info *pm8001_ha;
 239         irqreturn_t ret = IRQ_HANDLED;
 240         struct sas_ha_struct *sha = dev_id;
 241         pm8001_ha = sha->lldd_ha;
 242         if (unlikely(!pm8001_ha))
 243                 return IRQ_NONE;
 244         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 245                 return IRQ_NONE;
 246
 247 #ifdef PM8001_USE_TASKLET
 248         tasklet_schedule(&pm8001_ha->tasklet[0]);
 249 #else
 250         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 251 #endif
 252         return ret;
 253 }
 254
 255 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 256 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 257
 258 /**
 259  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 260  * @pm8001_ha:our hba structure.
 261  *
 262  */
 263 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 264                         const struct pci_device_id *ent)
 265 {
 266         int i;
 267         spin_lock_init(&pm8001_ha->lock);
 268         spin_lock_init(&pm8001_ha->bitmap_lock);
 269         PM8001_INIT_DBG(pm8001_ha,
 270                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 271                                 pm8001_ha->chip->n_phy));
 272         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 273                 pm8001_phy_init(pm8001_ha, i);
 274                 pm8001_ha->port[i].wide_port_phymap = 0;
 275                 pm8001_ha->port[i].port_attached = 0;
 276                 pm8001_ha->port[i].port_state = 0;
 277                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 278         }
 279
 280         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
 281         if (!pm8001_ha->tags)
 282                 goto err_out;
 283         /* MPI Memory region 1 for AAP Event Log for fw */
 284         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 285         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 286         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 287         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 288
 289         /* MPI Memory region 2 for IOP Event Log for fw */
 290         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 291         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 292         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 293         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 294
 295         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 296                 /* MPI Memory region 3 for consumer Index of inbound queues */
 297                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
 298                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
 299                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
 300                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
 301
 302                 if ((ent->driver_data) != chip_8001) {
 303                         /* MPI Memory region 5 inbound queues */
 304                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 305                                                 PM8001_MPI_QUEUE;
 306                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
 307                         pm8001_ha->memoryMap.region[IB+i].total_len =
 308                                                 PM8001_MPI_QUEUE * 128;
 309                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
 310                 } else {
 311                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 312                                                 PM8001_MPI_QUEUE;
 313                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
 314                         pm8001_ha->memoryMap.region[IB+i].total_len =
 315                                                 PM8001_MPI_QUEUE * 64;
 316                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
 317                 }
 318         }
 319
 320         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 321                 /* MPI Memory region 4 for producer Index of outbound queues */
 322                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
 323                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
 324                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
 325                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
 326
 327                 if (ent->driver_data != chip_8001) {
 328                         /* MPI Memory region 6 Outbound queues */
 329                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 330                                                 PM8001_MPI_QUEUE;
 331                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
 332                         pm8001_ha->memoryMap.region[OB+i].total_len =
 333                                                 PM8001_MPI_QUEUE * 128;
 334                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
 335                 } else {
 336                         /* MPI Memory region 6 Outbound queues */
 337                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 338                                                 PM8001_MPI_QUEUE;
 339                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
 340                         pm8001_ha->memoryMap.region[OB+i].total_len =
 341                                                 PM8001_MPI_QUEUE * 64;
 342                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
 343                 }
 344
 345         }
 346         /* Memory region write DMA*/
 347         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 348         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 349         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 350         /* Memory region for devices*/
 351         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
 352         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
 353                 sizeof(struct pm8001_device);
 354         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
 355                 sizeof(struct pm8001_device);
 356
 357         /* Memory region for ccb_info*/
 358         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
 359         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
 360                 sizeof(struct pm8001_ccb_info);
 361         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
 362                 sizeof(struct pm8001_ccb_info);
 363
 364         /* Memory region for fw flash */
 365         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 366
 367         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 368         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 369         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 370         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 371         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 372                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 373                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 374                         &pm8001_ha->memoryMap.region[i].phys_addr,
 375                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 376                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 377                         pm8001_ha->memoryMap.region[i].total_len,
 378                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 379                                 PM8001_FAIL_DBG(pm8001_ha,
 380                                         pm8001_printk("Mem%d alloc failed\n",
 381                                         i));
 382                                 goto err_out;
 383                 }
 384         }
 385
 386         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
 387         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 388                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 389                 pm8001_ha->devices[i].id = i;
 390                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 391                 pm8001_ha->devices[i].running_req = 0;
 392         }
 393         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
 394         for (i = 0; i < PM8001_MAX_CCB; i++) {
 395                 pm8001_ha->ccb_info[i].ccb_dma_handle =
 396                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
 397                         i * sizeof(struct pm8001_ccb_info);
 398                 pm8001_ha->ccb_info[i].task = NULL;
 399                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
 400                 pm8001_ha->ccb_info[i].device = NULL;
 401                 ++pm8001_ha->tags_num;
 402         }
 403         pm8001_ha->flags = PM8001F_INIT_TIME;
 404         /* Initialize tags */
 405         pm8001_tag_init(pm8001_ha);
 406         return 0;
 407 err_out:
 408         return 1;
 409 }
 410
 411 /**
 412  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 413  * address so that we can access them.
 414  * @pm8001_ha:our hba structure.
 415  */
 416 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 417 {
 418         u32 bar;
 419         u32 logicalBar = 0;
 420         struct pci_dev *pdev;
 421
 422         pdev = pm8001_ha->pdev;
 423         /* map pci mem (PMC pci base 0-3)*/
 424         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 425                 /*
 426                 ** logical BARs for SPC:
 427                 ** bar 0 and 1 - logical BAR0
 428                 ** bar 2 and 3 - logical BAR1
 429                 ** bar4 - logical BAR2
 430                 ** bar5 - logical BAR3
 431                 ** Skip the appropriate assignments:
 432                 */
 433                 if ((bar == 1) || (bar == 3))
 434                         continue;
 435                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 436                         pm8001_ha->io_mem[logicalBar].membase =
 437                                 pci_resource_start(pdev, bar);
 438                         pm8001_ha->io_mem[logicalBar].memsize =
 439                                 pci_resource_len(pdev, bar);
 440                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 441                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 442                                 pm8001_ha->io_mem[logicalBar].memsize);
 443                         PM8001_INIT_DBG(pm8001_ha,
 444                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 445                                 bar, logicalBar));
 446                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 447                                 "base addr %llx virt_addr=%llx len=%d\n",
 448                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 449                                 (u64)(unsigned long)
 450                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 451                                 pm8001_ha->io_mem[logicalBar].memsize));
 452                 } else {
 453                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 454                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 455                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 456                 }
 457                 logicalBar++;
 458         }
 459         return 0;
 460 }
 461
 462 /**
 463  * pm8001_pci_alloc - initialize our ha card structure
 464  * @pdev: pci device.
 465  * @ent: ent
 466  * @shost: scsi host struct which has been initialized before.
 467  */
 468 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 469                                  const struct pci_device_id *ent,
 470                                 struct Scsi_Host *shost)
 471
 472 {
 473         struct pm8001_hba_info *pm8001_ha;
 474         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 475         int j;
 476
 477         pm8001_ha = sha->lldd_ha;
 478         if (!pm8001_ha)
 479                 return NULL;
 480
 481         pm8001_ha->pdev = pdev;
 482         pm8001_ha->dev = &pdev->dev;
 483         pm8001_ha->chip_id = ent->driver_data;
 484         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 485         pm8001_ha->irq = pdev->irq;
 486         pm8001_ha->sas = sha;
 487         pm8001_ha->shost = shost;
 488         pm8001_ha->id = pm8001_id++;
 489         pm8001_ha->logging_level = logging_level;
 490         pm8001_ha->non_fatal_count = 0;
 491         if (link_rate >= 1 && link_rate <= 15)
 492                 pm8001_ha->link_rate = (link_rate << 8);
 493         else {
 494                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 495                         LINKRATE_60 | LINKRATE_120;
 496                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
 497                         "Setting link rate to default value\n"));
 498         }
 499         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 500         /* IOMB size is 128 for 8088/89 controllers */
 501         if (pm8001_ha->chip_id != chip_8001)
 502                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 503         else
 504                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 505
 506 #ifdef PM8001_USE_TASKLET
 507         /* Tasklet for non msi-x interrupt handler */
 508         if ((!pdev->msix_cap || !pci_msi_enabled())
 509             || (pm8001_ha->chip_id == chip_8001))
 510                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 511                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 512         else
 513                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 514                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 515                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 516 #endif
 517         pm8001_ioremap(pm8001_ha);
 518         if (!pm8001_alloc(pm8001_ha, ent))
 519                 return pm8001_ha;
 520         pm8001_free(pm8001_ha);
 521         return NULL;
 522 }
 523
 524 /**
 525  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 526  * @pdev: pci device.
 527  */
 528 static int pci_go_44(struct pci_dev *pdev)
 529 {
 530         int rc;
 531
 532         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 533         if (rc) {
 534                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 535                 if (rc)
 536                         dev_printk(KERN_ERR, &pdev->dev,
 537                                 "32-bit DMA enable failed\n");
 538         }
 539         return rc;
 540 }
 541
 542 /**
 543  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 544  * @shost: scsi host which has been allocated outside.
 545  * @chip_info: our ha struct.
 546  */
 547 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 548                                    const struct pm8001_chip_info *chip_info)
 549 {
 550         int phy_nr, port_nr;
 551         struct asd_sas_phy **arr_phy;
 552         struct asd_sas_port **arr_port;
 553         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 554
 555         phy_nr = chip_info->n_phy;
 556         port_nr = phy_nr;
 557         memset(sha, 0x00, sizeof(*sha));
 558         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 559         if (!arr_phy)
 560                 goto exit;
 561         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 562         if (!arr_port)
 563                 goto exit_free2;
 564
 565         sha->sas_phy = arr_phy;
 566         sha->sas_port = arr_port;
 567         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 568         if (!sha->lldd_ha)
 569                 goto exit_free1;
 570
 571         shost->transportt = pm8001_stt;
 572         shost->max_id = PM8001_MAX_DEVICES;
 573         shost->max_lun = 8;
 574         shost->max_channel = 0;
 575         shost->unique_id = pm8001_id;
 576         shost->max_cmd_len = 16;
 577         shost->can_queue = PM8001_CAN_QUEUE;
 578         shost->cmd_per_lun = 32;
 579         return 0;
 580 exit_free1:
 581         kfree(arr_port);
 582 exit_free2:
 583         kfree(arr_phy);
 584 exit:
 585         return -1;
 586 }
 587
 588 /**
 589  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 590  * @shost: scsi host which has been allocated outside
 591  * @chip_info: our ha struct.
 592  */
 593 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 594                                      const struct pm8001_chip_info *chip_info)
 595 {
 596         int i = 0;
 597         struct pm8001_hba_info *pm8001_ha;
 598         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 599
 600         pm8001_ha = sha->lldd_ha;
 601         for (i = 0; i < chip_info->n_phy; i++) {
 602                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 603                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 604                 sha->sas_phy[i]->sas_addr =
 605                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 606         }
 607         sha->sas_ha_name = DRV_NAME;
 608         sha->dev = pm8001_ha->dev;
 609         sha->strict_wide_ports = 1;
 610         sha->lldd_module = THIS_MODULE;
 611         sha->sas_addr = &pm8001_ha->sas_addr[0];
 612         sha->num_phys = chip_info->n_phy;
 613         sha->core.shost = shost;
 614 }
 615
 616 /**
 617  * pm8001_init_sas_add - initialize sas address
 618  * @chip_info: our ha struct.
 619  *
 620  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 621  * it should read from the EEPROM
 622  */
 623 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 624 {
 625         u8 i, j;
 626         u8 sas_add[8];
 627 #ifdef PM8001_READ_VPD
 628         /* For new SPC controllers WWN is stored in flash vpd
 629         *  For SPC/SPCve controllers WWN is stored in EEPROM
 630         *  For Older SPC WWN is stored in NVMD
 631         */
 632         DECLARE_COMPLETION_ONSTACK(completion);
 633         struct pm8001_ioctl_payload payload;
 634         u16 deviceid;
 635         int rc;
 636
 637         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 638         pm8001_ha->nvmd_completion = &completion;
 639
 640         if (pm8001_ha->chip_id == chip_8001) {
 641                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 642                         payload.minor_function = 4;
 643                         payload.rd_length = 4096;
 644                 } else {
 645                         payload.minor_function = 0;
 646                         payload.rd_length = 128;
 647                 }
 648         } else if ((pm8001_ha->chip_id == chip_8070 ||
 649                         pm8001_ha->chip_id == chip_8072) &&
 650                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 651                 payload.minor_function = 4;
 652                 payload.rd_length = 4096;
 653         } else {
 654                 payload.minor_function = 1;
 655                 payload.rd_length = 4096;
 656         }
 657         payload.offset = 0;
 658         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 659         if (!payload.func_specific) {
 660                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
 661                 return;
 662         }
 663         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 664         if (rc) {
 665                 kfree(payload.func_specific);
 666                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 667                 return;
 668         }
 669         wait_for_completion(&completion);
 670
 671         for (i = 0, j = 0; i <= 7; i++, j++) {
 672                 if (pm8001_ha->chip_id == chip_8001) {
 673                         if (deviceid == 0x8081)
 674                                 pm8001_ha->sas_addr[j] =
 675                                         payload.func_specific[0x704 + i];
 676                         else if (deviceid == 0x0042)
 677                                 pm8001_ha->sas_addr[j] =
 678                                         payload.func_specific[0x010 + i];
 679                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 680                                 pm8001_ha->chip_id == chip_8072) &&
 681                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 682                         pm8001_ha->sas_addr[j] =
 683                                         payload.func_specific[0x010 + i];
 684                 } else
 685                         pm8001_ha->sas_addr[j] =
 686                                         payload.func_specific[0x804 + i];
 687         }
 688         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 689         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 690                 if (i && ((i % 4) == 0))
 691                         sas_add[7] = sas_add[7] + 4;
 692                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 693                         sas_add, SAS_ADDR_SIZE);
 694                 PM8001_INIT_DBG(pm8001_ha,
 695                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 696                         pm8001_ha->phy[i].dev_sas_addr));
 697         }
 698         kfree(payload.func_specific);
 699 #else
 700         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 701                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 702                 pm8001_ha->phy[i].dev_sas_addr =
 703                         cpu_to_be64((u64)
 704                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 705         }
 706         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 707                 SAS_ADDR_SIZE);
 708 #endif
 709 }
 710
 711 /*
 712  * pm8001_get_phy_settings_info : Read phy setting values.
 713  * @pm8001_ha : our hba.
 714  */
 715 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 716 {
 717
 718 #ifdef PM8001_READ_VPD
 719         /*OPTION ROM FLASH read for the SPC cards */
 720         DECLARE_COMPLETION_ONSTACK(completion);
 721         struct pm8001_ioctl_payload payload;
 722         int rc;
 723
 724         pm8001_ha->nvmd_completion = &completion;
 725         /* SAS ADDRESS read from flash / EEPROM */
 726         payload.minor_function = 6;
 727         payload.offset = 0;
 728         payload.rd_length = 4096;
 729         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 730         if (!payload.func_specific)
 731                 return -ENOMEM;
 732         /* Read phy setting values from flash */
 733         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 734         if (rc) {
 735                 kfree(payload.func_specific);
 736                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 737                 return -ENOMEM;
 738         }
 739         wait_for_completion(&completion);
 740         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 741         kfree(payload.func_specific);
 742 #endif
 743         return 0;
 744 }
 745
 746 struct pm8001_mpi3_phy_pg_trx_config {
 747         u32 LaneLosCfg;
 748         u32 LanePgaCfg1;
 749         u32 LanePisoCfg1;
 750         u32 LanePisoCfg2;
 751         u32 LanePisoCfg3;
 752         u32 LanePisoCfg4;
 753         u32 LanePisoCfg5;
 754         u32 LanePisoCfg6;
 755         u32 LaneBctCtrl;
 756 };
 757
 758 /**
 759  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
 760  * @pm8001_ha : our adapter
 761  * @phycfg : PHY config page to populate
 762  */
 763 static
 764 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 765                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 766 {
 767         phycfg->LaneLosCfg   = 0x00000132;
 768         phycfg->LanePgaCfg1  = 0x00203949;
 769         phycfg->LanePisoCfg1 = 0x000000FF;
 770         phycfg->LanePisoCfg2 = 0xFF000001;
 771         phycfg->LanePisoCfg3 = 0xE7011300;
 772         phycfg->LanePisoCfg4 = 0x631C40C0;
 773         phycfg->LanePisoCfg5 = 0xF8102036;
 774         phycfg->LanePisoCfg6 = 0xF74A1000;
 775         phycfg->LaneBctCtrl  = 0x00FB33F8;
 776 }
 777
 778 /**
 779  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
 780  * @pm8001_ha : our adapter
 781  * @phycfg : PHY config page to populate
 782  */
 783 static
 784 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 785                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 786 {
 787         phycfg->LaneLosCfg   = 0x00000132;
 788         phycfg->LanePgaCfg1  = 0x00203949;
 789         phycfg->LanePisoCfg1 = 0x000000FF;
 790         phycfg->LanePisoCfg2 = 0xFF000001;
 791         phycfg->LanePisoCfg3 = 0xE7011300;
 792         phycfg->LanePisoCfg4 = 0x63349140;
 793         phycfg->LanePisoCfg5 = 0xF8102036;
 794         phycfg->LanePisoCfg6 = 0xF80D9300;
 795         phycfg->LaneBctCtrl  = 0x00FB33F8;
 796 }
 797
 798 /**
 799  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
 800  * @pm8001_ha : our adapter
 801  * @phymask : The PHY mask
 802  */
 803 static
 804 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 805 {
 806         switch (pm8001_ha->pdev->subsystem_device) {
 807         case 0x0070: /* H1280 - 8 external 0 internal */
 808         case 0x0072: /* H12F0 - 16 external 0 internal */
 809                 *phymask = 0x0000;
 810                 break;
 811
 812         case 0x0071: /* H1208 - 0 external 8 internal */
 813         case 0x0073: /* H120F - 0 external 16 internal */
 814                 *phymask = 0xFFFF;
 815                 break;
 816
 817         case 0x0080: /* H1244 - 4 external 4 internal */
 818                 *phymask = 0x00F0;
 819                 break;
 820
 821         case 0x0081: /* H1248 - 4 external 8 internal */
 822                 *phymask = 0x0FF0;
 823                 break;
 824
 825         case 0x0082: /* H1288 - 8 external 8 internal */
 826                 *phymask = 0xFF00;
 827                 break;
 828
 829         default:
 830                 PM8001_INIT_DBG(pm8001_ha,
 831                         pm8001_printk("Unknown subsystem device=0x%.04x",
 832                                 pm8001_ha->pdev->subsystem_device));
 833         }
 834 }
 835
 836 /**
 837  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
 838  * @pm8001_ha : our adapter
 839  */
 840 static
 841 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 842 {
 843         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 844         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 845         int phymask = 0;
 846         int i = 0;
 847
 848         memset(&phycfg_int, 0, sizeof(phycfg_int));
 849         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 850
 851         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 852         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 853         pm8001_get_phy_mask(pm8001_ha, &phymask);
 854
 855         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 856                 if (phymask & (1 << i)) {/* Internal PHY */
 857                         pm8001_set_phy_profile_single(pm8001_ha, i,
 858                                         sizeof(phycfg_int) / sizeof(u32),
 859                                         (u32 *)&phycfg_int);
 860
 861                 } else { /* External PHY */
 862                         pm8001_set_phy_profile_single(pm8001_ha, i,
 863                                         sizeof(phycfg_ext) / sizeof(u32),
 864                                         (u32 *)&phycfg_ext);
 865                 }
 866         }
 867
 868         return 0;
 869 }
 870
 871 /**
 872  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 873  * @pm8001_ha : our hba.
 874  */
 875 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 876 {
 877         switch (pm8001_ha->pdev->subsystem_vendor) {
 878         case PCI_VENDOR_ID_ATTO:
 879                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 880                         return 0;
 881                 else
 882                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 883
 884         case PCI_VENDOR_ID_ADAPTEC2:
 885         case 0:
 886                 return 0;
 887
 888         default:
 889                 return pm8001_get_phy_settings_info(pm8001_ha);
 890         }
 891 }
 892
 893 #ifdef PM8001_USE_MSIX
 894 /**
 895  * pm8001_setup_msix - enable MSI-X interrupt
 896  * @chip_info: our ha struct.
 897  * @irq_handler: irq_handler
 898  */
 899 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 900 {
 901         u32 number_of_intr;
 902         int rc;
 903
 904         /* SPCv controllers supports 64 msi-x */
 905         if (pm8001_ha->chip_id == chip_8001) {
 906                 number_of_intr = 1;
 907         } else {
 908                 number_of_intr = PM8001_MAX_MSIX_VEC;
 909         }
 910
 911         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
 912                         number_of_intr, PCI_IRQ_MSIX);
 913         number_of_intr = rc;
 914         if (rc < 0)
 915                 return rc;
 916         pm8001_ha->number_of_intr = number_of_intr;
 917
 918         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 919                 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 920                                 rc, pm8001_ha->number_of_intr));
 921         return 0;
 922 }
 923
 924 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 925 {
 926         u32 i = 0, j = 0;
 927         int flag = 0, rc = 0;
 928
 929         if (pm8001_ha->chip_id != chip_8001)
 930                 flag &= ~IRQF_SHARED;
 931
 932         PM8001_INIT_DBG(pm8001_ha,
 933                 pm8001_printk("pci_enable_msix request number of intr %d\n",
 934                 pm8001_ha->number_of_intr));
 935
 936         for (i = 0; i < pm8001_ha->number_of_intr; i++) {
 937                 snprintf(pm8001_ha->intr_drvname[i],
 938                         sizeof(pm8001_ha->intr_drvname[0]),
 939                         "%s-%d", pm8001_ha->name, i);
 940                 pm8001_ha->irq_vector[i].irq_id = i;
 941                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 942
 943                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
 944                         pm8001_interrupt_handler_msix, flag,
 945                         pm8001_ha->intr_drvname[i],
 946                         &(pm8001_ha->irq_vector[i]));
 947                 if (rc) {
 948                         for (j = 0; j < i; j++) {
 949                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
 950                                         &(pm8001_ha->irq_vector[i]));
 951                         }
 952                         pci_free_irq_vectors(pm8001_ha->pdev);
 953                         break;
 954                 }
 955         }
 956
 957         return rc;
 958 }
 959 #endif
 960
 961 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
 962 {
 963         struct pci_dev *pdev;
 964
 965         pdev = pm8001_ha->pdev;
 966
 967 #ifdef PM8001_USE_MSIX
 968         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
 969                 return pm8001_setup_msix(pm8001_ha);
 970         PM8001_INIT_DBG(pm8001_ha,
 971                 pm8001_printk("MSIX not supported!!!\n"));
 972 #endif
 973         return 0;
 974 }
 975
 976 /**
 977  * pm8001_request_irq - register interrupt
 978  * @chip_info: our ha struct.
 979  */
 980 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 981 {
 982         struct pci_dev *pdev;
 983         int rc;
 984
 985         pdev = pm8001_ha->pdev;
 986
 987 #ifdef PM8001_USE_MSIX
 988         if (pdev->msix_cap && pci_msi_enabled())
 989                 return pm8001_request_msix(pm8001_ha);
 990         else {
 991                 PM8001_INIT_DBG(pm8001_ha,
 992                         pm8001_printk("MSIX not supported!!!\n"));
 993                 goto intx;
 994         }
 995 #endif
 996
 997 intx:
 998         /* initialize the INT-X interrupt */
 999         pm8001_ha->irq_vector[0].irq_id = 0;
1000         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1001         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1002                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1003         return rc;
1004 }
1005
1006 /**
1007  * pm8001_pci_probe - probe supported device
1008  * @pdev: pci device which kernel has been prepared for.
1009  * @ent: pci device id
1010  *
1011  * This function is the main initialization function, when register a new
1012  * pci driver it is invoked, all struct an hardware initilization should be done
1013  * here, also, register interrupt
1014  */
1015 static int pm8001_pci_probe(struct pci_dev *pdev,
1016                             const struct pci_device_id *ent)
1017 {
1018         unsigned int rc;
1019         u32     pci_reg;
1020         u8      i = 0;
1021         struct pm8001_hba_info *pm8001_ha;
1022         struct Scsi_Host *shost = NULL;
1023         const struct pm8001_chip_info *chip;
1024         struct sas_ha_struct *sha;
1025
1026         dev_printk(KERN_INFO, &pdev->dev,
1027                 "pm80xx: driver version %s\n", DRV_VERSION);
1028         rc = pci_enable_device(pdev);
1029         if (rc)
1030                 goto err_out_enable;
1031         pci_set_master(pdev);
1032         /*
1033          * Enable pci slot busmaster by setting pci command register.
1034          * This is required by FW for Cyclone card.
1035          */
1036
1037         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1038         pci_reg |= 0x157;
1039         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1040         rc = pci_request_regions(pdev, DRV_NAME);
1041         if (rc)
1042                 goto err_out_disable;
1043         rc = pci_go_44(pdev);
1044         if (rc)
1045                 goto err_out_regions;
1046
1047         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1048         if (!shost) {
1049                 rc = -ENOMEM;
1050                 goto err_out_regions;
1051         }
1052         chip = &pm8001_chips[ent->driver_data];
1053         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1054         if (!sha) {
1055                 rc = -ENOMEM;
1056                 goto err_out_free_host;
1057         }
1058         SHOST_TO_SAS_HA(shost) = sha;
1059
1060         rc = pm8001_prep_sas_ha_init(shost, chip);
1061         if (rc) {
1062                 rc = -ENOMEM;
1063                 goto err_out_free;
1064         }
1065         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1066         /* ent->driver variable is used to differentiate between controllers */
1067         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1068         if (!pm8001_ha) {
1069                 rc = -ENOMEM;
1070                 goto err_out_free;
1071         }
1072         /* Setup Interrupt */
1073         rc = pm8001_setup_irq(pm8001_ha);
1074         if (rc) {
1075                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1076                         "pm8001_setup_irq failed [ret: %d]\n", rc));
1077                 goto err_out_shost;
1078         }
1079
1080         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1081         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1082         if (rc) {
1083                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1084                         "chip_init failed [ret: %d]\n", rc));
1085                 goto err_out_ha_free;
1086         }
1087
1088         rc = scsi_add_host(shost, &pdev->dev);
1089         if (rc)
1090                 goto err_out_ha_free;
1091         /* Request Interrupt */
1092         rc = pm8001_request_irq(pm8001_ha);
1093         if (rc) {
1094                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1095                         "pm8001_request_irq failed [ret: %d]\n", rc));
1096                 goto err_out_shost;
1097         }
1098
1099         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1100         if (pm8001_ha->chip_id != chip_8001) {
1101                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1102                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1103                 /* setup thermal configuration. */
1104                 pm80xx_set_thermal_config(pm8001_ha);
1105         }
1106
1107         pm8001_init_sas_add(pm8001_ha);
1108         /* phy setting support for motherboard controller */
1109         if (pm8001_configure_phy_settings(pm8001_ha))
1110                 goto err_out_shost;
1111
1112         pm8001_post_sas_ha_init(shost, chip);
1113         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1114         if (rc) {
1115                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1116                         "sas_register_ha failed [ret: %d]\n", rc));
1117                 goto err_out_shost;
1118         }
1119         list_add_tail(&pm8001_ha->list, &hba_list);
1120         scsi_scan_host(pm8001_ha->shost);
1121         pm8001_ha->flags = PM8001F_RUN_TIME;
1122         return 0;
1123
1124 err_out_shost:
1125         scsi_remove_host(pm8001_ha->shost);
1126 err_out_ha_free:
1127         pm8001_free(pm8001_ha);
1128 err_out_free:
1129         kfree(sha);
1130 err_out_free_host:
1131         scsi_host_put(shost);
1132 err_out_regions:
1133         pci_release_regions(pdev);
1134 err_out_disable:
1135         pci_disable_device(pdev);
1136 err_out_enable:
1137         return rc;
1138 }
1139
1140 static void pm8001_pci_remove(struct pci_dev *pdev)
1141 {
1142         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1143         struct pm8001_hba_info *pm8001_ha;
1144         int i, j;
1145         pm8001_ha = sha->lldd_ha;
1146         sas_unregister_ha(sha);
1147         sas_remove_host(pm8001_ha->shost);
1148         list_del(&pm8001_ha->list);
1149         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1150         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1151
1152 #ifdef PM8001_USE_MSIX
1153         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1154                 synchronize_irq(pci_irq_vector(pdev, i));
1155         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1156                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1157         pci_free_irq_vectors(pdev);
1158 #else
1159         free_irq(pm8001_ha->irq, sha);
1160 #endif
1161 #ifdef PM8001_USE_TASKLET
1162         /* For non-msix and msix interrupts */
1163         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1164             (pm8001_ha->chip_id == chip_8001))
1165                 tasklet_kill(&pm8001_ha->tasklet[0]);
1166         else
1167                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1168                         tasklet_kill(&pm8001_ha->tasklet[j]);
1169 #endif
1170         scsi_host_put(pm8001_ha->shost);
1171         pm8001_free(pm8001_ha);
1172         kfree(sha->sas_phy);
1173         kfree(sha->sas_port);
1174         kfree(sha);
1175         pci_release_regions(pdev);
1176         pci_disable_device(pdev);
1177 }
1178
1179 /**
1180  * pm8001_pci_suspend - power management suspend main entry point
1181  * @pdev: PCI device struct
1182  * @state: PM state change to (usually PCI_D3)
1183  *
1184  * Returns 0 success, anything else error.
1185  */
1186 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1187 {
1188         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1189         struct pm8001_hba_info *pm8001_ha;
1190         int  i, j;
1191         u32 device_state;
1192         pm8001_ha = sha->lldd_ha;
1193         sas_suspend_ha(sha);
1194         flush_workqueue(pm8001_wq);
1195         scsi_block_requests(pm8001_ha->shost);
1196         if (!pdev->pm_cap) {
1197                 dev_err(&pdev->dev, " PCI PM not supported\n");
1198                 return -ENODEV;
1199         }
1200         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1201         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1202 #ifdef PM8001_USE_MSIX
1203         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1204                 synchronize_irq(pci_irq_vector(pdev, i));
1205         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1206                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1207         pci_free_irq_vectors(pdev);
1208 #else
1209         free_irq(pm8001_ha->irq, sha);
1210 #endif
1211 #ifdef PM8001_USE_TASKLET
1212         /* For non-msix and msix interrupts */
1213         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1214             (pm8001_ha->chip_id == chip_8001))
1215                 tasklet_kill(&pm8001_ha->tasklet[0]);
1216         else
1217                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1218                         tasklet_kill(&pm8001_ha->tasklet[j]);
1219 #endif
1220         device_state = pci_choose_state(pdev, state);
1221         pm8001_printk("pdev=0x%p, slot=%s, entering "
1222                       "operating state [D%d]\n", pdev,
1223                       pm8001_ha->name, device_state);
1224         pci_save_state(pdev);
1225         pci_disable_device(pdev);
1226         pci_set_power_state(pdev, device_state);
1227         return 0;
1228 }
1229
1230 /**
1231  * pm8001_pci_resume - power management resume main entry point
1232  * @pdev: PCI device struct
1233  *
1234  * Returns 0 success, anything else error.
1235  */
1236 static int pm8001_pci_resume(struct pci_dev *pdev)
1237 {
1238         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1239         struct pm8001_hba_info *pm8001_ha;
1240         int rc;
1241         u8 i = 0, j;
1242         u32 device_state;
1243         DECLARE_COMPLETION_ONSTACK(completion);
1244         pm8001_ha = sha->lldd_ha;
1245         device_state = pdev->current_state;
1246
1247         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1248                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1249
1250         pci_set_power_state(pdev, PCI_D0);
1251         pci_enable_wake(pdev, PCI_D0, 0);
1252         pci_restore_state(pdev);
1253         rc = pci_enable_device(pdev);
1254         if (rc) {
1255                 pm8001_printk("slot=%s Enable device failed during resume\n",
1256                               pm8001_ha->name);
1257                 goto err_out_enable;
1258         }
1259
1260         pci_set_master(pdev);
1261         rc = pci_go_44(pdev);
1262         if (rc)
1263                 goto err_out_disable;
1264         sas_prep_resume_ha(sha);
1265         /* chip soft rst only for spc */
1266         if (pm8001_ha->chip_id == chip_8001) {
1267                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1268                 PM8001_INIT_DBG(pm8001_ha,
1269                         pm8001_printk("chip soft reset successful\n"));
1270         }
1271         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1272         if (rc)
1273                 goto err_out_disable;
1274
1275         /* disable all the interrupt bits */
1276         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1277
1278         rc = pm8001_request_irq(pm8001_ha);
1279         if (rc)
1280                 goto err_out_disable;
1281 #ifdef PM8001_USE_TASKLET
1282         /*  Tasklet for non msi-x interrupt handler */
1283         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1284             (pm8001_ha->chip_id == chip_8001))
1285                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1286                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1287         else
1288                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1289                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1290                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1291 #endif
1292         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1293         if (pm8001_ha->chip_id != chip_8001) {
1294                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1295                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1296         }
1297
1298         /* Chip documentation for the 8070 and 8072 SPCv    */
1299         /* states that a 500ms minimum delay is required    */
1300         /* before issuing commands. Otherwise, the firmware */
1301         /* will enter an unrecoverable state.               */
1302
1303         if (pm8001_ha->chip_id == chip_8070 ||
1304                 pm8001_ha->chip_id == chip_8072) {
1305                 mdelay(500);
1306         }
1307
1308         /* Spin up the PHYs */
1309
1310         pm8001_ha->flags = PM8001F_RUN_TIME;
1311         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1312                 pm8001_ha->phy[i].enable_completion = &completion;
1313                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1314                 wait_for_completion(&completion);
1315         }
1316         sas_resume_ha(sha);
1317         return 0;
1318
1319 err_out_disable:
1320         scsi_remove_host(pm8001_ha->shost);
1321         pci_disable_device(pdev);
1322 err_out_enable:
1323         return rc;
1324 }
1325
1326 /* update of pci device, vendor id and driver data with
1327  * unique value for each of the controller
1328  */
1329 static struct pci_device_id pm8001_pci_table[] = {
1330         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1331         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1332         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1333         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1334         /* Support for SPC/SPCv/SPCve controllers */
1335         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1336         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1337         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1338         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1339         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1340         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1341         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1342         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1343         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1344         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1345         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1346         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1347         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1348         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1349         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1350         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1351                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1352         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1353                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1354         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1355                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1356         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1357                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1358         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1359                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1360         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1361                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1362         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1363                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1364         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1365                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1366         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1367                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1368         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1369                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1370         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1371                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1372         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1373                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1374         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1375                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1376         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1377                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1378         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1379                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1380         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1381                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1382         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1383                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1384         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1385                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1386         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1387                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1388         { PCI_VENDOR_ID_ATTO, 0x8070,
1389                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1390         { PCI_VENDOR_ID_ATTO, 0x8070,
1391                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1392         { PCI_VENDOR_ID_ATTO, 0x8072,
1393                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1394         { PCI_VENDOR_ID_ATTO, 0x8072,
1395                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1396         { PCI_VENDOR_ID_ATTO, 0x8070,
1397                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1398         { PCI_VENDOR_ID_ATTO, 0x8072,
1399                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1400         { PCI_VENDOR_ID_ATTO, 0x8072,
1401                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1402         {} /* terminate list */
1403 };
1404
1405 static struct pci_driver pm8001_pci_driver = {
1406         .name           = DRV_NAME,
1407         .id_table       = pm8001_pci_table,
1408         .probe          = pm8001_pci_probe,
1409         .remove         = pm8001_pci_remove,
1410         .suspend        = pm8001_pci_suspend,
1411         .resume         = pm8001_pci_resume,
1412 };
1413
1414 /**
1415  *      pm8001_init - initialize scsi transport template
1416  */
1417 static int __init pm8001_init(void)
1418 {
1419         int rc = -ENOMEM;
1420
1421         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1422         if (!pm8001_wq)
1423                 goto err;
1424
1425         pm8001_id = 0;
1426         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1427         if (!pm8001_stt)
1428                 goto err_wq;
1429         rc = pci_register_driver(&pm8001_pci_driver);
1430         if (rc)
1431                 goto err_tp;
1432         return 0;
1433
1434 err_tp:
1435         sas_release_transport(pm8001_stt);
1436 err_wq:
1437         destroy_workqueue(pm8001_wq);
1438 err:
1439         return rc;
1440 }
1441
1442 static void __exit pm8001_exit(void)
1443 {
1444         pci_unregister_driver(&pm8001_pci_driver);
1445         sas_release_transport(pm8001_stt);
1446         destroy_workqueue(pm8001_wq);
1447 }
1448
1449 module_init(pm8001_init);
1450 module_exit(pm8001_exit);
1451
1452 MODULE_AUTHOR("Jack Wang <[email protected]>");
1453 MODULE_AUTHOR("Anand Kumar Santhanam <[email protected]>");
1454 MODULE_AUTHOR("Sangeetha Gnanasekaran <[email protected]>");
1455 MODULE_AUTHOR("Nikith Ganigarakoppal <[email protected]>");
1456 MODULE_DESCRIPTION(
1457                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1458                 "SAS/SATA controller driver");
1459 MODULE_VERSION(DRV_VERSION);
1460 MODULE_LICENSE("GPL");
1461 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1462