drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "amdgpu_pm.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29
  30 #include "vcn/vcn_2_0_0_offset.h"
  31 #include "vcn/vcn_2_0_0_sh_mask.h"
  32 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  33
  34 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET                         0x1bfff
  35 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET                            0x4029
  36 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET                          0x402a
  37 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET                          0x402b
  38 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET          0x40ea
  39 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x40eb
  40 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET                          0x40cf
  41 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET                             0x40d1
  42 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET                 0x40e8
  43 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET                0x40e9
  44 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET                              0x4082
  45 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET          0x40ec
  46 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x40ed
  47 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET                     0x4085
  48 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET                          0x4084
  49 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET                               0x4089
  50 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET                                0x401f
  51
  52 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR                                0x18000
  53
  54 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  55 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
  56 static int jpeg_v2_0_set_powergating_state(void *handle,
  57                                 enum amd_powergating_state state);
  58
  59 /**
  60  * jpeg_v2_0_early_init - set function pointers
  61  *
  62  * @handle: amdgpu_device pointer
  63  *
  64  * Set ring and irq function pointers
  65  */
  66 static int jpeg_v2_0_early_init(void *handle)
  67 {
  68         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  69
  70         adev->jpeg.num_jpeg_inst = 1;
  71
  72         jpeg_v2_0_set_dec_ring_funcs(adev);
  73         jpeg_v2_0_set_irq_funcs(adev);
  74
  75         return 0;
  76 }
  77
  78 /**
  79  * jpeg_v2_0_sw_init - sw init for JPEG block
  80  *
  81  * @handle: amdgpu_device pointer
  82  *
  83  * Load firmware and sw initialization
  84  */
  85 static int jpeg_v2_0_sw_init(void *handle)
  86 {
  87         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  88         struct amdgpu_ring *ring;
  89         int r;
  90
  91         /* JPEG TRAP */
  92         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  93                 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
  94         if (r)
  95                 return r;
  96
  97         r = amdgpu_jpeg_sw_init(adev);
  98         if (r)
  99                 return r;
 100
 101         r = amdgpu_jpeg_resume(adev);
 102         if (r)
 103                 return r;
 104
 105         ring = &adev->jpeg.inst->ring_dec;
 106         ring->use_doorbell = true;
 107         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
 108         sprintf(ring->name, "jpeg_dec");
 109         r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
 110                              0, AMDGPU_RING_PRIO_DEFAULT);
 111         if (r)
 112                 return r;
 113
 114         adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
 115         adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
 116
 117         return 0;
 118 }
 119
 120 /**
 121  * jpeg_v2_0_sw_fini - sw fini for JPEG block
 122  *
 123  * @handle: amdgpu_device pointer
 124  *
 125  * JPEG suspend and free up sw allocation
 126  */
 127 static int jpeg_v2_0_sw_fini(void *handle)
 128 {
 129         int r;
 130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 131
 132         r = amdgpu_jpeg_suspend(adev);
 133         if (r)
 134                 return r;
 135
 136         r = amdgpu_jpeg_sw_fini(adev);
 137
 138         return r;
 139 }
 140
 141 /**
 142  * jpeg_v2_0_hw_init - start and test JPEG block
 143  *
 144  * @handle: amdgpu_device pointer
 145  *
 146  */
 147 static int jpeg_v2_0_hw_init(void *handle)
 148 {
 149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 150         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 151         int r;
 152
 153         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 154                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
 155
 156         r = amdgpu_ring_test_helper(ring);
 157         if (!r)
 158                 DRM_INFO("JPEG decode initialized successfully.\n");
 159
 160         return r;
 161 }
 162
 163 /**
 164  * jpeg_v2_0_hw_fini - stop the hardware block
 165  *
 166  * @handle: amdgpu_device pointer
 167  *
 168  * Stop the JPEG block, mark ring as not ready any more
 169  */
 170 static int jpeg_v2_0_hw_fini(void *handle)
 171 {
 172         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 173
 174         if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 175               RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
 176                 jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 177
 178         return 0;
 179 }
 180
 181 /**
 182  * jpeg_v2_0_suspend - suspend JPEG block
 183  *
 184  * @handle: amdgpu_device pointer
 185  *
 186  * HW fini and suspend JPEG block
 187  */
 188 static int jpeg_v2_0_suspend(void *handle)
 189 {
 190         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 191         int r;
 192
 193         r = jpeg_v2_0_hw_fini(adev);
 194         if (r)
 195                 return r;
 196
 197         r = amdgpu_jpeg_suspend(adev);
 198
 199         return r;
 200 }
 201
 202 /**
 203  * jpeg_v2_0_resume - resume JPEG block
 204  *
 205  * @handle: amdgpu_device pointer
 206  *
 207  * Resume firmware and hw init JPEG block
 208  */
 209 static int jpeg_v2_0_resume(void *handle)
 210 {
 211         int r;
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213
 214         r = amdgpu_jpeg_resume(adev);
 215         if (r)
 216                 return r;
 217
 218         r = jpeg_v2_0_hw_init(adev);
 219
 220         return r;
 221 }
 222
 223 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
 224 {
 225         uint32_t data;
 226         int r = 0;
 227
 228         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 229                 data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 230                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 231
 232                 SOC15_WAIT_ON_RREG(JPEG, 0,
 233                         mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
 234                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
 235
 236                 if (r) {
 237                         DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
 238                         return r;
 239                 }
 240         }
 241
 242         /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
 243         data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
 244         WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
 245
 246         return 0;
 247 }
 248
 249 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device* adev)
 250 {
 251         if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
 252                 uint32_t data;
 253                 int r = 0;
 254
 255                 data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
 256                 data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
 257                 data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
 258                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
 259
 260                 data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
 261                 WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
 262
 263                 SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
 264                         (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
 265                         UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK, r);
 266
 267                 if (r) {
 268                         DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
 269                         return r;
 270                 }
 271         }
 272
 273         return 0;
 274 }
 275
 276 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device* adev)
 277 {
 278         uint32_t data;
 279
 280         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 281         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 282                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 283         else
 284                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 285
 286         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 287         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 288         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 289
 290         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 291         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 292                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 293                 | JPEG_CGC_GATE__JPEG_ENC_MASK
 294                 | JPEG_CGC_GATE__JMCIF_MASK
 295                 | JPEG_CGC_GATE__JRBBM_MASK);
 296         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 297 }
 298
 299 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device* adev)
 300 {
 301         uint32_t data;
 302
 303         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
 304         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 305                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 306         else
 307                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 308
 309         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 310         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 311         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
 312
 313         data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
 314         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 315                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 316                 |JPEG_CGC_GATE__JPEG_ENC_MASK
 317                 |JPEG_CGC_GATE__JMCIF_MASK
 318                 |JPEG_CGC_GATE__JRBBM_MASK);
 319         WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
 320 }
 321
 322 /**
 323  * jpeg_v2_0_start - start JPEG block
 324  *
 325  * @adev: amdgpu_device pointer
 326  *
 327  * Setup and start the JPEG block
 328  */
 329 static int jpeg_v2_0_start(struct amdgpu_device *adev)
 330 {
 331         struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
 332         int r;
 333
 334         if (adev->pm.dpm_enabled)
 335                 amdgpu_dpm_enable_jpeg(adev, true);
 336
 337         /* disable power gating */
 338         r = jpeg_v2_0_disable_power_gating(adev);
 339         if (r)
 340                 return r;
 341
 342         /* JPEG disable CGC */
 343         jpeg_v2_0_disable_clock_gating(adev);
 344
 345         WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 346
 347         /* enable JMI channel */
 348         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
 349                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 350
 351         /* enable System Interrupt for JRBC */
 352         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
 353                 JPEG_SYS_INT_EN__DJRBC_MASK,
 354                 ~JPEG_SYS_INT_EN__DJRBC_MASK);
 355
 356         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
 357         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 358         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 359                 lower_32_bits(ring->gpu_addr));
 360         WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 361                 upper_32_bits(ring->gpu_addr));
 362         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
 363         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
 364         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 365         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 366         ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 367
 368         return 0;
 369 }
 370
 371 /**
 372  * jpeg_v2_0_stop - stop JPEG block
 373  *
 374  * @adev: amdgpu_device pointer
 375  *
 376  * stop the JPEG block
 377  */
 378 static int jpeg_v2_0_stop(struct amdgpu_device *adev)
 379 {
 380         int r;
 381
 382         /* reset JMI */
 383         WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
 384                 UVD_JMI_CNTL__SOFT_RESET_MASK,
 385                 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 386
 387         /* enable JPEG CGC */
 388         jpeg_v2_0_enable_clock_gating(adev);
 389
 390         /* enable power gating */
 391         r = jpeg_v2_0_enable_power_gating(adev);
 392         if (r)
 393                 return r;
 394
 395         if (adev->pm.dpm_enabled)
 396                 amdgpu_dpm_enable_jpeg(adev, false);
 397
 398         return 0;
 399 }
 400
 401 /**
 402  * jpeg_v2_0_dec_ring_get_rptr - get read pointer
 403  *
 404  * @ring: amdgpu_ring pointer
 405  *
 406  * Returns the current hardware read pointer
 407  */
 408 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
 409 {
 410         struct amdgpu_device *adev = ring->adev;
 411
 412         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
 413 }
 414
 415 /**
 416  * jpeg_v2_0_dec_ring_get_wptr - get write pointer
 417  *
 418  * @ring: amdgpu_ring pointer
 419  *
 420  * Returns the current hardware write pointer
 421  */
 422 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
 423 {
 424         struct amdgpu_device *adev = ring->adev;
 425
 426         if (ring->use_doorbell)
 427                 return adev->wb.wb[ring->wptr_offs];
 428         else
 429                 return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
 430 }
 431
 432 /**
 433  * jpeg_v2_0_dec_ring_set_wptr - set write pointer
 434  *
 435  * @ring: amdgpu_ring pointer
 436  *
 437  * Commits the write pointer to the hardware
 438  */
 439 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
 440 {
 441         struct amdgpu_device *adev = ring->adev;
 442
 443         if (ring->use_doorbell) {
 444                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 445                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 446         } else {
 447                 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 448         }
 449 }
 450
 451 /**
 452  * jpeg_v2_0_dec_ring_insert_start - insert a start command
 453  *
 454  * @ring: amdgpu_ring pointer
 455  *
 456  * Write a start command to the ring.
 457  */
 458 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
 459 {
 460         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 461                 0, 0, PACKETJ_TYPE0));
 462         amdgpu_ring_write(ring, 0x68e04);
 463
 464         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 465                 0, 0, PACKETJ_TYPE0));
 466         amdgpu_ring_write(ring, 0x80010000);
 467 }
 468
 469 /**
 470  * jpeg_v2_0_dec_ring_insert_end - insert a end command
 471  *
 472  * @ring: amdgpu_ring pointer
 473  *
 474  * Write a end command to the ring.
 475  */
 476 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
 477 {
 478         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 479                 0, 0, PACKETJ_TYPE0));
 480         amdgpu_ring_write(ring, 0x68e04);
 481
 482         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 483                 0, 0, PACKETJ_TYPE0));
 484         amdgpu_ring_write(ring, 0x00010000);
 485 }
 486
 487 /**
 488  * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
 489  *
 490  * @ring: amdgpu_ring pointer
 491  * @fence: fence to emit
 492  *
 493  * Write a fence and a trap command to the ring.
 494  */
 495 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 496                                 unsigned flags)
 497 {
 498         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 499
 500         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
 501                 0, 0, PACKETJ_TYPE0));
 502         amdgpu_ring_write(ring, seq);
 503
 504         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
 505                 0, 0, PACKETJ_TYPE0));
 506         amdgpu_ring_write(ring, seq);
 507
 508         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
 509                 0, 0, PACKETJ_TYPE0));
 510         amdgpu_ring_write(ring, lower_32_bits(addr));
 511
 512         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
 513                 0, 0, PACKETJ_TYPE0));
 514         amdgpu_ring_write(ring, upper_32_bits(addr));
 515
 516         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
 517                 0, 0, PACKETJ_TYPE0));
 518         amdgpu_ring_write(ring, 0x8);
 519
 520         amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
 521                 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
 522         amdgpu_ring_write(ring, 0);
 523
 524         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 525                 0, 0, PACKETJ_TYPE0));
 526         amdgpu_ring_write(ring, 0x3fbc);
 527
 528         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 529                 0, 0, PACKETJ_TYPE0));
 530         amdgpu_ring_write(ring, 0x1);
 531
 532         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
 533         amdgpu_ring_write(ring, 0);
 534 }
 535
 536 /**
 537  * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
 538  *
 539  * @ring: amdgpu_ring pointer
 540  * @ib: indirect buffer to execute
 541  *
 542  * Write ring commands to execute the indirect buffer.
 543  */
 544 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
 545                                 struct amdgpu_job *job,
 546                                 struct amdgpu_ib *ib,
 547                                 uint32_t flags)
 548 {
 549         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 550
 551         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
 552                 0, 0, PACKETJ_TYPE0));
 553         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
 554
 555         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
 556                 0, 0, PACKETJ_TYPE0));
 557         amdgpu_ring_write(ring, (vmid | (vmid << 4)));
 558
 559         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
 560                 0, 0, PACKETJ_TYPE0));
 561         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
 562
 563         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
 564                 0, 0, PACKETJ_TYPE0));
 565         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 566
 567         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
 568                 0, 0, PACKETJ_TYPE0));
 569         amdgpu_ring_write(ring, ib->length_dw);
 570
 571         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
 572                 0, 0, PACKETJ_TYPE0));
 573         amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
 574
 575         amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
 576                 0, 0, PACKETJ_TYPE0));
 577         amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
 578
 579         amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
 580         amdgpu_ring_write(ring, 0);
 581
 582         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
 583                 0, 0, PACKETJ_TYPE0));
 584         amdgpu_ring_write(ring, 0x01400200);
 585
 586         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
 587                 0, 0, PACKETJ_TYPE0));
 588         amdgpu_ring_write(ring, 0x2);
 589
 590         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
 591                 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
 592         amdgpu_ring_write(ring, 0x2);
 593 }
 594
 595 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
 596                                 uint32_t val, uint32_t mask)
 597 {
 598         uint32_t reg_offset = (reg << 2);
 599
 600         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
 601                 0, 0, PACKETJ_TYPE0));
 602         amdgpu_ring_write(ring, 0x01400200);
 603
 604         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
 605                 0, 0, PACKETJ_TYPE0));
 606         amdgpu_ring_write(ring, val);
 607
 608         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 609                 0, 0, PACKETJ_TYPE0));
 610         if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
 611                 amdgpu_ring_write(ring, 0);
 612                 amdgpu_ring_write(ring,
 613                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
 614         } else {
 615                 amdgpu_ring_write(ring, reg_offset);
 616                 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 617                         0, 0, PACKETJ_TYPE3));
 618         }
 619         amdgpu_ring_write(ring, mask);
 620 }
 621
 622 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
 623                                 unsigned vmid, uint64_t pd_addr)
 624 {
 625         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
 626         uint32_t data0, data1, mask;
 627
 628         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 629
 630         /* wait for register write */
 631         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
 632         data1 = lower_32_bits(pd_addr);
 633         mask = 0xffffffff;
 634         jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
 635 }
 636
 637 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
 638 {
 639         uint32_t reg_offset = (reg << 2);
 640
 641         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 642                 0, 0, PACKETJ_TYPE0));
 643         if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
 644                 amdgpu_ring_write(ring, 0);
 645                 amdgpu_ring_write(ring,
 646                         PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
 647         } else {
 648                 amdgpu_ring_write(ring, reg_offset);
 649                 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 650                         0, 0, PACKETJ_TYPE0));
 651         }
 652         amdgpu_ring_write(ring, val);
 653 }
 654
 655 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
 656 {
 657         int i;
 658
 659         WARN_ON(ring->wptr % 2 || count % 2);
 660
 661         for (i = 0; i < count / 2; i++) {
 662                 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
 663                 amdgpu_ring_write(ring, 0);
 664         }
 665 }
 666
 667 static bool jpeg_v2_0_is_idle(void *handle)
 668 {
 669         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 670
 671         return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
 672                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 673                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 674 }
 675
 676 static int jpeg_v2_0_wait_for_idle(void *handle)
 677 {
 678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 679         int ret = 0;
 680
 681         SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 682                 UVD_JRBC_STATUS__RB_JOB_DONE_MASK, ret);
 683
 684         return ret;
 685 }
 686
 687 static int jpeg_v2_0_set_clockgating_state(void *handle,
 688                                           enum amd_clockgating_state state)
 689 {
 690         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 691         bool enable = (state == AMD_CG_STATE_GATE);
 692
 693         if (enable) {
 694                 if (!jpeg_v2_0_is_idle(handle))
 695                         return -EBUSY;
 696                 jpeg_v2_0_enable_clock_gating(adev);
 697         } else {
 698                 jpeg_v2_0_disable_clock_gating(adev);
 699         }
 700
 701         return 0;
 702 }
 703
 704 static int jpeg_v2_0_set_powergating_state(void *handle,
 705                                         enum amd_powergating_state state)
 706 {
 707         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 708         int ret;
 709
 710         if (state == adev->jpeg.cur_state)
 711                 return 0;
 712
 713         if (state == AMD_PG_STATE_GATE)
 714                 ret = jpeg_v2_0_stop(adev);
 715         else
 716                 ret = jpeg_v2_0_start(adev);
 717
 718         if (!ret)
 719                 adev->jpeg.cur_state = state;
 720
 721         return ret;
 722 }
 723
 724 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
 725                                         struct amdgpu_irq_src *source,
 726                                         unsigned type,
 727                                         enum amdgpu_interrupt_state state)
 728 {
 729         return 0;
 730 }
 731
 732 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
 733                                       struct amdgpu_irq_src *source,
 734                                       struct amdgpu_iv_entry *entry)
 735 {
 736         DRM_DEBUG("IH: JPEG TRAP\n");
 737
 738         switch (entry->src_id) {
 739         case VCN_2_0__SRCID__JPEG_DECODE:
 740                 amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
 741                 break;
 742         default:
 743                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 744                           entry->src_id, entry->src_data[0]);
 745                 break;
 746         }
 747
 748         return 0;
 749 }
 750
 751 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
 752         .name = "jpeg_v2_0",
 753         .early_init = jpeg_v2_0_early_init,
 754         .late_init = NULL,
 755         .sw_init = jpeg_v2_0_sw_init,
 756         .sw_fini = jpeg_v2_0_sw_fini,
 757         .hw_init = jpeg_v2_0_hw_init,
 758         .hw_fini = jpeg_v2_0_hw_fini,
 759         .suspend = jpeg_v2_0_suspend,
 760         .resume = jpeg_v2_0_resume,
 761         .is_idle = jpeg_v2_0_is_idle,
 762         .wait_for_idle = jpeg_v2_0_wait_for_idle,
 763         .check_soft_reset = NULL,
 764         .pre_soft_reset = NULL,
 765         .soft_reset = NULL,
 766         .post_soft_reset = NULL,
 767         .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
 768         .set_powergating_state = jpeg_v2_0_set_powergating_state,
 769 };
 770
 771 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
 772         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 773         .align_mask = 0xf,
 774         .vmhub = AMDGPU_MMHUB_0,
 775         .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
 776         .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
 777         .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
 778         .emit_frame_size =
 779                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 780                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 781                 8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
 782                 18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
 783                 8 + 16,
 784         .emit_ib_size = 22, /* jpeg_v2_0_dec_ring_emit_ib */
 785         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 786         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 787         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 788         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 789         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 790         .insert_nop = jpeg_v2_0_dec_ring_nop,
 791         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 792         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 793         .pad_ib = amdgpu_ring_generic_pad_ib,
 794         .begin_use = amdgpu_jpeg_ring_begin_use,
 795         .end_use = amdgpu_jpeg_ring_end_use,
 796         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 797         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 798         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 799 };
 800
 801 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
 802 {
 803         adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs;
 804         DRM_INFO("JPEG decode is enabled in VM mode\n");
 805 }
 806
 807 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
 808         .set = jpeg_v2_0_set_interrupt_state,
 809         .process = jpeg_v2_0_process_interrupt,
 810 };
 811
 812 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
 813 {
 814         adev->jpeg.inst->irq.num_types = 1;
 815         adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
 816 }
 817
 818 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block =
 819 {
 820                 .type = AMD_IP_BLOCK_TYPE_JPEG,
 821                 .major = 2,
 822                 .minor = 0,
 823                 .rev = 0,
 824                 .funcs = &jpeg_v2_0_ip_funcs,
 825 };