drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  42         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  43         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  44         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  45         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  49         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  53         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  56         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  59         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  62         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  66         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  67         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  68         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  69         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
  70         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 const char * const amdgpu_pp_profile_name[] = {
  86         "BOOTUP_DEFAULT",
  87         "3D_FULL_SCREEN",
  88         "POWER_SAVING",
  89         "VIDEO",
  90         "VR",
  91         "COMPUTE",
  92         "CUSTOM",
  93         "WINDOW_3D",
  94         "CAPPED",
  95         "UNCAPPED",
  96 };
  97
  98 /**
  99  * DOC: power_dpm_state
 100  *
 101  * The power_dpm_state file is a legacy interface and is only provided for
 102  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 103  * certain power related parameters.  The file power_dpm_state is used for this.
 104  * It accepts the following arguments:
 105  *
 106  * - battery
 107  *
 108  * - balanced
 109  *
 110  * - performance
 111  *
 112  * battery
 113  *
 114  * On older GPUs, the vbios provided a special power state for battery
 115  * operation.  Selecting battery switched to this state.  This is no
 116  * longer provided on newer GPUs so the option does nothing in that case.
 117  *
 118  * balanced
 119  *
 120  * On older GPUs, the vbios provided a special power state for balanced
 121  * operation.  Selecting balanced switched to this state.  This is no
 122  * longer provided on newer GPUs so the option does nothing in that case.
 123  *
 124  * performance
 125  *
 126  * On older GPUs, the vbios provided a special power state for performance
 127  * operation.  Selecting performance switched to this state.  This is no
 128  * longer provided on newer GPUs so the option does nothing in that case.
 129  *
 130  */
 131
 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 133                                           struct device_attribute *attr,
 134                                           char *buf)
 135 {
 136         struct drm_device *ddev = dev_get_drvdata(dev);
 137         struct amdgpu_device *adev = drm_to_adev(ddev);
 138         enum amd_pm_state_type pm;
 139         int ret;
 140
 141         if (amdgpu_in_reset(adev))
 142                 return -EPERM;
 143         if (adev->in_suspend && !adev->in_runpm)
 144                 return -EPERM;
 145
 146         ret = pm_runtime_get_sync(ddev->dev);
 147         if (ret < 0) {
 148                 pm_runtime_put_autosuspend(ddev->dev);
 149                 return ret;
 150         }
 151
 152         amdgpu_dpm_get_current_power_state(adev, &pm);
 153
 154         pm_runtime_mark_last_busy(ddev->dev);
 155         pm_runtime_put_autosuspend(ddev->dev);
 156
 157         return sysfs_emit(buf, "%s\n",
 158                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160 }
 161
 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 163                                           struct device_attribute *attr,
 164                                           const char *buf,
 165                                           size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = drm_to_adev(ddev);
 169         enum amd_pm_state_type  state;
 170         int ret;
 171
 172         if (amdgpu_in_reset(adev))
 173                 return -EPERM;
 174         if (adev->in_suspend && !adev->in_runpm)
 175                 return -EPERM;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else
 184                 return -EINVAL;
 185
 186         ret = pm_runtime_get_sync(ddev->dev);
 187         if (ret < 0) {
 188                 pm_runtime_put_autosuspend(ddev->dev);
 189                 return ret;
 190         }
 191
 192         amdgpu_dpm_set_power_state(adev, state);
 193
 194         pm_runtime_mark_last_busy(ddev->dev);
 195         pm_runtime_put_autosuspend(ddev->dev);
 196
 197         return count;
 198 }
 199
 200
 201 /**
 202  * DOC: power_dpm_force_performance_level
 203  *
 204  * The amdgpu driver provides a sysfs API for adjusting certain power
 205  * related parameters.  The file power_dpm_force_performance_level is
 206  * used for this.  It accepts the following arguments:
 207  *
 208  * - auto
 209  *
 210  * - low
 211  *
 212  * - high
 213  *
 214  * - manual
 215  *
 216  * - profile_standard
 217  *
 218  * - profile_min_sclk
 219  *
 220  * - profile_min_mclk
 221  *
 222  * - profile_peak
 223  *
 224  * auto
 225  *
 226  * When auto is selected, the driver will attempt to dynamically select
 227  * the optimal power profile for current conditions in the driver.
 228  *
 229  * low
 230  *
 231  * When low is selected, the clocks are forced to the lowest power state.
 232  *
 233  * high
 234  *
 235  * When high is selected, the clocks are forced to the highest power state.
 236  *
 237  * manual
 238  *
 239  * When manual is selected, the user can manually adjust which power states
 240  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 241  * and pp_dpm_pcie files and adjust the power state transition heuristics
 242  * via the pp_power_profile_mode sysfs file.
 243  *
 244  * profile_standard
 245  * profile_min_sclk
 246  * profile_min_mclk
 247  * profile_peak
 248  *
 249  * When the profiling modes are selected, clock and power gating are
 250  * disabled and the clocks are set for different profiling cases. This
 251  * mode is recommended for profiling specific work loads where you do
 252  * not want clock or power gating for clock fluctuation to interfere
 253  * with your results. profile_standard sets the clocks to a fixed clock
 254  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 255  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 256  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 257  *
 258  */
 259
 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             char *buf)
 263 {
 264         struct drm_device *ddev = dev_get_drvdata(dev);
 265         struct amdgpu_device *adev = drm_to_adev(ddev);
 266         enum amd_dpm_forced_level level = 0xff;
 267         int ret;
 268
 269         if (amdgpu_in_reset(adev))
 270                 return -EPERM;
 271         if (adev->in_suspend && !adev->in_runpm)
 272                 return -EPERM;
 273
 274         ret = pm_runtime_get_sync(ddev->dev);
 275         if (ret < 0) {
 276                 pm_runtime_put_autosuspend(ddev->dev);
 277                 return ret;
 278         }
 279
 280         level = amdgpu_dpm_get_performance_level(adev);
 281
 282         pm_runtime_mark_last_busy(ddev->dev);
 283         pm_runtime_put_autosuspend(ddev->dev);
 284
 285         return sysfs_emit(buf, "%s\n",
 286                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 287                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 288                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 289                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 290                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 291                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 292                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 293                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 294                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 295                           "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 299                                                             struct device_attribute *attr,
 300                                                             const char *buf,
 301                                                             size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = drm_to_adev(ddev);
 305         enum amd_dpm_forced_level level;
 306         int ret = 0;
 307
 308         if (amdgpu_in_reset(adev))
 309                 return -EPERM;
 310         if (adev->in_suspend && !adev->in_runpm)
 311                 return -EPERM;
 312
 313         if (strncmp("low", buf, strlen("low")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_LOW;
 315         } else if (strncmp("high", buf, strlen("high")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 317         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 319         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 321         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 323         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 325         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 327         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 329         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 331         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 333         }  else {
 334                 return -EINVAL;
 335         }
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 344         if (amdgpu_dpm_force_performance_level(adev, level)) {
 345                 pm_runtime_mark_last_busy(ddev->dev);
 346                 pm_runtime_put_autosuspend(ddev->dev);
 347                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 348                 return -EINVAL;
 349         }
 350         /* override whatever a user ctx may have set */
 351         adev->pm.stable_pstate_ctx = NULL;
 352         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 353
 354         pm_runtime_mark_last_busy(ddev->dev);
 355         pm_runtime_put_autosuspend(ddev->dev);
 356
 357         return count;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data;
 367         uint32_t i;
 368         int buf_len, ret;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 382                 memset(&data, 0, sizeof(data));
 383
 384         pm_runtime_mark_last_busy(ddev->dev);
 385         pm_runtime_put_autosuspend(ddev->dev);
 386
 387         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 388         for (i = 0; i < data.nums; i++)
 389                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 390                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 391                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 392                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 393                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 394
 395         return buf_len;
 396 }
 397
 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 399                 struct device_attribute *attr,
 400                 char *buf)
 401 {
 402         struct drm_device *ddev = dev_get_drvdata(dev);
 403         struct amdgpu_device *adev = drm_to_adev(ddev);
 404         struct pp_states_info data = {0};
 405         enum amd_pm_state_type pm = 0;
 406         int i = 0, ret = 0;
 407
 408         if (amdgpu_in_reset(adev))
 409                 return -EPERM;
 410         if (adev->in_suspend && !adev->in_runpm)
 411                 return -EPERM;
 412
 413         ret = pm_runtime_get_sync(ddev->dev);
 414         if (ret < 0) {
 415                 pm_runtime_put_autosuspend(ddev->dev);
 416                 return ret;
 417         }
 418
 419         amdgpu_dpm_get_current_power_state(adev, &pm);
 420
 421         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 422
 423         pm_runtime_mark_last_busy(ddev->dev);
 424         pm_runtime_put_autosuspend(ddev->dev);
 425
 426         if (ret)
 427                 return ret;
 428
 429         for (i = 0; i < data.nums; i++) {
 430                 if (pm == data.states[i])
 431                         break;
 432         }
 433
 434         if (i == data.nums)
 435                 i = -EINVAL;
 436
 437         return sysfs_emit(buf, "%d\n", i);
 438 }
 439
 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 441                 struct device_attribute *attr,
 442                 char *buf)
 443 {
 444         struct drm_device *ddev = dev_get_drvdata(dev);
 445         struct amdgpu_device *adev = drm_to_adev(ddev);
 446
 447         if (amdgpu_in_reset(adev))
 448                 return -EPERM;
 449         if (adev->in_suspend && !adev->in_runpm)
 450                 return -EPERM;
 451
 452         if (adev->pm.pp_force_state_enabled)
 453                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 454         else
 455                 return sysfs_emit(buf, "\n");
 456 }
 457
 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = drm_to_adev(ddev);
 465         enum amd_pm_state_type state = 0;
 466         struct pp_states_info data;
 467         unsigned long idx;
 468         int ret;
 469
 470         if (amdgpu_in_reset(adev))
 471                 return -EPERM;
 472         if (adev->in_suspend && !adev->in_runpm)
 473                 return -EPERM;
 474
 475         adev->pm.pp_force_state_enabled = false;
 476
 477         if (strlen(buf) == 1)
 478                 return count;
 479
 480         ret = kstrtoul(buf, 0, &idx);
 481         if (ret || idx >= ARRAY_SIZE(data.states))
 482                 return -EINVAL;
 483
 484         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 485
 486         ret = pm_runtime_get_sync(ddev->dev);
 487         if (ret < 0) {
 488                 pm_runtime_put_autosuspend(ddev->dev);
 489                 return ret;
 490         }
 491
 492         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 493         if (ret)
 494                 goto err_out;
 495
 496         state = data.states[idx];
 497
 498         /* only set user selected power states */
 499         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 500             state != POWER_STATE_TYPE_DEFAULT) {
 501                 ret = amdgpu_dpm_dispatch_task(adev,
 502                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 503                 if (ret)
 504                         goto err_out;
 505
 506                 adev->pm.pp_force_state_enabled = true;
 507         }
 508
 509         pm_runtime_mark_last_busy(ddev->dev);
 510         pm_runtime_put_autosuspend(ddev->dev);
 511
 512         return count;
 513
 514 err_out:
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517         return ret;
 518 }
 519
 520 /**
 521  * DOC: pp_table
 522  *
 523  * The amdgpu driver provides a sysfs API for uploading new powerplay
 524  * tables.  The file pp_table is used for this.  Reading the file
 525  * will dump the current power play table.  Writing to the file
 526  * will attempt to upload a new powerplay table and re-initialize
 527  * powerplay using that new table.
 528  *
 529  */
 530
 531 static ssize_t amdgpu_get_pp_table(struct device *dev,
 532                 struct device_attribute *attr,
 533                 char *buf)
 534 {
 535         struct drm_device *ddev = dev_get_drvdata(dev);
 536         struct amdgpu_device *adev = drm_to_adev(ddev);
 537         char *table = NULL;
 538         int size, ret;
 539
 540         if (amdgpu_in_reset(adev))
 541                 return -EPERM;
 542         if (adev->in_suspend && !adev->in_runpm)
 543                 return -EPERM;
 544
 545         ret = pm_runtime_get_sync(ddev->dev);
 546         if (ret < 0) {
 547                 pm_runtime_put_autosuspend(ddev->dev);
 548                 return ret;
 549         }
 550
 551         size = amdgpu_dpm_get_pp_table(adev, &table);
 552
 553         pm_runtime_mark_last_busy(ddev->dev);
 554         pm_runtime_put_autosuspend(ddev->dev);
 555
 556         if (size <= 0)
 557                 return size;
 558
 559         if (size >= PAGE_SIZE)
 560                 size = PAGE_SIZE - 1;
 561
 562         memcpy(buf, table, size);
 563
 564         return size;
 565 }
 566
 567 static ssize_t amdgpu_set_pp_table(struct device *dev,
 568                 struct device_attribute *attr,
 569                 const char *buf,
 570                 size_t count)
 571 {
 572         struct drm_device *ddev = dev_get_drvdata(dev);
 573         struct amdgpu_device *adev = drm_to_adev(ddev);
 574         int ret = 0;
 575
 576         if (amdgpu_in_reset(adev))
 577                 return -EPERM;
 578         if (adev->in_suspend && !adev->in_runpm)
 579                 return -EPERM;
 580
 581         ret = pm_runtime_get_sync(ddev->dev);
 582         if (ret < 0) {
 583                 pm_runtime_put_autosuspend(ddev->dev);
 584                 return ret;
 585         }
 586
 587         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 588
 589         pm_runtime_mark_last_busy(ddev->dev);
 590         pm_runtime_put_autosuspend(ddev->dev);
 591
 592         if (ret)
 593                 return ret;
 594
 595         return count;
 596 }
 597
 598 /**
 599  * DOC: pp_od_clk_voltage
 600  *
 601  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 602  * in each power level within a power state.  The pp_od_clk_voltage is used for
 603  * this.
 604  *
 605  * Note that the actual memory controller clock rate are exposed, not
 606  * the effective memory clock of the DRAMs. To translate it, use the
 607  * following formula:
 608  *
 609  * Clock conversion (Mhz):
 610  *
 611  * HBM: effective_memory_clock = memory_controller_clock * 1
 612  *
 613  * G5: effective_memory_clock = memory_controller_clock * 1
 614  *
 615  * G6: effective_memory_clock = memory_controller_clock * 2
 616  *
 617  * DRAM data rate (MT/s):
 618  *
 619  * HBM: effective_memory_clock * 2 = data_rate
 620  *
 621  * G5: effective_memory_clock * 4 = data_rate
 622  *
 623  * G6: effective_memory_clock * 8 = data_rate
 624  *
 625  * Bandwidth (MB/s):
 626  *
 627  * data_rate * vram_bit_width / 8 = memory_bandwidth
 628  *
 629  * Some examples:
 630  *
 631  * G5 on RX460:
 632  *
 633  * memory_controller_clock = 1750 Mhz
 634  *
 635  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 636  *
 637  * data rate = 1750 * 4 = 7000 MT/s
 638  *
 639  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 640  *
 641  * G6 on RX5700:
 642  *
 643  * memory_controller_clock = 875 Mhz
 644  *
 645  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 646  *
 647  * data rate = 1750 * 8 = 14000 MT/s
 648  *
 649  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 650  *
 651  * < For Vega10 and previous ASICs >
 652  *
 653  * Reading the file will display:
 654  *
 655  * - a list of engine clock levels and voltages labeled OD_SCLK
 656  *
 657  * - a list of memory clock levels and voltages labeled OD_MCLK
 658  *
 659  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 660  *
 661  * To manually adjust these settings, first select manual using
 662  * power_dpm_force_performance_level. Enter a new value for each
 663  * level by writing a string that contains "s/m level clock voltage" to
 664  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 665  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 666  * 810 mV.  When you have edited all of the states as needed, write
 667  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 668  * default power levels, write "r" (reset) to the file to reset them.
 669  *
 670  *
 671  * < For Vega20 and newer ASICs >
 672  *
 673  * Reading the file will display:
 674  *
 675  * - minimum and maximum engine clock labeled OD_SCLK
 676  *
 677  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 678  *   clock labeled OD_MCLK
 679  *
 680  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 681  *   They can be used to calibrate the sclk voltage curve.
 682  *
 683  * - voltage offset(in mV) applied on target voltage calculation.
 684  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 685  *   Cavefish. For these ASICs, the target voltage calculation can be
 686  *   illustrated by "voltage = voltage calculated from v/f curve +
 687  *   overdrive vddgfx offset"
 688  *
 689  * - a list of valid ranges for sclk, mclk, and voltage curve points
 690  *   labeled OD_RANGE
 691  *
 692  * < For APUs >
 693  *
 694  * Reading the file will display:
 695  *
 696  * - minimum and maximum engine clock labeled OD_SCLK
 697  *
 698  * - a list of valid ranges for sclk labeled OD_RANGE
 699  *
 700  * < For VanGogh >
 701  *
 702  * Reading the file will display:
 703  *
 704  * - minimum and maximum engine clock labeled OD_SCLK
 705  * - minimum and maximum core clocks labeled OD_CCLK
 706  *
 707  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 708  *
 709  * To manually adjust these settings:
 710  *
 711  * - First select manual using power_dpm_force_performance_level
 712  *
 713  * - For clock frequency setting, enter a new value by writing a
 714  *   string that contains "s/m index clock" to the file. The index
 715  *   should be 0 if to set minimum clock. And 1 if to set maximum
 716  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 717  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 718  *   clocks on VanGogh, the string contains "p core index clock".
 719  *   E.g., "p 2 0 800" would set the minimum core clock on core
 720  *   2 to 800Mhz.
 721  *
 722  *   For sclk voltage curve, enter the new values by writing a
 723  *   string that contains "vc point clock voltage" to the file. The
 724  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 725  *   update point1 with clock set as 300Mhz and voltage as
 726  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 727  *   as 1000Mhz and voltage 1000mV.
 728  *
 729  *   To update the voltage offset applied for gfxclk/voltage calculation,
 730  *   enter the new value by writing a string that contains "vo offset".
 731  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 732  *   And the offset can be a positive or negative value.
 733  *
 734  * - When you have edited all of the states as needed, write "c" (commit)
 735  *   to the file to commit your changes
 736  *
 737  * - If you want to reset to the default power levels, write "r" (reset)
 738  *   to the file to reset them
 739  *
 740  */
 741
 742 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 743                 struct device_attribute *attr,
 744                 const char *buf,
 745                 size_t count)
 746 {
 747         struct drm_device *ddev = dev_get_drvdata(dev);
 748         struct amdgpu_device *adev = drm_to_adev(ddev);
 749         int ret;
 750         uint32_t parameter_size = 0;
 751         long parameter[64];
 752         char buf_cpy[128];
 753         char *tmp_str;
 754         char *sub_str;
 755         const char delimiter[3] = {' ', '\n', '\0'};
 756         uint32_t type;
 757
 758         if (amdgpu_in_reset(adev))
 759                 return -EPERM;
 760         if (adev->in_suspend && !adev->in_runpm)
 761                 return -EPERM;
 762
 763         if (count > 127)
 764                 return -EINVAL;
 765
 766         if (*buf == 's')
 767                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 768         else if (*buf == 'p')
 769                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 770         else if (*buf == 'm')
 771                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 772         else if(*buf == 'r')
 773                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 774         else if (*buf == 'c')
 775                 type = PP_OD_COMMIT_DPM_TABLE;
 776         else if (!strncmp(buf, "vc", 2))
 777                 type = PP_OD_EDIT_VDDC_CURVE;
 778         else if (!strncmp(buf, "vo", 2))
 779                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 780         else
 781                 return -EINVAL;
 782
 783         memcpy(buf_cpy, buf, count+1);
 784
 785         tmp_str = buf_cpy;
 786
 787         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 788              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 789                 tmp_str++;
 790         while (isspace(*++tmp_str));
 791
 792         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 793                 if (strlen(sub_str) == 0)
 794                         continue;
 795                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 796                 if (ret)
 797                         return -EINVAL;
 798                 parameter_size++;
 799
 800                 while (isspace(*tmp_str))
 801                         tmp_str++;
 802         }
 803
 804         ret = pm_runtime_get_sync(ddev->dev);
 805         if (ret < 0) {
 806                 pm_runtime_put_autosuspend(ddev->dev);
 807                 return ret;
 808         }
 809
 810         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 811                                               type,
 812                                               parameter,
 813                                               parameter_size))
 814                 goto err_out;
 815
 816         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 817                                           parameter, parameter_size))
 818                 goto err_out;
 819
 820         if (type == PP_OD_COMMIT_DPM_TABLE) {
 821                 if (amdgpu_dpm_dispatch_task(adev,
 822                                              AMD_PP_TASK_READJUST_POWER_STATE,
 823                                              NULL))
 824                         goto err_out;
 825         }
 826
 827         pm_runtime_mark_last_busy(ddev->dev);
 828         pm_runtime_put_autosuspend(ddev->dev);
 829
 830         return count;
 831
 832 err_out:
 833         pm_runtime_mark_last_busy(ddev->dev);
 834         pm_runtime_put_autosuspend(ddev->dev);
 835         return -EINVAL;
 836 }
 837
 838 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 839                 struct device_attribute *attr,
 840                 char *buf)
 841 {
 842         struct drm_device *ddev = dev_get_drvdata(dev);
 843         struct amdgpu_device *adev = drm_to_adev(ddev);
 844         int size = 0;
 845         int ret;
 846         enum pp_clock_type od_clocks[6] = {
 847                 OD_SCLK,
 848                 OD_MCLK,
 849                 OD_VDDC_CURVE,
 850                 OD_RANGE,
 851                 OD_VDDGFX_OFFSET,
 852                 OD_CCLK,
 853         };
 854         uint clk_index;
 855
 856         if (amdgpu_in_reset(adev))
 857                 return -EPERM;
 858         if (adev->in_suspend && !adev->in_runpm)
 859                 return -EPERM;
 860
 861         ret = pm_runtime_get_sync(ddev->dev);
 862         if (ret < 0) {
 863                 pm_runtime_put_autosuspend(ddev->dev);
 864                 return ret;
 865         }
 866
 867         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 868                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 869                 if (ret)
 870                         break;
 871         }
 872         if (ret == -ENOENT) {
 873                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 874                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 875                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 876                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 877                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 878                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 879         }
 880
 881         if (size == 0)
 882                 size = sysfs_emit(buf, "\n");
 883
 884         pm_runtime_mark_last_busy(ddev->dev);
 885         pm_runtime_put_autosuspend(ddev->dev);
 886
 887         return size;
 888 }
 889
 890 /**
 891  * DOC: pp_features
 892  *
 893  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 894  * features to be enabled. The file pp_features is used for this. And
 895  * this is only available for Vega10 and later dGPUs.
 896  *
 897  * Reading back the file will show you the followings:
 898  * - Current ppfeature masks
 899  * - List of the all supported powerplay features with their naming,
 900  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 901  *
 902  * To manually enable or disable a specific feature, just set or clear
 903  * the corresponding bit from original ppfeature masks and input the
 904  * new ppfeature masks.
 905  */
 906 static ssize_t amdgpu_set_pp_features(struct device *dev,
 907                                       struct device_attribute *attr,
 908                                       const char *buf,
 909                                       size_t count)
 910 {
 911         struct drm_device *ddev = dev_get_drvdata(dev);
 912         struct amdgpu_device *adev = drm_to_adev(ddev);
 913         uint64_t featuremask;
 914         int ret;
 915
 916         if (amdgpu_in_reset(adev))
 917                 return -EPERM;
 918         if (adev->in_suspend && !adev->in_runpm)
 919                 return -EPERM;
 920
 921         ret = kstrtou64(buf, 0, &featuremask);
 922         if (ret)
 923                 return -EINVAL;
 924
 925         ret = pm_runtime_get_sync(ddev->dev);
 926         if (ret < 0) {
 927                 pm_runtime_put_autosuspend(ddev->dev);
 928                 return ret;
 929         }
 930
 931         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 932
 933         pm_runtime_mark_last_busy(ddev->dev);
 934         pm_runtime_put_autosuspend(ddev->dev);
 935
 936         if (ret)
 937                 return -EINVAL;
 938
 939         return count;
 940 }
 941
 942 static ssize_t amdgpu_get_pp_features(struct device *dev,
 943                                       struct device_attribute *attr,
 944                                       char *buf)
 945 {
 946         struct drm_device *ddev = dev_get_drvdata(dev);
 947         struct amdgpu_device *adev = drm_to_adev(ddev);
 948         ssize_t size;
 949         int ret;
 950
 951         if (amdgpu_in_reset(adev))
 952                 return -EPERM;
 953         if (adev->in_suspend && !adev->in_runpm)
 954                 return -EPERM;
 955
 956         ret = pm_runtime_get_sync(ddev->dev);
 957         if (ret < 0) {
 958                 pm_runtime_put_autosuspend(ddev->dev);
 959                 return ret;
 960         }
 961
 962         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 963         if (size <= 0)
 964                 size = sysfs_emit(buf, "\n");
 965
 966         pm_runtime_mark_last_busy(ddev->dev);
 967         pm_runtime_put_autosuspend(ddev->dev);
 968
 969         return size;
 970 }
 971
 972 /**
 973  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 974  *
 975  * The amdgpu driver provides a sysfs API for adjusting what power levels
 976  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 977  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 978  * this.
 979  *
 980  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 981  * Vega10 and later ASICs.
 982  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 983  *
 984  * Reading back the files will show you the available power levels within
 985  * the power state and the clock information for those levels.
 986  *
 987  * To manually adjust these states, first select manual using
 988  * power_dpm_force_performance_level.
 989  * Secondly, enter a new value for each level by inputing a string that
 990  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
 991  * E.g.,
 992  *
 993  * .. code-block:: bash
 994  *
 995  *      echo "4 5 6" > pp_dpm_sclk
 996  *
 997  * will enable sclk levels 4, 5, and 6.
 998  *
 999  * NOTE: change to the dcefclk max dpm level is not supported now
1000  */
1001
1002 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1003                 enum pp_clock_type type,
1004                 char *buf)
1005 {
1006         struct drm_device *ddev = dev_get_drvdata(dev);
1007         struct amdgpu_device *adev = drm_to_adev(ddev);
1008         int size = 0;
1009         int ret = 0;
1010
1011         if (amdgpu_in_reset(adev))
1012                 return -EPERM;
1013         if (adev->in_suspend && !adev->in_runpm)
1014                 return -EPERM;
1015
1016         ret = pm_runtime_get_sync(ddev->dev);
1017         if (ret < 0) {
1018                 pm_runtime_put_autosuspend(ddev->dev);
1019                 return ret;
1020         }
1021
1022         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1023         if (ret == -ENOENT)
1024                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1025
1026         if (size == 0)
1027                 size = sysfs_emit(buf, "\n");
1028
1029         pm_runtime_mark_last_busy(ddev->dev);
1030         pm_runtime_put_autosuspend(ddev->dev);
1031
1032         return size;
1033 }
1034
1035 /*
1036  * Worst case: 32 bits individually specified, in octal at 12 characters
1037  * per line (+1 for \n).
1038  */
1039 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1040
1041 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1042 {
1043         int ret;
1044         unsigned long level;
1045         char *sub_str = NULL;
1046         char *tmp;
1047         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1048         const char delimiter[3] = {' ', '\n', '\0'};
1049         size_t bytes;
1050
1051         *mask = 0;
1052
1053         bytes = min(count, sizeof(buf_cpy) - 1);
1054         memcpy(buf_cpy, buf, bytes);
1055         buf_cpy[bytes] = '\0';
1056         tmp = buf_cpy;
1057         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1058                 if (strlen(sub_str)) {
1059                         ret = kstrtoul(sub_str, 0, &level);
1060                         if (ret || level > 31)
1061                                 return -EINVAL;
1062                         *mask |= 1 << level;
1063                 } else
1064                         break;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1071                 enum pp_clock_type type,
1072                 const char *buf,
1073                 size_t count)
1074 {
1075         struct drm_device *ddev = dev_get_drvdata(dev);
1076         struct amdgpu_device *adev = drm_to_adev(ddev);
1077         int ret;
1078         uint32_t mask = 0;
1079
1080         if (amdgpu_in_reset(adev))
1081                 return -EPERM;
1082         if (adev->in_suspend && !adev->in_runpm)
1083                 return -EPERM;
1084
1085         ret = amdgpu_read_mask(buf, count, &mask);
1086         if (ret)
1087                 return ret;
1088
1089         ret = pm_runtime_get_sync(ddev->dev);
1090         if (ret < 0) {
1091                 pm_runtime_put_autosuspend(ddev->dev);
1092                 return ret;
1093         }
1094
1095         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1096
1097         pm_runtime_mark_last_busy(ddev->dev);
1098         pm_runtime_put_autosuspend(ddev->dev);
1099
1100         if (ret)
1101                 return -EINVAL;
1102
1103         return count;
1104 }
1105
1106 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1107                 struct device_attribute *attr,
1108                 char *buf)
1109 {
1110         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1111 }
1112
1113 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1114                 struct device_attribute *attr,
1115                 const char *buf,
1116                 size_t count)
1117 {
1118         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1119 }
1120
1121 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1122                 struct device_attribute *attr,
1123                 char *buf)
1124 {
1125         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1126 }
1127
1128 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1129                 struct device_attribute *attr,
1130                 const char *buf,
1131                 size_t count)
1132 {
1133         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1134 }
1135
1136 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1137                 struct device_attribute *attr,
1138                 char *buf)
1139 {
1140         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1141 }
1142
1143 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1144                 struct device_attribute *attr,
1145                 const char *buf,
1146                 size_t count)
1147 {
1148         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1149 }
1150
1151 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1152                 struct device_attribute *attr,
1153                 char *buf)
1154 {
1155         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1156 }
1157
1158 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1159                 struct device_attribute *attr,
1160                 const char *buf,
1161                 size_t count)
1162 {
1163         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1164 }
1165
1166 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1167                 struct device_attribute *attr,
1168                 char *buf)
1169 {
1170         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1171 }
1172
1173 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1174                 struct device_attribute *attr,
1175                 const char *buf,
1176                 size_t count)
1177 {
1178         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1179 }
1180
1181 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1182                 struct device_attribute *attr,
1183                 char *buf)
1184 {
1185         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1186 }
1187
1188 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1189                 struct device_attribute *attr,
1190                 const char *buf,
1191                 size_t count)
1192 {
1193         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1194 }
1195
1196 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1197                 struct device_attribute *attr,
1198                 char *buf)
1199 {
1200         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1201 }
1202
1203 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1204                 struct device_attribute *attr,
1205                 const char *buf,
1206                 size_t count)
1207 {
1208         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1209 }
1210
1211 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1212                 struct device_attribute *attr,
1213                 char *buf)
1214 {
1215         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1216 }
1217
1218 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1219                 struct device_attribute *attr,
1220                 const char *buf,
1221                 size_t count)
1222 {
1223         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1224 }
1225
1226 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1227                 struct device_attribute *attr,
1228                 char *buf)
1229 {
1230         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1231 }
1232
1233 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1234                 struct device_attribute *attr,
1235                 const char *buf,
1236                 size_t count)
1237 {
1238         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1239 }
1240
1241 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1242                 struct device_attribute *attr,
1243                 char *buf)
1244 {
1245         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1246 }
1247
1248 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1249                 struct device_attribute *attr,
1250                 const char *buf,
1251                 size_t count)
1252 {
1253         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1254 }
1255
1256 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1257                 struct device_attribute *attr,
1258                 char *buf)
1259 {
1260         struct drm_device *ddev = dev_get_drvdata(dev);
1261         struct amdgpu_device *adev = drm_to_adev(ddev);
1262         uint32_t value = 0;
1263         int ret;
1264
1265         if (amdgpu_in_reset(adev))
1266                 return -EPERM;
1267         if (adev->in_suspend && !adev->in_runpm)
1268                 return -EPERM;
1269
1270         ret = pm_runtime_get_sync(ddev->dev);
1271         if (ret < 0) {
1272                 pm_runtime_put_autosuspend(ddev->dev);
1273                 return ret;
1274         }
1275
1276         value = amdgpu_dpm_get_sclk_od(adev);
1277
1278         pm_runtime_mark_last_busy(ddev->dev);
1279         pm_runtime_put_autosuspend(ddev->dev);
1280
1281         return sysfs_emit(buf, "%d\n", value);
1282 }
1283
1284 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1285                 struct device_attribute *attr,
1286                 const char *buf,
1287                 size_t count)
1288 {
1289         struct drm_device *ddev = dev_get_drvdata(dev);
1290         struct amdgpu_device *adev = drm_to_adev(ddev);
1291         int ret;
1292         long int value;
1293
1294         if (amdgpu_in_reset(adev))
1295                 return -EPERM;
1296         if (adev->in_suspend && !adev->in_runpm)
1297                 return -EPERM;
1298
1299         ret = kstrtol(buf, 0, &value);
1300
1301         if (ret)
1302                 return -EINVAL;
1303
1304         ret = pm_runtime_get_sync(ddev->dev);
1305         if (ret < 0) {
1306                 pm_runtime_put_autosuspend(ddev->dev);
1307                 return ret;
1308         }
1309
1310         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1311
1312         pm_runtime_mark_last_busy(ddev->dev);
1313         pm_runtime_put_autosuspend(ddev->dev);
1314
1315         return count;
1316 }
1317
1318 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1319                 struct device_attribute *attr,
1320                 char *buf)
1321 {
1322         struct drm_device *ddev = dev_get_drvdata(dev);
1323         struct amdgpu_device *adev = drm_to_adev(ddev);
1324         uint32_t value = 0;
1325         int ret;
1326
1327         if (amdgpu_in_reset(adev))
1328                 return -EPERM;
1329         if (adev->in_suspend && !adev->in_runpm)
1330                 return -EPERM;
1331
1332         ret = pm_runtime_get_sync(ddev->dev);
1333         if (ret < 0) {
1334                 pm_runtime_put_autosuspend(ddev->dev);
1335                 return ret;
1336         }
1337
1338         value = amdgpu_dpm_get_mclk_od(adev);
1339
1340         pm_runtime_mark_last_busy(ddev->dev);
1341         pm_runtime_put_autosuspend(ddev->dev);
1342
1343         return sysfs_emit(buf, "%d\n", value);
1344 }
1345
1346 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1347                 struct device_attribute *attr,
1348                 const char *buf,
1349                 size_t count)
1350 {
1351         struct drm_device *ddev = dev_get_drvdata(dev);
1352         struct amdgpu_device *adev = drm_to_adev(ddev);
1353         int ret;
1354         long int value;
1355
1356         if (amdgpu_in_reset(adev))
1357                 return -EPERM;
1358         if (adev->in_suspend && !adev->in_runpm)
1359                 return -EPERM;
1360
1361         ret = kstrtol(buf, 0, &value);
1362
1363         if (ret)
1364                 return -EINVAL;
1365
1366         ret = pm_runtime_get_sync(ddev->dev);
1367         if (ret < 0) {
1368                 pm_runtime_put_autosuspend(ddev->dev);
1369                 return ret;
1370         }
1371
1372         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1373
1374         pm_runtime_mark_last_busy(ddev->dev);
1375         pm_runtime_put_autosuspend(ddev->dev);
1376
1377         return count;
1378 }
1379
1380 /**
1381  * DOC: pp_power_profile_mode
1382  *
1383  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1384  * related to switching between power levels in a power state.  The file
1385  * pp_power_profile_mode is used for this.
1386  *
1387  * Reading this file outputs a list of all of the predefined power profiles
1388  * and the relevant heuristics settings for that profile.
1389  *
1390  * To select a profile or create a custom profile, first select manual using
1391  * power_dpm_force_performance_level.  Writing the number of a predefined
1392  * profile to pp_power_profile_mode will enable those heuristics.  To
1393  * create a custom set of heuristics, write a string of numbers to the file
1394  * starting with the number of the custom profile along with a setting
1395  * for each heuristic parameter.  Due to differences across asic families
1396  * the heuristic parameters vary from family to family.
1397  *
1398  */
1399
1400 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1401                 struct device_attribute *attr,
1402                 char *buf)
1403 {
1404         struct drm_device *ddev = dev_get_drvdata(dev);
1405         struct amdgpu_device *adev = drm_to_adev(ddev);
1406         ssize_t size;
1407         int ret;
1408
1409         if (amdgpu_in_reset(adev))
1410                 return -EPERM;
1411         if (adev->in_suspend && !adev->in_runpm)
1412                 return -EPERM;
1413
1414         ret = pm_runtime_get_sync(ddev->dev);
1415         if (ret < 0) {
1416                 pm_runtime_put_autosuspend(ddev->dev);
1417                 return ret;
1418         }
1419
1420         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1421         if (size <= 0)
1422                 size = sysfs_emit(buf, "\n");
1423
1424         pm_runtime_mark_last_busy(ddev->dev);
1425         pm_runtime_put_autosuspend(ddev->dev);
1426
1427         return size;
1428 }
1429
1430
1431 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1432                 struct device_attribute *attr,
1433                 const char *buf,
1434                 size_t count)
1435 {
1436         int ret;
1437         struct drm_device *ddev = dev_get_drvdata(dev);
1438         struct amdgpu_device *adev = drm_to_adev(ddev);
1439         uint32_t parameter_size = 0;
1440         long parameter[64];
1441         char *sub_str, buf_cpy[128];
1442         char *tmp_str;
1443         uint32_t i = 0;
1444         char tmp[2];
1445         long int profile_mode = 0;
1446         const char delimiter[3] = {' ', '\n', '\0'};
1447
1448         if (amdgpu_in_reset(adev))
1449                 return -EPERM;
1450         if (adev->in_suspend && !adev->in_runpm)
1451                 return -EPERM;
1452
1453         tmp[0] = *(buf);
1454         tmp[1] = '\0';
1455         ret = kstrtol(tmp, 0, &profile_mode);
1456         if (ret)
1457                 return -EINVAL;
1458
1459         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1460                 if (count < 2 || count > 127)
1461                         return -EINVAL;
1462                 while (isspace(*++buf))
1463                         i++;
1464                 memcpy(buf_cpy, buf, count-i);
1465                 tmp_str = buf_cpy;
1466                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1467                         if (strlen(sub_str) == 0)
1468                                 continue;
1469                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1470                         if (ret)
1471                                 return -EINVAL;
1472                         parameter_size++;
1473                         while (isspace(*tmp_str))
1474                                 tmp_str++;
1475                 }
1476         }
1477         parameter[parameter_size] = profile_mode;
1478
1479         ret = pm_runtime_get_sync(ddev->dev);
1480         if (ret < 0) {
1481                 pm_runtime_put_autosuspend(ddev->dev);
1482                 return ret;
1483         }
1484
1485         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1486
1487         pm_runtime_mark_last_busy(ddev->dev);
1488         pm_runtime_put_autosuspend(ddev->dev);
1489
1490         if (!ret)
1491                 return count;
1492
1493         return -EINVAL;
1494 }
1495
1496 /**
1497  * DOC: gpu_busy_percent
1498  *
1499  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1500  * is as a percentage.  The file gpu_busy_percent is used for this.
1501  * The SMU firmware computes a percentage of load based on the
1502  * aggregate activity level in the IP cores.
1503  */
1504 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1505                                            struct device_attribute *attr,
1506                                            char *buf)
1507 {
1508         struct drm_device *ddev = dev_get_drvdata(dev);
1509         struct amdgpu_device *adev = drm_to_adev(ddev);
1510         int r, value, size = sizeof(value);
1511
1512         if (amdgpu_in_reset(adev))
1513                 return -EPERM;
1514         if (adev->in_suspend && !adev->in_runpm)
1515                 return -EPERM;
1516
1517         r = pm_runtime_get_sync(ddev->dev);
1518         if (r < 0) {
1519                 pm_runtime_put_autosuspend(ddev->dev);
1520                 return r;
1521         }
1522
1523         /* read the IP busy sensor */
1524         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1525                                    (void *)&value, &size);
1526
1527         pm_runtime_mark_last_busy(ddev->dev);
1528         pm_runtime_put_autosuspend(ddev->dev);
1529
1530         if (r)
1531                 return r;
1532
1533         return sysfs_emit(buf, "%d\n", value);
1534 }
1535
1536 /**
1537  * DOC: mem_busy_percent
1538  *
1539  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1540  * is as a percentage.  The file mem_busy_percent is used for this.
1541  * The SMU firmware computes a percentage of load based on the
1542  * aggregate activity level in the IP cores.
1543  */
1544 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1545                                            struct device_attribute *attr,
1546                                            char *buf)
1547 {
1548         struct drm_device *ddev = dev_get_drvdata(dev);
1549         struct amdgpu_device *adev = drm_to_adev(ddev);
1550         int r, value, size = sizeof(value);
1551
1552         if (amdgpu_in_reset(adev))
1553                 return -EPERM;
1554         if (adev->in_suspend && !adev->in_runpm)
1555                 return -EPERM;
1556
1557         r = pm_runtime_get_sync(ddev->dev);
1558         if (r < 0) {
1559                 pm_runtime_put_autosuspend(ddev->dev);
1560                 return r;
1561         }
1562
1563         /* read the IP busy sensor */
1564         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1565                                    (void *)&value, &size);
1566
1567         pm_runtime_mark_last_busy(ddev->dev);
1568         pm_runtime_put_autosuspend(ddev->dev);
1569
1570         if (r)
1571                 return r;
1572
1573         return sysfs_emit(buf, "%d\n", value);
1574 }
1575
1576 /**
1577  * DOC: pcie_bw
1578  *
1579  * The amdgpu driver provides a sysfs API for estimating how much data
1580  * has been received and sent by the GPU in the last second through PCIe.
1581  * The file pcie_bw is used for this.
1582  * The Perf counters count the number of received and sent messages and return
1583  * those values, as well as the maximum payload size of a PCIe packet (mps).
1584  * Note that it is not possible to easily and quickly obtain the size of each
1585  * packet transmitted, so we output the max payload size (mps) to allow for
1586  * quick estimation of the PCIe bandwidth usage
1587  */
1588 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1589                 struct device_attribute *attr,
1590                 char *buf)
1591 {
1592         struct drm_device *ddev = dev_get_drvdata(dev);
1593         struct amdgpu_device *adev = drm_to_adev(ddev);
1594         uint64_t count0 = 0, count1 = 0;
1595         int ret;
1596
1597         if (amdgpu_in_reset(adev))
1598                 return -EPERM;
1599         if (adev->in_suspend && !adev->in_runpm)
1600                 return -EPERM;
1601
1602         if (adev->flags & AMD_IS_APU)
1603                 return -ENODATA;
1604
1605         if (!adev->asic_funcs->get_pcie_usage)
1606                 return -ENODATA;
1607
1608         ret = pm_runtime_get_sync(ddev->dev);
1609         if (ret < 0) {
1610                 pm_runtime_put_autosuspend(ddev->dev);
1611                 return ret;
1612         }
1613
1614         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1615
1616         pm_runtime_mark_last_busy(ddev->dev);
1617         pm_runtime_put_autosuspend(ddev->dev);
1618
1619         return sysfs_emit(buf, "%llu %llu %i\n",
1620                           count0, count1, pcie_get_mps(adev->pdev));
1621 }
1622
1623 /**
1624  * DOC: unique_id
1625  *
1626  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1627  * The file unique_id is used for this.
1628  * This will provide a Unique ID that will persist from machine to machine
1629  *
1630  * NOTE: This will only work for GFX9 and newer. This file will be absent
1631  * on unsupported ASICs (GFX8 and older)
1632  */
1633 static ssize_t amdgpu_get_unique_id(struct device *dev,
1634                 struct device_attribute *attr,
1635                 char *buf)
1636 {
1637         struct drm_device *ddev = dev_get_drvdata(dev);
1638         struct amdgpu_device *adev = drm_to_adev(ddev);
1639
1640         if (amdgpu_in_reset(adev))
1641                 return -EPERM;
1642         if (adev->in_suspend && !adev->in_runpm)
1643                 return -EPERM;
1644
1645         if (adev->unique_id)
1646                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1647
1648         return 0;
1649 }
1650
1651 /**
1652  * DOC: thermal_throttling_logging
1653  *
1654  * Thermal throttling pulls down the clock frequency and thus the performance.
1655  * It's an useful mechanism to protect the chip from overheating. Since it
1656  * impacts performance, the user controls whether it is enabled and if so,
1657  * the log frequency.
1658  *
1659  * Reading back the file shows you the status(enabled or disabled) and
1660  * the interval(in seconds) between each thermal logging.
1661  *
1662  * Writing an integer to the file, sets a new logging interval, in seconds.
1663  * The value should be between 1 and 3600. If the value is less than 1,
1664  * thermal logging is disabled. Values greater than 3600 are ignored.
1665  */
1666 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1667                                                      struct device_attribute *attr,
1668                                                      char *buf)
1669 {
1670         struct drm_device *ddev = dev_get_drvdata(dev);
1671         struct amdgpu_device *adev = drm_to_adev(ddev);
1672
1673         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1674                           adev_to_drm(adev)->unique,
1675                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1676                           adev->throttling_logging_rs.interval / HZ + 1);
1677 }
1678
1679 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1680                                                      struct device_attribute *attr,
1681                                                      const char *buf,
1682                                                      size_t count)
1683 {
1684         struct drm_device *ddev = dev_get_drvdata(dev);
1685         struct amdgpu_device *adev = drm_to_adev(ddev);
1686         long throttling_logging_interval;
1687         unsigned long flags;
1688         int ret = 0;
1689
1690         ret = kstrtol(buf, 0, &throttling_logging_interval);
1691         if (ret)
1692                 return ret;
1693
1694         if (throttling_logging_interval > 3600)
1695                 return -EINVAL;
1696
1697         if (throttling_logging_interval > 0) {
1698                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1699                 /*
1700                  * Reset the ratelimit timer internals.
1701                  * This can effectively restart the timer.
1702                  */
1703                 adev->throttling_logging_rs.interval =
1704                         (throttling_logging_interval - 1) * HZ;
1705                 adev->throttling_logging_rs.begin = 0;
1706                 adev->throttling_logging_rs.printed = 0;
1707                 adev->throttling_logging_rs.missed = 0;
1708                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1709
1710                 atomic_set(&adev->throttling_logging_enabled, 1);
1711         } else {
1712                 atomic_set(&adev->throttling_logging_enabled, 0);
1713         }
1714
1715         return count;
1716 }
1717
1718 /**
1719  * DOC: apu_thermal_cap
1720  *
1721  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1722  * limit temperature in millidegrees Celsius
1723  *
1724  * Reading back the file shows you core limit value
1725  *
1726  * Writing an integer to the file, sets a new thermal limit. The value
1727  * should be between 0 and 100. If the value is less than 0 or greater
1728  * than 100, then the write request will be ignored.
1729  */
1730 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1731                                          struct device_attribute *attr,
1732                                          char *buf)
1733 {
1734         int ret, size;
1735         u32 limit;
1736         struct drm_device *ddev = dev_get_drvdata(dev);
1737         struct amdgpu_device *adev = drm_to_adev(ddev);
1738
1739         ret = pm_runtime_get_sync(ddev->dev);
1740         if (ret < 0) {
1741                 pm_runtime_put_autosuspend(ddev->dev);
1742                 return ret;
1743         }
1744
1745         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1746         if (!ret)
1747                 size = sysfs_emit(buf, "%u\n", limit);
1748         else
1749                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1750
1751         pm_runtime_mark_last_busy(ddev->dev);
1752         pm_runtime_put_autosuspend(ddev->dev);
1753
1754         return size;
1755 }
1756
1757 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1758                                          struct device_attribute *attr,
1759                                          const char *buf,
1760                                          size_t count)
1761 {
1762         int ret;
1763         u32 value;
1764         struct drm_device *ddev = dev_get_drvdata(dev);
1765         struct amdgpu_device *adev = drm_to_adev(ddev);
1766
1767         ret = kstrtou32(buf, 10, &value);
1768         if (ret)
1769                 return ret;
1770
1771         if (value > 100) {
1772                 dev_err(dev, "Invalid argument !\n");
1773                 return -EINVAL;
1774         }
1775
1776         ret = pm_runtime_get_sync(ddev->dev);
1777         if (ret < 0) {
1778                 pm_runtime_put_autosuspend(ddev->dev);
1779                 return ret;
1780         }
1781
1782         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1783         if (ret) {
1784                 dev_err(dev, "failed to update thermal limit\n");
1785                 return ret;
1786         }
1787
1788         pm_runtime_mark_last_busy(ddev->dev);
1789         pm_runtime_put_autosuspend(ddev->dev);
1790
1791         return count;
1792 }
1793
1794 /**
1795  * DOC: gpu_metrics
1796  *
1797  * The amdgpu driver provides a sysfs API for retrieving current gpu
1798  * metrics data. The file gpu_metrics is used for this. Reading the
1799  * file will dump all the current gpu metrics data.
1800  *
1801  * These data include temperature, frequency, engines utilization,
1802  * power consume, throttler status, fan speed and cpu core statistics(
1803  * available for APU only). That's it will give a snapshot of all sensors
1804  * at the same time.
1805  */
1806 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1807                                       struct device_attribute *attr,
1808                                       char *buf)
1809 {
1810         struct drm_device *ddev = dev_get_drvdata(dev);
1811         struct amdgpu_device *adev = drm_to_adev(ddev);
1812         void *gpu_metrics;
1813         ssize_t size = 0;
1814         int ret;
1815
1816         if (amdgpu_in_reset(adev))
1817                 return -EPERM;
1818         if (adev->in_suspend && !adev->in_runpm)
1819                 return -EPERM;
1820
1821         ret = pm_runtime_get_sync(ddev->dev);
1822         if (ret < 0) {
1823                 pm_runtime_put_autosuspend(ddev->dev);
1824                 return ret;
1825         }
1826
1827         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1828         if (size <= 0)
1829                 goto out;
1830
1831         if (size >= PAGE_SIZE)
1832                 size = PAGE_SIZE - 1;
1833
1834         memcpy(buf, gpu_metrics, size);
1835
1836 out:
1837         pm_runtime_mark_last_busy(ddev->dev);
1838         pm_runtime_put_autosuspend(ddev->dev);
1839
1840         return size;
1841 }
1842
1843 static int amdgpu_device_read_powershift(struct amdgpu_device *adev,
1844                                                 uint32_t *ss_power, bool dgpu_share)
1845 {
1846         struct drm_device *ddev = adev_to_drm(adev);
1847         uint32_t size;
1848         int r = 0;
1849
1850         if (amdgpu_in_reset(adev))
1851                 return -EPERM;
1852         if (adev->in_suspend && !adev->in_runpm)
1853                 return -EPERM;
1854
1855         r = pm_runtime_get_sync(ddev->dev);
1856         if (r < 0) {
1857                 pm_runtime_put_autosuspend(ddev->dev);
1858                 return r;
1859         }
1860
1861         if (dgpu_share)
1862                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1863                                    (void *)ss_power, &size);
1864         else
1865                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1866                                    (void *)ss_power, &size);
1867
1868         pm_runtime_mark_last_busy(ddev->dev);
1869         pm_runtime_put_autosuspend(ddev->dev);
1870         return r;
1871 }
1872
1873 static int amdgpu_show_powershift_percent(struct device *dev,
1874                                         char *buf, bool dgpu_share)
1875 {
1876         struct drm_device *ddev = dev_get_drvdata(dev);
1877         struct amdgpu_device *adev = drm_to_adev(ddev);
1878         uint32_t ss_power;
1879         int r = 0, i;
1880
1881         r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1882         if (r == -EOPNOTSUPP) {
1883                 /* sensor not available on dGPU, try to read from APU */
1884                 adev = NULL;
1885                 mutex_lock(&mgpu_info.mutex);
1886                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1887                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1888                                 adev = mgpu_info.gpu_ins[i].adev;
1889                                 break;
1890                         }
1891                 }
1892                 mutex_unlock(&mgpu_info.mutex);
1893                 if (adev)
1894                         r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share);
1895         }
1896
1897         if (!r)
1898                 r = sysfs_emit(buf, "%u%%\n", ss_power);
1899
1900         return r;
1901 }
1902 /**
1903  * DOC: smartshift_apu_power
1904  *
1905  * The amdgpu driver provides a sysfs API for reporting APU power
1906  * shift in percentage if platform supports smartshift. Value 0 means that
1907  * there is no powershift and values between [1-100] means that the power
1908  * is shifted to APU, the percentage of boost is with respect to APU power
1909  * limit on the platform.
1910  */
1911
1912 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1913                                                char *buf)
1914 {
1915         return amdgpu_show_powershift_percent(dev, buf, false);
1916 }
1917
1918 /**
1919  * DOC: smartshift_dgpu_power
1920  *
1921  * The amdgpu driver provides a sysfs API for reporting dGPU power
1922  * shift in percentage if platform supports smartshift. Value 0 means that
1923  * there is no powershift and values between [1-100] means that the power is
1924  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1925  * limit on the platform.
1926  */
1927
1928 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1929                                                 char *buf)
1930 {
1931         return amdgpu_show_powershift_percent(dev, buf, true);
1932 }
1933
1934 /**
1935  * DOC: smartshift_bias
1936  *
1937  * The amdgpu driver provides a sysfs API for reporting the
1938  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1939  * and the default is 0. -100 sets maximum preference to APU
1940  * and 100 sets max perference to dGPU.
1941  */
1942
1943 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1944                                           struct device_attribute *attr,
1945                                           char *buf)
1946 {
1947         int r = 0;
1948
1949         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1950
1951         return r;
1952 }
1953
1954 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1955                                           struct device_attribute *attr,
1956                                           const char *buf, size_t count)
1957 {
1958         struct drm_device *ddev = dev_get_drvdata(dev);
1959         struct amdgpu_device *adev = drm_to_adev(ddev);
1960         int r = 0;
1961         int bias = 0;
1962
1963         if (amdgpu_in_reset(adev))
1964                 return -EPERM;
1965         if (adev->in_suspend && !adev->in_runpm)
1966                 return -EPERM;
1967
1968         r = pm_runtime_get_sync(ddev->dev);
1969         if (r < 0) {
1970                 pm_runtime_put_autosuspend(ddev->dev);
1971                 return r;
1972         }
1973
1974         r = kstrtoint(buf, 10, &bias);
1975         if (r)
1976                 goto out;
1977
1978         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1979                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1980         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1981                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1982
1983         amdgpu_smartshift_bias = bias;
1984         r = count;
1985
1986         /* TODO: update bias level with SMU message */
1987
1988 out:
1989         pm_runtime_mark_last_busy(ddev->dev);
1990         pm_runtime_put_autosuspend(ddev->dev);
1991         return r;
1992 }
1993
1994
1995 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1996                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1997 {
1998         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1999                 *states = ATTR_STATE_UNSUPPORTED;
2000
2001         return 0;
2002 }
2003
2004 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2005                                uint32_t mask, enum amdgpu_device_attr_states *states)
2006 {
2007         uint32_t ss_power, size;
2008
2009         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2010                 *states = ATTR_STATE_UNSUPPORTED;
2011         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
2012                  (void *)&ss_power, &size))
2013                 *states = ATTR_STATE_UNSUPPORTED;
2014         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
2015                  (void *)&ss_power, &size))
2016                 *states = ATTR_STATE_UNSUPPORTED;
2017
2018         return 0;
2019 }
2020
2021 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2022         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2023         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2024         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2025         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2026         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2027         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2028         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2029         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2030         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2031         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2032         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2033         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2034         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2035         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2036         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2037         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2038         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2039         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2040         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2041         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2042         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2043         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2044         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2045         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2046         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2047         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2048         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2049         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2050         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2051                               .attr_update = ss_power_attr_update),
2052         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2053                               .attr_update = ss_power_attr_update),
2054         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2055                               .attr_update = ss_bias_attr_update),
2056 };
2057
2058 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2059                                uint32_t mask, enum amdgpu_device_attr_states *states)
2060 {
2061         struct device_attribute *dev_attr = &attr->dev_attr;
2062         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
2063         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
2064         const char *attr_name = dev_attr->attr.name;
2065
2066         if (!(attr->flags & mask)) {
2067                 *states = ATTR_STATE_UNSUPPORTED;
2068                 return 0;
2069         }
2070
2071 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2072
2073         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2074                 if (gc_ver < IP_VERSION(9, 0, 0))
2075                         *states = ATTR_STATE_UNSUPPORTED;
2076         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2077                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2078                     gc_ver == IP_VERSION(9, 4, 1) ||
2079                     gc_ver == IP_VERSION(9, 4, 2))
2080                         *states = ATTR_STATE_UNSUPPORTED;
2081         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2082                 if (mp1_ver < IP_VERSION(10, 0, 0))
2083                         *states = ATTR_STATE_UNSUPPORTED;
2084         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2085                 *states = ATTR_STATE_UNSUPPORTED;
2086                 if (amdgpu_dpm_is_overdrive_supported(adev))
2087                         *states = ATTR_STATE_SUPPORTED;
2088         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2089                 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2090                         *states = ATTR_STATE_UNSUPPORTED;
2091         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2092                 /* PCIe Perf counters won't work on APU nodes */
2093                 if (adev->flags & AMD_IS_APU)
2094                         *states = ATTR_STATE_UNSUPPORTED;
2095         } else if (DEVICE_ATTR_IS(unique_id)) {
2096                 switch (gc_ver) {
2097                 case IP_VERSION(9, 0, 1):
2098                 case IP_VERSION(9, 4, 0):
2099                 case IP_VERSION(9, 4, 1):
2100                 case IP_VERSION(9, 4, 2):
2101                 case IP_VERSION(10, 3, 0):
2102                 case IP_VERSION(11, 0, 0):
2103                 case IP_VERSION(11, 0, 1):
2104                 case IP_VERSION(11, 0, 2):
2105                         *states = ATTR_STATE_SUPPORTED;
2106                         break;
2107                 default:
2108                         *states = ATTR_STATE_UNSUPPORTED;
2109                 }
2110         } else if (DEVICE_ATTR_IS(pp_features)) {
2111                 if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0))
2112                         *states = ATTR_STATE_UNSUPPORTED;
2113         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2114                 if (gc_ver < IP_VERSION(9, 1, 0))
2115                         *states = ATTR_STATE_UNSUPPORTED;
2116         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2117                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2118                       gc_ver == IP_VERSION(10, 3, 0) ||
2119                       gc_ver == IP_VERSION(10, 1, 2) ||
2120                       gc_ver == IP_VERSION(11, 0, 0) ||
2121                       gc_ver == IP_VERSION(11, 0, 2) ||
2122                       gc_ver == IP_VERSION(11, 0, 3)))
2123                         *states = ATTR_STATE_UNSUPPORTED;
2124         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2125                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2126                            gc_ver == IP_VERSION(10, 3, 0) ||
2127                            gc_ver == IP_VERSION(11, 0, 2) ||
2128                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2129                         *states = ATTR_STATE_UNSUPPORTED;
2130         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2131                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2132                       gc_ver == IP_VERSION(10, 3, 0) ||
2133                       gc_ver == IP_VERSION(10, 1, 2) ||
2134                       gc_ver == IP_VERSION(11, 0, 0) ||
2135                       gc_ver == IP_VERSION(11, 0, 2) ||
2136                       gc_ver == IP_VERSION(11, 0, 3)))
2137                         *states = ATTR_STATE_UNSUPPORTED;
2138         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2139                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2140                            gc_ver == IP_VERSION(10, 3, 0) ||
2141                            gc_ver == IP_VERSION(11, 0, 2) ||
2142                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2143                         *states = ATTR_STATE_UNSUPPORTED;
2144         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2145                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2146                         *states = ATTR_STATE_UNSUPPORTED;
2147                 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev))
2148                         *states = ATTR_STATE_UNSUPPORTED;
2149         }
2150
2151         switch (gc_ver) {
2152         case IP_VERSION(9, 4, 1):
2153         case IP_VERSION(9, 4, 2):
2154                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2155                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2156                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2157                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2158                         dev_attr->attr.mode &= ~S_IWUGO;
2159                         dev_attr->store = NULL;
2160                 }
2161                 break;
2162         case IP_VERSION(10, 3, 0):
2163                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2164                     amdgpu_sriov_vf(adev)) {
2165                         dev_attr->attr.mode &= ~0222;
2166                         dev_attr->store = NULL;
2167                 }
2168                 break;
2169         default:
2170                 break;
2171         }
2172
2173         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2174                 /* SMU MP1 does not support dcefclk level setting */
2175                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2176                         dev_attr->attr.mode &= ~S_IWUGO;
2177                         dev_attr->store = NULL;
2178                 }
2179         }
2180
2181         /* setting should not be allowed from VF if not in one VF mode */
2182         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2183                 dev_attr->attr.mode &= ~S_IWUGO;
2184                 dev_attr->store = NULL;
2185         }
2186
2187 #undef DEVICE_ATTR_IS
2188
2189         return 0;
2190 }
2191
2192
2193 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2194                                      struct amdgpu_device_attr *attr,
2195                                      uint32_t mask, struct list_head *attr_list)
2196 {
2197         int ret = 0;
2198         struct device_attribute *dev_attr = &attr->dev_attr;
2199         const char *name = dev_attr->attr.name;
2200         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2201         struct amdgpu_device_attr_entry *attr_entry;
2202
2203         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2204                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2205
2206         BUG_ON(!attr);
2207
2208         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2209
2210         ret = attr_update(adev, attr, mask, &attr_states);
2211         if (ret) {
2212                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2213                         name, ret);
2214                 return ret;
2215         }
2216
2217         if (attr_states == ATTR_STATE_UNSUPPORTED)
2218                 return 0;
2219
2220         ret = device_create_file(adev->dev, dev_attr);
2221         if (ret) {
2222                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2223                         name, ret);
2224         }
2225
2226         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2227         if (!attr_entry)
2228                 return -ENOMEM;
2229
2230         attr_entry->attr = attr;
2231         INIT_LIST_HEAD(&attr_entry->entry);
2232
2233         list_add_tail(&attr_entry->entry, attr_list);
2234
2235         return ret;
2236 }
2237
2238 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2239 {
2240         struct device_attribute *dev_attr = &attr->dev_attr;
2241
2242         device_remove_file(adev->dev, dev_attr);
2243 }
2244
2245 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2246                                              struct list_head *attr_list);
2247
2248 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2249                                             struct amdgpu_device_attr *attrs,
2250                                             uint32_t counts,
2251                                             uint32_t mask,
2252                                             struct list_head *attr_list)
2253 {
2254         int ret = 0;
2255         uint32_t i = 0;
2256
2257         for (i = 0; i < counts; i++) {
2258                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2259                 if (ret)
2260                         goto failed;
2261         }
2262
2263         return 0;
2264
2265 failed:
2266         amdgpu_device_attr_remove_groups(adev, attr_list);
2267
2268         return ret;
2269 }
2270
2271 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2272                                              struct list_head *attr_list)
2273 {
2274         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2275
2276         if (list_empty(attr_list))
2277                 return ;
2278
2279         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2280                 amdgpu_device_attr_remove(adev, entry->attr);
2281                 list_del(&entry->entry);
2282                 kfree(entry);
2283         }
2284 }
2285
2286 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2287                                       struct device_attribute *attr,
2288                                       char *buf)
2289 {
2290         struct amdgpu_device *adev = dev_get_drvdata(dev);
2291         int channel = to_sensor_dev_attr(attr)->index;
2292         int r, temp = 0, size = sizeof(temp);
2293
2294         if (amdgpu_in_reset(adev))
2295                 return -EPERM;
2296         if (adev->in_suspend && !adev->in_runpm)
2297                 return -EPERM;
2298
2299         if (channel >= PP_TEMP_MAX)
2300                 return -EINVAL;
2301
2302         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2303         if (r < 0) {
2304                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2305                 return r;
2306         }
2307
2308         switch (channel) {
2309         case PP_TEMP_JUNCTION:
2310                 /* get current junction temperature */
2311                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2312                                            (void *)&temp, &size);
2313                 break;
2314         case PP_TEMP_EDGE:
2315                 /* get current edge temperature */
2316                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2317                                            (void *)&temp, &size);
2318                 break;
2319         case PP_TEMP_MEM:
2320                 /* get current memory temperature */
2321                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2322                                            (void *)&temp, &size);
2323                 break;
2324         default:
2325                 r = -EINVAL;
2326                 break;
2327         }
2328
2329         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2330         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2331
2332         if (r)
2333                 return r;
2334
2335         return sysfs_emit(buf, "%d\n", temp);
2336 }
2337
2338 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2339                                              struct device_attribute *attr,
2340                                              char *buf)
2341 {
2342         struct amdgpu_device *adev = dev_get_drvdata(dev);
2343         int hyst = to_sensor_dev_attr(attr)->index;
2344         int temp;
2345
2346         if (hyst)
2347                 temp = adev->pm.dpm.thermal.min_temp;
2348         else
2349                 temp = adev->pm.dpm.thermal.max_temp;
2350
2351         return sysfs_emit(buf, "%d\n", temp);
2352 }
2353
2354 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2355                                              struct device_attribute *attr,
2356                                              char *buf)
2357 {
2358         struct amdgpu_device *adev = dev_get_drvdata(dev);
2359         int hyst = to_sensor_dev_attr(attr)->index;
2360         int temp;
2361
2362         if (hyst)
2363                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2364         else
2365                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2366
2367         return sysfs_emit(buf, "%d\n", temp);
2368 }
2369
2370 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2371                                              struct device_attribute *attr,
2372                                              char *buf)
2373 {
2374         struct amdgpu_device *adev = dev_get_drvdata(dev);
2375         int hyst = to_sensor_dev_attr(attr)->index;
2376         int temp;
2377
2378         if (hyst)
2379                 temp = adev->pm.dpm.thermal.min_mem_temp;
2380         else
2381                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2382
2383         return sysfs_emit(buf, "%d\n", temp);
2384 }
2385
2386 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2387                                              struct device_attribute *attr,
2388                                              char *buf)
2389 {
2390         int channel = to_sensor_dev_attr(attr)->index;
2391
2392         if (channel >= PP_TEMP_MAX)
2393                 return -EINVAL;
2394
2395         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2396 }
2397
2398 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2399                                              struct device_attribute *attr,
2400                                              char *buf)
2401 {
2402         struct amdgpu_device *adev = dev_get_drvdata(dev);
2403         int channel = to_sensor_dev_attr(attr)->index;
2404         int temp = 0;
2405
2406         if (channel >= PP_TEMP_MAX)
2407                 return -EINVAL;
2408
2409         switch (channel) {
2410         case PP_TEMP_JUNCTION:
2411                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2412                 break;
2413         case PP_TEMP_EDGE:
2414                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2415                 break;
2416         case PP_TEMP_MEM:
2417                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2418                 break;
2419         }
2420
2421         return sysfs_emit(buf, "%d\n", temp);
2422 }
2423
2424 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2425                                             struct device_attribute *attr,
2426                                             char *buf)
2427 {
2428         struct amdgpu_device *adev = dev_get_drvdata(dev);
2429         u32 pwm_mode = 0;
2430         int ret;
2431
2432         if (amdgpu_in_reset(adev))
2433                 return -EPERM;
2434         if (adev->in_suspend && !adev->in_runpm)
2435                 return -EPERM;
2436
2437         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2438         if (ret < 0) {
2439                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2440                 return ret;
2441         }
2442
2443         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2444
2445         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2446         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2447
2448         if (ret)
2449                 return -EINVAL;
2450
2451         return sysfs_emit(buf, "%u\n", pwm_mode);
2452 }
2453
2454 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2455                                             struct device_attribute *attr,
2456                                             const char *buf,
2457                                             size_t count)
2458 {
2459         struct amdgpu_device *adev = dev_get_drvdata(dev);
2460         int err, ret;
2461         int value;
2462
2463         if (amdgpu_in_reset(adev))
2464                 return -EPERM;
2465         if (adev->in_suspend && !adev->in_runpm)
2466                 return -EPERM;
2467
2468         err = kstrtoint(buf, 10, &value);
2469         if (err)
2470                 return err;
2471
2472         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2473         if (ret < 0) {
2474                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2475                 return ret;
2476         }
2477
2478         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2479
2480         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2481         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2482
2483         if (ret)
2484                 return -EINVAL;
2485
2486         return count;
2487 }
2488
2489 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2490                                          struct device_attribute *attr,
2491                                          char *buf)
2492 {
2493         return sysfs_emit(buf, "%i\n", 0);
2494 }
2495
2496 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2497                                          struct device_attribute *attr,
2498                                          char *buf)
2499 {
2500         return sysfs_emit(buf, "%i\n", 255);
2501 }
2502
2503 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2504                                      struct device_attribute *attr,
2505                                      const char *buf, size_t count)
2506 {
2507         struct amdgpu_device *adev = dev_get_drvdata(dev);
2508         int err;
2509         u32 value;
2510         u32 pwm_mode;
2511
2512         if (amdgpu_in_reset(adev))
2513                 return -EPERM;
2514         if (adev->in_suspend && !adev->in_runpm)
2515                 return -EPERM;
2516
2517         err = kstrtou32(buf, 10, &value);
2518         if (err)
2519                 return err;
2520
2521         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2522         if (err < 0) {
2523                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2524                 return err;
2525         }
2526
2527         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2528         if (err)
2529                 goto out;
2530
2531         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2532                 pr_info("manual fan speed control should be enabled first\n");
2533                 err = -EINVAL;
2534                 goto out;
2535         }
2536
2537         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2538
2539 out:
2540         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2541         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2542
2543         if (err)
2544                 return err;
2545
2546         return count;
2547 }
2548
2549 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2550                                      struct device_attribute *attr,
2551                                      char *buf)
2552 {
2553         struct amdgpu_device *adev = dev_get_drvdata(dev);
2554         int err;
2555         u32 speed = 0;
2556
2557         if (amdgpu_in_reset(adev))
2558                 return -EPERM;
2559         if (adev->in_suspend && !adev->in_runpm)
2560                 return -EPERM;
2561
2562         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2563         if (err < 0) {
2564                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2565                 return err;
2566         }
2567
2568         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2569
2570         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2571         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2572
2573         if (err)
2574                 return err;
2575
2576         return sysfs_emit(buf, "%i\n", speed);
2577 }
2578
2579 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2580                                            struct device_attribute *attr,
2581                                            char *buf)
2582 {
2583         struct amdgpu_device *adev = dev_get_drvdata(dev);
2584         int err;
2585         u32 speed = 0;
2586
2587         if (amdgpu_in_reset(adev))
2588                 return -EPERM;
2589         if (adev->in_suspend && !adev->in_runpm)
2590                 return -EPERM;
2591
2592         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2593         if (err < 0) {
2594                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2595                 return err;
2596         }
2597
2598         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2599
2600         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2601         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2602
2603         if (err)
2604                 return err;
2605
2606         return sysfs_emit(buf, "%i\n", speed);
2607 }
2608
2609 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2610                                          struct device_attribute *attr,
2611                                          char *buf)
2612 {
2613         struct amdgpu_device *adev = dev_get_drvdata(dev);
2614         u32 min_rpm = 0;
2615         u32 size = sizeof(min_rpm);
2616         int r;
2617
2618         if (amdgpu_in_reset(adev))
2619                 return -EPERM;
2620         if (adev->in_suspend && !adev->in_runpm)
2621                 return -EPERM;
2622
2623         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2624         if (r < 0) {
2625                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2626                 return r;
2627         }
2628
2629         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2630                                    (void *)&min_rpm, &size);
2631
2632         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2633         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2634
2635         if (r)
2636                 return r;
2637
2638         return sysfs_emit(buf, "%d\n", min_rpm);
2639 }
2640
2641 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2642                                          struct device_attribute *attr,
2643                                          char *buf)
2644 {
2645         struct amdgpu_device *adev = dev_get_drvdata(dev);
2646         u32 max_rpm = 0;
2647         u32 size = sizeof(max_rpm);
2648         int r;
2649
2650         if (amdgpu_in_reset(adev))
2651                 return -EPERM;
2652         if (adev->in_suspend && !adev->in_runpm)
2653                 return -EPERM;
2654
2655         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2656         if (r < 0) {
2657                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2658                 return r;
2659         }
2660
2661         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2662                                    (void *)&max_rpm, &size);
2663
2664         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2665         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2666
2667         if (r)
2668                 return r;
2669
2670         return sysfs_emit(buf, "%d\n", max_rpm);
2671 }
2672
2673 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2674                                            struct device_attribute *attr,
2675                                            char *buf)
2676 {
2677         struct amdgpu_device *adev = dev_get_drvdata(dev);
2678         int err;
2679         u32 rpm = 0;
2680
2681         if (amdgpu_in_reset(adev))
2682                 return -EPERM;
2683         if (adev->in_suspend && !adev->in_runpm)
2684                 return -EPERM;
2685
2686         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2687         if (err < 0) {
2688                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2689                 return err;
2690         }
2691
2692         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2693
2694         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2695         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2696
2697         if (err)
2698                 return err;
2699
2700         return sysfs_emit(buf, "%i\n", rpm);
2701 }
2702
2703 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2704                                      struct device_attribute *attr,
2705                                      const char *buf, size_t count)
2706 {
2707         struct amdgpu_device *adev = dev_get_drvdata(dev);
2708         int err;
2709         u32 value;
2710         u32 pwm_mode;
2711
2712         if (amdgpu_in_reset(adev))
2713                 return -EPERM;
2714         if (adev->in_suspend && !adev->in_runpm)
2715                 return -EPERM;
2716
2717         err = kstrtou32(buf, 10, &value);
2718         if (err)
2719                 return err;
2720
2721         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2722         if (err < 0) {
2723                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2724                 return err;
2725         }
2726
2727         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2728         if (err)
2729                 goto out;
2730
2731         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2732                 err = -ENODATA;
2733                 goto out;
2734         }
2735
2736         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2737
2738 out:
2739         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2740         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2741
2742         if (err)
2743                 return err;
2744
2745         return count;
2746 }
2747
2748 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2749                                             struct device_attribute *attr,
2750                                             char *buf)
2751 {
2752         struct amdgpu_device *adev = dev_get_drvdata(dev);
2753         u32 pwm_mode = 0;
2754         int ret;
2755
2756         if (amdgpu_in_reset(adev))
2757                 return -EPERM;
2758         if (adev->in_suspend && !adev->in_runpm)
2759                 return -EPERM;
2760
2761         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2762         if (ret < 0) {
2763                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2764                 return ret;
2765         }
2766
2767         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2768
2769         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2770         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2771
2772         if (ret)
2773                 return -EINVAL;
2774
2775         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2776 }
2777
2778 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2779                                             struct device_attribute *attr,
2780                                             const char *buf,
2781                                             size_t count)
2782 {
2783         struct amdgpu_device *adev = dev_get_drvdata(dev);
2784         int err;
2785         int value;
2786         u32 pwm_mode;
2787
2788         if (amdgpu_in_reset(adev))
2789                 return -EPERM;
2790         if (adev->in_suspend && !adev->in_runpm)
2791                 return -EPERM;
2792
2793         err = kstrtoint(buf, 10, &value);
2794         if (err)
2795                 return err;
2796
2797         if (value == 0)
2798                 pwm_mode = AMD_FAN_CTRL_AUTO;
2799         else if (value == 1)
2800                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2801         else
2802                 return -EINVAL;
2803
2804         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2805         if (err < 0) {
2806                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2807                 return err;
2808         }
2809
2810         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2811
2812         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2813         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2814
2815         if (err)
2816                 return -EINVAL;
2817
2818         return count;
2819 }
2820
2821 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2822                                         struct device_attribute *attr,
2823                                         char *buf)
2824 {
2825         struct amdgpu_device *adev = dev_get_drvdata(dev);
2826         u32 vddgfx;
2827         int r, size = sizeof(vddgfx);
2828
2829         if (amdgpu_in_reset(adev))
2830                 return -EPERM;
2831         if (adev->in_suspend && !adev->in_runpm)
2832                 return -EPERM;
2833
2834         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2835         if (r < 0) {
2836                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2837                 return r;
2838         }
2839
2840         /* get the voltage */
2841         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2842                                    (void *)&vddgfx, &size);
2843
2844         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2845         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2846
2847         if (r)
2848                 return r;
2849
2850         return sysfs_emit(buf, "%d\n", vddgfx);
2851 }
2852
2853 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2854                                               struct device_attribute *attr,
2855                                               char *buf)
2856 {
2857         return sysfs_emit(buf, "vddgfx\n");
2858 }
2859
2860 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2861                                        struct device_attribute *attr,
2862                                        char *buf)
2863 {
2864         struct amdgpu_device *adev = dev_get_drvdata(dev);
2865         u32 vddnb;
2866         int r, size = sizeof(vddnb);
2867
2868         if (amdgpu_in_reset(adev))
2869                 return -EPERM;
2870         if (adev->in_suspend && !adev->in_runpm)
2871                 return -EPERM;
2872
2873         /* only APUs have vddnb */
2874         if  (!(adev->flags & AMD_IS_APU))
2875                 return -EINVAL;
2876
2877         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2878         if (r < 0) {
2879                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2880                 return r;
2881         }
2882
2883         /* get the voltage */
2884         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2885                                    (void *)&vddnb, &size);
2886
2887         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2888         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2889
2890         if (r)
2891                 return r;
2892
2893         return sysfs_emit(buf, "%d\n", vddnb);
2894 }
2895
2896 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2897                                               struct device_attribute *attr,
2898                                               char *buf)
2899 {
2900         return sysfs_emit(buf, "vddnb\n");
2901 }
2902
2903 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2904                                            struct device_attribute *attr,
2905                                            char *buf)
2906 {
2907         struct amdgpu_device *adev = dev_get_drvdata(dev);
2908         u32 query = 0;
2909         int r, size = sizeof(u32);
2910         unsigned uw;
2911
2912         if (amdgpu_in_reset(adev))
2913                 return -EPERM;
2914         if (adev->in_suspend && !adev->in_runpm)
2915                 return -EPERM;
2916
2917         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2918         if (r < 0) {
2919                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2920                 return r;
2921         }
2922
2923         /* get the voltage */
2924         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2925                                    (void *)&query, &size);
2926
2927         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2928         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2929
2930         if (r)
2931                 return r;
2932
2933         /* convert to microwatts */
2934         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2935
2936         return sysfs_emit(buf, "%u\n", uw);
2937 }
2938
2939 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2940                                          struct device_attribute *attr,
2941                                          char *buf)
2942 {
2943         return sysfs_emit(buf, "%i\n", 0);
2944 }
2945
2946
2947 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2948                                         struct device_attribute *attr,
2949                                         char *buf,
2950                                         enum pp_power_limit_level pp_limit_level)
2951 {
2952         struct amdgpu_device *adev = dev_get_drvdata(dev);
2953         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2954         uint32_t limit;
2955         ssize_t size;
2956         int r;
2957
2958         if (amdgpu_in_reset(adev))
2959                 return -EPERM;
2960         if (adev->in_suspend && !adev->in_runpm)
2961                 return -EPERM;
2962
2963         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2964         if (r < 0) {
2965                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2966                 return r;
2967         }
2968
2969         r = amdgpu_dpm_get_power_limit(adev, &limit,
2970                                       pp_limit_level, power_type);
2971
2972         if (!r)
2973                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2974         else
2975                 size = sysfs_emit(buf, "\n");
2976
2977         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2978         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2979
2980         return size;
2981 }
2982
2983
2984 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2985                                          struct device_attribute *attr,
2986                                          char *buf)
2987 {
2988         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2989
2990 }
2991
2992 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2993                                          struct device_attribute *attr,
2994                                          char *buf)
2995 {
2996         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2997
2998 }
2999
3000 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
3001                                          struct device_attribute *attr,
3002                                          char *buf)
3003 {
3004         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
3005
3006 }
3007
3008 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
3009                                          struct device_attribute *attr,
3010                                          char *buf)
3011 {
3012         struct amdgpu_device *adev = dev_get_drvdata(dev);
3013         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3014
3015         if (gc_ver == IP_VERSION(10, 3, 1))
3016                 return sysfs_emit(buf, "%s\n",
3017                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3018                                   "fastPPT" : "slowPPT");
3019         else
3020                 return sysfs_emit(buf, "PPT\n");
3021 }
3022
3023 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3024                 struct device_attribute *attr,
3025                 const char *buf,
3026                 size_t count)
3027 {
3028         struct amdgpu_device *adev = dev_get_drvdata(dev);
3029         int limit_type = to_sensor_dev_attr(attr)->index;
3030         int err;
3031         u32 value;
3032
3033         if (amdgpu_in_reset(adev))
3034                 return -EPERM;
3035         if (adev->in_suspend && !adev->in_runpm)
3036                 return -EPERM;
3037
3038         if (amdgpu_sriov_vf(adev))
3039                 return -EINVAL;
3040
3041         err = kstrtou32(buf, 10, &value);
3042         if (err)
3043                 return err;
3044
3045         value = value / 1000000; /* convert to Watt */
3046         value |= limit_type << 24;
3047
3048         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3049         if (err < 0) {
3050                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3051                 return err;
3052         }
3053
3054         err = amdgpu_dpm_set_power_limit(adev, value);
3055
3056         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3057         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3058
3059         if (err)
3060                 return err;
3061
3062         return count;
3063 }
3064
3065 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3066                                       struct device_attribute *attr,
3067                                       char *buf)
3068 {
3069         struct amdgpu_device *adev = dev_get_drvdata(dev);
3070         uint32_t sclk;
3071         int r, size = sizeof(sclk);
3072
3073         if (amdgpu_in_reset(adev))
3074                 return -EPERM;
3075         if (adev->in_suspend && !adev->in_runpm)
3076                 return -EPERM;
3077
3078         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3079         if (r < 0) {
3080                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3081                 return r;
3082         }
3083
3084         /* get the sclk */
3085         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3086                                    (void *)&sclk, &size);
3087
3088         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3089         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3090
3091         if (r)
3092                 return r;
3093
3094         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3095 }
3096
3097 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3098                                             struct device_attribute *attr,
3099                                             char *buf)
3100 {
3101         return sysfs_emit(buf, "sclk\n");
3102 }
3103
3104 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3105                                       struct device_attribute *attr,
3106                                       char *buf)
3107 {
3108         struct amdgpu_device *adev = dev_get_drvdata(dev);
3109         uint32_t mclk;
3110         int r, size = sizeof(mclk);
3111
3112         if (amdgpu_in_reset(adev))
3113                 return -EPERM;
3114         if (adev->in_suspend && !adev->in_runpm)
3115                 return -EPERM;
3116
3117         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3118         if (r < 0) {
3119                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3120                 return r;
3121         }
3122
3123         /* get the sclk */
3124         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3125                                    (void *)&mclk, &size);
3126
3127         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3128         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3129
3130         if (r)
3131                 return r;
3132
3133         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3134 }
3135
3136 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3137                                             struct device_attribute *attr,
3138                                             char *buf)
3139 {
3140         return sysfs_emit(buf, "mclk\n");
3141 }
3142
3143 /**
3144  * DOC: hwmon
3145  *
3146  * The amdgpu driver exposes the following sensor interfaces:
3147  *
3148  * - GPU temperature (via the on-die sensor)
3149  *
3150  * - GPU voltage
3151  *
3152  * - Northbridge voltage (APUs only)
3153  *
3154  * - GPU power
3155  *
3156  * - GPU fan
3157  *
3158  * - GPU gfx/compute engine clock
3159  *
3160  * - GPU memory clock (dGPU only)
3161  *
3162  * hwmon interfaces for GPU temperature:
3163  *
3164  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3165  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3166  *
3167  * - temp[1-3]_label: temperature channel label
3168  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3169  *
3170  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3171  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3172  *
3173  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3174  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3175  *
3176  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3177  *   - these are supported on SOC15 dGPUs only
3178  *
3179  * hwmon interfaces for GPU voltage:
3180  *
3181  * - in0_input: the voltage on the GPU in millivolts
3182  *
3183  * - in1_input: the voltage on the Northbridge in millivolts
3184  *
3185  * hwmon interfaces for GPU power:
3186  *
3187  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3188  *
3189  * - power1_cap_min: minimum cap supported in microWatts
3190  *
3191  * - power1_cap_max: maximum cap supported in microWatts
3192  *
3193  * - power1_cap: selected power cap in microWatts
3194  *
3195  * hwmon interfaces for GPU fan:
3196  *
3197  * - pwm1: pulse width modulation fan level (0-255)
3198  *
3199  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3200  *
3201  * - pwm1_min: pulse width modulation fan control minimum level (0)
3202  *
3203  * - pwm1_max: pulse width modulation fan control maximum level (255)
3204  *
3205  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3206  *
3207  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3208  *
3209  * - fan1_input: fan speed in RPM
3210  *
3211  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3212  *
3213  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3214  *
3215  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3216  *       That will get the former one overridden.
3217  *
3218  * hwmon interfaces for GPU clocks:
3219  *
3220  * - freq1_input: the gfx/compute clock in hertz
3221  *
3222  * - freq2_input: the memory clock in hertz
3223  *
3224  * You can use hwmon tools like sensors to view this information on your system.
3225  *
3226  */
3227
3228 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3229 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3230 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3231 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3232 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3233 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3234 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3235 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3236 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3237 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3238 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3239 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3240 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3241 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3242 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3243 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3244 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3245 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3246 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3247 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3248 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3249 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3250 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3251 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3252 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3253 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3254 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3255 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3256 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3257 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3258 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3259 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3260 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3261 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3262 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3263 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3264 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3265 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3266 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3267 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3268 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3269 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3270 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3271 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3272
3273 static struct attribute *hwmon_attributes[] = {
3274         &sensor_dev_attr_temp1_input.dev_attr.attr,
3275         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3276         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3277         &sensor_dev_attr_temp2_input.dev_attr.attr,
3278         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3279         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3280         &sensor_dev_attr_temp3_input.dev_attr.attr,
3281         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3282         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3283         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3284         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3285         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3286         &sensor_dev_attr_temp1_label.dev_attr.attr,
3287         &sensor_dev_attr_temp2_label.dev_attr.attr,
3288         &sensor_dev_attr_temp3_label.dev_attr.attr,
3289         &sensor_dev_attr_pwm1.dev_attr.attr,
3290         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3291         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3292         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3293         &sensor_dev_attr_fan1_input.dev_attr.attr,
3294         &sensor_dev_attr_fan1_min.dev_attr.attr,
3295         &sensor_dev_attr_fan1_max.dev_attr.attr,
3296         &sensor_dev_attr_fan1_target.dev_attr.attr,
3297         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3298         &sensor_dev_attr_in0_input.dev_attr.attr,
3299         &sensor_dev_attr_in0_label.dev_attr.attr,
3300         &sensor_dev_attr_in1_input.dev_attr.attr,
3301         &sensor_dev_attr_in1_label.dev_attr.attr,
3302         &sensor_dev_attr_power1_average.dev_attr.attr,
3303         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3304         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3305         &sensor_dev_attr_power1_cap.dev_attr.attr,
3306         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3307         &sensor_dev_attr_power1_label.dev_attr.attr,
3308         &sensor_dev_attr_power2_average.dev_attr.attr,
3309         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3310         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3311         &sensor_dev_attr_power2_cap.dev_attr.attr,
3312         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3313         &sensor_dev_attr_power2_label.dev_attr.attr,
3314         &sensor_dev_attr_freq1_input.dev_attr.attr,
3315         &sensor_dev_attr_freq1_label.dev_attr.attr,
3316         &sensor_dev_attr_freq2_input.dev_attr.attr,
3317         &sensor_dev_attr_freq2_label.dev_attr.attr,
3318         NULL
3319 };
3320
3321 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3322                                         struct attribute *attr, int index)
3323 {
3324         struct device *dev = kobj_to_dev(kobj);
3325         struct amdgpu_device *adev = dev_get_drvdata(dev);
3326         umode_t effective_mode = attr->mode;
3327         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3328
3329         /* under multi-vf mode, the hwmon attributes are all not supported */
3330         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3331                 return 0;
3332
3333         /* under pp one vf mode manage of hwmon attributes is not supported */
3334         if (amdgpu_sriov_is_pp_one_vf(adev))
3335                 effective_mode &= ~S_IWUSR;
3336
3337         /* Skip fan attributes if fan is not present */
3338         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3339             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3340             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3341             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3342             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3343             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3344             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3345             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3346             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3347                 return 0;
3348
3349         /* Skip fan attributes on APU */
3350         if ((adev->flags & AMD_IS_APU) &&
3351             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3352              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3353              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3354              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3355              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3356              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3357              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3358              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3359              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3360                 return 0;
3361
3362         /* Skip crit temp on APU */
3363         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3364             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3365              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3366                 return 0;
3367
3368         /* Skip limit attributes if DPM is not enabled */
3369         if (!adev->pm.dpm_enabled &&
3370             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3371              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3372              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3373              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3374              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3375              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3376              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3377              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3378              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3379              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3380              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3381                 return 0;
3382
3383         /* mask fan attributes if we have no bindings for this asic to expose */
3384         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3385               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3386             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3387              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3388                 effective_mode &= ~S_IRUGO;
3389
3390         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3391               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3392               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3393               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3394                 effective_mode &= ~S_IWUSR;
3395
3396         /* In the case of APUs, this is only implemented on Vangogh */
3397         if (((adev->family == AMDGPU_FAMILY_SI) ||
3398              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) &&
3399             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3400              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3401              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3402              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3403                 return 0;
3404
3405         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3406         if (((adev->family == AMDGPU_FAMILY_SI) ||
3407              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3408             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3409                 return 0;
3410
3411         /* hide max/min values if we can't both query and manage the fan */
3412         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3413               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3414               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3415               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3416             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3417              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3418                 return 0;
3419
3420         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3421              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3422              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3423              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3424                 return 0;
3425
3426         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3427              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3428             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3429              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3430                 return 0;
3431
3432         /* only APUs have vddnb */
3433         if (!(adev->flags & AMD_IS_APU) &&
3434             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3435              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3436                 return 0;
3437
3438         /* no mclk on APUs */
3439         if ((adev->flags & AMD_IS_APU) &&
3440             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3441              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3442                 return 0;
3443
3444         /* only SOC15 dGPUs support hotspot and mem temperatures */
3445         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3446             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3447              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3448              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3449              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3450              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3451              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3452              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3453              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3454              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3455              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3456              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3457                 return 0;
3458
3459         /* only Vangogh has fast PPT limit and power labels */
3460         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3461             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3462              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3463              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3464              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3465              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3466              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3467                 return 0;
3468
3469         return effective_mode;
3470 }
3471
3472 static const struct attribute_group hwmon_attrgroup = {
3473         .attrs = hwmon_attributes,
3474         .is_visible = hwmon_attributes_visible,
3475 };
3476
3477 static const struct attribute_group *hwmon_groups[] = {
3478         &hwmon_attrgroup,
3479         NULL
3480 };
3481
3482 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3483 {
3484         int ret;
3485         uint32_t mask = 0;
3486
3487         if (adev->pm.sysfs_initialized)
3488                 return 0;
3489
3490         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3491
3492         if (adev->pm.dpm_enabled == 0)
3493                 return 0;
3494
3495         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3496                                                                    DRIVER_NAME, adev,
3497                                                                    hwmon_groups);
3498         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3499                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3500                 dev_err(adev->dev,
3501                         "Unable to register hwmon device: %d\n", ret);
3502                 return ret;
3503         }
3504
3505         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3506         case SRIOV_VF_MODE_ONE_VF:
3507                 mask = ATTR_FLAG_ONEVF;
3508                 break;
3509         case SRIOV_VF_MODE_MULTI_VF:
3510                 mask = 0;
3511                 break;
3512         case SRIOV_VF_MODE_BARE_METAL:
3513         default:
3514                 mask = ATTR_FLAG_MASK_ALL;
3515                 break;
3516         }
3517
3518         ret = amdgpu_device_attr_create_groups(adev,
3519                                                amdgpu_device_attrs,
3520                                                ARRAY_SIZE(amdgpu_device_attrs),
3521                                                mask,
3522                                                &adev->pm.pm_attr_list);
3523         if (ret)
3524                 return ret;
3525
3526         adev->pm.sysfs_initialized = true;
3527
3528         return 0;
3529 }
3530
3531 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3532 {
3533         if (adev->pm.int_hwmon_dev)
3534                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3535
3536         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3537 }
3538
3539 /*
3540  * Debugfs info
3541  */
3542 #if defined(CONFIG_DEBUG_FS)
3543
3544 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3545                                            struct amdgpu_device *adev) {
3546         uint16_t *p_val;
3547         uint32_t size;
3548         int i;
3549         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
3550
3551         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
3552                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
3553                                 GFP_KERNEL);
3554
3555                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3556                                             (void *)p_val, &size)) {
3557                         for (i = 0; i < num_cpu_cores; i++)
3558                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3559                                            *(p_val + i), i);
3560                 }
3561
3562                 kfree(p_val);
3563         }
3564 }
3565
3566 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3567 {
3568         uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0];
3569         uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
3570         uint32_t value;
3571         uint64_t value64 = 0;
3572         uint32_t query = 0;
3573         int size;
3574
3575         /* GPU Clocks */
3576         size = sizeof(value);
3577         seq_printf(m, "GFX Clocks and Power:\n");
3578
3579         amdgpu_debugfs_prints_cpu_info(m, adev);
3580
3581         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3582                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3583         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3584                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3585         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3586                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3587         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3588                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3589         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3590                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3591         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3592                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3593         size = sizeof(uint32_t);
3594         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3595                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3596         size = sizeof(value);
3597         seq_printf(m, "\n");
3598
3599         /* GPU Temp */
3600         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3601                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3602
3603         /* GPU Load */
3604         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3605                 seq_printf(m, "GPU Load: %u %%\n", value);
3606         /* MEM Load */
3607         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3608                 seq_printf(m, "MEM Load: %u %%\n", value);
3609
3610         seq_printf(m, "\n");
3611
3612         /* SMC feature mask */
3613         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3614                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3615
3616         /* ASICs greater than CHIP_VEGA20 supports these sensors */
3617         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
3618                 /* VCN clocks */
3619                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3620                         if (!value) {
3621                                 seq_printf(m, "VCN: Disabled\n");
3622                         } else {
3623                                 seq_printf(m, "VCN: Enabled\n");
3624                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3625                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3626                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3627                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3628                         }
3629                 }
3630                 seq_printf(m, "\n");
3631         } else {
3632                 /* UVD clocks */
3633                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3634                         if (!value) {
3635                                 seq_printf(m, "UVD: Disabled\n");
3636                         } else {
3637                                 seq_printf(m, "UVD: Enabled\n");
3638                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3639                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3640                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3641                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3642                         }
3643                 }
3644                 seq_printf(m, "\n");
3645
3646                 /* VCE clocks */
3647                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3648                         if (!value) {
3649                                 seq_printf(m, "VCE: Disabled\n");
3650                         } else {
3651                                 seq_printf(m, "VCE: Enabled\n");
3652                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3653                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3654                         }
3655                 }
3656         }
3657
3658         return 0;
3659 }
3660
3661 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
3662 {
3663         int i;
3664
3665         for (i = 0; clocks[i].flag; i++)
3666                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3667                            (flags & clocks[i].flag) ? "On" : "Off");
3668 }
3669
3670 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3671 {
3672         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3673         struct drm_device *dev = adev_to_drm(adev);
3674         u64 flags = 0;
3675         int r;
3676
3677         if (amdgpu_in_reset(adev))
3678                 return -EPERM;
3679         if (adev->in_suspend && !adev->in_runpm)
3680                 return -EPERM;
3681
3682         r = pm_runtime_get_sync(dev->dev);
3683         if (r < 0) {
3684                 pm_runtime_put_autosuspend(dev->dev);
3685                 return r;
3686         }
3687
3688         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
3689                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3690                 if (r)
3691                         goto out;
3692         }
3693
3694         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3695
3696         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
3697         amdgpu_parse_cg_state(m, flags);
3698         seq_printf(m, "\n");
3699
3700 out:
3701         pm_runtime_mark_last_busy(dev->dev);
3702         pm_runtime_put_autosuspend(dev->dev);
3703
3704         return r;
3705 }
3706
3707 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3708
3709 /*
3710  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3711  *
3712  * Reads debug memory region allocated to PMFW
3713  */
3714 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3715                                          size_t size, loff_t *pos)
3716 {
3717         struct amdgpu_device *adev = file_inode(f)->i_private;
3718         size_t smu_prv_buf_size;
3719         void *smu_prv_buf;
3720         int ret = 0;
3721
3722         if (amdgpu_in_reset(adev))
3723                 return -EPERM;
3724         if (adev->in_suspend && !adev->in_runpm)
3725                 return -EPERM;
3726
3727         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
3728         if (ret)
3729                 return ret;
3730
3731         if (!smu_prv_buf || !smu_prv_buf_size)
3732                 return -EINVAL;
3733
3734         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3735                                        smu_prv_buf_size);
3736 }
3737
3738 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3739         .owner = THIS_MODULE,
3740         .open = simple_open,
3741         .read = amdgpu_pm_prv_buffer_read,
3742         .llseek = default_llseek,
3743 };
3744
3745 #endif
3746
3747 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3748 {
3749 #if defined(CONFIG_DEBUG_FS)
3750         struct drm_minor *minor = adev_to_drm(adev)->primary;
3751         struct dentry *root = minor->debugfs_root;
3752
3753         if (!adev->pm.dpm_enabled)
3754                 return;
3755
3756         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3757                             &amdgpu_debugfs_pm_info_fops);
3758
3759         if (adev->pm.smu_prv_buffer_size > 0)
3760                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3761                                          adev,
3762                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3763                                          adev->pm.smu_prv_buffer_size);
3764
3765         amdgpu_dpm_stb_debug_fs_init(adev);
3766 #endif
3767 }